Self-light-emitting type display device and driving method for self-light-emitting type display device

Abstract

To provide a self-light-emitting type display device capable of in-plane homogenization, and a driving method for a self-light-emitting type display device.SOLUTION: A self-light-emitting type display device includes a substrate including a display region, a first pixel disposed in a first region at an outer edge of the display region, and a second pixel disposed in a second region surrounded by the first region. Each of the first pixel and the second pixel includes a first transistor, a second transistor, a first capacitor element, a third transistor, and a seventh transistor. The capacitance of a capacitor part connected to a gate electrode of the second transistor in the first pixel and the capacitance of a capacitor part connected to a gate electrode of the second transistor in the second pixel are different.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a self-luminous display device and a method for driving a self-luminous display device. [Background technology]

[0002] In recent years, self-luminous display devices have been implemented in televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.), and have become widespread. The self-luminous display device includes, for example, a plurality of pixels and a driver for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitance element, and a light-emitting element. The light-emitting element is, for example, a light-emitting diode (LED), a minute light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In the self-luminous display device, a driver supplies a voltage to each of the plurality of pixels, so that a current corresponding to the supplied voltage value flows through the light-emitting element included in each of the plurality of pixels. Each of the light-emitting elements emits light with a luminance corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the luminance. Meanwhile, there is an increasing demand for in-plane uniformity of the self-luminous display device.

[0003] For example, Patent Document 1 discloses a pixel including six transistors, one capacitive element, and one light-emitting element, and a self-luminous display device including the pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2016 / 0284276 Summary of the Invention [Problem to be solved by the invention]

[0005] In the self-luminous display device described in Patent Document 1, for example, a phenomenon has been confirmed in which the outermost periphery of the display area emits light more brightly than the other areas at low luminance.

[0006] In view of these problems, one embodiment of the present invention has an objective to provide a self-luminous display device and a method for driving a self-luminous display device that can achieve in-plane uniformity of light-emitting elements (self-luminous display devices). [Means for solving the problem]

[0007] A self-luminous display device according to an embodiment of the present invention includes a substrate having a display area, a first pixel arranged in a first area on the outer edge of the display area, and a second pixel arranged in a second area surrounded by the first area, each of the first pixel and the second pixel being controlled by a second control signal obtained by shifting a first control signal, and the first pixel and the second pixel being controlled by a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitance element electrically connected to a gate electrode of the second transistor, and a third control signal being shifted from the first control signal to the second control signal. a third transistor controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element using the third control signal, and electrically connected between the second node and the gate electrode of the second transistor; and a seventh transistor controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitive element using the third control signal, and electrically connected to the second node, wherein a capacitance of a capacitive section connected to the gate electrode of the second transistor of the first pixel is different from a capacitance of a capacitive section connected to the gate electrode of the second transistor of the second pixel.

[0008] A self-luminous display device according to an embodiment of the present invention includes a substrate having a display region, a third pixel arranged in a third region including one end of the display region, and a fourth pixel arranged in a fourth region adjacent to the third region, each of the third pixel and the fourth pixel being controlled using a second control signal obtained by shifting a first control signal, and including a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitance element electrically connected to a gate electrode of the second transistor, and a third control signal shifted from the first control signal to the fourth pixel. a third transistor controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element, and electrically connected between the second node and the gate electrode of the second transistor; and a seventh transistor controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitive element using the third control signal, and electrically connected to the second node, wherein a capacitance of a capacitive unit connected to the image data signal line connected to the third pixel is different from a capacitance of a capacitive unit connected to the image data signal line connected to the fourth pixel.

[0009] A method for driving a self-luminous display device according to an embodiment of the present invention includes a substrate having a display region, a sixth pixel arranged in a sixth region including one end of the display region, and a seventh pixel arranged in a seventh region adjacent to the sixth region, each of the sixth pixel and the seventh pixel being controlled by at least a second control signal obtained by shifting a first control signal, and including a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitance element electrically connected to a gate electrode of the second transistor, and a third control signal shifted from the first control signal to the seventh pixel. a third transistor controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitance element, and electrically connected between the second node and a gate electrode of the second transistor; and a seventh transistor controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitance element using the third control signal, and electrically connected to the second node, wherein a time during which the first control signal and the second control signal supplied to the sixth pixel overlap is longer than a time during which the second control signal and a fifth control signal obtained by shifting the second control signal, supplied to the seventh pixel, overlap.

[0010] A method for driving a self-luminous display device according to an embodiment of the present invention includes a substrate having a display region, a sixth pixel arranged in a sixth region including one end of the display region, and a seventh pixel arranged in a seventh region adjacent to the sixth region, each of the sixth pixel and the seventh pixel being controlled by at least a second control signal obtained by shifting a first control signal, and including a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a first capacitance element electrically connected to a gate electrode of the second transistor, and a third control signal shifted from the first control signal to the gate electrode of the second transistor and the first capacitance element. A method for driving a self-luminous display device including a third transistor controlled to supply a threshold voltage of the second transistor to a capacitive element, the third transistor being electrically connected between the second node and a gate electrode of the second transistor, and a seventh transistor controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitive element using the third control signal, the seventh transistor being electrically connected to the second node, wherein a voltage supplied during a time when the first control signal and the second control signal supplied to the sixth pixel overlap is greater than a voltage supplied during a time when the second control signal supplied to the seventh pixel overlaps with a fifth control signal obtained by shifting the second control signal. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram showing a configuration of a self-luminous display device according to a first embodiment of the present invention. [Diagram 2] 1 is a schematic diagram showing a configuration of a self-luminous display device according to a first embodiment of the present invention. [Diagram 3] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 4] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 5A] FIG. 2 is a schematic diagram showing a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 5B] FIG. 2 is a schematic diagram showing a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 6] FIG. 2 is a schematic diagram showing a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 7] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 8] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 9] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 10] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 11] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 12] 7A to 7C are schematic diagrams showing operation states of pixels at the timings shown in FIG. 6. [Figure 13] FIG. 2 is a schematic diagram showing a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 14] 14 is a schematic diagram showing an operation state of a pixel at the timing shown in FIG. 13. FIG. [Figure 15] FIG. 5 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 16] FIG. 11 is a schematic diagram showing a configuration of a self-luminous display device according to a third embodiment of the present invention. [Figure 17] FIG. 13 is a schematic diagram showing a configuration of a source driver circuit according to a fourth embodiment of the present invention. [Figure 18] FIG. 13 is a schematic diagram showing a configuration of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 19] FIG. 13 is a schematic diagram showing a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 20] FIG. 13 is a schematic diagram showing a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 21] FIG. 13 is a cross-sectional view showing an overview of a semiconductor device according to a seventh embodiment of the present invention. [Figure 22] FIG. 13 is a plan view showing an overview of a semiconductor device according to a seventh embodiment of the present invention. [Diagram 23] FIG. 13 is a sequence diagram showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Figure 24] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Diagram 25] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Figure 26] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Figure 27] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Figure 28] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Figure 29] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Diagram 30] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Diagram 31] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Diagram 32] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention. [Diagram 33] FIG. 13 is a schematic diagram showing a configuration of a pixel circuit according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different aspects, and should not be interpreted as being limited to the description of the embodiment exemplified below. In addition, in order to make the explanation clearer, the width, thickness, shape, configuration, etc. of each part may be shown diagrammatically compared to the actual aspect, but these are merely examples and do not limit the interpretation of the present invention. Note that the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no further meaning unless otherwise specified.

[0013] In addition, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] A self-luminous display device according to an embodiment of the present invention is, as an example, a light-emitting device that uses EL elements as light-emitting elements.

[0015] <1. First embodiment> <1-1. Overview of the self-luminous display device 10> An overview of a self-luminous display device 10 according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 and Fig. 2 are schematic diagrams showing a configuration of the self-luminous display device 10 according to the first embodiment. The configuration of the self-luminous display device 10 shown in Fig. 1 and Fig. 2 is an example, and the configuration of the self-luminous display device 10 is not limited to the configuration shown in Fig. 1 and Fig. 2.

[0016] 1 or 2, the self-luminous display device 10 includes an array substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 170. The self-luminous display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0017] A plurality of pixels 180 are arranged in a matrix in the display region 22. The pixel 180 is the smallest unit constituting a part of an image to be displayed in the display region 22. Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may be formed by three sub-pixels. There is no limitation on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the self-luminous display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0018] The display region 22 includes a region 22A and a region 22B. The region 22A is disposed on the outer edge of the display region 22 so as to surround the region 22B. The region 22A may include a pixel 180A arranged in one row and one column on the outermost periphery of the display region 22, or may include pixels 180A arranged in multiple rows and multiple columns. When the pixel 180A and the pixel 180B are not distinguished from each other, they are referred to as pixels 180. Although details will be described later, in this embodiment, the capacitance of the pixel 180A is different from the capacitance of the pixel 180B. The capacitance of the capacitance part connected to the gate electrode 622 of the second transistor T2 of the pixel 180A is different from the capacitance of the capacitance part connected to the gate electrode 622 of the second transistor T2 of the pixel 180B.

[0019] The sub-pixels R, G, and B are configured to display images of different colors. For example, each of the sub-pixels R, G, and B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. When any voltage or current is supplied to each of the three sub-pixels, the self-emissive display device 10 can display an image.

[0020] The peripheral region 24 is provided with a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130. The source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 are each connected to the terminal portion 150 using a connection wiring 341. The peripheral region 24 may be called a frame region. The connection wiring 341 may be referred to individually as the connection wiring 341, and a bundle of a plurality of the connection wirings 341 may be referred to as the connection wiring 341.

[0021] The terminal area 26 is provided with a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150. The terminal area 26 is an area on the opposite side of the peripheral area 24 from an area in which the display area 22 is provided in the first direction D1.

[0022] The FPC 160 is connected to an external device (not shown) outside the self-luminous display device 10. Therefore, the self-luminous display device 10 is connected to the external device via the FPC 160 and the terminal section 150 connected to the FPC. A control signal and a voltage are transmitted from the external device to the self-luminous display device 10 via the FPC 160 and the terminal section 150 connected to the FPC. The self-luminous display device 10 drives each pixel 180 provided in the self-luminous display device 10 using the control signal and voltage received from the external device. As a result, the self-luminous display device 10 can display an image in the display region 22.

[0023] The IC chip 170 is provided, for example, on the FPC 160. The IC chip 170 supplies signals, voltages, and the like for driving each pixel 180 to the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the pixels 180 (pixel circuits) via the FPC 160, the terminal portion 150, and the connection wiring 341.

[0024] In the first embodiment, each of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be referred to individually as a control circuit, and a group of circuits including some or all of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be referred to as a control circuit.

[0025] <1-2. Configuration of the source driver circuit 110> An overview of the source driver circuit 110 will be described with reference to Figures 1 and 2. As shown in Figure 1 or 2, the source driver circuit 110 is provided at a position adjacent to the display area 22 in a first direction D1 (column direction). Image data signal lines 321 extend from the source driver circuit 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0026] 2, the source driver circuit 110 includes, for example, a plurality of selection circuits 112. Each of the plurality of selection circuits 112 is controlled, for example, based on an on signal and an off signal supplied to a selection signal MUXR, a selection signal MUXG, and a selection signal MUXB. The selection circuit 112 is selected by an on signal supplied to a selection signal (for example, the selection signal MUXR), and supplies an image data signal SL(m+1) including a data signal VDATA supplied to an input terminal 114 to an image data signal line 321 and a pixel 180 electrically connected to the image data signal line 321. The details will be described later, but the data signal VDATA includes, for example, a voltage RDATA(n), a voltage GDATA(n), or a voltage BDATA(n).

[0027] The selection circuit 112 is, for example, a switch 118 including an input terminal 114 and an output terminal 116. For example, the input terminal 114 and the output terminal 116 are conductively connected to each other by an on signal supplied from the IC chip 170 to the selection signal MUXR, and the input terminal 114 and the output terminal 116 are cut off (disconnected) by an off signal supplied from the IC chip 170 to the selection signal MUXR. The on signal is a signal including a voltage that connects the input terminal 114 and the output terminal 116 to each other, and the off signal is a signal including a voltage that cuts off the input terminal 114 and the output terminal 116 from each other.

[0028] In the present invention, the on signal may be high (High, HI) and the off signal may be low (Low, LO), or the on signal may be low (Low, LO) and the off signal may be high (High, HI).

[0029] <1-3. Configuration of the Gate Driver Circuit 120> An overview of the gate driver circuit 120 will be described with reference to Figures 1 and 2. As shown in Figure 1 or 2, the gate driver circuit 120 is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). Scanning signal lines 329, 330, 331, and 332 extend from the gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0030] 2, the gate driver circuit 120 includes a plurality of shift registers (for example, shift registers 121, 122, and 123). The shift registers 121, 122, and 123 sequentially supply scanning signals (for example, scanning signal G(n-1), scanning signal G(n), scanning signal G(n+1)) having different timings to the scanning signal lines 329, 330, 331, and 332, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and drive the pixels 180 (pixel circuits) electrically connected to each scanning signal line. The scanning signal G(n) may be called a first control signal, the scanning signal G(n+1) may be called a second control signal, and the scanning signal G(n-1) may be called a third control signal.

[0031] For example, the shift register 121 is electrically connected to the shift register 122, and the shift register 122 is electrically connected to the shift register 123. The shift register 121 is electrically connected to the scanning signal line 329 and supplies, for example, a scanning signal G(n-1) to the scanning signal line 329. Similarly to the shift register 121, the shift register 122 is electrically connected to the scanning signal line 330 and supplies, for example, a scanning signal G(n) to the scanning signal line 330, and the shift register 123 is electrically connected to the scanning signal line 331 and supplies, for example, a scanning signal G(n+1) to the scanning signal line 331. Although not shown, the next-stage shift register electrically connected to the shift register 123 is electrically connected to the scanning signal line 332. The scanning signal G(n) includes a pulse width equivalent to that of the scanning signal G(n-1) and is a signal obtained by shifting the scanning signal G(n-1). Scanning signal G(n+1) has the same pulse width as scanning signal G(n), and is a shifted version of scanning signal G(n).Like scanning signal G(n+1), scanning signal G(n+2) has the same pulse width as scanning signal G(n+1), and is a shifted version of scanning signal G(n+1).

[0032] <1-4. Configuration of the light emission control circuit 130> An overview of the light emission control circuit 130 will be described with reference to Fig. 1 and Fig. 2. As shown in Fig. 1 or 2, the light emission control circuit 130 is adjacent to the display area 22 in the second direction D2 (row direction) and is provided on the opposite side of the display area 22 from the position where the gate driver circuit 120 is disposed. Light emission control signal lines 334, 335, 336, and 337 extend from the light emission control circuit 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits) arranged in the second direction D2.

[0033] 2, the light emission control circuit 130 includes a plurality of shift registers (for example, shift registers 131, 132, and 133). The shift registers 131, 132, and 133 sequentially supply light emission control signals (for example, light emission control signal EM(n), light emission control signal EM(n+1), light emission control signal EM(n+2), etc.) having different timings to light emission control signal lines 334, 335, 336, and 337, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and play a role of driving the pixels 180 (pixel circuits) electrically connected to the respective light emission control signal lines.

[0034] For example, the shift register 131 is electrically connected to the shift register 132, and the shift register 132 is electrically connected to the shift register 133. The shift register 131 is electrically connected to the light emission control signal line 334 and supplies, for example, a light emission control signal EM(n) to the light emission control signal line 334. Similarly to the shift register 131, the shift register 132 is electrically connected to the light emission control signal line 335 and supplies, for example, a light emission control signal EM(n+1) to the light emission control signal line 335, and the shift register 133 is electrically connected to the light emission control signal line 336 and supplies, for example, a light emission control signal EM(n+2) to the light emission control signal line 336. Although not shown in the figure, the next-stage shift register electrically connected to the shift register 133 is electrically connected to the light emission control signal line 337. The pulse width of the light emission control signal EM(n+1) is the same as that of the light emission control signal EM(n), and the light emission control signal EM(n+1) is a signal obtained by shifting the light emission control signal EM(n). Similarly, the pulse width of the light emission control signal EM(n+2) is the same as that of the first light emission control signal EM(n+1), and the light emission control signal EM(n+2) is a signal obtained by shifting the first light emission control signal EM(n+2). The light emission control signal EM is sometimes called a fourth control signal.

[0035] <1-5. Configuration of pixel 180> An overview of the pixel 180 will be described with reference to Figs. 3 and 4. Fig. 3 is a schematic diagram showing an input signal to a pixel circuit 181 included in the pixel 180. Fig. 4 is a circuit diagram showing a configuration of the pixel circuit 181. Figs. 3 and 4 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in Figs. 1 and 2. The configurations of the pixel 180 and the pixel circuit 181 are not limited to those shown in Figs. 3 and 4. Descriptions of configurations that are the same as or similar to those in Figs. 1 and 2 will be omitted here.

[0036] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181, but the colors emitted by the light-emitting element OLED are different. In the following description, as an example, the light-emitting element OLED that mainly emits red light will be described.

[0037] 3, a scanning signal G(n-1), a scanning signal G(n), a scanning signal G(n+1), an image data signal SL(m+1), a light emission control signal EM(n), a reset voltage VSH, and an initialization voltage VINI are supplied to the pixel circuit 181. In addition, as a power supply for driving the pixel 180, a driving voltage VDDEL or a driving voltage VDDELL, and a reference voltage VSSEL are supplied to the pixel circuit 181.

[0038] The reset voltage VSH is supplied to the reset voltage line VC, the initialization voltage VINI is supplied to the initialization voltage line VM, the driving voltages VDDEL and VDDELL are supplied to the driving power supply line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. The reset voltage line VC, the initialization voltage line VM, the driving power supply line PVDD, and the reference voltage line PVSS may be electrically connected to different connection wirings 341, for example, or may be different connection wirings 341. The reset voltage VSH, the initialization voltage VINI, the driving voltage VDDEL, the driving voltage VDDELL, and the reference voltage VSSEL may be supplied to the plurality of pixels 180 (pixel circuits 181) from an external circuit via the FPC 160, the terminal unit 150, the reset voltage line VC, the initialization voltage line VM, the driving power supply line PVDD, and the reference voltage line PVSS. Furthermore, the reset voltage VSH, the initialization voltage VINI, the driving voltage VDDEL, the driving voltage VDDELL, and the reference voltage VSSEL may be supplied from the IC chip 170 to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal section 150, the reset voltage line VC, the initialization voltage line VM, the driving power supply line PVDD, and the reference voltage line PVSS. The reset voltage VSH and the initialization voltage VINI are smaller than the driving voltage VDDEL and the driving voltage VDDELL. The driving voltage VDDELL is smaller than the driving voltage VDDEL. The reference voltage VSSEL is smaller than the driving voltage VDDELL. The reset voltage VSH is, for example, larger than a voltage included in the data signal VDATA (for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n)).

[0039] 4, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitance element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance element CS and the light-emitting element OLED has a pair of electrodes consisting of a first electrode and a second electrode. The fourth transistor T4 and the fifth transistor T5 are p-channel type field effect transistors.

[0040] The first transistor T1 has a function of supplying an image data signal SL(m+1) to the second transistor T2.

[0041] The second transistor T2 is a so-called drive transistor. The second transistor T2 has a function of causing a current to flow through the light-emitting element OLED using the input image data signal SL(m+1) to cause the light-emitting element OLED to emit light.

[0042] The third transistor T3 connects the second node N2 to the gate electrode 622 (and the second electrode 694 of the capacitance element CS) of the second transistor T2. The third transistor T3 has a function of supplying a reset voltage VSH to the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS to reset the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS. The third transistor T3 also has a function of accumulating a charge equivalent to the threshold voltage Vth of the second transistor T2 in the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS.

[0043] The fourth transistor T4 controls the connection / disconnection between the drive power supply line PVDD and the second transistor T2. That is, the fourth transistor T4 has a function of supplying a drive voltage VDDEL to the second transistor T2.

[0044] The fifth transistor T5 controls the connection / disconnection between the second transistor T2 and the light-emitting element OLED. That is, the fifth transistor T5 has a function of controlling the connection / disconnection between the second transistor T2 and the light-emitting element OLED, and also of supplying a current to the light-emitting element OLED to control whether the light-emitting element OLED emits light or not.

[0045] The sixth transistor T6 has the function of supplying an initialization voltage VINI to the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitance element CS, and initializing the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitance element CS.

[0046] The seventh transistor T7 has the function of supplying a reset voltage VSH to the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, the second electrode 636 of the third transistor T3, etc., and resetting the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, and the second electrode 636 of the third transistor T3.

[0047] The capacitance element CS has a function of holding, for example, a charge (first charge) equivalent to the threshold voltage Vth of the second transistor T2. The capacitance element CS also has a function of holding a charge (second charge) equivalent to a data voltage (for example, RDATA(n) (see FIG. 6)) included in the image data signal SL(m+1) input to the gate electrode 622 of the second transistor T2.

[0048] The light-emitting element OLED has diode characteristics and emits light based on a current flowing through the light-emitting element OLED (that is, the drain current of the second transistor T2).

[0049] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scanning signal line 331. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 624 of the second transistor T2, and the second electrode 656 of the fifth transistor T5. A scanning signal G(n+1) is supplied to the scanning signal line 331. The first transistor T1 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n+1). When the signal supplied to the scanning signal G(n+1) is low (LO), the first transistor T1 is in a non-conductive state. When the signal supplied to the scanning signal G(n+1) is high (HI), the first transistor T1 is in a conductive state.

[0050] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to a first electrode 634 of the third transistor T3 and a second electrode 694 of the capacitance element CS. The second electrode 626 is electrically connected to a second node N2, a second electrode 636 of the third transistor T3, a first electrode 674 of the seventh transistor T7, and a first electrode 644 of the fourth transistor T4.

[0051] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scanning signal line 330. A scanning signal G(n) is supplied to the scanning signal line 330. The third transistor T3 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n). When the signal supplied to the scanning signal G(n) is low (LO), the third transistor T3 is in a non-conductive state. When the signal supplied to the scanning signal G(n) is high (HI), the third transistor T3 is in a conductive state.

[0052] The fourth transistor T4 is a p-channel type field effect transistor. The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the light emission control signal line 334. The second electrode 646 is electrically connected to the driving power supply line PVDD. A driving voltage VDDEL is supplied to the driving power supply line PVDD. A light emission control signal EM(n) is supplied to the light emission control signal line 334. The fourth transistor T4 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the light emission control signal EM(n). When the signal supplied to the light emission control signal EM(n) is low (LO), the fourth transistor T4 is in a conductive state. When the signal supplied to the second light emission control signal EM(n) is high (HI), the fourth transistor T4 is in a non-conductive state.

[0053] The fifth transistor T4 is a p-channel type field effect transistor. The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the light emission control signal line 334. The first electrode 654 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 692 of the capacitance element CS, and the second electrode 684 of the light emitting element OLED. The light emission control signal EM(n) is supplied to the light emission control signal line 334. The fifth transistor T5 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the light emission control signal EM(n). When the signal supplied to the light emission control signal EM(n) is low (LO), the fifth transistor T5 is in a conductive state. When the signal supplied to the light emission control signal EM(n) is high (HI), the fifth transistor T5 is in a non-conductive state.

[0054] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the light emission control signal line 334. The first electrode 664 is electrically connected to the initialization voltage line VM. The light emission control signal line 334 is supplied with a light emission control signal EM(n), and the initialization voltage line VM is supplied with an initialization voltage VINI. As with the fourth transistor T4 and the fifth transistor T5, the sixth transistor T6 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the light emission control signal EM(n). When the signal supplied to the light emission control signal EM(n) is low (LO), the sixth transistor T6 is in a non-conductive state. When the signal supplied to the light emission control signal EM(n) is high (HI), the sixth transistor T6 is in a conductive state.

[0055] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scanning signal line 329. The scanning signal line 329 is supplied with a scanning signal G(n-1). The second electrode 676 is electrically connected to the reset voltage line VC. As described above, the reset voltage VSH is supplied to the reset voltage line VC. The seventh transistor T7 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n-1). When the signal supplied to the scanning signal G(n-1) is low (LO), the seventh transistor T7 is in a non-conductive state. When the signal supplied to the scanning signal G(n-1) is high (HI), the seventh transistor T7 is in a conductive state.

[0056] The capacitive element CS includes a first electrode 692 and a second electrode 694. The first electrode 692 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light-emitting element OLED. The second electrode 694 is electrically connected to the first electrode 634 of the third transistor T3 and the gate electrode 622 of the second transistor T2.

[0057] In this embodiment, the capacitance of the capacitance element CS of the pixel 180A arranged in the region 22A is smaller than the capacitance of the capacitance element CS of the pixel 180B arranged in the region 22B. The capacitance of the capacitance element CS of the pixel 180A is preferably 0.9 times or less than the capacitance of the capacitance element CS of the pixel 180B. For example, the area of ​​the electrode of the capacitance element CS of the pixel 180A and the electrode of the capacitance element CS of the pixel 180B may be different. The electrode of the capacitance element CS of the pixel 180A may be smaller than the electrode of the capacitance element CS of the pixel 180B. The area of ​​the electrode of the capacitance element CS of the pixel 180A may be more than 2 times smaller than the area of ​​the electrode of the capacitance element CS of the pixel 180B.

[0058] The region 22A may include pixels 180A in multiple rows and multiple columns. In this case, the capacitance of the capacitive element CS of the pixel 180A arranged at the outermost periphery may be different from the capacitance of the capacitive element CS of the pixel 180A adjacent to the pixel 180B in the region 22B. The capacitance of the capacitive element CS of the pixel 180A arranged at the outermost periphery may be smaller than the capacitance of the capacitive element CS of the pixel 180A adjacent to the pixel 180B in the region 22B. In the region 22A, the capacitance of the capacitive element CS may have a positive gradient from the pixel 180A arranged at the outermost periphery to the pixel 180A adjacent to the pixel 180B in the region 22B.

[0059] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0060] In the self-luminous display device 10, the conductive state of a transistor means, for example, that the source electrode and drain electrode of the transistor are conductive and the transistor is in an ON state, and the non-conductive state of a transistor means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an OFF state. Note that in each transistor, the source electrode and the drain electrode may be switched depending on the voltage or potential supplied to each electrode. In addition, it is easily understood by those skilled in the art that even when a transistor is in an OFF state, a small amount of current flows, such as a leakage current.

[0061] Each transistor shown in FIG. 4 may have a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties, in the channel region. For example, the channel region of each transistor has low-temperature polysilicon (LTPS). In the self-luminous display device 10, each transistor is formed using a thin film transistor (TFT), the fourth transistor T4 and the fifth transistor T5 are p-channel type field effect transistors, and the other transistors are n-channel type field effect transistors. Each transistor may have either an n-channel type field effect transistor or a p-channel type field effect transistor. The self-luminous display device 10 may be adapted in terms of the transistor configuration, the connection of the storage capacitor, the power supply voltage, and the like, as appropriate, depending on the application and specifications.

[0062] <1-6. Driving method of the self-luminous display device 10> A method of driving the self-luminous display device 10 will be described with reference to Figs. 5A to 14. Figs. 5A, 5B, 6, and 13 are schematic diagrams showing timing charts of the self-luminous display device 10. Figs. 7 to 12 are schematic diagrams showing the operation state of the pixel 180 (pixel circuit 181) at the timing shown in Fig. 6. Fig. 14 is a schematic diagram showing the operation state of the pixel 180 (pixel circuit 181) at the timing shown in Fig. 13. The method of driving the self-luminous display device 10 is not limited to the driving method shown in Figs. 5A to 14. Descriptions of configurations that are the same as or similar to those in Figs. 1 to 4 will be omitted here. The horizontal axis of the timing chart indicates time (TIME).

[0063] Fig. 5A is a timing chart of a method for driving the self-luminous display device 10 when the self-luminous display device 10 is driven at a high frequency. The high frequency is, for example, 60 Hz, and one frame (1FRAME) is driven at 60 Hz. Fig. 5A shows, for example, the current frame (KthFRAME), a portion of the frame immediately before the current frame (K-1stFRAME), and a portion of the frame immediately after the current frame (K+1stFRAME). The driving method shown in Fig. 5A is called, for example, high-frequency driving.

[0064] 5A, the method of driving the self-luminous display device 10 includes at least a reset period PRS, a sampling period PWR, and a light-emitting period PEM in one frame. In the pixel 180 (pixel circuit 181) included in the self-luminous display device 10, the sampling period PWR is executed after the reset period PRS, and the light-emitting period PEM is executed after the sampling period PWR. In addition, the reset period PRS of the current frame is executed after the light-emitting period PEM of the frame immediately preceding the current frame, and the reset period PRS and sampling period PWR of the frame immediately following the current frame are executed after the light-emitting period PEM of the current frame.

[0065] FIG. 5B is a timing chart of a method of driving the self-luminous display device 10 when the self-luminous display device 10 is driven at a low frequency, for example. The low frequency is, for example, 1 Hz, and is a frequency at which one frame (1FRAME) is driven at 1 Hz. The driving method shown in FIG. 5B is called, for example, low-frequency driving. Compared to high-frequency driving, low-frequency driving is a driving method in which a period for displaying black (black period PBWR) is executed multiple times during the light-emitting period PEM. In low-frequency driving, driving other than the black period PBWR is the same as high-frequency driving.

[0066] 6 is a diagram for explaining the reset period PRS, the sampling period PWR, and the light emission period PEM of the driving method of the pixel 180 (pixel circuit 181) of the self-luminous display device 10. FIG. 6 shows the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame, and the reset period PRS, the sampling period PWR, and the light emission period PEM of the current frame (KthFRAME). FIG. 6 also shows a plurality of horizontal periods (horizontal period N-2ndHP, horizontal period N-1stHP, horizontal period NthHP, horizontal period N+1stHP, horizontal period N+2ndHP). One horizontal period is, for example, a period during which an image data signal SL(m+1) including a data signal VDATA is input to a pixel (pixel circuit) electrically connected to one scanning signal line, and the image data signal SL(m+1) including a data signal VDATA is input to the pixels (pixel circuits) electrically connected to all scanning signal lines, and an image of the current frame corresponding to one FRAME is displayed.

[0067] 6 to 12, an example of a driving method in which the pixel 180 (pixel circuit 181) displays an image based on the voltage RDATA(n) included in the data signal VDATA input during one horizontal period NthHP will be described. Note that in the description of the driving method according to the first embodiment, as an example, a driving voltage VDDEL or a driving voltage VDDELL is supplied to a driving power supply line PVDD, and a reference voltage VSSEL is supplied to a reference voltage line PVSS.

[0068] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m+1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is, for example, analog data including a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. The voltage VDM is a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, the selection signal MUXR is used to select the voltage RDATA and supply it to the image data signal line, the selection signal MUXG is used to select the voltage GDATA and supply it to the image data signal line, and the selection signal MUXB is used to select the voltage BDATA and supply it to the image data signal line. In a period in which data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0069] Next, a method for driving the pixel 180 (pixel circuit 181) in the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame will be described with reference to Figures 6 and 7. The light emission period PEM of the frame (K-1stFRAME) immediately before the current frame is a period during which the pixel 180 (pixel circuit 181) emits light in response to the voltage RDATA(n-1).

[0070] The gate electrode 622 of the second transistor T2 is supplied with a voltage RDATA(n-1). The scanning signals G(n-1), G(n), and G(n+1) are supplied with a low (LO) signal, and the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an off state. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with a low (LO) signal from the light emission control signal EM(n), and the fourth transistor T4 and the fifth transistor T5 are in an on state, and the sixth transistor T6 is in an off state.

[0071] The second transistor T2 is in an on state based on the voltage RDATA(n-1), so that the second transistor T2 can pass a current IELA based on the gate-source voltage Vgs and the source-drain voltage Vds corresponding to the voltage RDATA(n-1).

[0072] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and a current IELA flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows to the light-emitting element OLED, and the light-emitting element OLED emits light.

[0073] Next, referring to FIG. 6, a method of driving the pixel 180 (pixel circuit 181) in the period between the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame and the reset period PRS of the current frame will be described. The period between the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame and the reset period PRS of the current frame overlaps with a part of one horizontal period N-2ndHP and a part of one horizontal period N-1stHP. During this period, the light emission control signal EM(n) is supplied from low (LO) to high (HI), the fifth transistor T5 and the fourth transistor T4 are in the off state, and the sixth transistor T6 is in the on state. In addition, the scanning signal G(n-1) is supplied from low (LO) to high (HI), and the seventh transistor T7 is in the on state. The first transistor T1 and the third transistor T3 remain in the off state.

[0074] Based on the sixth transistor T6 being turned on, an initialization voltage VINI is supplied to the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are initialized. In addition, the fourth transistor T4 and the fifth transistor T5 are in an off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is a current (almost 0) according to the potential difference (voltage VINI-reference voltage VSSEL) between the voltage of the second electrode 684 and the voltage of the first electrode 682 of the light-emitting element OLED, and the light-emitting element OLED does not emit light (does not emit light).

[0075] Next, a method for driving the pixel 180 (pixel circuit 181) in the reset period PRS of the frame will be described with reference to Fig. 6 and Fig. 8. The reset period PRS is a period in which a reset voltage VSH and an initialization voltage VINI are written to the pixel 180 (pixel circuit 181) to initialize the pixel 180 (pixel circuit 181). The reset period PRS of the frame is a period that overlaps with a part of one horizontal period N-1stHP.

[0076] During the reset period PRS, the scanning signal G(n) is changed from low (LO) to high (HI), the third transistor T3 is turned on, the sixth transistor T6 and the seventh transistor T7 remain on, and the first transistor T1, the fourth transistor T4, and the fifth transistor T5 remain off.

[0077] Based on the seventh transistor T7 and the third transistor T3 being in the ON state, a reset voltage VSH is supplied to the first node N1, the second node N2, the electrodes electrically connected to the first node N1, the electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS. As a result, the first node N1, the second node N2, the electrodes electrically connected to the first node N1, the electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS are reset. In addition, since the sixth transistor T6 remains in the ON state, the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are maintained at the initialization voltage VINI. As a result, a voltage of the reset voltage VSH-initialization voltage VINI (VSH-VINI) is applied to the capacitance element CS.

[0078] Moreover, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. As described above, the current IINI flowing through the light-emitting element OLED is approximately 0, and the light-emitting element OLED does not emit light (does not emit light).

[0079] 8 is in an on state, but when the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 (the potential difference between the gate electrode 622 and the first node N1) becomes equal to the threshold voltage Vth of the second transistor T2, the second transistor T2 is turned off. As a result, the difference (VSH-Vth) between the reset voltage VSH and the threshold voltage Vth is held in the first node N1 and each electrode electrically connected to the first node N1, and the reset voltage VSH is held in the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS.

[0080] Next, a method for driving the pixel 180 (pixel circuit 181) in the period between the reset period PRS and the sampling period PWR of the frame will be described with reference to Figures 6 and 9. The period between the reset period PRS and the sampling period PWR of the frame overlaps with a part of one horizontal period N-1stHP and a part of one horizontal period NthHP.

[0081] In the period between the reset period PRS and the sampling period PWR of the frame, the scanning signal G(n-1) is supplied from high (HI) to low (LO), and the seventh transistor T7 is in the off state. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0082] During the period between the reset period PRS and the sampling period PWR of the frame, the reset voltage VSH is held at the second node N2, the electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS. Since the sixth transistor T6 remains in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (does not emit light).

[0083] In the period between the reset period PRS and the sampling period PWR of this frame, an ON signal is supplied to the selection signal MUXR, and thus the voltage RDATA(n) is selected. Therefore, the image data signal SL(m+1) contains the voltage RDATA(n). In addition, the image data signal SL(m+1) containing the voltage RDATA(n) is supplied to the image data signal line 321. The image data signal line 321 holds the voltage RDATA(n) based on the selection signal MUXR being supplied with an OFF signal.

[0084] Next, a method of driving the pixel 180 (pixel circuit 181) in the sampling period PWR of the frame will be described with reference to Fig. 6 and Fig. 10. The sampling period PWR is a period during which a voltage corresponding to image data to be displayed by the pixel 180 (pixel circuit 181) is written to the pixel 180 (pixel circuit 181). The sampling period PWR of the frame overlaps with a part of one horizontal period NthHP.

[0085] During the sampling period PWR of the frame, the scanning signal G(n+1) is changed from low (LO) to high (HI), the first transistor T1 is turned on, the third transistor T3 and the sixth transistor T6 remain on, and the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain off.

[0086] Based on the first transistor T1 being turned on, the voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. When the voltage RDATA(n) is supplied to the first node N1, the voltage between the gate and source of the second transistor T2 also changes, and the second transistor T2 is turned on. As a result, the voltages of the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS drop from the voltage VSH to the voltage RDATA(n)+threshold voltage Vth (RDATA(n)+Vth). Thus, the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes the same as the threshold voltage Vth of the second transistor T2, and the voltage drop (discharge) of the second node N2 and the like ends, and the second transistor T2 is turned off.

[0087] In this embodiment, the capacitance of the capacitive element CS of the pixel 180A arranged in the region 22A is smaller than the capacitance of the capacitive element CS of the pixel 180B arranged in the region 22B. If the capacitance of the capacitive element CS is small, the discharge during the sampling period PWR proceeds quickly. Therefore, the voltage held in the capacitive element CS of the pixel 180A arranged in the region 22A is smaller than the voltage held in the capacitive element CS of the pixel 180B arranged in the region 22B.

[0088] Furthermore, since the sixth transistor T6 remains in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Furthermore, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (does not emit light).

[0089] Although detailed illustration is omitted, at this time, since the first transistor T1 remains in the on state, the voltage of the first node N1 and each electrode electrically connected to the first node N1 is fixed to the voltage RDATA(n). In addition, a charge equivalent to the threshold voltage Vth is held between the gate electrode 622 and the first electrode 624 of the second transistor T2. Therefore, the sampling period PWR of the frame is a period during which a voltage corresponding to the image data displayed by the pixel 180 (pixel circuit 181) is written to the pixel 180 (pixel circuit 181), and is also a period (threshold correction period) during which a charge equivalent to the threshold voltage Vth is held between the gate electrode 622 and the first electrode 624 of the second transistor T2 and the threshold of the second transistor T2 is corrected.

[0090] Next, a method for driving the pixel 180 (pixel circuit 181) after the sampling period PWR of the frame will be described with reference to Figures 6 and 11. The period after the sampling period PWR of the frame is a period overlapping a part of one horizontal period NthHP and one horizontal period N+1stHP.

[0091] In the period following the sampling period PWR of the frame, the scanning signal G(n) is supplied from high (HI) to low (LO), and the third transistor T3 is in the off state. In addition, the first transistor T1 and the sixth transistor T6 remain in the on state, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state. A high (HI) is supplied to the scanning signal G(n+1), and the first transistor T1 is in the on state. The voltages of the first electrode 614 and the second electrode 616 of the first transistor T1 are both the voltage RDATA(n). That is, the voltages of the first electrode 614 and the second electrode 616 of the first transistor T1 are the same. Therefore, no current flows through the first transistor T1.

[0092] Since the second transistor T2 and the seventh transistor T7 are in the off state, the voltage RDATA(n)+threshold voltage Vth (RDATA(n)+Vth) is held at the second node N2, the electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS. Furthermore, since the third transistor T3 is in the off state, the voltages of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS are reduced (punched through) to the voltage RDATA(n)+threshold voltage Vth-voltage α (RDATA(n)+Vth-α) due to capacitive coupling between the gate and drain (gate electrode 632 and first electrode 634) of the third transistor T3. Here, for example, the voltage α is a positive value and is a voltage value that changes according to the capacitance of the capacitance element CS. For example, when the capacitance of the capacitive element CS becomes high (large), the voltage α becomes low (small), and when the capacitance of the capacitive element CS becomes low (small), the voltage α becomes high (large). In this embodiment, the capacitance of the capacitive element CS of the pixel 180A arranged in the region 22A is smaller than the capacitance of the capacitive element CS of the pixel 180B arranged in the region 22B. When the capacitance of the capacitive element CS is small, the penetration of the voltage α during the sampling period PWR becomes large. Therefore, the voltage held in the capacitive element CS of the pixel 180A arranged in the region 22A becomes smaller than the voltage held in the capacitive element CS of the pixel 180B arranged in the region 22B.

[0093] Furthermore, since the sixth transistor T6 is in an on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the capacitance element CS is held at a voltage RDATA(n)+threshold voltage Vth-voltage α-initialization voltage VINI (RDATA(n)+Vth-α-VINI). As in the sampling period PWR of the frame, a current IINI also flows from the initialization voltage line VM to the reference voltage line PVSS during the period following the sampling period PWR of the frame. The current IINI flowing through the light-emitting element OLED is approximately 0, and the light-emitting element OLED does not emit light (does not emit light).

[0094] As shown in FIG. 6, the scanning signal G(n) is supplied from high (HI) to low (LO) and the third transistor T3 is turned off, and then the scanning signal G(n+1) is supplied from high (HI) to low (LO) and the first transistor T1 is turned off.

[0095] At this time, since the first transistor T1 is in an off state, the voltage RDATA(n) is held in the first node N1 and each electrode electrically connected to the first node N1. Also, since the second transistor T2, the third transistor T3, and the seventh transistor T7 are in an off state, the voltage RDATA(n)+threshold voltage Vth-voltage α(RDATA(n)+Vth-α) is held in the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitance element CS. Also, since the sixth transistor T6 is in an on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitance element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Therefore, a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS following the period following the sampling period PWR of the frame. The current IINI flowing through the light-emitting element OLED is approximately 0, and the light-emitting element OLED does not emit light (does not emit light).

[0096] Next, a method for driving the pixel 180 (pixel circuit 181) in the light emission period PEM of the frame will be described with reference to Fig. 6, Fig. 11, and Fig. 12. The light emission period PEM of the frame is a period during which the pixel 180 (pixel circuit 181) emits light in response to the voltage RDATA(n). The light emission period PEM of the frame overlaps with one horizontal period N+2ndHP.

[0097] 6 and 12, the scanning signal G(n-1), the scanning signal G(n), and the scanning signal G(n+1) are supplied with a low (LO) signal, and the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an off state. Also, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with a low (LO) signal from the light emission control signal EM(n), and the fourth transistor T4 and the fifth transistor T5 are in an on state, and the sixth transistor T6 is in an off state.

[0098] As shown in FIG. 11, the voltage held by the second electrode 656 of the fifth transistor T5 is RDATA(n), and the voltage held by the first electrode 654 of the fifth transistor T5 is the initialization voltage VINI.

[0099] When the fifth transistor T5 shown in FIG. 6 and FIG. 12 is turned on from a state in which the voltage of the second electrode 656 and the voltage of the first electrode 654 of the fifth transistor T5 are the voltage RDATA(n) (RDATA(n)) and the initialization voltage VINI (VINI), a current flows from the second electrode 656 to the first electrode 654 of the fifth transistor T5, redistribution of charge occurs, and the voltage of the second electrode 656 and the voltage of the first electrode 654 become the initialization voltage VINI (VINI). At this time, the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS become the voltage RDATA(n) + threshold voltage Vth - voltage α - initialization voltage VINI (RDATA(n) + Vth - α - VINI). Depending on the value of the voltage RDATA(n), the second transistor T2 takes an on state or an off state.

[0100] Also, for example, as shown in Figures 6 and 12, based on the fifth transistor T5 being in an on state, a current flows from the second electrode 656 of the fifth transistor T5 to the first electrode 654, and the voltage of the first electrode 654 and each electrode electrically connected to the first electrode 654 (the second electrode 684 of the light-emitting element OLED, the second electrode 666 of the sixth transistor T6, and the first electrode 692 of the capacitance element CS) rises from voltage VINI to voltage VINI + voltage β, and the voltage held by the first node N1 (the second electrode 656 of the fifth transistor T5 and the first electrode 624 of the second transistor T2) drops from RDATA(n). As the first electrode 692 of the capacitance element CS rises to voltage VINI+voltage β, the voltages of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS rise from voltage RDATA(n)+threshold voltage Vth-voltage α(RDATA(n)+Vth-α) to voltage RDATA(n)+threshold voltage Vth-voltage α+voltage β(RDATA(n)+Vth-α+β) due to capacitive coupling. As a result, the gate-source voltage between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes higher than the threshold voltage Vth of the second transistor T2, so that the second transistor T2 is turned on.

[0101] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and a current IELA flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows to the light-emitting element OLED, and the light-emitting element OLED emits light. The current IELA is, for example, a current based on the voltage RDATA(n) written to the second transistor T2+threshold voltage Vth-voltage α+voltage β (RDATA(n)+Vth-α+β). This voltage is applied between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, and thus a current in which the influence of the variation in the threshold voltage Vth of the second transistor T2 between each pixel 180 (pixel circuit 181) is offset flows to the light-emitting element OLED, and the in-plane uniformity can be improved. Here, for example, the voltage β is a positive value and is a voltage value that changes according to the voltage RDATA(n). For example, when the voltage RDATA(n) becomes higher (larger), the voltage β becomes higher (larger), and when the voltage RDATA(n) becomes lower (smaller), the voltage β becomes lower (smaller). For example, the voltage β is determined so that the value of the current that the second transistor T2 passes according to the gate electrode 622, the first electrode 624, and the second electrode 626 is the same as the value of the current that the light-emitting element OLED passes.

[0102] On the other hand, in this embodiment, the capacitance of the capacitance element CS of the pixel 180A arranged in the region 22A is smaller than the capacitance of the capacitance element CS of the pixel 180B arranged in the region 22B. If the capacitance of the capacitance element CS is small, the discharge in the sampling period PWR proceeds quickly, and the penetration of the voltage α becomes large. Therefore, the voltage held in the capacitance element CS of the pixel 180A arranged in the region 22A is smaller than the voltage held in the capacitance element CS of the pixel 180B arranged in the region 22B. By applying this voltage between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows in the light-emitting element OLED of the pixel 180A arranged in the region 22A than in the light-emitting element OLED of the pixel 180B arranged in the region 22B. In this way, the phenomenon that the outermost periphery of the display area emits light more brightly at low luminance is eliminated, and the in-plane uniformity can be further improved.

[0103] The self-luminous display device 10 is driven as described above, image data corresponding to each pixel 180 (pixel circuit 181) is supplied to each pixel 180 (pixel circuit 181), a current according to the image data is supplied to the light-emitting element OLED included in each pixel 180 (pixel circuit 181), and each light-emitting element OLED emits light with a luminance according to the image data. As a result, the self-luminous display device 10 can display a desired image.

[0104] Next, referring to FIG. 5B, FIG. 13, and FIG. 14, an example of a driving method in which the pixel 180 (pixel circuit 181) displays black based on the voltage RDATAB included in the data signal VDATA input during one horizontal period NthHP will be described. As described above, in the low-frequency driving, driving other than during the black period PBWR is the same as in the high-frequency driving. Therefore, the driving of the pixel 180 (pixel circuit 181) during the black period PBWR will mainly be described here. Descriptions of configurations that are the same as or similar to those in FIG. 1 to FIG. 5A and FIG. 6 to FIG. 12 will be omitted here. The horizontal axis of the timing chart indicates time (TIME).

[0105] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m+1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is, for example, analog data including a voltage VDL for displaying black. The voltage VDM is a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, the voltage VDL is selected using the selection signal MUXR and supplied to the image data signal line, the voltage VDL is selected using the selection signal MUXG and supplied to the image data signal line, and the voltage VDL is selected using the selection signal MUXB and supplied to the image data signal line. In a period in which data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0106] The driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame is the same as the driving method described with reference to Figures 1 to 5A and 6 to 12. Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED in the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame are between the voltage VDL and the voltage VDH.

[0107] Next, a method for driving the pixel 180 (pixel circuit 181) in the black period PBWR executed following the light emission period PEM of the frame (K-1stFRAME) immediately before the current frame will be described. The black period PBWR of the current frame is a period overlapping with a part of one horizontal period N-2ndHP, one horizontal period N-1stHP, one horizontal period NthHP, one horizontal period N+1stHP, and one horizontal period N+2ndHP.

[0108] The scanning signals G(n-1), G(n), and G(n+1) are supplied with a low (LO) signal, and the light emission control signal EM(n) is supplied with a high (HI) signal. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in an off state, and the sixth transistor T6 is in an on state.

[0109] Since the sixth transistor T6 is in an on state, the voltage RDATAB is supplied to the first electrode 692 of the capacitance element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Therefore, a current IRB flows from the initialization voltage line VM to the reference voltage line PVSS. The current IRB flowing through the light-emitting element OLED is a current for displaying black based on the voltage RDATAB, and the light-emitting element OLED hardly emits light (does not emit light). Therefore, the pixel 180 displays black.

[0110] The driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the current frame (KthFRAME) is the same as the driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the frame immediately preceding this frame (K-1stFRAME). Therefore, the explanation here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light-emitting element OLED in the light emission period PEM of the current frame (KthFRAME) are between the voltage VDL and the voltage VDH.

[0111] In the black period PBWR of the self-luminous display device 10, the voltage RDATAB is supplied from the initialization voltage line VM to the second electrode 684 of the light-emitting element OLED, thereby allowing the self-luminous display device 10 to display black.

[0112] <2. Second embodiment> A self-luminous display device according to the second embodiment will be described with reference to FIG. 15. The self-luminous display device according to the second embodiment has the same configuration as the self-luminous display device 10 described in the first embodiment, except that the configuration of the pixel circuit is different. Descriptions of the same or similar configuration as the self-luminous display device described in the first embodiment and the same or similar configuration as in FIGS. 1 to 14 will be omitted here. In this embodiment, the capacitance of pixel 180A is different from the capacitance of pixel 180B. The capacitance connected to the gate electrode 622 of the second transistor T2 of pixel 180A is different from the capacitance connected to the gate electrode 622 of the second transistor T2 of pixel 180B.

[0113] <2-1. Configuration of pixel 180> An overview of the pixel circuit 182 will be described with reference to Fig. 15. Fig. 15 is a circuit diagram showing the configuration of the pixel circuit 182. Fig. 15 shows the configuration of the pixel circuit 182 of the pixel 180 shown in Fig. 2 as an example. The configurations of the pixel 180 and the pixel circuit 182 are not limited to the configuration shown in Fig. 15. Descriptions of configurations that are the same as or similar to those in Figs. 1 to 14 will be omitted here.

[0114] The pixel circuit 182 is a circuit for driving the pixel 180, similar to the pixel circuit 181, and has the same configuration and function as the pixel circuit 181, except for the third transistor T3. In the description of the pixel circuit 182, differences from the pixel circuit 181 will be mainly described.

[0115] 15, the pixel circuit 182 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitance element CS, and a light-emitting element OLED, similar to the pixel circuit 181. In the pixel circuit 182, similar to the pixel circuit 181, the fourth transistor T4 and the fifth transistor T5 are p-channel type field effect transistors.

[0116] In this embodiment, the capacitance of the capacitance element CS of the pixel 180A arranged in the region 22A is approximately the same as the capacitance of the capacitance element CS of the pixel 180B arranged in the region 22B. On the other hand, the capacitance between the gate and drain of the third transistor T3 of the pixel 180A arranged in the region 22A is larger than the capacitance between the gate and drain of the third transistor T3 of the pixel 180B arranged in the region 22B. The capacitance between the gate and drain of the third transistor T3 of the pixel 180A is preferably 1.1 times or more the capacitance between the gate and drain of the third transistor T3 of the pixel 180B. For example, the electrode layout of the third transistor T3 of the pixel 180A and the third transistor T3 of the pixel 180B may be different. For example, the capacitance Cgd of the pixel 180A may be adjusted by appropriately adjusting the area of ​​the area where the gate electrode 632 or the wiring connected to the gate electrode 632 of the third transistor T3 overlaps with the first electrode 634 or the wiring connected to the first electrode 634. The capacitance Cgd of the pixel 180B may also be adjusted by appropriately adjusting the area of ​​an overlapping region between the gate electrode 632 of the third transistor T3 or a wiring connected to the gate electrode 632 and the first electrode 634 or a wiring connected to the first electrode 634. In this case, the capacitance Cgd of the pixel 180A may be larger than the capacitance Cgd of the pixel 180B.

[0117] The region 22A may include pixels 180A in multiple rows and multiple columns. In this case, the capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged at the outermost periphery may be different from the capacitance between the gate and drain of the transistor T3 of the pixel 180B in the region 22B and the pixel 180A adjacent thereto. The capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged at the outermost periphery may be larger than the capacitance between the gate and drain of the transistor T3 of the pixel 180B in the region 22B and the pixel 180A adjacent thereto. In the region 22A, the capacitance between the gate and drain of the transistor T3 may have a negative gradient from the pixel 180A arranged at the outermost periphery to the pixel 180B in the region 22B and the pixel 180A adjacent thereto.

[0118] In this embodiment, the capacitance between the gate and drain of the transistor T3 of the pixel 180A arranged in the region 22A is larger than the capacitance between the gate and drain of the transistor T3 of the pixel 180B arranged in the region 22B. If the capacitance between the gate and drain of the transistor T3 is large, the penetration of the voltage α during the sampling period PWR becomes large. Therefore, the voltage held in the capacitance element CS of the pixel 180A arranged in the region 22A becomes smaller than the voltage held in the capacitance element CS of the pixel 180B arranged in the region 22B. By applying this voltage between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2 during the light emission period PEM, a smaller current flows in the light-emitting element OLED of the pixel 180A arranged in the region 22A than in the light-emitting element OLED of the pixel 180B arranged in the region 22B. In this way, the phenomenon that the outermost periphery of the display area emits light more brightly at low luminance is eliminated, and the in-plane uniformity can be further improved.

[0119] <3. Third embodiment> A self-luminous display device according to the third embodiment will be described with reference to Fig. 16. In a self-luminous display device 11 according to the third embodiment, the capacitances of the pixels 180 are substantially the same, and instead the capacitances connected to the image data signal lines 321 at the left and right ends are different from the others. Other than this, the configuration is the same as that of the self-luminous display device 10 described in the first embodiment. Descriptions of configurations that are the same as or similar to the configuration of the self-luminous display device described in the first embodiment and configurations that are the same as or similar to those in Figs. 1 to 15 will be omitted here.

[0120] <3-1. Overview of the self-luminous display device 11> An overview of a self-luminous display device 11 according to the third embodiment will be described with reference to Fig. 16. Fig. 16 is a schematic diagram showing a configuration of the self-luminous display device 11 according to the third embodiment. The configuration of the self-luminous display device 11 shown in Fig. 16 is one example, and the configuration of the self-luminous display device 11 is not limited to the configuration shown in Fig. 16.

[0121] 16, the self-luminous display device 11 includes a plurality of pixels 180, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130. The source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 are each connected to a terminal unit 150 using a connection wiring 341.

[0122] In the display region 22, a plurality of pixels 180 are arranged in a matrix. The display region 22 includes a region 22C and a region 22D. The region 22C is adjacent to the region 22D in the second direction D2 (row direction) and is arranged to face both left and right ends of the display region 22. However, the present invention is not limited to this, and the region 22C may be adjacent to the region 22D in the second direction D2 (row direction) and arranged only on one side of the display region 22, left or right. The region 22D is arranged to be sandwiched between the regions 22C in the second direction D2 (row direction). The region 22C may include one column of pixels 180C arranged in the first direction D1 (column direction) on the outer edge of the display region 22, or may include multiple columns of pixels 180C. The multiple pixels 180C arranged in the first direction D1 (column direction) of the region 22C share one image data signal line 321C. In this embodiment, since the capacitance of pixel 180C is the same as the capacitance of pixel 180D, pixel 180C and pixel 180D will be referred to as pixel 180 when there is no need to distinguish between them.

[0123] The source driver circuit 110 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 110 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1. The source driver circuit 110 includes a plurality of selection circuits 112 as in the first embodiment, and supplies an image data signal SL(m+1) including a data signal VDATA selected by an on signal supplied to the selection signal and supplied to an input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321.

[0124] In this embodiment, the capacitance of the capacitive element CS of the pixel 180C arranged in the region 22C is approximately the same as the capacitance of the capacitive element CS of the pixel 180D arranged in the region 22D. On the other hand, the capacitance of the image data signal line 321C connected to the pixel 180C arranged in the region 22C is larger than the capacitance of the image data signal line 321D connected to the pixel 180D arranged in the region 22D. It is preferable that the capacitance of the image data signal line 321C connected to the pixel 180C is 1.2 times or more the capacitance of the image data signal line 321D connected to the pixel 180D. For example, the image data signal line 321C may have a dummy capacitance connected to the ground (GND). Also, the image data signal line 321D may have a dummy capacitance connected to the ground (GND). In this case, the capacitance of the dummy capacitance of the pixel 180C may be larger than the capacitance of the dummy capacitance of the pixel 180D.

[0125] The left and right regions 22C may each include a plurality of columns of pixels 180C. In this case, the capacitance of the image data signal line 321C connected to the pixel 180C arranged at the extreme end may be different from the capacitance of the image data signal line 321C connected to the pixel 180C adjacent to the pixel 180D in the region 22D. The capacitance of the image data signal line 321C connected to the pixel 180C arranged at the extreme end may be larger than the capacitance of the image data signal line 321C connected to the pixel 180D in the region 22D and the pixel 180C adjacent to the pixel 180D. In the region 22C, there may be a negative gradient in capacitance from the image data signal line 321C connected to the pixel 180C arranged at the extreme end to the image data signal line 321C connected to the pixel 180C adjacent to the pixel 180D in the region 22D.

[0126] In this embodiment, the capacitance of the image data signal line 321C connected to the pixel 180C arranged in the region 22C is larger than the capacitance of the image data signal line 321D connected to the pixel 180D arranged in the region 22D. If the capacitance of the image data signal line 321C is large, the increase in potential due to the flow of the charge of the capacitive element CS into the image data signal line 321C during the sampling period PWR can be suppressed. Therefore, the voltage held in the capacitive element CS of the pixel 180C arranged in the region 22C sharing the image data signal line 321C is smaller than the voltage held in the capacitive element CS of the pixel 180D arranged in the region 22D sharing the image data signal line 321D. When this voltage is applied between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180C arranged in the region 22C than through the light-emitting element OLED of the pixel 180D arranged in the region 22D. In this way, the phenomenon in which the outermost edges of the display area emit light brighter at low luminance can be eliminated, and the in-plane uniformity can be further improved.

[0127] <4. Fourth embodiment> A self-luminous display device according to the fourth embodiment will be described with reference to FIG. 17. In the self-luminous display device 11 according to the fourth embodiment, the capacitances of the pixels 180 are substantially the same, and the capacitances connected to the image data signal lines 321 at the left and right ends are different from the others, except that the configuration is the same as that of the self-luminous display device 10 described in the first embodiment. In the self-luminous display device 11 according to the fourth embodiment, the capacitances connected to the image data signal lines 321 are substantially the same, and the configuration of the source driver circuit is different, except that the configuration is the same as that of the self-luminous display device 11 described in the third embodiment. The configurations that are the same as or similar to those of the self-luminous display devices described in the first and third embodiments and the configurations that are the same as or similar to those in FIG. 1 to FIG. 16 will not be described here.

[0128] <4-1. Overview of the self-luminous display device 11> An overview of a self-luminous display device 11 according to the fourth embodiment will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing a configuration of a source driver circuit 111 according to the fourth embodiment. The configuration of the source driver circuit 111 shown in Fig. 17 is an example, and the configuration of the source driver circuit 111 is not limited to the configuration shown in Fig. 17.

[0129] 16, the self-luminous display device 11 includes a plurality of pixels 180, a source driver circuit 111, a gate driver circuit 120, and a light emission control circuit 130. The source driver circuit 111, the gate driver circuit 120, and the light emission control circuit 130 are each connected to a terminal unit 150 using a connection wiring 341.

[0130] In the display region 22, a plurality of pixels 180 are arranged in a matrix. The display region 22 includes a region 22C and a region 22D. The region 22C is adjacent to the region 22D in the second direction D2 (row direction) and is arranged to face both left and right ends of the display region 22. However, the present invention is not limited to this, and the region 22C may be adjacent to the region 22D in the second direction D2 (row direction) and arranged only on one side of the display region 22, left or right. The region 22D is arranged to be sandwiched between the regions 22C in the second direction D2 (row direction). The region 22C may include one column of pixels 180C arranged in the first direction D1 (column direction) on the outer edge of the display region 22, or may include multiple columns of pixels 180C. The multiple pixels 180C arranged in the first direction D1 (column direction) of the region 22C share one image data signal line 321C. In this embodiment, since the capacitance of pixel 180C is the same as the capacitance of pixel 180D, pixel 180C and pixel 180D will be referred to as pixel 180 when there is no need to distinguish between them.

[0131] As in the self-luminous display device 11 according to the third embodiment, the source driver circuit 111 is provided at a position adjacent to the display region 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 111 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1. As in the first embodiment, the source driver circuit 111 includes a plurality of selection circuits 112, and supplies an image data signal SL(m+1) including a data signal VDATA selected by an on signal supplied to the selection signal and supplied to the input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. A plurality of pixels 180C arranged in the first direction D1 (column direction) of the region 22C share one selection circuit 112C.

[0132] In this embodiment, the capacitance of the capacitive element CS of the pixel 180C arranged in the region 22C is approximately the same as the capacitance of the capacitive element CS of the pixel 180D arranged in the region 22D. The capacitance of the image data signal line 321C connected to the pixel 180C arranged in the region 22C is approximately the same as the capacitance of the image data signal line 321D connected to the pixel 180D arranged in the region 22D. On the other hand, the capacitance of the selection circuit 112C connected to the image data signal line 321C is larger than the capacitance of the selection circuit 112D connected to the image data signal line 321D. It is preferable that the capacitance of the selection circuit 112C connected to the image data signal line 321C is 1.1 times or more the capacitance of the selection circuit 112D connected to the image data signal line 321D. For example, the electrode layout of the selection circuit 112C connected to the image data signal line 321C and the selection circuit 112D connected to the image data signal line 321D may be different. For example, the capacitance Cgd(c) may be adjusted by appropriately adjusting the area of ​​an overlapping region between the gate electrode or the wiring connected to the gate electrode of the selection circuit 112C and the drain electrode or the wiring connected to the drain electrode. The capacitance Cgd(d) may be adjusted by appropriately adjusting the area of ​​an overlapping region between the gate electrode or the wiring connected to the gate electrode of the selection circuit 112D and the drain electrode or the wiring connected to the drain electrode. In this case, the capacitance Cgd(c) of the selection circuit 112C may be larger than the capacitance Cgd(d) of the selection circuit 112D.

[0133] As shown in the example of FIG. 17, the left and right regions 22C may each include a plurality of columns of pixels 180C. In this embodiment, the capacitance of the selection circuit 112C connected to the three columns of image data signal lines 321C of R, G, and B is uniformly increased by one unit of the data signal VDATA1 supplied from the IC chip 170. However, this is not limited to this, and the capacitance of the selection circuit 112C connected to the pixel 180C arranged at the end via the image data signal line 321C may be different from the capacitance of the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C. The capacitance of the selection circuit 112C connected to the pixel 180C arranged at the end via the image data signal line 321C may be larger than the capacitance of the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C. A negative gradient may be present in the capacitance from the selection circuit 112C connected to the pixel 180C arranged at the very end in the region 22C via the image data signal line 321C to the selection circuit 112C connected to the pixel 180C adjacent to the pixel 180D in the region 22D via the image data signal line 321C. On the other hand, only the capacitance of the selection circuit 112C connected to the image data signal lines 321C (SL(1) and SL(m+3)) in one column on both the left and right ends may be increased.

[0134] In this embodiment, the capacitance of the selection circuit 112C connected to the pixel 180C arranged in the region 22C via the image data signal line 321C is larger than the capacitance of the selection circuit 112D connected to the pixel 180D arranged in the region 22D via the image data signal line 321D. If the capacitance of the selection circuit 112C is large, the potential drop of the image data signal line 321C due to the capacitive coupling between the gate and drain when the selection circuit 112C is turned off becomes large, and the voltage RDATA(n) applied to the pixel 180C during the sampling period PWR becomes small. Therefore, the voltage held in the capacitance element CS of the pixel 180C arranged in the region 22C sharing the selection circuit 112C becomes smaller than the voltage held in the capacitance element CS of the pixel 180D arranged in the region 22D sharing the selection circuit 112D. When this voltage is applied between the gate and source of the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows through the light-emitting element OLED of the pixel 180C arranged in the region 22C than through the light-emitting element OLED of the pixel 180D arranged in the region 22D. In this way, the phenomenon in which the outermost edges of the display region emit light more brightly at low luminance is eliminated, and the in-plane uniformity can be further improved.

[0135] <5. Fifth Embodiment> A self-luminous display device according to a fifth embodiment will be described with reference to Fig. 18 and Fig. 19. In a self-luminous display device 12 according to the fifth embodiment, the capacitances of the pixels 180 are substantially the same, and instead the method of driving the upper and lower end pixels 180 (pixel circuits) by scanning signals is different from the others, and other than this, the configuration is the same as that of the self-luminous display device 10 described in the first embodiment. Descriptions of configurations that are the same as or similar to the configuration of the self-luminous display device described in the first embodiment and configurations that are the same as or similar to those in Figs. 1 to 17 will be omitted here.

[0136] <5-1. Overview of the self-luminous display device 12> An overview of the self-luminous display device 12 according to the fifth embodiment will be described with reference to Fig. 18. Fig. 18 is a schematic diagram showing the configuration of the self-luminous display device 12 according to the fifth embodiment. The configuration of the self-luminous display device 12 shown in Fig. 18 is one example, and the configuration of the self-luminous display device 12 is not limited to the configuration shown in Fig. 18.

[0137] 18, the self-luminous display device 12 includes a plurality of pixels 180, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130. The source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 are each connected to a terminal unit 150 using a connection wiring 341.

[0138] In the display region 22, a plurality of pixels 180 are arranged in a matrix. The display region 22 includes a region 22E and a region 22F. The region 22E is adjacent to the region 22F in the first direction D1 (column direction) and is arranged to face both upper and lower ends of the display region 22. The region 22F is arranged to be sandwiched between the regions 22E in the first direction D1 (column direction). The region 22E may include one row of pixels 180E arranged in the second direction D2 (row direction) on the outer edge of the display region 22, or may include multiple rows of pixels 180E. In this embodiment, the capacitance of the pixel 180E is the same as the capacitance of the pixel 180F, so that the pixel 180E and the pixel 180F are referred to as the pixel 180 when they are not distinguished from each other.

[0139] As in the self-luminous display device 10 according to the first embodiment, the gate driver circuit 120 is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). Scanning signal lines 329, 330, 331, and 332 extend from the gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. As in the first embodiment, the gate driver circuit 120 includes a plurality of shift registers (e.g., shift registers 121, 122, and 123), and sequentially supplies scanning signals (e.g., scanning signal G(n-1), scanning signal G(n), scanning signal G(n+1)) having different timings to the pixels 180 electrically connected to the scanning signal lines 329, 330, 331, and 332, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170.

[0140] <5-2. Driving method of the self-luminous display device 12> A method of driving the self-luminous display device 12 according to the fifth embodiment will be described with reference to FIG. 19. FIG. 19 is a schematic diagram showing a timing chart of the self-luminous display device 12 according to the fifth embodiment. In this embodiment, the sampling period PWR(1) of the pixel 180E is different from the sampling period PWR(2) of the pixel 180F. The sampling period PWR(1) of the pixel 180E is longer than the sampling period PWR(2) of the pixel 180F. That is, the time during which the scanning signal G(2) and the scanning signal G(3) supplied to the pixel 180E overlap may be longer than the time during which the scanning signal G(3) and the scanning signal G(4) supplied to the pixel 180F overlap. For example, the timing at which the scanning signal G(2) turns off may be delayed, as long as it is before the timing at which the scanning signal G(4) turns on. The pulse width during which the scanning signal G(2) is on may be longer than the other scanning signals G. The timing at which the scanning signal G(3) turns on may be early, as long as it is after the timing at which the scanning signal G(1) turns off. The pulse width during which the scanning signal G(3) is on may be longer than the other scanning signals G. Here, the driving method for the pixel 180E arranged in the uppermost region 22E has been described. The pixel 180E arranged in the lowermost region 22E can also be driven by a similar driving method.

[0141] As shown in FIG. 18, in this embodiment, the upper and lower end regions 22E each include one row of pixels 180E. However, without being limited thereto, the upper and lower end regions 22E may each include multiple rows of pixels 180E. In this case, the sampling period PWR of the pixel 180E arranged at the edge may be different from the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. The sampling period PWR of the pixel 180E arranged at the edge may be longer than the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. In the region 22E, there may be a negative gradient from the sampling period PWR of the pixel 180E arranged at the edge to the sampling period PWR of the pixel 180E adjacent to the pixel 180F in the region 22F.

[0142] In this embodiment, the sampling period PWR of the pixel 180E arranged in the region 22E is longer than the sampling period PWR of the pixel 180F arranged in the region 22F. If the sampling period PWR is long, the discharge in the sampling period PWR proceeds quickly. Therefore, the voltage held in the capacitance element CS of the pixel 180E arranged in the region 22E is smaller than the voltage held in the capacitance element CS of the pixel 180F arranged in the region 22F. This voltage is applied between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, so that a smaller current flows in the light-emitting element OLED of the pixel 180E arranged in the region 22E than in the light-emitting element OLED of the pixel 180F arranged in the region 22F. In this way, the phenomenon that the outermost edge of the display region emits light more brightly at low luminance is eliminated, and the in-plane uniformity can be further improved. In addition, the driving method of the self-luminous display device according to this embodiment can be applied to the self-luminous display device according to the third or fourth embodiment. By applying this to these self-luminous display devices, the phenomenon in which the outermost periphery of the display area emits light more brightly can be eliminated, and the in-plane uniformity can be further improved.

[0143] <6. Sixth Embodiment> A self-luminous display device according to the sixth embodiment will be described with reference to FIG. 20. In the self-luminous display device 12 according to the sixth embodiment, the capacitance of the pixels 180 is approximately the same, and the driving method of the pixels 180 (pixel circuits) at the upper and lower ends by the scanning signal is different from the others, except that the configuration is the same as that of the self-luminous display device 10 described in the first embodiment. In the self-luminous display device 12 according to the sixth embodiment, the sampling period PWR is approximately the same, and the driving method of the pixels 180 (pixel circuits) is the same as that of the fifth embodiment, except that the driving voltage of the pixels 180 (pixel circuits) is different instead. The description here of the configurations that are the same as or similar to the configurations of the self-luminous display devices described in the first and fifth embodiments and the configurations that are the same as or similar to those in FIG. 1 to FIG. 19 will be omitted.

[0144] <6-1. Driving method of the self-luminous display device 12> A method of driving the self-luminous display device 12 according to the sixth embodiment will be described with reference to FIG. 20. FIG. 20 is a schematic diagram showing a timing chart of the self-luminous display device 12 according to the sixth embodiment. In this embodiment, the High voltage of the sampling period PWR(1) of the pixel 180E is different from the High voltage of the sampling period PWR(2) of the pixel 180F. The High voltage of the sampling period PWR(1) of the pixel 180E is higher than the High voltage of the sampling period PWR(2) of the pixel 180F. That is, the voltages of the scanning signals G(2) and G(3) during the period in which the scanning signals G(2) and G(3) supplied to the pixel 180E overlap may be higher than the voltages of the scanning signals G(3) and G(4) supplied to the pixel 180F during the period in which the scanning signals G(3) and G(4) supplied to the pixel 180F overlap. For example, the voltage of the scanning signal G(2) and the scanning signal G(3) may be increased by applying an overdrive to the voltage of the scanning signal G(2) and the scanning signal G(3) during the period when the scanning signal G(2) and the scanning signal G(3) supplied to the pixel 180E overlap. Here, the driving method of the pixel 180E arranged in the uppermost region 22E has been described. The pixel 180E arranged in the lowermost region 22E can be driven by a similar driving method.

[0145] As shown in FIG. 18, in this embodiment, the upper and lower end regions 22E each include one row of pixels 180E. However, without being limited thereto, the upper and lower end regions 22E may each include multiple rows of pixels 180E. In this case, the voltage of the sampling period PWR of the pixel 180E arranged at the extreme end may be different from the voltage of the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. The voltage of the sampling period PWR of the pixel 180E arranged at the extreme end may be higher than the voltage of the sampling period PWR of the pixel E adjacent to the pixel 180F in the region 22F. In the region 22E, there may be a negative gradient from the voltage of the sampling period PWR of the pixel 180E arranged at the extreme end to the voltage of the sampling period PWR of the pixel 180E adjacent to the pixel 180F in the region 22F.

[0146] In this embodiment, the voltage of the sampling period PWR of the pixel 180E arranged in the region 22E is higher than the voltage of the sampling period PWR of the pixel 180F arranged in the region 22F. If the voltage of the sampling period PWR is high, the voltage of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitance element CS is reduced (punched through) due to the capacitive coupling between the gate and drain (gate electrode 632 and first electrode 634) of the third transistor T3 when the third transistor T3 is turned off. Therefore, the voltage held in the capacitance element CS of the pixel 180E arranged in the region 22E is lower than the voltage held in the capacitance element CS of the pixel 180F arranged in the region 22F. By applying this voltage between the gate and source between the gate electrode 622 and the first electrode 624 of the second transistor T2, a smaller current flows in the light-emitting element OLED of the pixel 180E arranged in the region 22E than in the light-emitting element OLED of the pixel 180F arranged in the region 22F. In this way, the phenomenon in which the outermost edge of the display area emits light more brightly at low luminance can be eliminated, and in-plane uniformity can be further improved. The method for driving the self-luminous display device according to this embodiment can be applied to the self-luminous display device according to the third or fourth embodiment. By applying the method to these self-luminous display devices, the phenomenon in which the outermost edge of the display area emits light more brightly can be eliminated, and in-plane uniformity can be further improved.

[0147] <7. Seventh embodiment> An example of a manufacturing method, electrical characteristics, and pixel circuit of the semiconductor device 40 used in the self-luminous display device according to the seventh embodiment will be described with reference to Figs. 21 to 34. Figs. 21 and 22 are a cross-sectional view and a plan view showing an overview of the semiconductor device 40 used in the self-luminous display device according to one embodiment of the present invention. Fig. 23 is a sequence diagram showing a manufacturing method of the semiconductor device 40. Figs. 24 to 32 are cross-sectional views showing a manufacturing method of the semiconductor device 40. Fig. 33 is a graph showing an example of electrical characteristics of the semiconductor device 40 and an example of electrical characteristics of a semiconductor device of a comparative example. Fig. 34 is a schematic diagram showing the configuration of a pixel circuit using the semiconductor device 40. Descriptions of configurations that are the same as or similar to those in Figs. 1 to 20 will be omitted here.

[0148] In the description of the seventh embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper", and the direction from the oxide semiconductor layer toward the substrate is referred to as "lower" or "lower". In the description of the seventh embodiment, for example, the substrate and the oxide semiconductor layer may be arranged upside down. The expression "oxide semiconductor layer on the substrate" merely describes the up-down relationship of the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. The expression "upper" or "lower" means the stacking order in a structure in which multiple layers are stacked. For example, when the pixel electrode is expressed as being above the transistor, the positional relationship between the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when the pixel electrode is expressed as being vertically above the transistor, the positional relationship between the transistor and the pixel electrode overlaps in a planar view.

[0149] <7-1. Configuration of the semiconductor device 40> 21, the semiconductor device 40 is provided above a substrate 400. The semiconductor device 40 includes a gate electrode 405, gate insulating layers 410 and 420, a metal oxide layer 430, an oxide semiconductor layer 440, a gate insulating layer 450, a gate electrode 460, insulating layers 470 and 480, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0150] The gate electrode 405 is provided on the substrate 400. The gate insulating layer 410 and the gate insulating layer 420 are provided on the substrate 400 and the gate electrode 405. The metal oxide layer 430 is provided on the gate insulating layer 420. The metal oxide layer 430 is in contact with the gate insulating layer 420. The oxide semiconductor layer 440 is provided on the metal oxide layer 430. The oxide semiconductor layer 440 is in contact with the metal oxide layer 430. Of the main surfaces of the oxide semiconductor layer 440, the surface in contact with the metal oxide layer 430 is called a lower surface 442. An end of the metal oxide layer 430 and an end of the oxide semiconductor layer 440 are approximately aligned.

[0151] In the seventh embodiment, between the metal oxide layer 430 and the substrate 400, no semiconductor layer or oxide semiconductor layer is provided.

[0152] In the seventh embodiment, a configuration in which the metal oxide layer 430 is in contact with the gate insulating layer 420 and the oxide semiconductor layer 440 is in contact with the metal oxide layer 430 is exemplified, but is not limited to this configuration. Another layer may be provided between the gate insulating layer 420 and the metal oxide layer 430. Another layer may be provided between the metal oxide layer 430 and the oxide semiconductor layer 440.

[0153] 21, the sidewall of the metal oxide layer 430 and the sidewall of the oxide semiconductor layer 440 are aligned in a straight line, but the present invention is not limited to this configuration. The angle of the sidewall of the metal oxide layer 430 with respect to the main surface of the substrate 400 may be different from the angle of the sidewall of the oxide semiconductor layer 440. The cross-sectional shape of the sidewall of at least one of the metal oxide layer 430 and the oxide semiconductor layer 440 may be curved.

[0154] The gate electrode 460 faces the oxide semiconductor layer 440. The gate insulating layer 450 is provided between the oxide semiconductor layer 440 and the gate electrode 460. The gate insulating layer 450 is in contact with the oxide semiconductor layer 440. Of the main surfaces of the oxide semiconductor layer 440, a surface in contact with the gate insulating layer 450 is called an upper surface 441. A surface between the upper surface 441 and the lower surface 442 is called a side surface 443. The insulating layers 470 and 480 are provided on the gate insulating layer 450 and the gate electrode 460. The insulating layers 470 and 480 are provided with openings 471 and 473 that reach the oxide semiconductor layer 440. The source electrode 201 is provided inside the opening 471. The source electrode 201 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 471. The drain electrode 203 is provided inside the opening 473. The drain electrode 203 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 473.

[0155] The gate electrode 405 functions as a bottom gate of the semiconductor device 40 and as a light shielding film for the oxide semiconductor layer 440. The gate insulating layer 410 functions as a barrier film that blocks impurities diffusing from the substrate 400 toward the oxide semiconductor layer 440. The gate insulating layers 410 and 420 function as gate insulating layers for the bottom gate. The metal oxide layer 430 is a layer containing a metal oxide mainly composed of aluminum, and functions as a gas barrier film that blocks gases such as oxygen and hydrogen.

[0156] The oxide semiconductor layer 440 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 440 vertically below the gate electrode 460. The source region S is a region of the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 440 in the channel region CH has properties as a semiconductor. The oxide semiconductor layer 440 in the source region S and the drain region D has properties as a conductor.

[0157] The gate electrode 460 functions as a light-shielding film for the top gate of the semiconductor device 40 and the oxide semiconductor layer 440. The gate insulating layer 450 functions as a gate insulating layer for the top gate and releases oxygen by heat treatment in the manufacturing process. The insulating layers 470 and 480 insulate the gate electrode 460 from the source-drain electrodes 200 and reduce the parasitic capacitance between them. The operation of the semiconductor device 40 is mainly controlled by the voltage supplied to the gate electrode 460. An auxiliary voltage is supplied to the gate electrode 405. However, when the gate electrode 405 is simply used as a light-shielding film, the gate electrode 405 may be floating without being supplied with a specific voltage. That is, the gate electrode 405 may be simply called a "light-shielding film".

[0158] In the fourth embodiment, a configuration in which a dual-gate transistor in which a gate electrode is provided both above and below an oxide semiconductor layer is used as the semiconductor device 40 is illustrated, but the present invention is not limited to this configuration. For example, a bottom-gate transistor in which a gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which a gate electrode is provided only above the oxide semiconductor layer may be used as the semiconductor device 40. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0159] As shown in FIG. 22, in a plan view, the plane pattern of the metal oxide layer 430 is substantially the same as the plane pattern of the oxide semiconductor layer 440. With reference to FIGS. 21 and 22, the lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In particular, in the fourth embodiment, the entire lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In the D1 direction, the width of the gate electrode 405 is larger than the width of the gate electrode 460. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 40. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 440 and the gate electrode 460 overlap is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0160] In the fourth embodiment, the configuration in which the entire lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 442 of the oxide semiconductor layer 440 may not be in contact with the metal oxide layer 430. For example, the entire lower surface 442 of the oxide semiconductor layer 440 in the channel region CH may be covered by the metal oxide layer 430, and the entire or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be covered by the metal oxide layer 430. That is, the entire or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be in contact with the metal oxide layer 430. However, in the above configuration, a part of the lower surface 442 of the oxide semiconductor layer 440 in the channel region CH may not be covered by the metal oxide layer 430, and the other part of the lower surface 442 may be in contact with the metal oxide layer 430.

[0161] In the fourth embodiment, the gate insulating layer 450 is formed on the entire surface, and the openings 471 and 473 are provided in the gate insulating layer 450. However, the present invention is not limited to this configuration. The gate insulating layer 450 may be patterned into a shape different from the shape in which the openings 471 and 473 are provided. For example, the gate insulating layer 450 may be patterned so as to expose all or part of the oxide semiconductor layer 440 in the source region S and the drain region D. That is, the gate insulating layer 450 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 440 and the insulating layer 470 may be in contact with each other in these regions.

[0162] 22 illustrates a configuration in which the source-drain electrode 200 does not overlap the gate electrode 405 and the gate electrode 460 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain electrode 200 may overlap at least one of the gate electrode 405 and the gate electrode 460 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0163] <7-2. Materials of each component of the semiconductor device 40> As the substrate 400, a rigid substrate having light transmission properties, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 400 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used as the substrate 400. When a substrate containing a resin is used as the substrate 400, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 400. In particular, when the semiconductor device 40 is used in a top-emission type self-luminous display device, the substrate 400 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 400 may be used.

[0164] Common metal materials are used for the gate electrode 405, the gate electrode 460, and the source-drain electrodes 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used for these members. The above materials may be used as a single layer for the gate electrode 405, the gate electrode 460, and the source-drain electrodes 200, or may be used as a laminated layer.

[0165] A general insulating material is used for the gate insulating layers 410 and 420 and the insulating layers 470 and 480. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) or other inorganic insulating layers are used.

[0166] The gate insulating layer 450 may be an insulating layer containing oxygen among the above insulating layers. For example, the gate insulating layer 450 may be a silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ) or other inorganic insulating layers are used.

[0167] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 420. The temperature of the heat treatment at which the gate insulating layer 420 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 420 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 40 when a glass substrate is used as the substrate 400.

[0168] An insulating layer with few defects is used as the gate insulating layer 450. For example, when the oxygen composition ratio in the gate insulating layer 450 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 450 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 450 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, silicon oxide (SiO x ), the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 450 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the insulating layer 480. For example, the gate insulating layer 450 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0169] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiNx O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0170] Metal oxide containing aluminum as a main component is used for the metal oxide layer 430 and the metal oxide layer 490 used in the manufacturing process as described below. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. The term "metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) is 1% or more of the entire metal oxide layer 430 (or the metal oxide layer 490). The ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 430. The above ratio may be a mass ratio or a weight ratio.

[0171] The oxide semiconductor layer 440 may be made of a metal oxide having semiconductor properties. For example, the oxide semiconductor layer 440 may be made of an oxide semiconductor containing two or more metals including indium (In). The ratio of indium to the entire oxide semiconductor layer 440 is 50% or more. In addition to indium, the oxide semiconductor layer 440 may be made of gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid. The oxide semiconductor layer 440 may be made of elements other than those mentioned above.

[0172] The oxide semiconductor layer 440 may be amorphous or crystalline. The oxide semiconductor layer 440 may be a mixed phase of amorphous and crystalline. As described below, oxygen vacancies are likely to be formed in the oxide semiconductor layer 440 having an indium ratio of 50% or more. Oxygen vacancies are less likely to be formed in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 440 described above is preferably crystalline.

[0173] <7-3. New problems identified in the process of developing the present invention> A high-mobility semiconductor device 40 can be realized by setting the ratio of indium in the oxide semiconductor layer 440 to 50% or more. On the other hand, in such an oxide semiconductor layer 440, oxygen contained in the oxide semiconductor layer 440 is easily reduced, and oxygen vacancies are easily formed in the oxide semiconductor layer 440.

[0174] In the semiconductor device 40, during a heat treatment step in the manufacturing process, hydrogen is released from a layer (e.g., the gate insulating layers 410, 420) provided on the substrate 400 side of the oxide semiconductor layer 440, and the hydrogen reaches the oxide semiconductor layer 440, causing oxygen vacancies in the oxide semiconductor layer 440. The occurrence of oxygen vacancies is more prominent as the pattern size of the oxide semiconductor layer 440 becomes larger. In order to suppress the occurrence of such oxygen vacancies, it is necessary to suppress hydrogen from reaching the lower surface 442 of the oxide semiconductor layer 440. The above is the first problem.

[0175] In addition to the above problem, there is a second problem as follows: The upper surface 441 of the oxide semiconductor layer 440 is affected by a process (e.g., a patterning process or an etching process) after the oxide semiconductor layer 440 is formed. On the other hand, the lower surface 442 of the oxide semiconductor layer 440 (the surface of the oxide semiconductor layer 440 on the substrate 400 side) is not affected in the above manner.

[0176] Therefore, the number of oxygen vacancies formed on the upper surface 441 of the oxide semiconductor layer 440 is greater than the number of oxygen vacancies formed on the lower surface 442 of the oxide semiconductor layer 440. That is, the oxygen vacancies in the oxide semiconductor layer 440 are not uniformly present in the thickness direction of the oxide semiconductor layer 440, but are non-uniformly distributed in the thickness direction of the oxide semiconductor layer 440. Specifically, the number of oxygen vacancies in the oxide semiconductor layer 440 is smaller toward the lower surface 442 of the oxide semiconductor layer 440 and is greater toward the upper surface 441 of the oxide semiconductor layer 440.

[0177] When oxygen supplying treatment is performed uniformly on the oxide semiconductor layer 440 having the above-described oxygen vacancy distribution, if an amount of oxygen necessary to repair the oxygen vacancies formed on the upper surface 441 side of the oxide semiconductor layer 440 is supplied, an excess of oxygen is supplied to the lower surface 442 side of the oxide semiconductor layer 440. As a result, a defect level different from the oxygen vacancies is formed on the lower surface 442 side due to the excess oxygen, causing phenomena such as characteristic fluctuation in a reliability test or a decrease in field-effect mobility. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface 441 side of the oxide semiconductor layer 440 while suppressing the supply of oxygen to the lower surface 442 side of the oxide semiconductor layer 440.

[0178] The above problem is a problem newly recognized in the process of arriving at the present invention, and is not a problem that has been recognized in the past. In the conventional configuration and manufacturing method, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a trade-off between the initial characteristics and the reliability test, that is, the characteristics fluctuate due to the reliability test. However, the configuration according to the fourth embodiment solves the above problem, and the semiconductor device 40 can have good initial characteristics and good reliability test results.

[0179] <7-4. Method for manufacturing the semiconductor device 40> 23 to 32, a method for manufacturing the semiconductor device 40 will be described. Here, an example of a method for manufacturing the semiconductor device 40 in which aluminum oxide is used for the metal oxide layers 430, 490 will be described.

[0180] As shown in Figures 23 and 24, a gate electrode 405 is formed as a bottom gate on a substrate 400, and gate insulating layers 410, 420 are formed on the gate electrode 405 ("Bottom GI / GE formation" in step S2001 of Figure 23). For example, silicon nitride is formed as the gate insulating layer 410. For example, silicon oxide is formed as the gate insulating layer 420. The gate insulating layers 410, 420 are formed by a chemical vapor deposition (CVD) method. One or both of the gate insulating layers 410, 420 may be referred to as a "first insulating layer."

[0181] By using silicon nitride as the gate insulating layer 410, the gate insulating layer 410 can block impurities diffusing from the substrate 400 side toward the oxide semiconductor layer 440. The silicon oxide used as the gate insulating layer 420 is silicon oxide that has a physical property of releasing oxygen by heat treatment.

[0182] As shown in FIG. 23 and FIG. 24, a metal oxide layer 430 and an oxide semiconductor layer 440 are formed on a gate insulating layer 420 (step S2002 "OS / AlOx film formation" in FIG. 23). This process may be referred to as forming the gate insulating layers 410 and 420 on a substrate 400, and forming the metal oxide layer 430 on the gate insulating layers 410 and 420. Alternatively, it may be referred to as forming the metal oxide layer 430 on the substrate 400, and forming the oxide semiconductor layer 440 on the metal oxide layer 430. Specifically, the oxide semiconductor layer 440 is formed so as to be in contact with the metal oxide layer 430. The metal oxide layer 430 and the oxide semiconductor layer 440 are formed by sputtering or atomic layer deposition (ALD).

[0183] The thickness of the metal oxide layer 430 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 430. Aluminum oxide has high barrier properties against gas. In the fourth embodiment, aluminum oxide used as the metal oxide layer 430 blocks hydrogen and oxygen released from the gate insulating layer 420 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 440.

[0184] The oxide semiconductor layer 440 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm The oxide semiconductor layer 440 is amorphous before a heat treatment (OS annealing) described later.

[0185] When the oxide semiconductor layer 440 is crystallized by OS annealing described later, the oxide semiconductor layer 440 is preferably amorphous (having few crystalline components of the oxide semiconductor) after deposition and before OS annealing. That is, the deposition conditions of the oxide semiconductor layer 440 are preferably such that the oxide semiconductor layer 440 immediately after deposition is as little crystallized as possible. For example, when the oxide semiconductor layer 440 is deposited by a sputtering method, the oxide semiconductor layer 440 is deposited while controlling the temperature of the deposition target (the substrate 400 and a structure formed thereon).

[0186] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object increases with the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor layer 440 contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing is inhibited. In order to control the temperature of the target object as described above, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface (surface) of the target object to be formed (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer 440 while cooling the target object, the oxide semiconductor layer 440 having a small amount of crystalline components immediately after the film formation can be formed.

[0187] As shown in FIG. 23 and FIG. 26, a pattern of the oxide semiconductor layer 440 is formed ("OS pattern formation" in step S2003 in FIG. 23). Although not shown, a resist mask is formed on the oxide semiconductor layer 440, and the oxide semiconductor layer 440 is etched using the resist mask. For etching the oxide semiconductor layer 440, wet etching or dry etching may be used. For wet etching, etching can be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid can be used as the etchant.

[0188] After the oxide semiconductor layer 440 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 440 ("OS annealing" in step S2004 in FIG. 23). In the fourth embodiment, the oxide semiconductor layer 440 is crystallized by this OS annealing.

[0189] As shown in FIG. 23 and FIG. 27, a pattern of the metal oxide layer 430 is formed (see step S2005 of FIG. 23, “AlO xThe metal oxide layer 430 is etched using the oxide semiconductor layer 440 patterned in the above process as a mask. The metal oxide layer 430 may be etched by wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used. As described above, by etching the metal oxide layer 430 using the oxide semiconductor layer 440 as a mask, the photolithography process can be omitted.

[0190] As shown in FIG. 23 and FIG. 28, a gate insulating layer 450 is formed on the oxide semiconductor layer 440 ("GI formation" in step S2006 in FIG. 23). For example, silicon oxide is formed as the gate insulating layer 450. The gate insulating layer 450 is formed by a CVD method. For example, in order to form an insulating layer with few defects as the gate insulating layer 450 as described above, the gate insulating layer 450 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 450 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. After the gate insulating layer 450 is formed, a process of implanting oxygen into a part of the gate insulating layer 450 may be performed. The gate insulating layer 450 may be referred to as a "second insulating layer". A metal oxide layer 490 is formed on the gate insulating layer 450 ("AlOx film formation" in step S2007 in FIG. 23). The metal oxide layer 490 is formed by a sputtering method. By forming the metal oxide layer 490, oxygen is implanted into the gate insulating layer 450.

[0191] The thickness of the metal oxide layer 490 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 490. Aluminum oxide has high barrier properties against gas. In the fourth embodiment, aluminum oxide used as the metal oxide layer 490 suppresses outward diffusion of oxygen implanted into the gate insulating layer 450 during deposition of the metal oxide layer 490.

[0192] For example, when the metal oxide layer 490 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 490. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 490. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 490.

[0193] In a state where the gate insulating layer 450 is formed on the oxide semiconductor layer 440 and the metal oxide layer 490 is formed on the gate insulating layer 450, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 440 (step S2008 "oxidation annealing" in FIG. 23). In other words, the metal oxide layer 430 and the oxide semiconductor layer 440 patterned as described above are subjected to a heat treatment (oxidation annealing). In the process from when the oxide semiconductor layer 440 is formed to when the gate insulating layer 450 is formed on the oxide semiconductor layer 440, many oxygen vacancies are generated on the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. By the above-mentioned oxidation annealing, oxygen released from the gate insulating layers 420 and 450 is supplied to the oxide semiconductor layer 440, and the oxygen vacancies are repaired.

[0194] Oxygen released from the gate insulating layer 420 by the oxidation annealing is blocked by the metal oxide layer 430, so that oxygen is not easily supplied to the lower surface 442 of the oxide semiconductor layer 440. Oxygen released from the gate insulating layer 420 diffuses from a region where the metal oxide layer 430 is not formed to the gate insulating layer 450 provided on the gate insulating layer 420, and reaches the oxide semiconductor layer 440 via the gate insulating layer 450. As a result, oxygen released from the gate insulating layer 420 is not easily supplied to the lower surface 442 of the oxide semiconductor layer 440, and is mainly supplied to the side surface 443 and the upper surface 441 of the oxide semiconductor layer 440. Furthermore, oxygen released from the gate insulating layer 450 by the oxidation annealing is supplied to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. Hydrogen may be released from the gate insulating layers 410 and 420 by the above oxidation annealing, but the hydrogen is blocked by the metal oxide layer 430.

[0195] As described above, the oxidation annealing process can suppress the supply of oxygen to the lower surface 442 of the oxide semiconductor layer 440, which has a small amount of oxygen vacancies, while supplying oxygen to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440, which has a large amount of oxygen vacancies.

[0196] Similarly, in the above-described oxidation annealing, oxygen implanted into the gate insulating layer 450 is prevented from being released into the atmosphere because it is blocked by the metal oxide layer 490. Therefore, the oxygen is efficiently supplied to the oxide semiconductor layer 440 by the oxidation annealing, and oxygen vacancies are repaired.

[0197] As shown in FIG. 23 and FIG. 29, after the oxidation annealing, the metal oxide layer 490 is etched (removed) ("AlOx removal" in step S2009 in FIG. 23). Wet etching or dry etching may be used for the etching of the metal oxide layer 490. For example, diluted hydrofluoric acid (DHF) is used for the wet etching. The metal oxide layer 490 formed on the entire surface is removed by this etching. In other words, the metal oxide layer 490 is removed without using a mask. In further other words, the etching removes all of the metal oxide layer 490 in a region overlapping with the oxide semiconductor layer 440 formed in a certain pattern, at least in a plan view.

[0198] 23 and 30, a gate electrode 460 is formed on the gate insulating layer 450 ("GE formation" in step S2010 in FIG. 23). The gate electrode 460 is formed by sputtering or atomic layer deposition, and is patterned through a photolithography process. As described above, the gate electrode 460 is formed to contact the gate insulating layer 450 exposed by removing the metal oxide layer 490.

[0199] With the gate electrode 460 patterned, the source region S and the drain region D of the oxide semiconductor layer 440 are made to have low resistance (step S2011 "SD low resistance" in FIG. 23). Specifically, impurities are implanted into the oxide semiconductor layer 440 from the gate electrode 460 side through the gate insulating layer 450 by ion implantation. For example, argon (Ar), phosphorus (P), or boron (B) is implanted into the oxide semiconductor layer 440 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 440 by ion implantation, thereby making the oxide semiconductor layer 440 have low resistance. Since the gate electrode 460 is provided above the oxide semiconductor layer 440 that functions as the channel region CH of the semiconductor device 40, impurities are not implanted into the oxide semiconductor layer 440 in the channel region CH.

[0200] As shown in FIG. 23 and FIG. 31, insulating layers 470, 480 are formed as interlayer films on the gate insulating layer 450 and the gate electrode 460 ("Interlayer film formation" in step S2012 in FIG. 23). The insulating layers 470, 480 are formed by a CVD method. For example, silicon nitride is formed as the insulating layer 470, and silicon oxide is formed as the insulating layer 480. The materials used for the insulating layers 470, 480 are not limited to the above. The thickness of the insulating layer 470 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 480 is 50 nm or more and 500 nm or less.

[0201] 23 and 32, openings 471, 473 are formed in the gate insulating layer 450 and the insulating layers 470, 480 ("contact opening" in step S2013 in FIG. 23). The opening 471 exposes the oxide semiconductor layer 440 in the source region S. The opening 473 exposes the oxide semiconductor layer 440 in the drain region D. The source-drain electrodes 200 are formed on the oxide semiconductor layer 440 exposed by the openings 471, 473 and on the insulating layer 480 ("SD formation" in step S2044 in FIG. 23), thereby completing the semiconductor device 40 shown in FIG. 23.

[0202] In the semiconductor device 40 manufactured by the above manufacturing method, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 50 [cm 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60 [cm 2 / Vs] or more can be obtained. The mobility in the fourth embodiment means the field effect mobility in the saturation region of the semiconductor device 40, and means the maximum value of the field effect mobility in a region (i.e., the saturation region) in which the potential difference (Vds) between the source electrode and the drain electrode is greater than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the semiconductor device 40 (Vg-Vth).

[0203] <7-5. Configuration of pixel 180> A pixel circuit 183 according to the seventh embodiment will be described with reference to FIG. 33. The semiconductor device 40 is used in a channel region CH of a second transistor OT2 in the pixel circuit shown in FIG. 33. The second transistor OT2 is a transistor called a driving transistor. The channel region CH of the second transistor OT2 according to the seventh embodiment is formed using an oxide semiconductor layer 440, whereas the channel region of the second transistor TR according to the first embodiment is formed using, for example, a low-temperature polysilicon layer (LTPS layer) or an oxide semiconductor layer having characteristics different from those of the oxide semiconductor layer 440.

[0204] The pixel circuit according to the fourth embodiment shown in FIG. 33 is a circuit in which the second transistor T2 of the pixel circuit 181 according to the first embodiment described with reference to FIG. 4 is replaced with a second transistor OT2 formed by using the semiconductor device 40. The configuration and function of the pixel circuit according to the seventh embodiment other than the second transistor OT2 are similar to those of the pixel circuit 181 according to the first embodiment described with reference to FIG. 4. Therefore, the description here is omitted. The channel regions of the transistors (the first transistor T1, the third transistor T3 to the seventh transistor T7) other than the second transistor OT2 are formed by using, for example, a low-temperature polysilicon layer (LTPS layer), but are not limited to this configuration. The semiconductor device 40 may be used for the channel region CH of the third transistor T3 in the pixel circuit shown in FIG. 33.

[0205] The above-described embodiments of the present invention or parts of the embodiments can be combined as appropriate as long as they are not mutually inconsistent.

[0206] Even if the effects and advantages brought about by the aspects of each of the above-mentioned embodiments are different from those brought about by the aspects of each of the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they will naturally be understood to be brought about by the present invention. [Explanation of symbols]

[0207] 10 self-luminous display device, 22 display area, 24 peripheral area, 26 terminal area, 40 semiconductor device, 100 array substrate, 110 source driver circuit, 112 selection circuit, 114 input terminal, 116 output terminal, 118 switch, 120 gate driver circuit, 121 shift register, 130 light emission control circuit, 131 shift register, 150 terminal section, 160 flexible printed circuit board, 170 chip, 180 pixel, 181 pixel circuit, 200 source / drain electrode, 201 source electrode, 203 drain electrode, 321 image data signal line, 329-332 scanning signal line, 334-337 light emission control signal line, 341 connection wiring, 400 substrate, 405 gate electrode, 410 gate insulating layer, 420 gate insulating layer, 430 metal oxide layer, 440 oxide semiconductor layer, 450 Gate insulating layer, 460 gate electrode, 470 insulating layer, 480 insulating layer, 490 metal oxide layer

Claims

1. a substrate having a display area; a first pixel arranged in a first region on the outer edge of the display region, and a second pixel arranged in a second region surrounded by the first region, Each of the first pixel and the second pixel is a first transistor (T1) controlled by a second control signal (Scan2, G(n+1)) obtained by shifting a first control signal (Scan1, G(n)), and electrically connected between an image data signal line (321) and a first node (N1); a second transistor (T2, a drive transistor) electrically connected between the first node and a second node (N2); a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor (T3) electrically connected between the second node and the gate electrode of the second transistor, the third transistor (T3) being controlled to supply a threshold voltage of the second transistor to the gate electrode of the second transistor and the first capacitance element using the first control signal obtained by shifting a third control signal (Scan3, G(n-1)); a seventh transistor (T7) electrically connected to the second node, the gate electrode of the second transistor, and the first capacitance element, the seventh transistor being controlled to supply a reset voltage to the second node, the gate electrode of the second transistor, and the first capacitance element using the third control signal; A self-luminous display device (10), in which the capacitance of a capacitance section connected to the gate electrode of the second transistor of the first pixel is different from the capacitance of a capacitance section connected to the gate electrode of the second transistor of the second pixel.

2. 2. The self-luminous display device according to claim 1, further comprising a control circuit that sequentially shifts and outputs the third control signal, the first control signal, and the second control signal.

3. A light emitting element (OLED) electrically connected to a reference voltage line (PVSS) to which a reference voltage (VSSEL) is supplied; a fourth transistor (T4) controlled by a fourth control signal (EM2, ES) and electrically connected between a drive power supply line (PVDD) to which a drive voltage is supplied and the second node; a fifth transistor (T5) controlled by the fourth control signal (EM2, ES) and electrically connected to the light emitting element and the first node; a sixth transistor (T6) electrically connected to the light emitting element and controlled to supply an initialization voltage to the light emitting element, a terminal of the fifth transistor connected to the light emitting element, and the first capacitance element; 3. The self-luminous display device according to claim 2, further comprising a light emission control circuit (130) that controls a timing for supplying the fourth control signal to the fourth transistor and the fifth transistor.

4. the capacitance portion is the first capacitance element, 4. The self-luminous display device according to claim 3, wherein a capacitance of the first capacitance element of the first pixel is smaller than a capacitance of the first capacitance element of the second pixel.

5. the capacitance portion is the third transistor, 4. The self-luminous display device according to claim 3, wherein a capacitance between the gate and drain of the third transistor of the first pixel is larger than a capacitance between the gate and drain of the third transistor of the second pixel.

6. the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors; the sixth transistor is controlled using the fourth control signal; 6. The self-luminous display device according to claim 4.

7. the light emission control circuit supplies an ON signal to the fourth control signal; the control circuit supplies an on signal to the third control signal, supplies an on signal to the first control signal, supplies an off signal to the second control signal, and supplies the reset voltage to the second node, the gate electrode, and the first capacitive element; 7. The self-luminous display device according to claim 6.

8. the light emission control circuit supplies an ON signal to the fourth control signal; the control circuit supplies an OFF signal to the third control signal, supplies an ON signal to the first control signal, supplies an ON signal to the second control signal, and supplies image data signals from the image data signal line to the first node, the second node, and the gate electrode; 7. The self-luminous display device according to claim 6.

9. the light emission control circuit supplies an off signal to the fourth control signal, the control circuit supplies an OFF signal to the third control signal, supplies an OFF signal to the first control signal, supplies an OFF signal to the second control signal, and supplies an image data signal from the image data signal line to the first node and the light emitting element; 7. The self-luminous display device according to claim 6.

10. a channel region of each of the fourth transistor, the fifth transistor, and the sixth transistor includes low temperature polysilicon; a channel region of the second transistor includes an oxide semiconductor; 7. The self-luminous display device according to claim 6.

11. a substrate having a display area; a third pixel arranged in a third region including one end of the display region; and a fourth pixel arranged in a fourth region adjacent to the third region, Each of the third pixel and the fourth pixel is a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor, which is controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element by using the first control signal obtained by shifting a third control signal, and is electrically connected between the second node and the gate electrode of the second transistor; a seventh transistor that is controlled to supply a reset voltage to the second node, a gate electrode of the second transistor, and the first capacitance element using the third control signal, and is electrically connected to the second node; A self-luminous display device, wherein a capacitance of a capacitive section connected to the image data signal line connected to the third pixel is different from a capacitance of a capacitive section connected to the image data signal line connected to the fourth pixel.

12. a fifth pixel disposed in a fifth region including one end of the display region and the other end opposite the one end of the display region; The fifth pixel is a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a first capacitance element electrically connected to a gate electrode of the second transistor; a third transistor, which is controlled to supply a threshold voltage of the second transistor to a gate electrode of the second transistor and the first capacitive element by using the first control signal obtained by shifting a third control signal, and is electrically connected between the second node and the gate electrode of the second transistor; a seventh transistor that is controlled to supply a reset voltage to the second node, a gate electrode of the second transistor, and the first capacitance element using the third control signal, and is electrically connected to the second node; The self-luminous display device according to claim 11 , wherein a capacitance of a capacitance section connected to the image data signal line connected to the fifth pixel is different from a capacitance of a capacitance section connected to the image data signal line connected to the fourth pixel.

13. 13. The self-luminous display device according to claim 12, wherein a capacitance of a capacitance section connected to the image data signal line connected to the third pixel is the same as a capacitance of a capacitance section connected to the image data signal line connected to the fifth pixel.

14. a light emitting element electrically connected to a reference voltage line to which a reference voltage is supplied; a fourth transistor controlled by a fourth control signal and electrically connected between a drive power supply line to which a drive voltage is supplied and the second node; a fifth transistor controlled by the fourth control signal and electrically connected to the light emitting element and the first node; a sixth transistor electrically connected to the light emitting element and controlled to supply an initialization voltage to the light emitting element, a terminal of the fifth transistor connected to the light emitting element, and the first capacitance element; a light emission control circuit that controls a timing at which the fourth control signal is supplied to the fourth transistor and the fifth transistor, The self-luminous display device according to claim 13 , wherein the third control signal, the first control signal, and the second control signal are sequentially shifted and output.

15. the capacitance portion is a second capacitance element connected to the image data signal line, 15. The self-luminous display device according to claim 14, wherein a capacitance of the second capacitance element connected to the image data signal line of the third pixel is larger than a capacitance of the second capacitance element connected to the image data signal line of the fourth pixel.

16. the capacitance section is a selection circuit connected to the image data signal line, 15. The self-luminous display device according to claim 14, wherein a capacitance between the gate and drain of the selection circuit connected to the image data signal line of the third pixel is larger than a capacitance between the gate and drain of the selection circuit connected to the image data signal line of the fourth pixel.

17. The third pixels are arranged in a plurality of the third regions and share at least one of the image data signal lines; The self-luminous display device according to claim 15 , wherein a plurality of the fourth pixels are arranged in the fourth region and share at least one of the image data signal lines.

18. the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors; the sixth transistor is controlled using the fourth control signal; The self-luminous display device according to claim 17.

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