Semiconductor package and manufacturing method thereof

Abstract

To provide a semiconductor package and a manufacturing method thereof, in which, in the T-type under bump metallization (UBM) technology including a lower structure extending in a vertical direction and an upper structure extending in a horizontal direction, a wire line is used in place of the upper structure that does not have a wiring function, and a redistribution via and a UBM via are electrically connected in the horizontal direction by the wire line.SOLUTION: A semiconductor package 100 includes: a first redistribution layer structure 110 including a plurality of redistribution vias 114 and a plurality of UBM (under bump metallization) structures 112; and a first semiconductor die 130 on the first redistribution layer structure. Each of the plurality of UBM structures includes a UBM via, and a UBM wire line 113 extending in a horizontal direction on the UBM via and electrically connecting one redistribution via among the plurality of redistribution vias in the horizontal direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. [Background technology]

[0002] Solder or bumps are generally used as a medium for connecting a semiconductor chip to a substrate and an interposer. However, since it is difficult to directly connect the solder or bump to the conductive pad of the semiconductor chip, an under bump metallization (UBM) is disposed between the conductive pad and the solder or bump to improve the adhesion between the conductive pad and the solder or bump. However, even if the UBM is used in this manner, the adhesion between the UBM and the dielectric layer surrounding the UBM is not good, and the side of the UBM may peel off from the dielectric layer. To solve this problem, a T-type UBM technology has been developed that realizes a UBM in a T-shape and interposes an adhesion layer between the UBM and the dielectric layer to improve the adhesion between the UBM and the dielectric layer.

[0003] However, when the T-type UBM technology is used, one layer is required to form a horizontally extending upper structure in a T-shape and another layer is required to form an additional via structure to connect the upper structure to a redistribution line, which increases the turn around time (TAT) required to manufacture a semiconductor package and increases the cost of manufacturing the semiconductor package. In addition, since the thickness of the front side redistribution layer (FRDL) structure including the T-type UBM becomes thicker, a thickness difference occurs between the front side redistribution structure including the T-type UBM and the back side redistribution layer (BRDL) structure in a package on package (PoP) structure, which may cause warpage in the semiconductor package when performing a room temperature or high temperature process.

[0004] Therefore, there is a need to develop a new semiconductor packaging technology that can overcome these problems of the conventional technology. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-87719 A Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems in the conventional technology, and an object of the present invention is to provide a semiconductor package and a manufacturing method thereof in which a horizontally extending upper structure that did not function as a wiring line in the conventional technology and an additional via structure for connecting the upper structure to a rewiring line are eliminated in T-type UBM technology. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, a semiconductor package according to one embodiment of the present invention comprises a first rewiring structure including a plurality of rewiring vias and a plurality of UBM (under bump metal) structures, and a first semiconductor die on the first rewiring structure, each of the plurality of UBM structures including a UBM via and a UBM wiring line extending horizontally on the UBM via to horizontally electrically connect one of the plurality of rewiring vias to the UBM via.

[0008] In order to achieve the above-mentioned object, a semiconductor package according to another aspect of the present invention includes a first rewiring structure including a plurality of UBM (under bump metal) structures, a plurality of rewiring vias and a plurality of rewiring lines on the plurality of UBM structures, and a dielectric layer surrounding the plurality of UBM structures, the plurality of rewiring vias, and the plurality of rewiring lines, a plurality of connection members on a lower surface of the first rewiring structure, a first semiconductor die on the first rewiring structure, a plurality of conductive posts on the first rewiring structure, a molding material disposed on the first rewiring structure and molding the first semiconductor die and the plurality of conductive posts, a second rewiring structure on the molding material, and a second semiconductor die on the second rewiring structure, wherein each of the plurality of UBM structures includes a UBM via and a UBM wiring line extending horizontally on the UBM via to horizontally electrically connect one of the plurality of rewiring vias to the UBM via.

[0009] In order to achieve the above-mentioned object, a manufacturing method for a semiconductor package according to one embodiment of the present invention includes the steps of forming a first rewiring structure including a plurality of UBM (under bump metal) structures and a plurality of rewiring vias on a carrier, mounting a first semiconductor die on the first rewiring structure, forming a plurality of conductive posts on the first rewiring structure, molding the first semiconductor die and the plurality of conductive posts on the first rewiring structure with a molding material, and forming a second rewiring structure on the molding material, wherein each of the plurality of UBM structures includes a UBM via and a UBM wiring line extending horizontally on the UBM via to horizontally electrically connect one of the plurality of rewiring vias to the UBM via. Effect of the Invention

[0010] According to the present invention, in a T-type UBM technology including a lower structure extending vertically and an upper structure extending horizontally, the upper structure, which only has a function in terms of structural aspects to solve the peeling of the UBM side, and does not have a wiring function, can be replaced with a wiring line, and the redistribution via and the UBM via can be electrically connected in the horizontal direction by this wiring line.

[0011] Therefore, at least two layers can be eliminated from the front side redistribution layer (FRDL) structure, which reduces the turn around time (TAT) required to manufacture the semiconductor package and reduces the cost of manufacturing the semiconductor package.

[0012] In addition, since the thickness of the front redistribution layer (FRDL) structure is reduced, the thickness difference between the front redistribution layer (FRDL) structure and the rear redistribution layer (BRDL) structure is reduced, and the warpage characteristics of the semiconductor package can be improved when performing room temperature or high temperature processes.

[0013] In addition, the front side redistribution line (FRDL) structure shortens the signal and power transfer paths, reducing wiring resistance and improving power integrity (PI) characteristics. [Brief description of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Diagram 2] 2 is an enlarged cross-sectional view of a region A of the semiconductor package of FIG. 1. [Diagram 3] 2 is an enlarged cross-sectional view showing a region B of the semiconductor package in FIG. [Figure 4] 2 is an enlarged cross-sectional view showing regions C1 and C2 of the semiconductor package in FIG. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Diagram 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 28] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. [Figure 29] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The present invention can be implemented in several different forms and is not limited to the embodiments described herein.

[0016] In the drawings, in order to clearly illustrate the present invention, parts that are not relevant to the description are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components.

[0017] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0018] Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "indirectly connected" via another member. Furthermore, when a part is said to "include" a certain component, this does not mean that the other component is excluded, but that the part may further include the other component, unless otherwise specified.

[0019] Furthermore, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in the middle. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the opposite direction of gravity.

[0020] Additionally, throughout the specification, "on a plane" means when the subject part is viewed from above, and "on a cross section" means when the subject part is cut vertically and viewed from the side.

[0021] A semiconductor package 100 and a method for manufacturing the semiconductor package 100 according to an embodiment will be described below with reference to the drawings.

[0022] FIG. 1 is a cross-sectional view showing a semiconductor package 100 according to one embodiment.

[0023] 1, the semiconductor package 100 includes a front redistribution structure (first redistribution structure) 110, an external connection member 120, a first semiconductor die 130, conductive posts 150, a first molding material 160, a back redistribution structure (second redistribution structure) 170, a second semiconductor die 180, and a second molding material 161. In one embodiment, the semiconductor package 100 includes a package-on-package (PoP). In one embodiment, the semiconductor package 100 includes a Fan Out Wafer Level Package (FOWLP) or a Fan Out Panel Level Package (FOPLP).

[0024] According to the present invention, S is added after the drawing number of the configuration corresponding to the wiring path for transmitting a signal, P is added after the drawing number of the configuration corresponding to the wiring path for transmitting power, and G is added after the drawing number of the configuration corresponding to the wiring path connected to the ground. Also, in order to distinguish the wiring path for transmitting a signal, the wiring path for transmitting power, and the wiring path connected to the ground, different patterns are displayed for each wiring path. Therefore, even if the drawing number is not displayed, a configuration having the same pattern as the pattern of a configuration with S added after the drawing number indicates a wiring path for transmitting a signal, a configuration having the same pattern as the pattern of a configuration with P added after the drawing number indicates a wiring path for transmitting power, and a configuration having the same pattern as the pattern of a configuration with G added after the drawing number indicates a wiring path connected to the ground.

[0025] The front redistribution structure 110 includes a first dielectric layer 111, a UBM structure 140 within the first dielectric layer 111, a first redistribution via 114, a first redistribution line 115, a second redistribution via 116, a second redistribution line 117, a third redistribution via 118, and a first bonding pad 119. A first semiconductor die 130 and conductive posts 150 are disposed on an upper surface of the front redistribution structure 110. An external connection member 120 is disposed on a lower surface of the front redistribution structure 110.

[0026] The first dielectric layer 111 protects and insulates the UBM structure 140, the first redistribution via 114, the first redistribution line 115, the second redistribution via 116, the second redistribution line 117, and the third redistribution via 118. According to the present invention, the first dielectric layer 111 is previously shown in the manufacturing process as first dielectric layer 111A to first dielectric layer 111D having boundaries from the bottom in the order of film formation, but in the semiconductor package of the final product, the first dielectric layer 111A to first dielectric layer 111D are not distinguished from one another and are configured as an integrated first dielectric layer 111.

[0027] The UBM structure 140 includes a signal UBM structure 140S, a ground UBM structure 140G, and a power UBM structure 140P. The signal UBM structure 140S, the ground UBM structure 140G, and the power UBM structure 140P are disposed at separate positions and are electrically isolated from each other.

[0028] The UBM structure 140 includes a first region including the UBM vias 112 and a second region including the UBM wiring lines 113. The first and second regions form an integral structure without an interface. The UBM structure 140 has a T-shape when the first and second regions are combined. The first region corresponds to a lower structure extending vertically in the T-shape. The second region corresponds to an upper structure extending horizontally in the T-shape. With respect to the first region, the second region has a first portion extending in one direction and in a horizontal direction, and a second portion extending in another direction opposite to the first direction and in a horizontal direction. In one embodiment, the first and second portions have different horizontal lengths. In one embodiment, the first and second portions have the same horizontal lengths.

[0029] The first region is surrounded by a first dielectric layer 111A. The UBM via 112 is disposed between the UBM wiring line 113 and the external connection member 120. The UBM via 112 electrically connects the UBM wiring line 113 to the external connection member 120 in the vertical direction. A seed metal layer SL is located between a side surface of the UBM via 112 and the first dielectric layer 111A. For example, the seed metal layer SL contacts a side surface of the UBM via 112, and the first dielectric layer 111A contacts a side surface of the seed metal layer SL.

[0030] The second region is surrounded by the first dielectric layer 111B. The UBM wiring line 113 is disposed on the UBM via 112 and extends in the horizontal direction. The UBM wiring line 113 is disposed between the UBM via 112 and the first redistribution via 114. The UBM wiring line 113 electrically connects the first redistribution via 114 to the UBM via 112 in the horizontal direction. The UBM wiring line 113 functions as routing. The horizontal width of the UBM wiring line 113 is greater than the horizontal width of the UBM via 112. The seed metal layer SL is located between the lower surface of the UBM wiring line 113 and the first dielectric layer 111A. For example, the seed metal layer SL contacts the lower surface of the UBM wiring line 113, and the first dielectric layer 111A contacts the lower surface of the seed metal layer SL below the UBM wiring line 113. The first dielectric layer 111B also contacts the sides of the UBM wiring lines 113 and the sides of the seed metal layer SL underneath the UBM wiring lines 113.

[0031] The UBM structure 140 according to the present invention has a structural function for solving peeling of the UBM side by including a UBM via 112 corresponding to a lower structure extending vertically in a T-shape and a UBM wiring line 113 corresponding to an upper structure extending horizontally in a T-shape, and the upper structure extending horizontally in a T-shape is formed by the UBM wiring line 113, thereby providing a routing function.

[0032] As a result, according to the present invention, at least two layers of redistribution lines and vias connecting the UBM structure and the redistribution lines, which must be formed on the UBM structure because the conventional T-shaped UBM structure does not have a routing function, can be eliminated from the front redistribution structure, thereby shortening the signal and power transfer paths in the front redistribution structure, reducing wiring resistance, and improving power integrity (PI) characteristics. In one embodiment, the length of the signal and power transfer paths in the front redistribution structure 110 of the semiconductor package according to the present invention is reduced by about 2 μm to about 40 μm, compared to a semiconductor package including a conventional T-shaped UBM structure.

[0033] The first redistribution via 114 is surrounded by the first dielectric layer 111B. The first redistribution via 114 is disposed between the first redistribution line 115 and the UBM distribution line 113. The first redistribution via 114 electrically connects the first redistribution line 115 to the UBM distribution line 113 in the vertical direction. A seed metal layer SL is located between the side surface of the first redistribution via 114 and the first dielectric layer 111B, and between the bottom surface of the first redistribution via 114 and the UBM distribution line 113. For example, the seed metal layer SL contacts the side surface and bottom surface of the first redistribution via 114, and the first dielectric layer 111B contacts the side surface of the seed metal layer SL.

[0034] The first redistribution line 115 is surrounded by the first dielectric layer 111C. The first redistribution line 115 is disposed between the second redistribution via 116 and the first redistribution via 114. The first redistribution line 115 electrically connects the second redistribution via 116 to the first redistribution via 114 in the horizontal direction. The seed metal layer SL is located between the lower surface of the first redistribution line 115 and the first dielectric layer 111B. For example, the seed metal layer SL contacts the lower surface of the first redistribution line 115, and the first dielectric layer 111B contacts the lower surface of the seed metal layer SL below the first redistribution line 115. Also, the first dielectric layer 111C contacts the side of the first redistribution line 115 and the side of the seed metal layer SL below the first redistribution line 115.

[0035] The second redistribution via 116 is surrounded by the first dielectric layer 111C. The second redistribution via 116 is disposed between the second redistribution line 117 and the first redistribution line 115. The second redistribution via 116 electrically connects the second redistribution line 117 to the first redistribution line 115 in a vertical direction. A seed metal layer SL is located between the side surface of the second redistribution via 116 and the first dielectric layer 111C, and between the bottom surface of the second redistribution via 116 and the first redistribution line 115. For example, the seed metal layer SL contacts the side surface and bottom surface of the second redistribution via 116, and the first dielectric layer 111C contacts the side surface of the seed metal layer SL.

[0036] The second redistribution line 117 is surrounded by the first dielectric layer 111D. The second redistribution line 117 is disposed between the third redistribution via 118 and the second redistribution via 116. The second redistribution line 117 electrically connects the third redistribution via 118 to the second redistribution via 116 in the horizontal direction. A seed metal layer SL is located between the lower surface of the second redistribution line 117 and the first dielectric layer 111C. For example, the seed metal layer SL contacts the lower surface of the second redistribution line 117, and the first dielectric layer 111C contacts the lower surface of the seed metal layer SL below the second redistribution line 117. Also, the first dielectric layer 111D contacts the side of the second redistribution line 117 and the side of the seed metal layer SL below the second redistribution line 117.

[0037] The third redistribution via 118 is surrounded by the first dielectric layer 111D. The third redistribution via 118 is disposed between the first bonding pad 119 and the second redistribution line 117. The third redistribution via 118 electrically connects the first bonding pad 119 to the second redistribution line 117 in a vertical direction. A seed metal layer SL is located between the side surface of the third redistribution via 118 and the first dielectric layer 111D, and between the bottom surface of the third redistribution via 118 and the second redistribution line 117. For example, the seed metal layer SL contacts the side surface and bottom surface of the third redistribution via 118, and the first dielectric layer 111D contacts the side surface of the seed metal layer SL.

[0038] The first bonding pad 119 is surrounded by a first molding material 160. The first bonding pad 119 is disposed between the conductive post 150 and the third redistribution via 118. The first bonding pad 119 electrically connects the conductive post 150 to the third redistribution via 118 in the vertical direction. A seed metal layer SL is located between the lower surface of the first bonding pad 11 and the first dielectric layer 111D. For example, the seed metal layer SL contacts the lower surface of the first bonding pad 119, and the first dielectric layer 111D contacts the lower surface of the seed metal layer SL below the first bonding pad 119. Also, the first molding material 160 contacts the side of the first bonding pad 119 and the side of the seed metal layer SL below the first bonding pad 119.

[0039] The external connection members 120 are disposed on the bottom surface of the front redistribution structure 110. The external connection members 120 directly contact the UBM vias 112 to electrically connect the semiconductor package 100 to an external device.

[0040] In one embodiment, the top surface of the external connection members 120 is located at a higher vertical level than the bottom surface of the first dielectric layer 111A. The seed metal layer SL formed on the side surface of the UBM via 112 contacts the external connection members 120. For example, the seed metal layer SL formed on the side surface of the UBM via 112 contacts each surface of the external connection members 120 recessed from the bottom surface of the first dielectric layer 111A.

[0041] The first semiconductor die 130 is disposed on the top surface of the front redistribution structure 110. In one embodiment, the first semiconductor die 130 includes a system on chip (SOC). In one embodiment, the first semiconductor die 130 includes an integrated circuit including at least one of a memory circuit and a logic circuit. The first semiconductor die 130 includes a connection member 131 and is electrically connected to the first bonding pad 119 of the front redistribution structure 110 through the connection member 131. For example, the connection member 131 contacts the first bonding pad 119 of the front redistribution structure 110. In one embodiment, the connection member 131 includes a microbump.

[0042] The conductive posts 150 are disposed on the upper surface of the front redistribution structure 110. The conductive posts 150 are disposed between the fourth redistribution vias 172 of the rear redistribution structure 170 and the first bonding pads 119. The conductive posts 150 electrically connect the fourth redistribution vias 172 of the rear redistribution structure 170 to the first bonding pads 119. For example, each conductive post 150 contacts a lower surface of the seed metal layer SL under one of the fourth redistribution vias 172 and an upper surface of a corresponding first bonding pad 119 of the first bonding pads 119. The conductive posts 150 are disposed through the first molding material 160. The side of the conductive post 150 is surrounded by the first molding material 160. For example, the first molding material 160 contacts the side of the conductive post 150. The conductive posts 150 include signal conductive posts 150S, power conductive posts 150P, and ground conductive posts 150G (not shown).

[0043] The first molding material 160 molds the first semiconductor die 130 and the conductive posts 150 on the front redistribution structure 110. For example, the first molding material 160 surrounds the first semiconductor die 130, the conductive posts 150, and the front redistribution structure 110, and contacts the first semiconductor die 130, the conductive posts 150, and the front redistribution structure 110. The top surface of the first molding material 160 is located on the same plane as the top surfaces of the conductive posts 150. The top surfaces of the first molding material 160 and the conductive posts 150 are located at a vertical level higher than the top surface of the first semiconductor die 130. The side of the first molding material 160 is aligned with the side of the front redistribution structure 110. The first molding material 160 protects the first semiconductor die 130 and the conductive posts 150 from the external environment, thereby ensuring the electrical or mechanical stability of the semiconductor package 100.

[0044] The rear redistribution structure 170 is disposed on the first molding material 160. The rear redistribution structure 170 includes a second dielectric layer 171, a fourth redistribution via 172, a third redistribution line 173, a fifth redistribution via 174, a fourth redistribution line 175, a sixth redistribution via 176, and a second bonding pad 177 located within the second dielectric layer 171. A second semiconductor die 180 is disposed on an upper surface of the rear redistribution structure 170. The first molding material 160 and the conductive posts 150 are disposed on a lower surface of the rear redistribution structure 170.

[0045] The second dielectric layer 171 protects and insulates the fourth redistribution via 172, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, and the sixth redistribution via 176. According to the present invention, the second dielectric layer 171 is previously shown as second dielectric layers 171A to 171C having boundaries from the bottom in the order of film formation, but in the semiconductor package of the final product, the second dielectric layers 171A to 171C are not distinguished from one another and are configured as the integrated second dielectric layer 171.

[0046] The fourth redistribution via 172 is surrounded by the second dielectric layer 171A. The fourth redistribution via 172 is disposed between the third redistribution line 173 and the conductive post 150. The fourth redistribution via 172 electrically connects the third redistribution line 173 to the conductive post 150 in the vertical direction. A seed metal layer SL is located between the side of the fourth redistribution via 172 and the second dielectric layer 171A, and between the lower surface of the fourth redistribution via 172 and the conductive post 150. For example, the seed metal layer SL contacts the lower surface and the side of the fourth redistribution via 172. The second dielectric layer 171A contacts the side of the seed metal layer SL. Each of the conductive posts 150 contacts the lower surface of the seed metal layer SL below the fourth redistribution via 172.

[0047] The third redistribution line 173 is surrounded by the second dielectric layer 171B. The third redistribution line 173 is disposed between the fifth redistribution via 174 and the fourth redistribution via 172. The third redistribution line 173 electrically connects the fifth redistribution via 174 to the fourth redistribution via 172 in the horizontal direction. A seed metal layer SL is located between the lower surface of the third redistribution line 173 and the second dielectric layer 171A. For example, the seed metal layer SL contacts the lower surface of the third redistribution line 173. The second dielectric layer 171A contacts the lower surface of the seed metal layer SL below the third redistribution line 173. Also, the second dielectric layer 171B contacts the side of the third redistribution line 173 and the side of the seed metal layer SL below the third redistribution line 173.

[0048] The fifth redistribution via 174 is surrounded by the second dielectric layer 171B. The fifth redistribution via 174 is disposed between the fourth redistribution line 175 and the third redistribution line 173. The fifth redistribution via 174 electrically connects the fourth redistribution line 175 to the third redistribution line 173 in a vertical direction. A seed metal layer SL is located between the side of the fifth redistribution via 174 and the second dielectric layer 171B, and between the bottom surface of the fifth redistribution via 174 and the third redistribution line 173. For example, the seed metal layer SL contacts the bottom surface and the side surface of the third redistribution via 174. The second dielectric layer 171B contacts the side surface of the seed metal layer SL.

[0049] The fourth redistribution line 175 is surrounded by the second dielectric layer 171C. The fourth redistribution line 175 is disposed between the sixth redistribution via 176 and the fifth redistribution via 174. The fourth redistribution line 175 electrically connects the sixth redistribution via 176 to the fifth redistribution via 174 in the horizontal direction. A seed metal layer SL is located between the lower surface of the fourth redistribution line 175 and the second dielectric layer 171B. For example, the seed metal layer SL contacts the lower surface of the fourth redistribution line 175. The second dielectric layer 171B contacts the lower surface of the seed metal layer SL below the fourth redistribution line 175. Also, the second dielectric layer 171C contacts the side of the fourth redistribution line 175 and the side of the seed metal layer SL below the fourth redistribution line 175.

[0050] The sixth redistribution via 176 is surrounded by the second dielectric layer 171C. The sixth redistribution via 176 is disposed between the second bonding pad 177 and the fourth redistribution line 175. The sixth redistribution via 176 electrically connects the second bonding pad 177 to the fourth redistribution line 175 in the vertical direction. A seed metal layer SL is located between the side of the sixth redistribution via 176 and the second dielectric layer 171C and between the bottom surface of the sixth redistribution via 176 and the fourth redistribution line 175. For example, the seed metal layer SL contacts the bottom surface and the side of the sixth redistribution via 176. The second dielectric layer 171C contacts the side of the seed metal layer SL.

[0051] The second bonding pad 177 is surrounded by the second molding material 161. The second bonding pad 177 is disposed between the connection member 181 of the second semiconductor die 180 and the sixth redistribution via 176. The second bonding pad 177 electrically connects the connection member 181 to the sixth redistribution via 176 in the vertical direction. A seed metal layer SL is located between the lower surface of the second bonding pad 177 and the second dielectric layer 171C. For example, the seed metal layer SL contacts the side of the second bonding pad 177. The second dielectric layer 171C contacts the lower surface of the seed metal layer S) below the second bonding pad 177. Also, the second molding material 161 contacts the side of the second bonding pad 177 and the side of the seed metal layer SL below the second bonding pad 177.

[0052] The second semiconductor die 180 is disposed on the rear redistribution structure 170. In one embodiment, the second semiconductor die 180 includes a single chip such as a DRAM or multiple chips such as a High Bandwidth Memory (HBM). In one embodiment, the second semiconductor die 180 includes an integrated circuit including at least one of a memory circuit and a logic circuit. The second semiconductor die 180 includes a connection member 181 and is electrically connected to the second bonding pad 177 of the rear redistribution structure 170 via the connection member 181. In one embodiment, the connection member 181 includes a microbump.

[0053] The second molding material 161 molds the second semiconductor die 180 on the rear redistribution structure 170. For example, the second molding material 161 surrounds and contacts the second semiconductor die 180. A top surface of the second molding material 161 is coplanar with a top surface of the second semiconductor die 180. A side surface of the second molding material 161 is aligned with a side surface of the rear redistribution structure 170. The second molding material 161 protects the second semiconductor die 180 from an external environment, thereby ensuring electrical and mechanical stability of the semiconductor package 100.

[0054] In the embodiment of FIG. 1, each of the UBM vias 112 (e.g., UBM vias 112P, 112G, and 112S), the first redistribution vias 114 (e.g., first redistribution vias 114P, 114G, and 114S), the second redistribution vias 116 (e.g., second redistribution vias 116P, 116G, and 116S), the third redistribution vias 118 (e.g., third redistribution vias 118P, 118G, and 118S), the fourth redistribution vias 172 (e.g., fourth redistribution vias 172P and 172S), the fifth redistribution vias 174 (e.g., fifth redistribution vias 174P and 174S), and the sixth redistribution vias 176 (e.g., sixth redistribution vias 176P and 176S) has a tapered shape. For example, the width of each of the UBM via 112, the first redistribution via 114, the second redistribution via 116, the third redistribution via 118, the fourth redistribution via 172, the fifth redistribution via 174, and the sixth redistribution via 176 is wider at its top and narrower at its bottom.

[0055] According to the present invention, at least two layers, that is, the redistribution line that must be formed on the top of the UBM structure because the conventional T-shaped UBM structure does not have a routing function, and the via connecting the UBM structure and the redistribution line, can be eliminated from the front redistribution structure. Therefore, the thickness of the front redistribution structure is reduced, and the thickness difference between the front redistribution structure and the rear redistribution structure is reduced, and warpage characteristics of the semiconductor package can be improved when performing a room temperature or high temperature process. In a semiconductor package including a conventional T-shaped UBM structure, the vertical thickness ratio of the front redistribution structure 110 and the rear redistribution structure 170 is about 9:5, but in the semiconductor package 100 according to the present invention, the vertical thickness ratio of the front redistribution structure 110 and the rear redistribution structure 170 is about 7:5, and the thickness balance between the upper structure and the lower structure of the semiconductor package 100 can be improved. In one embodiment, the vertical thickness of the front redistribution structure 110 is about 30 μm to about 40 μm.

[0056] FIG. 2 is an enlarged cross-sectional view of region A of the semiconductor package 100 of FIG. 1. Referring to FIG. 2, region A shows a signal UBM structure 140S of the UBM structure 140. The signal UBM structure 140S includes a signal UBM via 112S and a signal UBM wiring line 113S. The signal UBM structure 140S includes one signal UBM via 112S and one corresponding signal UBM wiring line 113S. The signal UBM via 112S and the signal UBM wiring line 113S form an integral structure without an interface. The signal UBM structure 140S has a T-shape with the signal UBM via 112S and the signal UBM wiring line 113S together. The signal UBM via 112S corresponds to a lower structure extending vertically from the T-shape. The signal UBM wiring line 113S corresponds to an upper structure extending horizontally from the T-shape.

[0057] The signal UBM wiring line 113S has a first portion 113SL extending in one direction and in the horizontal direction with respect to the signal UBM via 112S, and a second portion 113SR extending in the other direction opposite to the one direction and in the horizontal direction. In one embodiment, the horizontal length of the first portion 113SL is different from the horizontal length of the second portion 113SR. In one embodiment, the first portion 113SL and the second portion 113SR have the same horizontal length.

[0058] The signal UBM via 112S is surrounded by the first dielectric layer 111A. The signal UBM via 112S is disposed between the signal UBM wiring line 113S and the external connection member 120. The signal UBM via 112S electrically connects the signal UBM wiring line 113S to the external connection member 120 in the vertical direction. A seed metal layer SL is located between the side surface of the signal UBM via 112S and the first dielectric layer 111A.

[0059] The signal UBM wiring line 113S is surrounded by the first dielectric layer 111B. The signal UBM wiring line 113S is disposed on the signal UBM via 112S and extends in the horizontal direction. The signal UBM wiring line 113S is disposed between the signal UBM via 112S and the first signal redistribution via 114S. The signal UBM wiring line 113S electrically connects the first signal redistribution via 114S to the signal UBM via 112S in the horizontal direction. The signal UBM wiring line 113S functions as routing. The horizontal width of the signal UBM wiring line 113S is larger than the horizontal width of the signal UBM via 112S. The signal UBM wiring line 113S has a horizontal length that is more than twice the maximum horizontal width of the signal UBM via 112S to perform the routing function. A seed metal layer SL is located between the lower surface of the signal UBM wiring line 113S and the first dielectric layer 111A. In one embodiment, the signal UBM wiring line 113S has a horizontally elongated shape, but is not limited thereto.

[0060] 3 is an enlarged cross-sectional view of region B of the semiconductor package 100 of FIG. 1. Referring to FIG. 3, region B includes a ground UBM structure 140G of the UBM structure 140. The ground UBM structure 140G includes a ground UBM via 112G and a ground UBM wiring line 113G. The ground UBM structure 140G includes one or more ground UBM vias 112G and a corresponding ground UBM wiring line 113G. The ground UBM vias 112G and the ground UBM wiring line 113G form an integral structure without an interface. In one embodiment, the ground UBM structure 140G has a structure that combines a plurality of ground UBM vias 112G and a ground UBM wiring line 113G. The single ground UBM wiring line 113G merges a plurality of ground UBM vias 112G. The plurality of ground UBM vias 112G correspond to a substructure extending in a vertical direction. The ground UBM wiring line 113G corresponds to the upper structure extending in the horizontal direction.

[0061] The ground UBM via 112G is surrounded by the first dielectric layer 111A. The ground UBM via 112G is disposed between the ground UBM wiring line 113G and the external connection member 120. The ground UBM via 112G electrically connects the ground UBM wiring line 113G to the external connection member 120 in the vertical direction. A seed metal layer SL is located between the side surface of the ground UBM via 112G and the first dielectric layer 111A.

[0062] The ground UBM wiring line 113G is surrounded by the first dielectric layer 111B. The ground UBM wiring line 113G is disposed on the ground UBM via 112G and extends in the horizontal direction. The ground UBM wiring line 113G is disposed between the ground UBM via 112G and the first ground redistribution via 114G. The ground UBM wiring line 113G electrically connects the first ground redistribution via 114G to the ground UBM via 112G in the horizontal direction. The ground UBM wiring line 113G functions as routing. The horizontal width of the ground UBM wiring line 113G is larger than the horizontal width of the ground UBM via 112G. The ground UBM wiring line 113G has a horizontal length that is more than twice the maximum horizontal width of the ground UBM via 112G to perform the routing function. A seed metal layer SL is located between the lower surface of the ground UBM wiring line 113G and the first dielectric layer 111A. In one embodiment, the ground UBM wiring line 113G has a plate shape in plan view, but is not limited thereto.

[0063] FIG. 4 is an enlarged cross-sectional view showing regions C1 and C2 of the semiconductor package 100 in FIG.

[0064] Referring to FIG. 4, regions C1 and C2 include a power UBM structure 140P of the UBM structure 140. In region C1, the power UBM structure 140P includes a power UBM via 112P and a power UBM wiring line 113P. The power UBM structure 140P includes one power UBM via 112P and one corresponding power UBM wiring line 113P. The power UBM via 112P and the power UBM wiring line 113P form an integral structure without an interface. The power UBM structure 140P has a T-shape with the power UBM via 112P and the power UBM wiring line 113P together. The power UBM via 112P corresponds to a lower structure extending vertically in a T-shape. The power UBM wiring line 113P corresponds to an upper structure extending horizontally in a T-shape.

[0065] In region C1, power UBM wiring line 113P has a first portion 113PL extending in one direction and in the horizontal direction with respect to power UBM via 112P, and a second portion 113PR extending in the other direction opposite to the one direction and in the horizontal direction. In one embodiment, the horizontal length of first portion 113PL is different from the horizontal length of second portion 113PR. In one embodiment, first portion 113PL and second portion 113PR have the same horizontal length.

[0066] In region C2, power UBM structure 140P includes one or more power UBM vias 112P and a corresponding power UBM wiring line 113P, and power UBM vias 112P and power UBM wiring line 113P form an integral structure without an interface. In one embodiment, power UBM structure 140P has a structure combining multiple power UBM vias 112P and power UBM wiring line 113P. One power UBM wiring line 113P merges multiple power UBM vias 112P. Multiple power UBM vias 112P correspond to a lower structure extending vertically. Power UBM wiring line 113P corresponds to an upper structure extending horizontally.

[0067] In regions C1 and C2, the power UBM via 112P is surrounded by the first dielectric layer 111A. The power UBM via 112P is disposed between the power UBM wiring line 113P and the external connection member 120. The power UBM via 112P electrically connects the power UBM wiring line 113P to the external connection member 120 in the vertical direction. A seed metal layer SL is located between the side surface of the power UBM via 112P and the first dielectric layer 111A.

[0068] In regions C1 and C2, the power UBM wiring line 113P is surrounded by the first dielectric layer 111B. The power UBM wiring line 113P is disposed on the power UBM via 112P and extends in the horizontal direction. The power UBM wiring line 113P is disposed between the power UBM via 112P and the first power redistribution via 114P. The power UBM wiring line 113P electrically connects the first power redistribution via 114P to the power UBM via 112P in the horizontal direction. The power UBM wiring line 113P functions as routing. The horizontal width of the power UBM wiring line 113P is larger than the horizontal width of the power UBM via 112P. The power UBM wiring line 113P has a horizontal length that is more than twice the maximum horizontal width of the power UBM via 112P to perform the routing function. A seed metal layer SL is located between the bottom surface of the power UBM wiring line 113P and the first dielectric layer 111A.

[0069] 5 to 29 are cross-sectional views showing a method for manufacturing the semiconductor package 100 according to an embodiment.

[0070] FIG. 5 is a cross-sectional view showing a step of depositing a first dielectric layer 111A on a carrier 210. As shown in FIG.

[0071] 5, a carrier 210 is provided. The carrier 210 may comprise a silicon-based material, such as glass or silicon oxide, an organic material, or other materials, such as aluminum oxide, any combination of these materials, or the like.

[0072] A release layer 220 is disposed on the carrier 210. The release layer may be composed of multiple layers, including, for example, an adhesive layer and a release layer. The release layer 220 is removed together with the carrier 210 from the front redistribution structure 110 after a subsequent process. The top surface of the release layer 220 is planarized and has a high degree of coplanarity. In one embodiment, the release layer 220 includes a polymer-based material. In one embodiment, the release layer 220 includes a light-to-heat-conversion (LTHC) release coating material and is thermally released by heating. In one embodiment, the release layer 220 includes a UV adhesive that is released by ultraviolet (UV) light. In one embodiment, the release layer 220 is released by a physical method. In one embodiment, the release layer 220 is applied in a liquid and cured state. In one embodiment, release layer 220 is a laminate film laminated onto carrier 210 .

[0073] A first dielectric layer 111A is formed on the carrier 210. In one embodiment, the first dielectric layer 111 includes a photoimageable insulator (PID) used in a redistribution process. The photoimageable insulator is a material that can be formed into a fine pattern by applying a photolithography process. In one embodiment, the photoimageable insulator (PID) includes a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, a polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In one embodiment, the first dielectric layer 111 is formed of an inorganic dielectric material such as silicon nitrate or silicon oxide. In one embodiment, the first dielectric layer 111 is formed by a CVD, ALD, or PECVD process.

[0074] FIG. 6 is a cross-sectional view showing a step of forming a photoresist pattern PR1 on the first dielectric layer 111A.

[0075] Referring to FIG. 6, a photoresist PR is formed on the first dielectric layer 111A. In one embodiment, the photoresist PR is formed through spin coating. In one embodiment, the photoresist PR includes an organic polymer resin including a photoactive material. In another embodiment, the photoresist PR includes an inorganic material. In another embodiment, the photoresist PR is formed through a sputtering process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or the like. Thereafter, the photoresist PR is exposed and developed to form a pattern in the photoresist PR, thereby forming a photoresist pattern PR1.

[0076] FIG. 7 is a cross-sectional view showing a step of etching a portion of the first dielectric layer 111A.

[0077] 7, the first dielectric layer 111A is etched using the photoresist pattern PR1 as an etching mask to form a first opening OP1 in the first dielectric layer 111A. An upper surface of the carrier 210 or the release layer 220 is exposed through the first opening OP1 formed in the first dielectric layer 111A. The width of the first opening OP1 decreases in a direction from the upper surface of the first dielectric layer 111A to the lower surface of the first dielectric layer 111A.

[0078] FIG. 8 is a cross-sectional view showing a step of removing the photoresist pattern PR1.

[0079] 8, the photoresist pattern PR1 on the first dielectric layer 111A is removed. In one embodiment, the photoresist pattern PR1 is removed by performing at least one of an ashing process and a stripping process.

[0080] FIG. 9 is a cross-sectional view showing a step of depositing a seed metal layer SL.

[0081] Referring to FIG. 9, a seed metal layer SL is conformally deposited on the top surface of the carrier 210 or the release layer 220, the inner wall of the first opening OP1 of the first dielectric layer 111A, and the top surface of the first dielectric layer 111A. In one embodiment, the seed metal layer SL includes copper. In one embodiment, the seed metal layer SL includes a conductive material that can be electroplated. The seed metal layer SL includes an adhesion layer. The adhesion layer improves adhesion between the first dielectric layer 111A and the UBM structure 140 and prevents the UBM structure 140 from peeling off from the first dielectric layer 111A. In one embodiment, the adhesion layer includes at least one of titanium, titanium nitride, and copper. In one embodiment, the seed metal layer SL is formed by electroless plating. In one embodiment, a cleaning process or a metal catalyst activation pretreatment process is performed prior to the electroless plating. In another embodiment, the seed metal layer SL is formed by sputtering.

[0082] FIG. 10 is a cross-sectional view showing a step of forming a photoresist pattern PR2 on the seed metal layer SL.

[0083] 10, a photoresist PR is formed on the seed metal layer SL. In one embodiment, the photoresist PR is formed through spin coating.

[0084] In one embodiment, the photoresist PR comprises an organic polymer resin including a photoactive material. In another embodiment, the photoresist PR comprises an inorganic material. In another embodiment, the photoresist PR is formed through a sputtering process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or the like. The photoresist PR is then exposed and developed to form a pattern in the photoresist PR to form a photoresist pattern PR2. The photoresist pattern PR2 includes a second opening OP. A portion of the upper surface of the seed metal layer SL and the first opening OP1 are exposed in the second opening OP2 of the photoresist pattern PR2.

[0085] FIG. 11 is a cross-sectional view showing a step of forming a UBM structure 140 in the first opening OP1 of the first dielectric layer 111A and the second opening OP2 of the photoresist pattern PR2.

[0086] Referring to FIG. 11, the UBM structure 140 is formed in the first opening OP1 of the first dielectric layer 111A and the second opening OP2 of the photoresist pattern PR2. The UBM vias 112 and the UBM wiring lines 113 of the UBM structure 140 are integrally formed by a single deposition process. In one embodiment, the UBM structure 140 includes copper. In another embodiment, the UBM structure 140 includes a conductive material that can be electroplated. In one embodiment, the UBM structure 140 is formed by electroplating. A metal film is grown by electroplating from the seed metal layer SL that is first formed to form the UBM structure 140. During the electroplating process, the electroplating is stopped before the UBM structure 140 is deposited beyond the top surface of the photoresist pattern PR2. In this case, a separate chemical mechanical polishing (CMP) process is not performed. In one embodiment, an annealing process is performed after the UBM structure 140 is formed.

[0087] FIG. 12 is a cross-sectional view showing a step of removing the photoresist pattern PR2.

[0088] 12, the photoresist pattern PR2 on the seed metal layer SL is removed. In one embodiment, the photoresist pattern PR2 is removed by performing at least one of an ashing process and a stripping process.

[0089] FIG. 13 is a cross-sectional view illustrating a step of depositing a first dielectric layer 111B on the first dielectric layer 111A and the UBM structure 140. As shown in FIG.

[0090] 13, a first dielectric layer 111B is deposited on the first dielectric layer 111A and the UBM structure 140. The first dielectric layer 111B is formed to cover the UBM structure 140. For example, the first dielectric layer 111B contacts an upper surface of the UBM structure 140.

[0091] FIG. 14 is a cross-sectional view illustrating a step of forming a first redistribution via 114 and a first redistribution line 115 on the UBM structure 140. As shown in FIG.

[0092] 14, a first redistribution via 114 and a first redistribution line 115 are formed on a UBM structure 140. The steps of forming the first redistribution via 114 and the first redistribution line 115 are similar to those described in FIGS. 6 to 12 for explaining the steps of forming the UBM structure 140. In one embodiment, the first redistribution via 114 and the first redistribution line 115 include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0093] FIG. 15 is a cross-sectional view showing a step of depositing a first dielectric layer 111C on the first dielectric layer 111B and the first redistribution line 115. As shown in FIG.

[0094] 15, a first dielectric layer 111C is deposited on the first dielectric layer 111B and the first redistribution line 115. The first dielectric layer 111C is formed to cover the first redistribution line 115. For example, the first dielectric layer 111C contacts an upper surface of the first redistribution line 115.

[0095] FIG. 16 is a cross-sectional view showing a step of forming a second redistribution via 116 and a second redistribution line 117 on the first redistribution line 115. As shown in FIG.

[0096] 16, a second redistribution via 116 and a second redistribution line 117 are formed on a first redistribution line 115. The steps of forming the second redistribution via 116 and the second redistribution line 117 are similarly applied to the steps of forming the UBM structure 140 described in FIGS. 6 to 12. In one embodiment, the second redistribution via 116 and the second redistribution line 117 include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0097] FIG. 17 is a cross-sectional view showing a step of depositing a first dielectric layer 111D on the first dielectric layer 111C and the second redistribution line 117. As shown in FIG.

[0098] 17, a first dielectric layer 111D is deposited on the first dielectric layer 111C and the second redistribution line 117. The first dielectric layer 111D is formed to cover the second redistribution line 117. For example, the first dielectric layer 111D contacts an upper surface of the first redistribution line 117.

[0099] FIG. 18 is a cross-sectional view showing a step of forming a third redistribution via 118 and a first bonding pad 119 on the second redistribution line 117. As shown in FIG.

[0100] 18, a third redistribution via 118 and a first bonding pad 119 are formed on the second redistribution line 117. The steps of forming the third redistribution via 118 and the first bonding pad 119 are similarly described in FIGS. 6 to 12, which illustrate the steps of forming the UBM structure 140. In one embodiment, the third redistribution via 118 and the first bonding pad 119 include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0101] Thus, according to the present invention, at least two layers of redistribution lines formed on the conventional UBM structure 140 and vias connecting the UBM structure 140 and the redistribution lines can be eliminated from the front side redistribution structure, thereby reducing the turn around time (TAT) required to manufacture a semiconductor package and reducing the cost of manufacturing the semiconductor package.

[0102] FIG. 19 is a cross-sectional view illustrating a step of mounting a first semiconductor die 130 on the front side rewiring structure 110.

[0103] 19, a first semiconductor die 130 is mounted on the front redistribution structure 110. The connection member 131 of the first semiconductor die 130 is bonded to the first bonding pad 119 of the front redistribution structure 110, so that the first semiconductor die 130 and the front redistribution structure 110 are electrically connected to each other.

[0104] FIG. 20 is a cross-sectional view illustrating the step of forming conductive posts 150 on the front side redistribution structure 110. As shown in FIG.

[0105] 20, the conductive posts 150 are bonded onto the front redistribution structure 110 and formed in a vertical direction. In one embodiment, the conductive posts 150 are formed by performing a sputtering process. In another embodiment, the conductive posts 150 are formed by performing an electrolytic plating process after forming a seed metal layer. In one embodiment, the conductive posts 150 include at least one of copper, aluminum, tungsten, nickel, gold, silver, chromium, antimony, tin, titanium, and alloys thereof.

[0106] FIG. 21 is a cross-sectional view illustrating molding the first semiconductor die 130 and conductive posts 150 onto the front side redistribution structure 110. As shown in FIG.

[0107] 21, the first semiconductor die 130 and the conductive posts 150 are molded on the front redistribution structure 110 by a first molding material 160. In one embodiment, the molding process with the first molding material 160 includes a compression molding process or a transfer molding process. In one embodiment, the first molding material 160 includes an epoxy molding compound (EMC).

[0108] FIG. 22 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the first molding material 160. As shown in FIG.

[0109] 22, in order to level the top surface of the first molding material 160, a chemical mechanical planarization (CMP) process is performed to planarize the top surface of the first molding material 160. After performing the chemical mechanical planarization (CMP) process, the top surfaces of the conductive posts 150 are exposed.

[0110] FIG. 23 is a cross-sectional view showing a step of forming a rear redistribution structure 170 on the first molding material 160. As shown in FIG.

[0111] With respect to the step of forming the rear redistribution structure 170, the contents described above in the step of forming the front redistribution structure 110 also apply, except that the rear redistribution structure 170 is formed on the first molding material 160 and does not include the UBM structure 140.

[0112] FIG. 24 is a cross-sectional view illustrating a step of mounting a second semiconductor die 180 on the rear redistribution structure 170.

[0113] 24, a second semiconductor die 180 is mounted on the rear redistribution structure 170. A connection member 181 of the second semiconductor die 180 is bonded to a second bonding pad 177 of the rear redistribution structure 170, so that the second semiconductor die 180 and the rear redistribution structure 170 are electrically connected to each other.

[0114] FIG. 25 is a cross-sectional view illustrating the step of molding a second semiconductor die 180 over the rear redistribution structure 170. As shown in FIG.

[0115] 25, the second semiconductor die 180 is molded on the rear redistribution structure 170 with a second molding material 161. In one embodiment, the molding process with the second molding material 161 includes a compression molding process or a transfer molding process. In one embodiment, the second molding material 161 includes an epoxy molding compound (EMC).

[0116] FIG. 26 is a cross-sectional view showing a step of performing a chemical mechanical planarization (CMP) process on the second molding material 161. As shown in FIG.

[0117] 26, a chemical mechanical planarization (CMP) process is performed to level the top surface of the second molding material 161, thereby planarizing the top surface of the second molding material 161. After performing the chemical mechanical planarization (CMP) process, the top surface of the second semiconductor die 180 is exposed.

[0118] FIG. 27 is a cross-sectional view illustrating the step of removing the carrier 210 from the front side rewiring structure 110.

[0119] Referring to FIG. 27, the carrier 210 including the release layer 220 from the bottom surface of the front redistribution structure 110 is removed.

[0120] FIG. 28 is a cross-sectional view illustrating a step of etching the seed metal layer SL on the bottom surface of the front side redistribution structure 110. As shown in FIG.

[0121] Referring to FIG. 28, the seed metal layer SL is etched on the bottom surface of the front side redistribution structure 110 to expose the bottom surfaces of the UBM vias 112.

[0122] FIG. 29 is a cross-sectional view showing a step of forming an external connection member 120 on the bottom surface of the UBM via 112.

[0123] Referring to FIG. 29, an external connection member 120 is formed on the bottom surface of the UBM via 112 .

[0124] The above describes in detail an embodiment of the present invention with reference to the drawings. However, the present invention is not limited to the above-described embodiment, and various modifications and variations can be made without departing from the technical spirit of the present invention. [Explanation of symbols]

[0125] 100 Semiconductor Packages 110, 170 Front, rear (1st, 2nd) rewiring structure 111, 111A to 111D First dielectric layer 112 UBM (Under Bump Metal) Via (First Area) 112G Ground UBM Via (Substructure) 112P Power UBM Via (Substructure) 112S Signal UBM Via (Substructure) 113 UBM wiring line (Second area) 113G Grounded UBM Wiring Line (Superstructure) 113P Power UBM wiring line (superstructure) 113S Signal UBM Wiring Line (Superstructure) 113PL, 113SL Part 1 113PR, 113SR 2nd part 114, 114G, 114P, 114S 1st Redistribution Via 115, 115G, 115P, 115S 1st Rewiring Line 116, 116G, 116P, 116S 2nd Redistribution Via 117, 117G, 117P, 117S 2nd rewiring line 118, 118G, 118P, 118S 3rd Redistribution Via 119, 119G, 119P, 119S 1st bonding pad 120 External connection parts 130, 180 First and second semiconductor dies 131 Connection parts 140, 140G, 140P, 140S UBM structure 150, 150P, 150S Conductive Post 160, 161 First and second molding materials 171, 171A to 171C Second dielectric layer 172, 172P, 172S 4th Redistribution Via 173, 173P, 173S 3rd rewiring line 174, 174P, 174S 5th Redistribution Via 175, 175P, 175S 4th rewiring line 176, 176P, 176S 6th Redistribution Via 177, 177P, 177S Second bonding pad 181 Connection parts 210 Career 220 release tier OP1, OP2 1st and 2nd openings PR1, PR2 photoresist patterns SL Seed metal layer

Claims

1. a first redistribution structure including a plurality of redistribution vias and a plurality of UBM (under bump metal) structures; a first semiconductor die on the first rewiring structure; Each of the plurality of UBM structures comprises: UBM vias, a UBM wiring line extending horizontally over the UBM via and electrically connecting one of the plurality of redistribution vias to the UBM via in the horizontal direction.

2. the plurality of UBM structures includes a plurality of signal UBM structures; the UBM vias of the plurality of signal UBM structures are signal UBM vias; 2. The semiconductor package of claim 1, wherein the UBM wiring lines of the plurality of signal UBM structures are signal UBM wiring lines.

3. Each signal UBM structure of the plurality of signal UBM structures comprises: One signal UBM via; and a signal UBM wiring line corresponding to the one signal UBM via.

4. 3. The semiconductor package according to claim 2, wherein the signal UBM wiring line has an elongated shape.

5. the plurality of UBM structures includes a plurality of ground UBM structures; the UBM vias of the plurality of ground UBM structures are ground UBM vias; 2. The semiconductor package of claim 1, wherein the UBM wiring lines of the plurality of ground UBM structures are ground UBM wiring lines.

6. Each ground UBM structure of the plurality of ground UBM structures comprises: one or more ground UBM vias; and a ground UBM wiring line corresponding to the one or more ground UBM vias.

7. the one or more ground UBM vias are multiple; 7. The semiconductor package of claim 6, wherein one ground UBM wiring line merges a plurality of ground UBM vias.

8. the plurality of UBM structures includes a plurality of power UBM structures; the UBM vias of the plurality of power UBM structures are power UBM vias; 2. The semiconductor package of claim 1, wherein the UBM wiring lines of the plurality of power UBM structures are power UBM wiring lines.

9. 2. The semiconductor package of claim 1, wherein each of the plurality of UBM structures has a T-shaped configuration with a vertically extending lower UBM via and a horizontally extending upper UBM wiring line.

10. the UBM wiring line includes a first portion extending in one direction and in a horizontal direction with respect to the UBM via, and a second portion extending in another direction opposite to the one direction and in a horizontal direction; 2. The semiconductor package according to claim 1, wherein the first portion has a horizontal length different from the second portion.

11. a first redistribution structure including a plurality of UBM (under bump metal) structures, a plurality of redistribution vias and a plurality of redistribution lines on the plurality of UBM structures, and a dielectric layer surrounding the plurality of UBM structures, the plurality of redistribution vias, and the plurality of redistribution lines; a plurality of connection members on a bottom surface of the first redistribution structure; a first semiconductor die on the first rewiring structure; a plurality of conductive posts on the first redistribution structure; A molding material disposed over the first redistribution structure to mold the first semiconductor die and the plurality of conductive posts. a second redistribution structure on the molding material; a second semiconductor die on the second rewiring structure; Each of the plurality of UBM structures comprises: UBM vias, a UBM wiring line extending horizontally on the UBM via and electrically connecting one of the plurality of redistribution vias to the UBM via in the horizontal direction.

12. 12. The semiconductor package of claim 11, further comprising a seed metal layer between a sidewall of the UBM via and the dielectric layer and between a bottom surface of the UBM wiring line and the dielectric layer.

13. The semiconductor package of claim 11 , wherein the first semiconductor die comprises a system on a chip (SoC).

14. The semiconductor package of claim 11 , wherein the second semiconductor die comprises a memory semiconductor.

15. 12. The semiconductor package of claim 11, wherein a ratio of a vertical thickness of the first redistribution structure to a vertical thickness of the second redistribution structure is 7:

5.

16. 12. The semiconductor package of claim 11, wherein the first redistribution structure has a vertical thickness of 30 μm to 40 μm.

17. forming a first redistribution structure on the carrier, the first redistribution structure including a plurality of UBM (under bump metal) structures and a plurality of redistribution vias; mounting a first semiconductor die on the first redistribution structure; forming a plurality of conductive posts on the first redistribution structure; molding the first semiconductor die and the plurality of conductive posts over the first redistribution structure with a molding material; forming a second redistribution structure on the molding material; Each of the plurality of UBM structures comprises: UBM vias, a UBM wiring line extending horizontally on the UBM via and electrically connecting one of the plurality of redistribution vias to the UBM via in the horizontal direction.

18. 20. The method of claim 17, wherein the UBM vias and the UBM wiring lines are formed by a single film deposition process.

19. forming a first redistribution structure on the carrier, the first redistribution structure including a plurality of UBM structures and a plurality of redistribution vias; depositing a dielectric layer on the carrier; forming a plurality of first openings in the dielectric layer such that a top surface of the carrier is exposed; forming a seed metal layer on the exposed top surface of the carrier, on inner walls of the first plurality of openings, and on the dielectric layer; forming a photoresist pattern on a seed metal layer on the dielectric layer, the photoresist pattern including a plurality of second openings, the plurality of first openings being exposed in the plurality of second openings; 20. The method of claim 17, further comprising the step of: filling the first and second openings with a conductive material.

20. 20. The method of claim 19, wherein the step of filling the first and second openings with a conductive material is performed by electrolytic plating.

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