Semiconductor packaging alignment mark manufacturing method and product thereof

Abstract

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a method for manufacturing a semiconductor packaging alignment mark and a product thereof. Background Art

[0002] Currently, most photolithography processes in TSV packaging rely on alignment using marks created by the front-end fabrication facility (Fab) along the wafer's dicing lanes. However, after copper plating and pre-cutting, the dicing lane marks are covered by metal or removed by the pre-cutting process, leaving no marks available for subsequent photolithography processes. In this situation, the standard approach is to laser-mark specific locations on the wafer for alignment purposes during all subsequent photolithography processes.

[0003] Typically, laser marking is performed after the passivation layer is applied. The goal is to leave a laser mark on the surface of the passivation layer. Because the thickness of the passivation layer varies from product to product, the marking depth for each product requires process tuning, which is time-consuming and labor-intensive. Furthermore, laser equipment capabilities are significantly inferior to other photolithography processes in the packaging process, making it unsuitable for some products requiring high precision. Therefore, exploring new methods to improve this issue is a key factor in reducing packaging costs and improving overall process capabilities. Summary of the Invention

[0004] In order to solve the technical problems existing in the prior art, the purpose of the present invention is to provide a method for manufacturing a semiconductor package alignment mark and a product thereof.

[0005] In order to achieve the above-mentioned purpose and the above-mentioned technical effect, the technical solution adopted by the present invention is:

[0006] A method for making an alignment mark for a semiconductor package comprises the following steps:

[0007] Step 1: Prepare a cofferdam on the optical glass at a position corresponding to the TSV area;

[0008] Step 2: Apply bonding glue on the cofferdam;

[0009] Step 3: Bond the wafer to the optical glass and complete wafer grinding and thinning;

[0010] Step 4: Etching to form a first-order groove and alignment mark;

[0011] Step 5: Complete through silicon via etching;

[0012] Step 6: Preparing a dielectric layer on the wafer;

[0013] Step 7: preparing a passivation layer on the dielectric layer;

[0014] Step 8: Prepare RDL redistribution layer;

[0015] Step 9: Pre-cut the groove and half-cut to the cofferdam;

[0016] Step 10: Prepare solder mask;

[0017] Step 11: Solder ball implantation or printing, then cutting into the final product.

[0018] Furthermore, in step 4, the pattern where grooves need to be engraved and alignment marks need to be made on the edge of the warer is exposed through a photolithography process, and then a first-order groove and alignment marks are formed by dry etching.

[0019] Furthermore, the alignment mark has a shape of a cross, a square, a triangle or a circle.

[0020] Furthermore, in step six, the dielectric layer is made of oxide or nitride of silicon, aluminum, zirconium, or titanium, and has a thickness of 0.5-5 μm.

[0021] Furthermore, in step seven, the thickness of the passivation layer is 5-20 μm, and the material of the passivation layer is photosensitive resin (not limited to resin material) or photosensitive film (not limited to PE, PI and other materials).

[0022] Furthermore, in step ten, the thickness of the solder resist layer is 6-40 μm, and the solder resist layer is a photosensitive resin (not limited to resin materials) or a photosensitive film (not limited to materials such as PE and PI).

[0023] The present invention also discloses a structure produced by a method for producing a semiconductor package alignment mark, comprising optical glass, a cofferdam prepared on the optical glass at a position corresponding to the TSV area, a wafer bonded to the cofferdam by bonding glue, a through-silicon via provided on the wafer, a dielectric layer provided on the wafer, a passivation layer prepared on the dielectric layer, an RDL redistribution layer provided on the passivation layer, a solder resist layer provided on the RDL redistribution layer, and solder balls provided on the surface pads of the RDL redistribution layer.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1) It can not only realize the alignment function of the pre-cutting and post-photolithography process, but also improve the overall process capability, reduce process steps, shorten product manufacturing cycle, reduce packaging costs, and enhance product competitiveness;

[0026] 2) No need for a dedicated laser marking station, reducing wafer surface contamination caused by laser marking, saving the original laser marking station operators and process personnel, saving manpower and material resources, saving a process, and reducing packaging costs;

[0027] 3) Through the alignment mark of the photolithography process, the equipment capability is less than + / -3μm, and the overall process capability is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of step 1 of the present invention;

[0029] Figure 2 This is a schematic structural diagram of step 2 of the present invention;

[0030] Figure 3 This is a schematic structural diagram of step three of the present invention;

[0031] Figure 4-5 This is a schematic structural diagram of step four of the present invention;

[0032] Figure 6 This is a schematic structural diagram of step five of the present invention;

[0033] Figure 7 This is a schematic structural diagram of step six of the present invention;

[0034] Figure 8 This is a schematic structural diagram of step seven of the present invention;

[0035] Figure 9 This is a schematic structural diagram of step eight of the present invention;

[0036] Figure 10 This is a schematic structural diagram of step nine of the present invention;

[0037] Figure 11 This is a schematic structural diagram of step 10 of the present invention;

[0038] Figure 12 This is a structural diagram of step 11 of the present invention. DETAILED DESCRIPTION

[0039] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0040] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0041] like Figure 1-12 As shown, the present invention discloses a method for making an alignment mark for a semiconductor package, comprising the following steps:

[0042] Step 1: If Figure 1 As shown, a cofferdam 11 is prepared at a position corresponding to the TSV area on the optical glass 10, and the processes used include but are not limited to yellow light, silk screen printing, 3D printing, etc.;

[0043] Step 2: If Figure 2 As shown, bonding glue 12 is coated on the cofferdam 11, and the process used includes but is not limited to silk screen printing, 3D printing, glue rolling, etc.;

[0044] Step 3: If Figure 3 As shown, the wafer 13 is bonded to the optical glass 10 and the wafer is ground and thinned;

[0045] Step 4: If Figure 4-5 As shown, the pattern where the grooves need to be etched and the alignment marks need to be made on the edge of the warer are exposed through the photolithography process, and then the first-order grooves 131 and the alignment marks are formed by dry etching. The alignment marks may have shapes including but not limited to crosses, squares, triangles, circles, etc. At the same time as the grooves are etched, the alignment marks are etched on the invalid DIE around the entire wafer.

[0046] Step 5: If Figure 6 As shown, the etching of the through silicon via 132 is completed;

[0047] Step 6: If Figure 7 As shown, a dielectric layer 14 is prepared on the wafer 13, and the material includes but is not limited to oxides or nitrides of elements such as silicon, aluminum, zirconium, and titanium;

[0048] Step 7: If Figure 8 As shown, a passivation layer 15 is prepared on the dielectric layer 14 by photolithography. The material of the passivation layer 15 is a photosensitive resin (not limited to resin materials) or a photosensitive film (not limited to PE, PI and other materials), with a thickness of 5-20 μm;

[0049] Step 8: Prepare the RDL redistribution layer 201 (using the alignment mark formed by etching in step 4) to obtain Figure 9 The structure shown;

[0050] Step 9: If Figure 10 As shown, the pre-cut groove 202 is half-cut to the cofferdam 11;

[0051] Step 10: Prepare solder resist layer 203, and open the surface pad by exposure (using the alignment mark formed by etching in step 4) and development to obtain the following Figure 11 The structure shown; the material of the solder resist layer 203 is a photosensitive resin (not limited to resin materials) or a photosensitive film (not limited to PE, PI and other materials), with a thickness of 6-40 μm;

[0052] Step 11: Plant solder balls 204 or print solder balls 204, and then cut them into final products, such as Figure 12 The structure shown.

[0053] It should be noted that laser marking has traditionally been used, creating indentations on the surface of the passivation layer. The cumulative offset tolerance for alignment marks exceeds ±7μm, and laser marking is affected by the thickness of the surface passivation layer. If the mark is too deep, it may cause regional passivation layer shedding. If the mark is too shallow, the mark is unclear, affecting alignment and gripping in steps 8 and 10. Therefore, the present invention emphasizes the use of dry etching to form marks for alignment in steps 8 and 10, with a cumulative offset tolerance of <4μm. Mark depth is formed by dry etching, unaffected by passivation layer thickness, and is therefore convenient and widely applicable.

[0054] The present invention also discloses a structure obtained by a method for making a semiconductor package alignment mark, comprising a light glass 10, a dam 11 prepared at a position on the light glass 10 corresponding to the TSV area, a wafer 13 bonded to the dam 11 by a bonding glue 12, a through-silicon via 132 provided on the wafer 13, a dielectric layer 14 provided on the wafer 13, a passivation layer 15 prepared on the dielectric layer 14, an RDL redistribution layer 201 provided on the passivation layer 15, a solder resist layer 203 provided on the RDL redistribution layer 201, and a solder ball 204 provided on the surface pad of the RDL redistribution layer 201. Parts or structures not specifically described in the present invention can be made using existing technologies or existing products, and will not be described in detail here. The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for making a semiconductor package alignment mark, characterized in that: The following steps are involved: Step 1: Prepare a cofferdam on the optical glass at a position corresponding to the TSV area; Step 2: Apply bonding glue on the cofferdam; Step 3: Bond the wafer to the optical glass and complete wafer grinding and thinning; Step 4: Etching to form a first-order groove and alignment mark; Step 5: Complete through silicon via etching; Step 6: Preparing a dielectric layer on the wafer; Step 7: preparing a passivation layer on the dielectric layer; Step 8: Prepare RDL redistribution layer; Step 9: Pre-cut the groove and half-cut to the cofferdam; Step 10: Prepare solder mask; Step 11: Solder ball implantation or printing, then cutting into the final product.

2. A method for making a semiconductor package alignment mark according to claim 1, characterized in that: In step 4, the pattern where grooves need to be cut and alignment marks need to be made on the edge of the warer is exposed through a photolithography process, and then a first-order groove and alignment marks are formed by dry etching.

3. The method for making a semiconductor package alignment mark according to claim 1, wherein: The alignment mark shape is cross, square, triangle or circle.

4. The method for making a semiconductor package alignment mark according to claim 1, wherein: In step six, the dielectric layer is made of oxide or nitride of silicon, aluminum, zirconium, or titanium, and has a thickness of 0.5-5 μm.

5. The method for making a semiconductor package alignment mark according to claim 1, wherein: In step seven, the thickness of the passivation layer is 5-20 μm.

6. The method for making a semiconductor package alignment mark according to claim 1, wherein: In step ten, the thickness of the solder resist layer is 6-40 μm.

7. A structure manufactured by the method for manufacturing a semiconductor package alignment mark according to any one of claims 1 to 6, characterized in that: It includes optical glass, a cofferdam is prepared on the optical glass at a position corresponding to the TSV area, a wafer is bonded to the cofferdam by bonding glue, the wafer is provided with a through silicon via, the wafer is provided with a dielectric layer, a passivation layer is prepared on the dielectric layer, an RDL redistribution layer is provided on the passivation layer, a solder resist layer is provided on the RDL redistribution layer, and solder balls are provided on the surface pads of the RDL redistribution layer.

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