Packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a packaging structure, a preparation method thereof and electronic equipment. The packaging structure comprises a circuit board; the organic substrate is arranged on the circuit board and electrically connected with the circuit board, and a first groove is formed in the side, away from the circuit board, of the organic substrate; the local connection assembly is embedded into the organic substrate and is electrically connected with the organic substrate, and the local connection assembly comprises a glass substrate and a rewiring layer formed on the glass substrate; the photon integrated circuit chip is arranged in the first groove; the calculation chip is electrically connected to the rewiring layer in the local connection assembly; the electrical interface chip is located on the side, away from the circuit board, of the organic substrate, and the electrical interface chip is connected with the photon integrated circuit chip through a vertical interconnection piece and connected with the calculation chip; the optical waveguide assembly is arranged on the organic substrate and at least partially located above the photonic integrated circuit chip, and the optical waveguide assembly is connected to the photonic integrated circuit chip so as to perform optical signal coupling with the photonic integrated circuit chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure, its fabrication method, and an electronic device. Background Technology

[0002] In the field of data computing, mainstream packaging structures generally adopt horizontal interconnection, resulting in excessively long signal transmission paths between computing chips and electrical interface chips. This not only degrades signal integrity but also significantly increases overall power consumption. Meanwhile, the optical coupling between photonic chips and external optical fibers faces severe technological challenges, requiring extremely high alignment precision and involving complex manufacturing processes.

[0003] To improve the performance of packaging structures, related technologies have attempted to use glass substrates to take advantage of their excellent electrical and optical properties. However, large-size glass substrates are expensive and fragile, and the process of integrating high-density vias, fine circuits, and waveguides on them is extremely complex, resulting in high manufacturing costs and difficulty in improving the yield of packaging structures. Summary of the Invention

[0004] This application discloses a packaging structure, its preparation method, and an electronic device, which can prevent electrical breakdown of the conductive base film and improve electroplating efficiency.

[0005] In a first aspect, embodiments of this application disclose a packaging structure, comprising: a circuit board; an organic substrate disposed on the circuit board and electrically connected to the circuit board, wherein a first groove is provided on the side of the organic substrate opposite to the circuit board; a local connection component embedded in the organic substrate and electrically connected to the organic substrate, the local connection component including a glass substrate and a redistribution layer formed on the glass substrate; a photonic integrated circuit chip disposed in the first groove; a computing chip disposed on the side of the organic substrate opposite to the circuit board, the computing chip being electrically connected to the redistribution layer in the local connection component; an electrical interface chip located on the side of the organic substrate opposite to the circuit board, the electrical interface chip being connected to the photonic integrated circuit chip via a vertical interconnect and electrically connected to the computing chip; and an optical waveguide component disposed on the organic substrate and at least partially located above the photonic integrated circuit chip, the optical waveguide component being connected to the photonic integrated circuit chip for optical signal coupling with the photonic integrated circuit chip.

[0006] In one possible implementation, the electrical interface chip is electrically connected to the computing chip via the local connection assembly; the redistribution layer in the local connection assembly is formed on both sides of the glass substrate; the glass substrate is provided with through-holes; the redistribution layers on both sides of the glass substrate are electrically connected via conductive elements within the through-holes.

[0007] In one possible implementation, the organic substrate has a second groove on the side opposite to the circuit board, and the local connection component is disposed in the second groove.

[0008] In one possible implementation, the organic substrate includes organic dielectric layers formed on the upper and lower sides of the local connection assembly, and a first electrical connector with exposed connection points is formed in the organic dielectric layer on the side opposite to the circuit board, and the redistribution layer of the local connection assembly is connected to the first electrical connector.

[0009] In one possible implementation, the organic substrate includes organic dielectric layers formed on the upper and lower sides of the local connection assembly, and the redistribution layer of the local connection assembly is electrically connected to the computing chip through conductive elements formed in substrate vias in the organic dielectric layers; the electrical interface chip is electrically connected to the computing chip through a second electrical connector, wherein the second electrical connector is formed on the surface of the organic substrate, or the second electrical connector is at least partially embedded in the organic dielectric layer on the side opposite to the circuit board.

[0010] In one possible implementation, the computing chip is electrically connected to the redistribution layer in the local connectivity assembly via microbumps.

[0011] In one possible implementation, the vertical interconnect is a metal pillar or microbump.

[0012] In one possible implementation, the optical waveguide assembly includes a glass waveguide sheet forming a fan-out optical waveguide and an optical fiber array; the fan-out optical waveguide includes an optical signal coupling end and an optical fiber connection end, the optical signal coupling end being connected to the photonic integrated circuit chip, and the optical fiber connection end being connected to the optical fiber array.

[0013] In one possible implementation, at the optical signal coupling end, a plurality of fan-out optical waveguides are arranged with a first waveguide spacing; at the optical fiber connection end, a plurality of fan-out optical waveguides are arranged with a second waveguide spacing; wherein the first waveguide spacing is smaller than the second waveguide spacing.

[0014] Secondly, embodiments of this application provide a method for fabricating a packaging structure, comprising: providing an organic substrate, wherein a local interconnect component is embedded in the organic substrate, the local interconnect component including a glass substrate and a redistribution layer formed on the glass substrate; embedding a photonic integrated circuit chip in the organic substrate; forming a vertical interconnect above the photonic integrated circuit chip, and electrically connecting an electrical interface chip to the photonic integrated circuit chip through the vertical interconnect; electrically connecting the electrical interface chip to a computing chip through the redistribution layer in the local interconnect component or a second electrical connector located on the organic substrate; fabricating an optical waveguide component; and mounting the optical waveguide component above the photonic integrated circuit chip, thereby enabling optical signal coupling between the optical waveguide component and the photonic integrated circuit chip.

[0015] In one possible implementation, the organic substrate is fabricated by: providing a glass substrate, forming glass vias on the glass substrate, and forming redistribution layers on both sides of the glass substrate to form the local connection assembly; providing an organic substrate and etching a second groove on the organic substrate; and embedding the local connection assembly into the second groove.

[0016] In one possible implementation, the organic substrate is fabricated by: providing a glass substrate, forming glass vias on the glass substrate, and fabricating redistribution layers on both sides of the glass substrate to form the local connection assembly; with the local connection assembly as the central layer, forming an organic dielectric layer and a first electrical connector embedded in the organic dielectric layer and connected to the circuit layer on each side surface of the local connection assembly; and exposing the first electrical connector to the organic dielectric layer.

[0017] Thirdly, embodiments of this application provide an electronic device including the packaging structure described in the first aspect of this application.

[0018] The packaging structure provided in this application, by fabricating and independently mounting the local connection components and the optical waveguide components, makes the two functional modules of high-speed electrical interconnection and optical interconnection structurally and technologically independent. The local connection components utilize the low dielectric loss characteristics of glass to achieve high-density, low-loss electrical connections between the photonic integrated circuit chip and the electrical interface chip through a redistribution layer. The optical waveguide components, on the other hand, are used to achieve low-loss, high-precision optical signal coupling between the photonic integrated circuit chip and external optical fiber. Notably, since the packaging structure no longer relies on a single, large-size glass substrate to achieve all functions, but instead integrates the separately optimized electrical and optical interconnect modules into a lower-cost, more resilient organic substrate, it can maintain ultra-high-speed interconnect performance while reducing manufacturing costs, improving process feasibility and packaging structure reliability, making it more suitable for future data centers and high-performance computing fields.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is one of the structural schematic diagrams of the packaging structure provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the packaging structure provided in the embodiments of this application; Figure 3 This is the third schematic diagram of the packaging structure provided in the embodiments of this application; Figure 4 A schematic flowchart illustrating the fabrication method of the packaging structure provided in this application embodiment; Figure 5 This is one of the process diagrams illustrating the fabrication method of the packaging structure provided in the embodiments of this application; Figure 6 This is a second schematic diagram illustrating the process of preparing the packaging structure provided in the embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: 1-Packaging structure, 10-Circuit board, 20-Organic substrate, 201-Organic dielectric layer, 202-First groove, 203-Second groove, 204-Solder ball, 205-Substrate via, 206-First electrical connector, 30-Partial connection assembly, 301-Glass substrate, 302-Rewiring layer, 303-Glass via, 40-Photonic integrated circuit chip, 50-Computing chip, 80-Electrical interface chip, 60-Vertical interconnect, 70-Waveguide assembly, 701-Glass waveguide sheet, 702-Connector, 90-Second electrical connector. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0025] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0026] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0027] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0028] As artificial intelligence and high-performance computing applications continue to deepen, the requirements for data exchange rates between chips within data centers are constantly increasing. Optoelectronic co-packaging architectures tightly integrate optical communication components and computing chips at the packaging level to shorten electrical signal transmission distances and reduce overall power consumption, and have become an important method for achieving high-speed interconnects.

[0029] In related technologies, optoelectronic co-packaging structures typically arrange electronic interface chips and photonic chips side-by-side on a substrate surface, interconnecting them via horizontal wiring. In this approach, the interconnection distance between the computing chip and the electronic interface chip is usually several millimeters. When transmitting high-speed signals, signal attenuation due to dielectric loss and impedance mismatch is quite significant.

[0030] In optical signal connections, photonic chips and fiber optic arrays typically employ end-to-end coupling. This process requires sub-micron level alignment between the fiber end face and the chip waveguide structure, resulting in low assembly efficiency and difficulty in mitigating minute displacements caused by temperature fluctuations or material deformation after sealing. Consequently, coupling efficiency may decline over long-term use.

[0031] To address these issues, co-packaging solutions using glass as the substrate material have emerged, leveraging the dielectric properties and surface flatness of glass to improve signal quality. However, these solutions face the following challenges in practical implementation: the processing cost of vias and metal circuits on glass substrates is high; large-size thin glass is prone to breakage during transportation and assembly; simultaneously, completing high-precision optical waveguide fabrication and chip flip bonding on a glass substrate places extremely high demands on process consistency, affecting the manufacturing cost and yield of the final package structure.

[0032] Based on the above, this application provides a packaging solution that can improve assembly efficiency and reduce material and process costs.

[0033] like Figures 1 to 2 As shown, this application embodiment provides a packaging structure 1. This packaging structure 1 can be used to fabricate optoelectronic co-packaged modules and as an optical interconnect solution in scenarios such as data centers and high-performance computing. When the high-speed electrical signal generated by the computing chip 50 (Application-Specific Integrated Circuit, ASIC) is modulated by the electrical interface chip 80 (Electrical Integrated Circuit, EIC), it is converted into an optical signal by the photonic integrated circuit chip 40 (Photonic Integrated Circuit, PIC), and transmitted to an external optical fiber through the optical waveguide component 70, thereby realizing high-speed, low-loss optoelectronic signal conversion and transmission.

[0034] The circuit board 10 can be a printed circuit board (PCB) to provide mechanical support and external electrical connections for the package structure 1. The circuit board 10 may have multiple conductive pads and wiring layers for electrical connection with the organic substrate 20.

[0035] An organic substrate 20 is disposed on a circuit board 10 and electrically connected to the circuit board 10 via solder balls 204. The organic substrate 20 can be made of organic materials such as epoxy resin and BT resin, which have low unit area cost, high toughness, and are not easily broken. A first groove 202 is provided on the side of the organic substrate 20 facing away from the circuit board 10. The first groove 202 is used to accommodate the photonic integrated circuit chip 40. The internal shape of the first groove 202 is adapted to the external shape of the photonic integrated circuit chip 40, so that the photonic integrated circuit chip 40 can be embedded and fixed in the first groove 202.

[0036] An organic substrate 20 has a substrate through-hole 205, within which a conductive element is formed, constituting a vertical conductive structure penetrating the substrate. The substrate through-hole 205 serves to achieve vertical interconnection between different wiring layers within the organic substrate 20, and to provide power, ground, and low-speed signal transmission channels to the lower circuit board 10 for the computing chip 50 and the electrical interface chip 80. A local connection component 30 is embedded in the organic substrate 20. The local connection component 30 is electrically connected to the organic substrate 20. Specifically, the substrate through-hole 205 in the organic substrate 20 is electrically connected to the redistribution layer 302 in the local connection component 30, thereby achieving electrical interconnection between the two.

[0037] The local interconnect component 30 includes a glass substrate 301 and a redistribution layer 302 on the glass substrate 301. The glass substrate 301 can be made of a glass material with low dielectric constant, low dielectric loss, and good dimensional stability, such as silicate glass. The redistribution layer 302 can be a redistribution layer (RDL). The glass substrate 301 has glass vias 303 and conductive elements (Through Glass Via, TGV) inside them. The conductive elements inside the glass vias 303 are connected to the redistribution layer 302 to achieve high-density, low-loss electrical interconnection. The local interconnect component 30 is mainly used to transmit high-speed signals between the computing chip 50 and the electrical interface chip 80. Therefore, the redistribution layer 302 of the glass substrate 301 can be designed as a double-sided structure, that is, a redistribution layer 302 is provided on both the side of the glass substrate 301 facing and the side away from the circuit board 10. The double-sided wiring structure can be used to realize high-speed signal transmission between the computing chip 50 and the electrical interface chip 80, and can also distribute power to the chip. It is understandable that embedding the local interconnect component 30 into the organic substrate 20 can shorten the high-speed signal interconnect distance between the computing chip 50 and the electrical interface chip 80 to 100–200 μm without changing the overall structure and materials of the organic substrate 20. This reduces signal loss, crosstalk, and reflection, and improves signal integrity and transmission bandwidth. More importantly, replacing the large-size monolithic glass substrate with a small-sized local glass substrate has several advantages. First, the smaller glass substrate has lower processing costs and is less prone to breakage during manufacturing, improving the production yield of the packaging structure and controlling costs. Second, the small glass substrate is surrounded by the organic substrate material, which better buffers the stress generated by thermal expansion and contraction, reducing the risk of delamination or cracking between the glass substrate and the organic substrate, thereby improving the long-term reliability of the entire packaging structure.

[0038] Since the local connection component 30 uses a glass substrate 301 and a redistribution layer 302 is fabricated on the glass substrate 301, the glass material has a low dielectric constant, low dielectric loss, and excellent dimensional stability, enabling more precise impedance control and lower crosstalk and attenuation. At the same time, the matching coefficient of thermal expansion (CTE) of the glass and silicon materials can suppress warping and delamination problems in high-temperature processes, improving the reliability and yield of the packaging structure 1.

[0039] The photonic integrated circuit chip 40 is disposed within the first recess 202. The photonic integrated circuit chip 40 can be fabricated using silicon-based optoelectronic technology and integrates optical components such as optical waveguides, modulators, and detectors. The photonic integrated circuit chip 40 is embedded into the first recess 202 of the organic substrate 20 in a top-mounted manner, with the surface of the photonic integrated circuit chip 40 flush with the surface of the organic substrate 20 to avoid stress stretching issues caused by the packaging process.

[0040] The photonic integrated circuit chip 40 is embedded into the first groove 202 of the organic substrate 20 in a positive mounting manner. Its surface is flush with the surface of the substrate, which can avoid the stress pulling caused by the shrinkage of the filling material in the traditional packaging process and protect the precision optical structure in the photonic integrated circuit chip 40 from damage.

[0041] The computing chip 50 is disposed on the side of the organic substrate 20 opposite to the circuit board 10. The computing chip 50 is electrically connected to the redistribution layer 302 in the local interconnect assembly 30 via a connector. The connector can be a microbump (μBump) used to realize the flip-chip connection between the ASIC chip and the local interconnect assembly 30.

[0042] The electrical interface chip 80 is located on the side of the organic substrate 20 opposite to the circuit board 10. The electrical interface chip 80 is connected to the photonic integrated circuit chip 40 and electrically connected to the computing chip 50 via vertical interconnects 60. The vertical interconnects 60 may include copper pillars and microbumps (μBumps) to achieve vertical electrical interconnection between the electrical interface chip 80 and the photonic integrated circuit chip 40. The distance of the vertical interconnects can be reduced to within a hundred micrometers, thereby reducing signal transmission loss and delay.

[0043] The electrical interface chip 80 is directly connected to the photonic integrated circuit chip 40 through the vertical interconnect 60, which shortens the electrical interconnect distance between the optical interface chip and the photonic integrated circuit chip 40 to the level of hundreds of micrometers, thereby further reducing signal transmission loss and delay.

[0044] In a practical implementation, the electrical interface chip 80 can be connected to the computing chip 50 via the local connection component 30. Based on the excellent dielectric properties of the glass substrate 301, a low-loss, high-integrity transmission path is provided for high-speed signals between the electrical interface chip 80 and the computing chip 50.

[0045] In a specific implementation, the electrical interface chip 80 can also achieve electrical connection through a separate second electrical connector 90, which can be formed on the surface of the organic substrate 20 or at least partially embedded in the interior of the organic substrate 20. This reduces the dependence on the wiring resources of the local connection component 30 and simplifies the process complexity of the local connection component 30. An optical waveguide component 70 is disposed on the organic substrate 20 and at least partially located above the photonic integrated circuit chip 40. The optical waveguide component 70 is connected to the photonic integrated circuit chip 40 to couple optical signals with it. The optical waveguide component 70 can be made of SiO2 material and has an internal optical waveguide structure. One end of the optical waveguide component 70 transmits optical signals to the photonic integrated circuit chip 40 via evanescent wave coupling.

[0046] The computing chip 50, the electrical interface chip 80, and the photonic integrated circuit chip 40, through the aforementioned electrical interconnection, together constitute a high-speed, low-loss electro-optical signal conversion path. The computing chip 50 generates the original electrical signal, the electrical interface chip 80 is used to condition and drive the original electrical signal, and then the photonic integrated circuit chip 40 completes the efficient conversion from electrical signal to optical signal through the optical waveguide component 70.

[0047] Thus, the packaging structure 1 provided in this application embodiment, by separately fabricating and independently installing the local connection component 30 and the optical waveguide component 70, makes the two functional modules of high-speed electrical interconnection and optical interconnection independent in structure and process. The local connection component 30 utilizes the low dielectric loss characteristics of glass to achieve high-density, low-loss electrical connection between the photonic integrated circuit chip 40 and the electrical interface chip 80 through the redistribution layer 302 on it. The optical waveguide component 70 is used to achieve low-loss, high-precision optical signal coupling between the photonic integrated circuit chip 40 and the external optical fiber. It is worth noting that since the packaging structure 1 no longer relies on a single, large-size glass substrate to achieve all functions, but instead integrates the separately optimized electrical and optical interconnect modules into a lower-cost, more resilient organic substrate 20, it can reduce manufacturing costs, improve process feasibility and the reliability of the packaging structure 1 while maintaining ultra-high-speed interconnect performance, making it more suitable for future data centers and high-performance computing fields.

[0048] In some embodiments, the optical waveguide component 70 can be configured to convert a first optical signal parameter at one end of the photonic integrated circuit chip 40 to a second optical signal parameter at one end of the photonic integrated circuit chip 40, the second optical signal parameter being matched to the coupling requirements of the external optical fiber.

[0049] Specifically, this configuration enables the optical waveguide assembly 70 to function as an adapter, resolving the issues of excessively high alignment accuracy requirements and high coupling loss caused by the mismatch in physical parameters such as mode field size and waveguide spacing between the photonic integrated circuit chip 40 and the external optical fiber. For example, through the gradient design of the internal waveguide of the optical waveguide assembly 70, the smaller mode field size and smaller waveguide spacing at its interface with the photonic integrated circuit chip 40 can be converted to a larger mode field size and larger waveguide spacing at its interface with the optical fiber connector 702. This parameter conversion reduces the accuracy requirements for optical fiber alignment, improves the efficiency of optical coupling and assembly yield, and is more suitable for large-scale automated production of the packaging structure 1.

[0050] The optical waveguide component 70 transmits optical signals to the photonic integrated circuit chip 40 via evanescent wave coupling. Compared with end-face coupling, it eliminates the need for end-face polishing and reduces the requirements for alignment accuracy (e.g., from submicron level to several micron level), thereby achieving low-loss coupling.

[0051] The optical waveguide assembly 70 adopts a fan-out structure, which transforms the small-pitch, small-mode waveguide on the side of the photonic integrated circuit chip 40 into a large-pitch, large-mode waveguide on the fiber side, thereby reducing the accuracy requirements of fiber alignment and improving coupling efficiency and assembly yield.

[0052] In some embodiments, such as Figure 1 and Figure 2 As shown, the electrical interface chip 80 is electrically connected to the computing chip 50 through the local connection component 30. This connection method utilizes the low loss and high stability characteristics of the glass substrate 301 to provide a high-quality transmission channel for high-speed signals between the electrical interface chip 80 and the computing chip 50.

[0053] like Figure 1 and Figure 2 As shown, the redistribution layer 302 in the partial connection assembly 30 is formed on both sides of the glass substrate 301. The glass substrate 301 is provided with a through glass via 303, and the redistribution layer 302 on both sides of the glass substrate 301 is electrically connected through conductive elements in the glass via 303.

[0054] Specifically, the redistribution layers 302 on both sides of the glass substrate 301 can be fabricated using a semi-additive process (SAP) or a wafer-level process. The redistribution layers 302 can include multiple layers of ultra-fine redistribution layers, thereby providing high-density input / output interface interconnection between the computing chip 50 and the electrical interface chip 80.

[0055] The glass via 303 is formed by laser drilling or wet etching on the glass substrate 301. The conductive elements inside are formed by electroplating copper or filling with conductive paste, forming a vertical electrical signal channel that penetrates the glass substrate 301. Redistribution layers 302 are fabricated on both sides of the glass substrate 301 and vertical interconnection is achieved through the glass via 303, realizing flexible distribution and routing of signals in the vertical direction.

[0056] The inherent low dielectric constant and low loss characteristics of the glass substrate 301, combined with the precision redistribution layer 302, can provide a stable and controllable characteristic impedance, reducing dielectric loss and crosstalk during signal transmission. Meanwhile, the vertical interconnect path through the glass via 303 is extremely short, and the parasitic inductance and capacitance introduced are far lower than those of long-distance horizontal traces, which helps ensure the integrity of high-frequency signals.

[0057] Thus, by introducing glass vias 303 and dual-sided redistribution layers 302 into the aforementioned local connection component 30, a high-density, high-performance vertical interconnect structure can be constructed within a limited size to achieve ultra-short distance, low-loss, and high-integrity signal transmission between the computing chip 50 and the electrical interface chip 80.

[0058] like Figure 1 As shown, in some embodiments, a specific implementation of a local connection component 30 embedded in an organic substrate 20 is provided: the organic substrate 20 has a second groove 203 on the side opposite to the circuit board 10, and the local connection component 30 is disposed in the second groove 203.

[0059] Specifically, the shape and size of the second groove 203 match the local connection component 30, and its depth is configured such that after the local connection component 30 is embedded, its top surface is approximately flush with the top surface of the organic substrate 20. The second groove 203 can be formed on the organic substrate 20 by a laser ablation process.

[0060] Placing the local connection component 30 within the second recess 203 not only improves the integration and stability of the package structure 1, but also, because the local connection component 30 is embedded and fixed in the second recess 203, its top surface together with the organic substrate 20 forms a relatively flat mounting plane. This creates a favorable structural foundation for subsequently mounting the computing chip 50 and the electrical interface chip 80 onto the redistribution layer 302 of the local connection component 30 using flip-chip bonding.

[0061] Thus, by setting the second groove 203 and embedding the partial connection component 30 therein, the package structure 1 is compact, mechanically robust and easy to integrate, providing a reliable carrier for realizing high-density, low-loss interconnection between the high-performance computing chip 50 and the electrical interface chip 80.

[0062] like Figure 2 As shown, in some embodiments, another specific implementation of embedding the local connection component 30 into the organic substrate 20 is provided: the organic substrate 20 includes organic dielectric layers 201 formed on the upper and lower sides of the local connection component 30. Specifically, the local connection component 30 is sandwiched between two organic dielectric layers 201, forming a three-layer sandwich substrate structure. The redistribution layer 302 of the local connection component 30 is connected to a first electrical connector 206 within the organic dielectric layer 201, so that connection points connected to the redistribution layer 302 are formed on the side opposite to the circuit board 10.

[0063] Specifically, the organic substrate 20 uses a local interconnect component 30 as an intermediate layer, and organic dielectric layers 201 and corresponding wiring structures are fabricated on its upper and lower sides. The local interconnect component 30 itself includes glass vias 303 and redistribution layers 302, forming a basic interconnect framework.

[0064] Subsequently, organic dielectric layers 201 are fabricated on both sides of the local connection component 30 using processes such as semi-additive method. A first electrical connector 206 can be further fabricated inside the organic dielectric layer 201. The first electrical connector 206 is connected to the redistribution layer 302 in the local connection component 30.

[0065] The first electrical connector 206 formed within the organic dielectric layer 201 is connected to the redistribution layer 302 of the local connection assembly 30 and exposed on the organic substrate 20. This is equivalent to exposing connection points on the redistribution layer 302 of the local connection assembly 30, thereby providing an electrical interface for the computing chip 50 and the electrical interface chip 80. These connection points are led out through the redistribution layer 302 and glass vias 303 inside the local connection assembly 30 to achieve electrical connections on both sides, including a high-speed signal interface connecting the computing chip 50 and the electrical interface chip 80.

[0066] The local connection component 30 is encased within two organic dielectric layers 201, forming a stable composite structure similar to a "sandwich". This structure allows stress to be distributed more evenly throughout the organic substrate 20, reducing stress concentration. At the same time, the upper and lower organic dielectric layers 201 provide better support and protection for the brittle glass substrate 301, improving the packaging substrate's resistance to warping, impact, and thermal fatigue during subsequent processing and use.

[0067] The computing chip 50 and the electrical interface chip 80 are soldered to connection points led out from the organic mechanism layer via microbumps. This connection method shortens the interconnect distance between chips to the level of hundreds of micrometers, reduces parasitic effects and transmission losses on the signal path, and provides channel quality for high-speed signal transmission.

[0068] like Figure 3 As shown, in some embodiments, another specific implementation of the local connection component 30 being embedded in the organic substrate 20 is provided: the organic substrate 20 includes an organic dielectric layer 201 formed on the upper and lower sides of the local connection component 30, and the redistribution layer 302 of the local connection component 30 is electrically connected to the computing chip 50 through conductive elements in the substrate vias 205 formed in the organic dielectric layer 201.

[0069] The electrical interface chip 80 is electrically connected to the computing chip 50 via the second electrical connector 90, wherein the second electrical connector 90 is formed on the surface of the organic substrate 20, or the second electrical connector 90 is at least partially embedded in the organic dielectric layer 201 on the side opposite to the circuit board 10.

[0070] In this structure, the organic substrate 20 is constructed by stacking layers on the upper and lower sides of the local connection component 30, such that the local connection component 30 is encased as a core layer within two organic dielectric layers 201. The redistribution layer 302 of the local connection component 30 is connected to the substrate via 205 formed in the organic dielectric layer 201, thereby achieving electrical connection with the computing chip 50 located on the top layer.

[0071] In this configuration, the electrical connection between the electrical interface chip 80 and the computing chip 50 does not pass through the local connection component 30. Specifically, the two are directly interconnected through a separate second electrical connector 90. The second electrical connector 90 can be a conventional wiring (i.e., surface wiring) fabricated on the top surface of the organic substrate 20, or it can be a rewiring layer (i.e., buried wiring) that is at least partially embedded inside the top organic dielectric layer 201.

[0072] Thus, when the local connection component 30 is sandwiched between two organic dielectric layers 201, an independent second electrical connector 90 provides an extremely short signal transmission path for the interconnection between the computing chip 50 and the electrical interface chip 80, independent of the local connection component 30. When a few signals have high requirements for transmission loss, they can be transmitted through the low-loss glass lines in the local connection component 30. However, for a large number of signals between the computing chip 50 and the electrical interface chip 80 that are sensitive to transmission delay, they can be transmitted directly and through a short path via the second electrical connector 90, thereby reducing signal transmission delay.

[0073] Furthermore, the wiring requirements of the local interconnect component 30 are alleviated, allowing the redistribution layer 302 of the local interconnect component 30 to focus more on providing data transmission for the few most critical high-speed signals. Its shape, size, and location can be designed more flexibly, no longer constrained to be positioned directly below the connection between the computing chip 50 and the electrical interface chip 80, thus creating favorable conditions for layout optimization and size reduction of the package structure. In some embodiments, the computing chip 50 is electrically connected to the redistribution layer 302 in the local interconnect component 30 via microbumps. The vertical interconnect 60 includes metal pillars formed on the electrodes of the photonic integrated circuit chip 40 and microbumps formed between the local interconnect component 30 and the electrical interface chip 80.

[0074] Specifically, the computing chip 50 is electrically connected to the local interconnect component 30 via a flip-chip bonding process. This connection method concentrates the high-speed signal transmission path between the computing chip 50 and the electrical interface chip 80 entirely within the local interconnect component 30, reducing the interconnect distance to as short as 100-200 micrometers.

[0075] The metal pillars in the vertical interconnect 60 can be electroplated copper pillars. The vertical interconnect 60 uses a combination of copper pillars and microbumps to directly connect the electrodes of the electrical interface chip 80 and the photonic integrated circuit chip 40, thereby establishing a vertical interconnect path between the two.

[0076] Signals between the computing chip 50 and the electrical interface chip 80 are transmitted through the local connection component 30, shortening the transmission path. The electrical interface chip 80 and the photonic integrated circuit chip 40 are directly connected through the vertical interconnect 60, avoiding long-distance horizontal wiring.

[0077] In this way, high-speed signals between computing chip 50 and electrical interface chip 80 are transmitted through fine circuitry within local connection component 30, resulting in a short path and controllable impedance. Signals between electrical interface chip 80 and photonic integrated circuit chip 40 are transmitted vertically through copper pillars, reducing signal attenuation and crosstalk, thereby providing a reliable electrical connection for the transmission of high-speed signals such as 112G / 224G PAM4.

[0078] In some embodiments, the optical waveguide assembly 70 includes a glass waveguide sheet 701 with a fan-out optical waveguide and an optical fiber array. The fan-out optical waveguide includes an optical signal coupling end and an optical fiber connection end. The optical signal coupling end is connected to the photonic integrated circuit chip 40 via evanescent wave coupling, and the optical fiber connection end is mated to the optical fiber array via a pluggable connector 702. The glass waveguide sheet 701 can be formed into a waveguide structure using an ion exchange process.

[0079] In some embodiments, the optical signal coupling end of the fan-out optical waveguide has a first waveguide spacing that matches the photonic integrated circuit chip 40, and the optical fiber connection end has a second waveguide spacing that matches the optical fiber array, wherein the second waveguide spacing is greater than the first waveguide spacing. The waveguide structure achieves the transition from the first waveguide spacing to the second waveguide spacing through a gradient design.

[0080] The glass waveguide sheet 701 with fan-out optical waveguides serves to solve the mismatch problem of mode field size and waveguide spacing between the photonic integrated circuit chip 40 and the standard optical fiber. The small-pitch design at the optical signal coupling end allows for direct docking with the high-density waveguide array of the photonic integrated circuit chip 40, while the large-pitch design at the optical fiber connection end facilitates reliable connection with standard-pitch optical fiber arrays.

[0081] Thus, by converting the waveguide spacing, the small-pitch waveguide at the end of the photonic integrated circuit chip 40 is transformed into a large-pitch waveguide at the end of the fiber array, reducing the alignment accuracy requirements during assembly and improving assembly efficiency. The optical waveguide assembly 70 provides a reliable optical interface between the photonic integrated circuit chip 40 and the external fiber optic network.

[0082] Secondly, such as Figure 4 As shown in the embodiments of this application, a method for preparing a packaging structure is also provided, which includes the following steps: Step 100: Provide an organic substrate.

[0083] The organic substrate contains embedded local interconnect components, which include a glass substrate and a redistribution layer formed on the glass substrate.

[0084] Cavities for embedding local interconnect components can be fabricated on an organic substrate using laser grooving. The pre-fabricated local interconnect components are then precisely embedded into the cavities, and underfill adhesive is used to fill the gaps for fixation and insulation protection. The fabrication of the local interconnect components includes: forming glass through-holes in a glass substrate using laser drilling technology; fabricating redistribution layers on both sides of the glass substrate using electroplating; and further fabricating microbumps on the redistribution layers.

[0085] Step 200: Embed the photonic integrated circuit chip in the organic substrate.

[0086] Laser grooving is performed on the organic substrate to form a first groove for embedding the photonic integrated circuit chip; after attaching a chip bonding film to the bottom of the photonic integrated circuit chip, it is placed in the groove; glue is filled into the groove to fix the photonic integrated circuit chip and the surface of the organic substrate is polished to maintain the overall planarity of the organic substrate and the photonic integrated circuit chip.

[0087] Step 300: Form a vertical interconnect above the photonic integrated circuit chip and electrically connect the electrical interface chip to the photonic integrated circuit chip through the vertical interconnect.

[0088] A copper pillar structure is formed around the photonic integrated circuit chip using pulse electroplating technology to construct vertical interconnect channels. Then, a redistribution layer is fabricated on the surface of an organic substrate using a semi-additive process. This redistribution layer electrically connects the vertical interconnects to local connection components and also provides pads for the electrical interface chip. Finally, the electrical interface chip is flip-chip bonded to the pads above the vertical interconnects via microbumps on its bottom.

[0089] Step 400: Electrically connect the electrical interface chip to the computing chip via a redistribution layer in the local connection assembly or a second electrical connector located on the organic substrate.

[0090] The computing chip is flip-chip bonded to the corresponding pads on the local interconnect component via microbumps, allowing high-speed signals between the computing chip and the electrical interface chip to be transmitted through the redistribution layer and glass vias in the local interconnect component. The interconnect distance can be controlled within the range of 100–200 micrometers.

[0091] Alternatively, the electrical interface chip and the computing chip can be electrically connected via a second electrical connector located within the organic substrate. Specifically, a metal wiring is fabricated on the top or subsurface layer of the organic substrate using a semi-additive process to form the second electrical connector. Subsequently, the computing chip and the electrical interface chip are flip-chip bonded to corresponding pads at both ends of the second electrical connector via microbumps.

[0092] Step 500: Fabricate optical waveguide components.

[0093] Waveguide structures are formed in glass substrates using ion exchange processes; fan-out optical waveguides are fabricated using photolithography and etching processes, with a waveguide spacing of 50 micrometers at the optical signal coupling end and a waveguide spacing of 250 micrometers at the fiber connection end, realizing the conversion of mode field size and spacing from chip standard to fiber standard.

[0094] Step 600: Attach the optical waveguide assembly above the photonic integrated circuit chip to enable optical signal coupling between the optical waveguide assembly and the photonic integrated circuit chip.

[0095] The optical signal coupling end of the optical waveguide component is aligned with the waveguide structure of the photonic integrated circuit chip through evanescent wave coupling. Submicron-level positioning accuracy is achieved using passive alignment technology, and the component is fixed by applying coupling adhesive. The optical fiber connection end is connected to the external optical fiber array through a pluggable connector to complete the construction of the optical signal transmission link.

[0096] In some embodiments, such as Figure 5 As shown, step 100 includes steps 1001 to 1002: Step 1001: Provide a glass substrate, form glass through holes in the glass substrate, and fabricate redistribution layers on both sides of the glass substrate to form a local connection assembly.

[0097] like Figure 5 (a) and Figure 5 As shown in (b), a glass substrate with a low dielectric constant and excellent dimensional stability is provided. A through-hole can then be formed in the glass substrate using laser drilling technology.

[0098] Redistribution layers are fabricated on both sides of a glass substrate using semiconductor processes, with each side comprising multiple redistribution layers. These redistribution layers contain ultra-fine wiring with a linewidth / spacing of less than 2 μm. Conductive elements are formed within glass vias using electroplating, achieving electrical connection between the redistribution layers on both sides.

[0099] like Figure 5 As shown in (c), microbumps are fabricated on the redistribution layer, including a C2 microbump for chip-to-chip interconnection and a C4 microbump for chip-to-organic substrate interconnection.

[0100] Step 1002: Provide an organic substrate and fabricate a second groove on the organic substrate; embed the partial connection component into the second groove.

[0101] like Figure 5As shown in (d), an organic substrate with a complete wiring layer is provided. A second groove matching the size of the local interconnect component can be precisely etched on the top layer of the organic substrate using a laser ablation process. The prepared local interconnect component is precisely embedded in the second groove, with its top surface flush with the top surface of the organic substrate; the gap between the local interconnect component and the organic substrate is filled with underfill adhesive to achieve mechanical fixation and stress buffering.

[0102] Thus, the ultra-fine redistribution layer and glass vias on the glass substrate provide high-density, low-loss interconnect channels for the computing chip and electrical interface chip, while the structure embedded in the organic substrate ensures the overall mechanical strength and thermal reliability of the package. This step-by-step fabrication and re-integration method reduces the process difficulty of coordinating and optimizing electrical interconnects and optical waveguides on the monolithic glass substrate, improving manufacturing yield and cost-effectiveness.

[0103] In some embodiments, such as Figure 6 As shown, step 100 may include steps 1003 to 1005: Step 1003: Provide a glass substrate, form glass through holes in the glass substrate, and fabricate redistribution layers on both sides of the glass substrate to form a local connection assembly.

[0104] Step 1004: With the local connection component as the center, an organic dielectric layer and a first electrical connector embedded in the organic dielectric layer and connected to the circuit layer are formed on each side surface of the local connection component.

[0105] like Figure 6 (a) Figure 6 (b) and Figure 6 As shown in (c), a glass substrate with a low dielectric constant and excellent dimensional stability is provided. A through-hole can then be formed in the glass substrate using laser drilling technology.

[0106] Redistribution layers are fabricated on both sides of a glass substrate using semiconductor processes, with each side comprising multiple redistribution layers. These redistribution layers contain ultra-fine wiring with a linewidth / spacing of less than 2 μm. Conductive elements are formed within glass vias using electroplating, achieving electrical connection between the redistribution layers on both sides.

[0107] During the formation of the organic dielectric layer, a first electrical connector that is connected to the redistribution layer is formed within the organic dielectric layer, such as by pattern etching and metal filling to form a first electrical connector perpendicular to the glass substrate.

[0108] Step 1005: Expose the first electrical connector to the organic dielectric layer to form the connection point of the redistribution layer exposed on the organic substrate.

[0109] like Figure 6As shown in (d), an organic substrate is fabricated using a stacked process, centered on a local interconnect component. Specifically, organic dielectric layers and first electrical connectors are alternately stacked on the upper and lower sides of the local interconnect component using a semi-additive process. A vertical interconnect structure is formed through the first electrical connectors within the organic dielectric layers, and the electrical connection between the redistribution layers on the upper and lower sides of the local interconnect component is achieved using glass vias. Finally, the first electrical connectors form exposed connection points in the topmost organic dielectric layer for flip-chip bonding to the computing chip and electrical interface chip.

[0110] Thus, by stacking local interconnect components as built-in core layers, a composite substrate structure is formed. This utilizes the performance advantages of glass substrates in high-speed interconnection, combines the advantages of organic dielectric layers in complex wiring and cost control, and improves the overall structural strength and reliability of the package.

[0111] In some embodiments, step 100 may include steps 1006 to 1009: Step 1007: Provide a glass substrate, form glass through holes in the glass substrate, and fabricate redistribution layers on both sides of the glass substrate to form a partial connection assembly.

[0112] Step 1008: With the local connection component as the central layer, an organic dielectric layer is formed on the upper and lower sides of the local connection component, and a substrate through-hole is formed in the organic dielectric layer. A conductive element connected to the redistribution layer is formed in the substrate through-hole.

[0113] Step 1009: Metal wiring is fabricated in the top layer or organic dielectric layer of the organic substrate to form a second electrical connector connecting the computing chip and the electrical interface chip.

[0114] This application also provides an electronic device, including the packaging structure provided in any embodiment of this application, and therefore possesses all the beneficial effects of the packaging structure of this application, which will not be repeated here. This electronic device can be a network switching device, such as a data center core switch or router; it can be a high-performance computing device, such as a computing cluster or server; or it can be an optoelectronic fusion processing device, such as a switching chip or smart network card.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A package structure, characterized by, The package structure comprises: a circuit board; an organic substrate arranged on the circuit board and electrically connected to the circuit board, the organic substrate being provided with a first recess on a side facing away from the circuit board; a local connection assembly embedded in the organic substrate and electrically connected to the organic substrate, the local connection assembly comprising a glass substrate and a redistribution layer formed on the glass substrate; a photonic integrated circuit chip arranged in the first recess; a computing chip arranged on the side of the organic substrate facing away from the circuit board, the computing chip being electrically connected to the redistribution layer in the local connection assembly; an electrical interface chip arranged on the side of the organic substrate facing away from the circuit board, the electrical interface chip being connected to the photonic integrated circuit chip through a vertical interconnect and being electrically connected to the computing chip; an optical waveguide assembly arranged on the organic substrate and at least partially above the photonic integrated circuit chip, the optical waveguide assembly being connected to the photonic integrated circuit chip for optical signal coupling with the photonic integrated circuit chip.

2. The package structure according to claim 1, wherein: the electrical interface chip is electrically connected to the computing chip through the local connection assembly; the redistribution layer in the local connection assembly is formed on both sides of the glass substrate, the glass substrate is provided with a through glass via, and the redistribution layers on both sides of the glass substrate are electrically connected through a conductive element in the through glass via.

3. The package structure according to claim 2, wherein: the side of the organic substrate facing away from the circuit board is provided with a second recess, and the local connection assembly is arranged in the second recess.

4. The package structure according to claim 2, wherein: the organic substrate comprises organic dielectric layers formed on both sides of the local connection assembly, a first electrical connection element with a connection point is formed in the organic dielectric layer on the side facing away from the circuit board, and the redistribution layer of the local connection assembly is connected to the first electrical connection element.

5. The package structure according to claim 1, wherein: the organic substrate comprises organic dielectric layers formed on both sides of the local connection assembly, the redistribution layer of the local connection assembly is electrically connected to the computing chip through a conductive element in a substrate via formed in the organic dielectric layer; the electrical interface chip is electrically connected to the computing chip through a second electrical connection element, wherein the second electrical connection element is formed on the surface of the organic substrate, or the second electrical connection element is at least partially embedded in the organic dielectric layer on the side facing away from the circuit board.

6. The package structure according to any one of claims 1 to 5, wherein: the optical waveguide assembly comprises a glass waveguide sheet formed with fan-out optical waveguides and an optical fiber array; the fan-out optical waveguides comprise optical signal coupling ends and optical fiber connection ends, the optical signal coupling ends are connected to the photonic integrated circuit chip, and the optical fiber connection ends are connected to the optical fiber array.

7. The package structure according to claim 6, wherein: The plurality of fan-out optical waveguides are arranged at a first waveguide spacing at the optical signal coupling end; and the plurality of fan-out optical waveguides are arranged at a second waveguide spacing at the optical fiber connecting end. The first waveguide spacing is smaller than the second waveguide spacing.

8. A method for preparing a packaging structure, characterized in that, The method comprises: providing an organic substrate, wherein a local connection assembly is embedded in the organic substrate, the local connection assembly comprising a glass substrate and a redistribution layer formed on the glass substrate; embedding a photonic integrated circuit chip in the organic substrate; forming a vertical interconnect above the photonic integrated circuit chip, and electrically connecting an electrical interface chip to the photonic integrated circuit chip through the vertical interconnect; electrically connecting the electrical interface chip to a computing chip through the redistribution layer in the local connection assembly or a second electrical connection on the organic substrate; preparing an optical waveguide assembly; and mounting the optical waveguide assembly above the photonic integrated circuit chip, so that the optical waveguide assembly and the photonic integrated circuit chip are optically coupled.

9. The method of claim 8, wherein the method further comprises: The organic substrate is prepared by: providing a glass substrate, forming a glass via on the glass substrate, and forming a redistribution layer on both sides of the glass substrate to form the local connection assembly; providing an organic substrate, and forming a second recess on the organic substrate; embedding the local connection assembly in the second recess; or providing a glass substrate, forming a glass via on the glass substrate, and forming a redistribution layer on both sides of the glass substrate to form the local connection assembly; forming an organic medium layer on each side surface of the local connection assembly with the local connection assembly as a center layer, and embedding a first electrical connection in the organic medium layer and connecting the first electrical connection to the circuit layer; and exposing the first electrical connection outside the organic medium layer.

10. An electronic device, comprising: The package structure comprises the package structure according to any one of claims 1 to 7. The first waveguide spacing is smaller than the second waveguide spacing. The method comprises: providing an organic substrate, wherein a local connection assembly is embedded in the organic substrate, the local connection assembly comprising a glass substrate and a redistribution layer formed on the glass substrate; embedding a photonic integrated circuit chip in the organic substrate; forming a vertical interconnect above the photonic integrated circuit chip, and electrically connecting an electrical interface chip to the photonic integrated circuit chip through the vertical interconnect; electrically connecting the electrical interface chip to a computing chip through the redistribution layer in the local connection assembly or a second electrical connection on the organic substrate; preparing an optical waveguide assembly; and mounting the optical waveguide assembly above the photonic integrated circuit chip, so that the optical waveguide assembly and the photonic integrated circuit chip are optically coupled. The organic substrate is prepared by: providing a glass substrate, forming a glass via on the glass substrate, and forming a redistribution layer on both sides of the glass substrate to form the local connection assembly; providing an organic substrate, and forming a second recess on the organic substrate; embedding the local connection assembly in the second recess; or providing a glass substrate, forming a glass via on the glass substrate, and forming a redistribution layer on both sides of the glass substrate to form the local connection assembly; forming an organic medium layer on each side surface of the local connection assembly with the local connection assembly as a center layer, and embedding a first electrical connection in the organic medium layer and connecting the first electrical connection to the circuit layer; and exposing the first electrical connection outside the organic medium layer. The package structure comprises the package structure according to any one of claims 1 to 7.

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