Information processing device, information processing method, program, and circuit information

Abstract

To generate a combination optimization problem at high speed.SOLUTION: An information processing device according to an embodiment performs processing for data. The information processing device comprises a solver device and an information processing circuit. The information processing circuit acquires data. The information processing circuit generates a combination optimization problem on the basis of the data, and causes the solver device to solve the combination optimization problem. A first portion weight group, which is a part of a plurality of weighted values, is the same as a second portion weight group, which is a portion of others. The information processing circuit writes the first portion weight group and the second portion weight group into a common region in a first memory, and gives first information indicative of a storage location of each of the plurality of weighted values in the first memory to the solver device. The solver device reads the plurality of weighted values from the first memory and finds the solution, on the basis of the first information.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to an information processing device, an information processing method, a program, and circuit information. [Background technology]

[0002] In many application fields, such as control, finance, communication, logistics, and chemistry, system optimization is often mathematically reduced to a combinatorial optimization problem. Information processing systems have been proposed that realize various information processing functions, such as recognition, judgment, and planning, and improve the efficiency of such functions by solving combinatorial optimization problems.

[0003] A combinatorial optimization problem is a problem in which a cost function is defined with arguments being multiple decision variables (e.g., discrete variables) that represent the state of the system to be optimized, and the combination of values ​​of multiple decision variables that minimizes the defined cost function is solved. The state of the system represented by multiple decision variables is called a solution. In a combinatorial optimization problem, the number of states that can be taken as a solution increases exponentially as the number of decision variables increases. The increase in the number of states that can be taken as a solution is called combinatorial explosion. Combinatorial optimization, which involves selecting an optimal solution from all candidate solutions, is known to be a computationally difficult problem. Performing large-scale combinatorial optimization in a short period of time remains a challenging task.

[0004] In recent years, a special-purpose device called an Ising machine that searches for the ground state of an Ising spin model has been attracting attention. The problem of searching for the ground state of an Ising spin model is called the Ising problem. The Ising problem is a combinatorial optimization problem that minimizes a cost function given by a quadratic function of Ising spin, which is one of the binary variables. In the Ising problem, the cost function is called the Ising energy. Many practical combinatorial optimization problems can be converted into Ising problems. An Ising machine can solve an Ising problem quickly. Therefore, many practical combinatorial optimization problems can be solved quickly using an Ising machine.

[0005] However, when the situation is constantly changing, a new combinatorial optimization problem may be generated and solved in response to the change in the situation, and processing may be performed based on the obtained solution. For example, when applying a combinatorial optimization problem to a trading device that electronically trades stocks in a financial market, a new combinatorial optimization problem is generated in response to fluctuations in stock prices, and trading is performed based on the obtained solution. Also, when applying a combinatorial optimization problem to a control system that controls a moving object based on images of captured surrounding scenery, a new combinatorial optimization problem is generated in response to changes in the image, and the moving object is controlled based on the obtained solution.

[0006] In such a system, a combinatorial optimization problem is generated each time a situation changes, and the generated combinatorial optimization problem is provided to a solver device. For example, when a combinatorial optimization problem is an Ising problem of size N, N×N quadratic coefficients and N linear coefficients must be generated and provided to the solver device. For this reason, in such a system, in order to improve the responsiveness from when a situation changes to when processing is performed based on the solution, it is preferable to be able to generate a combinatorial optimization problem quickly and provide it to the solver device. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6629864 [Patent Document 2] JP 2021-060864 A [Patent Document 3] JP 2019-145010 A [Patent Document 4] JP 2019-159566 A [Patent Document 5] Patent Publication No. 2021-043667 [Patent Document 6] JP 2021-043589 A [Non-patent literature]

[0008] [Non-Patent Document 1] Hayato Goto, Kosuke Tatsumura and Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems,” Science Advances 5, eaav2372, 2019 [Non-Patent Document 2] Hayato Goto, Kotaro Endo, Masaru Suzuki, Yoshisato Sakai, Taro Kanao, Yohei Hamakawa, Ryo Hidaka, Masaya Yamasaki and Kosuke Tatsumura, “High-performance combinatorial optimization based on classical mechanics”, Science Advances 7, eabe7953, 2021 Summary of the Invention [Problem to be solved by the invention]

[0009] The problem to be solved by the present invention is to generate combinatorial optimization problems at high speed. [Means for solving the problem]

[0010] An information processing device according to an embodiment executes processing on data. The information processing device includes a solver device that solves a combinatorial optimization problem, and an information processing circuit. The information processing circuit acquires the data. The information processing circuit generates the combinatorial optimization problem based on the data, and causes the solver device to solve the combinatorial optimization problem. A cost function in the combinatorial optimization problem includes a plurality of decision variables and a plurality of weight values. A term included in the cost function is expressed by multiplying one or more decision variables of the plurality of decision variables by any one of the plurality of weight values. A first partial weight group that is a part of the plurality of weight values ​​is the same as a second partial weight group that is the other part. The solver device includes a first memory that stores the plurality of weight values. In generating the combinatorial optimization problem, the information processing circuit generates the plurality of weight values ​​based on the data, and writes the plurality of weight values ​​to the first memory. The information processing circuit writes the first and second partial weight groups to a common area in the first memory and provides the solver device with first information indicating storage positions of the weight values ​​in the first memory. The solver device reads the weight values ​​from the first memory based on the first information to find a solution. [Brief description of the drawings]

[0011] [Figure 1] A diagram showing a model of the Ising problem. [Diagram 2] FIG. 2 illustrates internal variables used by the simulated branching algorithm. [Diagram 3] 4 is a flowchart showing a process flow of a simulated branching machine. [Figure 4] FIG. 1 is a diagram showing a configuration of an information processing system including an Ising machine. [Diagram 5] FIG. 1 is a diagram showing a configuration of an information processing system including a simulated branching machine. [Figure 6] Diagram of the market system. [Figure 7]FIG. 1 is a diagram showing the arrangement of an information processing apparatus according to a first embodiment. [Figure 8] FIG. 4 is a diagram showing processing timing of the information processing device. [Figure 9] FIG. 13 shows pseudocode for generating the Q matrix. [Figure 10] FIG. 13 is a diagram showing an example of a plurality of weight values. [Figure 11] FIG. 1 is a diagram showing M partial regions, K patterns, and pattern information. [Figure 12] FIG. 11 is a configuration diagram of a solver device according to a second embodiment. [Figure 13] FIG. 13 is a configuration diagram of a solver device according to a third embodiment. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] A diagram showing the matrix (J). [Figure 17] FIG. 11 is a configuration diagram of a matrix calculation circuit according to a third embodiment. [Figure 18] FIG. 13 is a configuration diagram of a matrix calculation circuit according to a fourth embodiment. [Figure 19] FIG. 1 is a diagram showing an example of the configuration of a control system. [Figure 20] FIG. 2 is a hardware configuration diagram of an information processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Premise) First, terms and techniques that are the basis for the description of the embodiments will be described.

[0013] A combinatorial optimization problem is a problem in which a cost function is defined with multiple decision variables (e.g., discrete variables) representing the state of a system to be optimized as arguments, and a combination of values ​​of multiple decision variables that minimizes the defined cost function is solved. The cost function includes multiple decision variables representing the state of the system as arguments, and is a linear or higher function of the multiple decision variables. For example, the cost function is expressed by a linear or quadratic function of the multiple decision variables. The cost function may be a cubic or higher function of the multiple decision variables. In other words, the cost function is a function that sums up multiple terms. Each of the multiple terms is a function that multiplies one or more of the multiple decision variables, up to a predetermined number of them, by a coefficient. In addition, the coefficient in each of the multiple terms is a real number and is also called a weight value. In other words, each of the multiple terms that constitute the cost function is expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values.

[0014] The state of the system, represented by the decision variables, is called a solution. The universe of possible solutions for the state of the system is called the solution space. The solution that gives the minimum of the cost function is called an exact solution. The solution that gives a value close to the minimum of the cost function is called a good solution.

[0015] An exact solution method is a method for finding an exact solution that gives a minimum value of a cost function for a combinatorial optimization problem, and is a method that guarantees that the solution is an exact solution.

[0016] A heuristic solution is a solution method for combinatorial optimization problems that finds an exact solution that minimizes the cost function or a good solution that is close to the minimum of the cost function. Heuristic solutions are also called discovery solutions. Heuristic solutions do not guarantee the accuracy of the solution, that is, an index that indicates how close the solution is to the minimum of the cost function. Heuristic solutions can output a solution with practically significant accuracy in a shorter solution time than exact solutions.

[0017] The computational complexity of a solution to a combinatorial optimization problem is the amount of calculations required to obtain a solution, such as the number of multiply-and-accumulate operations. The solution time required to obtain a solution to a combinatorial optimization problem depends not only on the computational complexity but also on the configuration of the computer that processes the calculations. For example, the solution time becomes shorter as the computer's computational parallelism and operating frequency increase.

[0018] A QUBO (Quadratic Unconstrained Binary Optimization) problem is an unconstrained quadratic optimization problem in which the decision variables are binary. In a QUBO problem, each of a number of terms included in a cost function is expressed by a linear or quadratic expression of the decision variables. In a narrowly defined QUBO problem, the decision variables are binary variables of 0 or 1. In this embodiment, the QUBO problem represents a narrowly defined problem in which the decision variables are 0 or 1. In a narrowly defined QUBO problem, the decision variables may also be called bit variables.

[0019] The cost function for the QUBO problem is H in Eq. (1). total_QUBO It is expressed by:

number

[0020] FIG. 1 is a diagram showing a model of the Ising problem. The Ising problem is a problem of searching for the ground state of the Ising model. The Ising problem is one of the QUBO problems. The decision variables of the Ising problem represent discrete variables of -1 or +1.

[0021] The cost function for the Ising problem is H in Eq. (2). total_Ising It is expressed by:

number

[0022] If the decision variable is s i The QUBO problem corresponds to the problem of searching for the ground state of the Ising model, which is one of the magnetic models in statistical mechanics. i is sometimes called the spin variable. The number of decision variables, N, is sometimes called the spin number. H total_Ising is sometimes called the Zing energy. total_Ising N s for which i The vector represented by is sometimes called the ground state (ground spin configuration).

[0023] The cost function of the QUBO problem and the cost function of the Ising problem differ only in the value of the constant. Therefore, the QUBO problem and the Ising problem are the same as combinatorial optimization problems. In other words, the QUBO problem and the Ising problem can be converted into each other. For example, the Ising problem and the QUBO problem can be converted into each other by formula (3-1), formula (3-2), formula (3-3), and formula (3-4).

number

[0024] QUBO and Ising problems are known to be NP-complete. That is, many NP-hard problems can be transformed into QUBO or Ising problems in polynomial time. Therefore, many practical combinatorial optimization problems can be transformed into QUBO or Ising problems.

[0025] An Ising machine is a device that solves Ising problems. Most Ising machines solve Ising problems using heuristic solutions. Ising machines based on various principles, such as electronic engineering, optics, quantum mechanics, and statistical mechanics, have been proposed. Many Ising machines can output exact or good solutions in a short time.

[0026] The simulated branching algorithm is an algorithm for solving combinatorial optimization problems. The simulated branching algorithm is a heuristic solution algorithm.

[0027] The simulated bifurcation algorithm is shown in, for example, Non-Patent Documents 1-2 and Patent Documents 2-6. The simulated bifurcation algorithm was discovered based on the idea of ​​a quantum mechanical optimization method based on the quantum adiabatic theorem, and is therefore also called a quantum-inspired algorithm. The simulated bifurcation algorithm can solve a combinatorial optimization problem in which the cost function is a quadratic function of multiple decision variables. The simulated bifurcation algorithm can also solve a combinatorial optimization problem in which the cost function is a cubic or higher function of multiple decision variables, that is, a HUBO (Higher Order Binary Optimization) problem. For example, a simulated bifurcation algorithm that solves a HUBO problem is shown in Patent Document 5. The simulated bifurcation algorithm can also solve a combinatorial optimization problem in which some or all of the multiple decision variables include variables with continuous values. A simulated bifurcation algorithm that solves a combinatorial optimization problem in which some or all of the multiple decision variables include variables with continuous values ​​is shown in Patent Document 6.

[0028] The simulated bifurcation machine is a computing device that executes processing according to a simulated bifurcation algorithm. The simulated bifurcation machine that solves the QUBO problem or the Ising problem is an example of an Ising machine. In this embodiment, the simulated bifurcation machine solves the Ising problem.

[0029] FIG. 2 is a diagram showing the internal variables used by the simulated branching algorithm.

[0030] The simulated branching algorithm is a method to determine the number of decision variables (s1 to s N When solving a combinatorial optimization problem in which the cost function is expressed using N ) and N momentum variables (y1~y N ) is used. That is, the simulated bifurcation algorithm uses 2×N internal variables.

[0031] N location variables (x i ) is the number of N decision variables (si ) in one-to-one correspondence. That is, the i-th position variable (x i ) is the i-th decision variable (s i ) corresponding to the N momentum variables (y i ) is the number of N decision variables (s i ) corresponds to the i-th momentum variable (y i ) is the i-th decision variable (s i )

[0032] 3 is a flow chart showing the flow of processing of the simulated branching machine. The simulated branching machine executes processing according to the simulated branching algorithm in the flow shown in FIG.

[0033] First, in S11, the simulated bifurcation machine obtains an Ising problem. Specifically, the simulated bifurcation machine obtains J, which is a matrix including N×N coefficients, and h, which includes N bias coefficients.

[0034] Next, in S12, the simulated branching machine calculates 2×N internal variables, i.e., N position variables (x1 to x N ) and N momentum variables (y1~y N ) is initialized. The simulated branching machine initializes N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N The initial values ​​of N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N The initial value of x1 to x2 may be generated by a random number generator or may be set to a predetermined value. Since the simulated branching machine is a heuristic, the initial value of x1 to x2 may be set to a predetermined value even if the same problem is being solved. N ) and the initial values ​​of N momentum variables (y1~y N) is different, a different good solution may be output.

[0035] Next, the simulated branching machine repeats the process from S14 to S16 a preset number of times (loop process between S13 and S17). The process from S14 to S16 is performed by iterating N position variables (x1 to x N ) by a matrix containing weight values ​​of N rows and N columns, and N ) and N momentum variables (y1~y N ) is a time evolution process.

[0036] In S14, the simulated bifurcation machine calculates N momentum variables (y1 to y N ) in the y update process. The simulated bifurcation machine updates the i-th momentum variable (y i In the update process of N position variables (x1~x N ) and the i-th position variable (x i ) and the other (N-1) location variables (x 1~i-1, x i+1~N ) and N coefficients (J i,j ) and the i-th bias coefficient (h i ) and the i-th momentum variable (y i ) to update the

[0037] Next, in S15, the simulated branching machine calculates N position variables (x1 to x N ) in the x update process. The simulated branch machine updates the i-th position variable (x i In the update process of the i-th momentum variable (y i ) to the i-th position variable (x i ) to update the

[0038] The simulated branching machine may execute the process of S14 and the process of S15 in an interchangeable order.

[0039] Next, in S16, the simulated branching machine calculates N position variables (x1 to x N ), the simulated branching machine performs wall processing on the position variables whose absolute values ​​exceed 1. Furthermore, the simulated branching machine also performs wall processing on the momentum variables corresponding to the position variables whose absolute values ​​exceed 1. For example, in wall processing, the simulated branching machine changes the absolute value of the position variable whose absolute value exceeds 1 to 1 or a value smaller than 1 while keeping the sign the same. Also, for example, in wall processing, the simulated branching machine changes the value of the momentum variable corresponding to the position variable whose absolute value exceeds 1 to 0.

[0040] The simulated bifurcation algorithm has variations in the calculation of x-update processing, y-update processing, and wall processing. For example, the simulated bifurcation algorithm has variations such as the adiabatic simulated bifurcation (aSB) algorithm, the ballistic simulated bifurcation (bSB) algorithm, and the discrete simulated bifurcation (dSB) algorithm.

[0041] When executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine executes the calculation shown in formula (4-1) in the y update processing (S14), and executes the calculation shown in formula (4-2) in the x update processing (S15). Note that when executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine does not execute the wall processing (S15).

number

[0042] When executing processing according to the ballistic simulated branching algorithm, the simulated branching machine performs the calculation shown in equation (5-1) in the y update processing (S14), the calculation shown in equation (5-2) in the x update processing (S15), and the calculation shown in equation (5-3) in the wall processing (S16).

number

[0043] When executing processing according to the discrete simulated branching algorithm, the simulated branching machine performs the calculation shown in equation (6-1) in the y update processing (S14), the calculation shown in equation (6-2) in the x update processing (S15), and the calculation shown in equation (6-3) in the wall processing (S16).

number

[0044] In addition, in formulas (4-1), (4-2), (5-1), (5-2), (5-3), (6-1), (6-2) and (6-3), t k and t k+1 represents the time. k+1 t k This is the time obtained by adding a unit time (Δt) to the current time.

[0045] x i (t k ) is the time (t k ) the i-th position variable (x i ) value. i (t k+1 ) is the time (t k+1 ) the i-th position variable (x i ) value. i (t k ) is the time (t k ) the i-th momentum variable (y i ) value. i (t k+1 ) is the time (t k+1 ) the i-th momentum variable (yi ) value.

[0046] K, a0, η, and c0 are predetermined constants. k ) is a function that changes with time. k ) is a positive real number that increases as time increases, for example, a(t1)=0, and is a function that becomes a0 at the end time (T) (a(T)=a0). Also, sgn(x i (t k )) is the time (t k ) the i-th position variable (x i ), which is a function that outputs the sign of x i (t k ) is 0 or more, then +1, x i (t k ) is less than 0, it becomes -1.

[0047] When the simulated branching machine has executed the processes of S14 to S16 a predetermined number of times, that is, when it has executed the operations until time t reaches the final time T, it exits the loop process between S13 and S17 and proceeds to S18.

[0048] In S18, the simulated branching machine calculates the N position variables (x1 to x N ), or N position variables (x1~x N ) are calculated based on N decision variables (s1 to s N ) The simulated branching machine outputs N decision variables (s1 to s N ) the i-th decision variable (s i ) to sgn(x i ) is used for the calculation.

[0049] When the simulated branching machine finishes the process of S18, it ends the process according to the simulated branching algorithm.

[0050] The number of times the time-evolution process (loop process between S13 and S17) is repeated is determined in advance depending on the application. The amount of calculation required for one process in the time-evolution process (one process from S14 to S16) does not vary. For this reason, the simulated branching machine can reduce fluctuations in the solution-finding time. Therefore, even if the simulated branching machine is applied to a real-time system with time constraints that require processing to be completed by a certain time, it can reliably output a solution by the certain time.

[0051] Also, as shown in Patent Document 2, for example, the simulated branching machine can be configured using a dedicated parallel processing circuit including a large number of arithmetic units. This allows the simulated branching machine to extremely shorten the calculation time for one processing in time-evolution processing. Also, unlike software processing, the simulated branching machine implemented in a dedicated hardware circuit does not generate any interrupt processing, so the solution-finding time is strictly fixed. For example, the simulated branching machine implemented in a dedicated hardware circuit can fix the time until a solution is obtained in clock cycle units. Therefore, when applied to a real-time system, the simulated branching machine implemented in a dedicated hardware circuit can output a solution while more reliably observing time constraints.

[0052] FIG. 4 is a diagram showing a configuration of an information processing system including an Ising machine and a host device. An information processing system having a function of solving a combinatorial optimization problem can be configured, for example, by an Ising machine and a host device. The host device executes processes other than the processes executed by the Ising machine. In this case, the Ising machine is introduced for the purpose of shortening the time required to solve the combinatorial optimization problem, and is considered to be an accelerator or offloader. The host device includes a general-purpose processor, an offloader other than the Ising machine, a memory, a storage, a sensor, an actuator, a communication interface, and the like.

[0053] The host device provides at least information for identifying the QUBO problem (matrix (Q)) or information for identifying an Ising problem (matrix (J) and bias coefficient array (h)) to the Ising machine. The Ising machine may obtain the information for identifying the QUBO problem (matrix (Q)) and convert it into information for identifying an Ising problem (matrix (J) and bias coefficient array (h)). Then, after the optimization process, the Ising machine outputs N decision variables (s1 to s N ) opt ) is returned to the host device.

[0054] FIG. 5 is a diagram showing a configuration of an information processing system including a simulated branching machine and a host device.

[0055] The information processing system having a function of solving a combinatorial optimization problem may include a simulated bifurcation machine as an Ising machine. In this case, the host device provides information (matrix (J) and bias coefficient (h)) for identifying an Ising problem to the simulated bifurcation machine. Furthermore, the host device provides N position variables (x1 to x N ) and the initial values ​​of N momentum variables (y1~y N ) to the simulated branch machine. The host device may also provide various constants and functions (e.g., K, a0, c 0、 a(t) and Δt) may be given to the simulated bifurcation machine. After the optimization process, the simulated bifurcation machine outputs N decision variables (s1 to s N ) opt ), we use N position variables (x1~x N ) opt ) may be sent back to the host device.

[0056] (First embodiment) Next, the market system 10 according to the first embodiment will be described.

[0057] 6 is a diagram showing the configuration of the market system 10. The market system 10 executes electronic trading of a plurality of targets by a plurality of participants. More specifically, the market system 10 accepts buy orders and sell orders from each of the plurality of participants for each of the plurality of targets, matches the price and quantity of the accepted buy order with the price and quantity of the sell order, and electronically completes the trade.

[0058] In this embodiment, the market system 10 executes buying and selling transactions of multiple stocks (multiple brands of stocks) as electronic transactions of multiple targets. Note that the targets are not limited to stocks, and may be securities such as bonds, stock investment trusts, real estate investment trusts, and futures thereof, financial products such as foreign exchange, interest rates, and interest rate futures, or commodities such as gold, crude oil, and grains, and commodity futures thereof, as long as they are tradable in the market.

[0059] The market system 10 includes a market server device 12 and a plurality of client devices 14 .

[0060] The market server device 12 is a computer used by a market administrator. The market server device 12 is connected to a plurality of client devices 14 via a network.

[0061] Each of the client devices 14 is a device used by a market participant, and is realized, for example, by a computer.

[0062] Each of the multiple client devices 14 determines which stock among the multiple stocks to trade. Each of the multiple client devices 14 generates an order packet including trading information for the stock among the multiple stocks that it has decided to trade, and transmits the packet to the market server device 12. The order packet includes, as the trading information, for example, identification information for identifying the stock to be traded among the multiple stocks, a buying / selling direction, price (i.e., stock price), and quantity (i.e., number of shares) representing a sell order or a buy order for the stock identified by the identification information. The price is not limited to a specific value, and may be, for example, a value at the time of the transaction being concluded after the market opens, or a value having a certain range.

[0063] Market server device 12 executes trading of a plurality of stocks. Market server device 12 includes a receiving unit 16, a matching unit 17, and a distribution unit 18.

[0064] The receiving unit 16 receives the order packets transmitted from each of the multiple client devices 14. The receiving unit 16 provides the matching unit 17 with information on the received order packets.

[0065] The matching unit 17 matches the price and quantity of sell orders with the price and quantity of buy orders for each of a plurality of stocks, and completes transactions between sell orders and buy orders whose prices and quantities match in the order in which they are received. The matching unit 17 provides the distribution unit 18 with information about orders that have been completed and information about orders that have not been completed.

[0066] The distribution unit 18 distributes market condition packets including information indicating the status of stock transactions to multiple client devices 14 simultaneously based on the information acquired from the matching unit 17. A market condition packet is generated, for example, for each of multiple stocks. The market condition packet includes identification information for identifying the stock and a transaction price, which is the latest price at which a transaction was concluded for the stock identified by the identification information.

[0067] The market condition packet may also include quote information for each of a plurality of stocks. The quote information is information indicating the price and quantity of unsettled buy orders and information indicating the price and quantity of unsettled sell orders for each of a plurality of stocks.

[0068] The distribution unit 18 distributes market condition packets irregularly. For example, when a trade is concluded, the distribution unit 18 distributes a market condition packet for the stock for which the trade is concluded. For example, each of the multiple client devices 14 acquires the market condition packet distributed irregularly, and determines which of the multiple stocks to trade based on information contained in the acquired market condition packet. Then, each of the multiple client devices 14 generates an order packet for the determined stock and transmits it to the market server device 12.

[0069] The information processing device 20 according to the present embodiment functions as a client device 14 in the market system 10. The information processing device 20 may be realized by a computer including a processor, a memory, and the like, or may be configured to include a dedicated hardware circuit in addition to a processor, a memory, and the like.

[0070] Here, the information processing device 20 generates a combinatorial optimization problem based on market condition packets acquired at irregular intervals, solves the generated combinatorial optimization problem, and based on the solution to the combinatorial optimization problem obtained by solving it, decides whether or not to trade each of the multiple stocks.

[0071] In this embodiment, the information processing device 20 uses a function shown in equation (7) as a cost function in a combinatorial optimization problem.

number

[0072] In formula (7), N is an integer equal to or greater than 2 and represents the number of stocks traded in market server device 12. i is an integer equal to or greater than 1 and equal to or less than N, and is an index that identifies each of the stocks.

[0073] The cost function in equation (7) includes N decision variables. i is a binary variable of 0 or 1, and is a decision variable representing whether to trade the i-th stock among multiple stocks. In this embodiment, b i represents 1 if a transaction is made and 0 if a transaction is not made.

[0074] t represents any time between the start time and the end time of trading in one day. t is 0 at the start time of trading and increases as time passes from the start time of trading. In this embodiment, t is an integer and represents time as an index.

[0075] p i (t) is the trading price of the i-th stock at time t, i.e., the stock price at time t. p i (0) is the trading price at the opening time of the i-th stock, i.e., the stock price at the opening time of the trading. α and β are preset constants.

[0076] p i (t) / p i (0)-1 represents the rate of change based on the trading price at the start of trading. i (t) / p i If (0)-1 is greater than 0, it indicates that the price of the i-th stock is rising, and if it is less than 0, it indicates that the price of the i-th stock is falling.

[0077] Also, sgn(p i (t) / p i (0)-1) is p i (t) / p i (0)-1 is 0 or more, then +1, p i (t) / p i (0) This is a sign function that becomes -1 when -1 is less than 0.

[0078] The first term on the right side of the cost function in formula (7) is a term that evaluates the difference between the rate of change of each of multiple stocks and a preset value α. Therefore, the cost function in formula (7) decreases when trading stocks whose rate of change is greater than α.

[0079] Furthermore, the information processing device 20 determines the direction of buying and selling for the i-th stock, i.e., whether to make a sell order or a buy order, based on the rate of change. For example, when making a buy order in the case of an upward trend, i.e., when following the trend, the information processing device 20 makes a buy order when the rate of change is positive and a sell order when the rate of change is negative. Conversely, when making a sell order in the case of an upward trend, i.e., when following the trend, the information processing device 20 makes a sell order when the rate of change is positive and a buy order when the rate of change is negative. In this embodiment, the information processing device 20 makes a sell order when the rate of change is positive and a buy order when the rate of change is negative.

[0080] The second term on the right side of the cost function of formula (7) is a term that evaluates the difference between the number of shares for which sell orders are made and the number of shares for which buy orders are made. The second term on the right side of the cost function of formula (7) is 0 when the difference between the number of shares for which sell orders are made and the number of shares for which buy orders are made is 0, and becomes larger as the difference becomes larger. Therefore, the cost function of formula (7) decreases, for example, when trading a pair of two stocks with a large absolute value of the difference in the rate of change, i.e., a small correlation between the rate of change, and with opposite buying and selling directions. In addition, the cost function of formula (7) decreases, for example, when trading a stock group that includes multiple stocks with the same number of stocks for which sell orders are made and the same number of stocks for which buy orders are made, and the absolute value of the difference between the rate of change between the stocks is large, i.e., a small correlation between the rate of change between the stocks is made.

[0081] From the above, it is possible to obtain a solution for the combinatorial optimization problem of minimizing the cost function of equation (7) that diversifies risk by buying and selling stocks with large fluctuation rates while minimizing the difference between the number of stocks for sell orders and the number of stocks for buy orders.

[0082] The information processing device 20 obtains a solution to a combinatorial optimization problem that minimizes such a cost function, i.e., the values ​​of the N decision variables. The information processing device 20 decides to trade stocks corresponding to the decision variables having a value of 1 among the N decision variables. The information processing device 20 then generates an order packet including trading information for the stocks for which it has been decided to execute the trade among the multiple stocks, and transmits the order packet to the market server device 12.

[0083] The information processing device 20 may solve a combinatorial optimization problem that minimizes a cost function other than the cost function shown in equation (7).

[0084] FIG. 7 is a diagram showing the configuration of the information processing device 20 according to the first embodiment.

[0085] The information processing device 20 acquires data provided irregularly, generates a combinatorial optimization problem based on the acquired data, and generates output data based on a solution to the generated combinatorial optimization problem. The information processing device 20 then outputs the generated output data to a first device different from the information processing device 20. In this embodiment, the information processing device 20 receives market condition packets provided irregularly from the market server device 12 as data. The information processing device 20 generates a combinatorial optimization problem based on the received market condition packets, and generates an order packet as output data based on the solution to the generated combinatorial optimization problem. In this embodiment, the information processing device 20 then transmits the generated order packet to the market server device 12, which is an example of a first device.

[0086] The information processing device 20 includes an input memory 32, an acquisition unit 36, a solver device 40, a problem generator 42, and a process execution unit 46.

[0087] The input memory 32 stores a plurality of input values ​​that are the basis of a plurality of weight values ​​included in the cost function of the combinatorial optimization problem. In this embodiment, the input memory 32 stores values ​​corresponding to a plurality of trading prices as a plurality of input values. The values ​​corresponding to the plurality of trading prices stored in the input memory 32 correspond one-to-one to a plurality of stocks. That is, the input memory 32 stores a value corresponding to the trading price for each of the plurality of stocks. The value corresponding to the trading price may be the trading price, or may be a value obtained by performing a predetermined process or calculation on the trading price. For example, the value corresponding to the trading price may be a rate of change that indicates the ratio of the latest trading price to the trading price at the start of trading.

[0088] The acquisition unit 36 ​​acquires data that is repeatedly given at irregular intervals. The data acquired by the acquisition unit 36 ​​includes input information related to at least one of the multiple targets. When the acquisition unit 36 ​​acquires data, the acquisition unit 36 ​​rewrites, based on the input information included in the acquired data, an input value corresponding to the target related to the input information included in the acquired data, among the multiple input values ​​stored in the input memory 32.

[0089] In this embodiment, the acquiring unit 36 ​​acquires a market condition packet, which is an example of data repeatedly provided at irregular intervals, from the market server device 12. The market condition packet includes, as input information, the trading price of at least one of the multiple stocks. When acquiring the market condition packet, the acquiring unit 36 ​​rewrites, based on the trading price included in the acquired market condition packet, the value corresponding to the trading price of the stock indicated in the acquired market condition packet, among the values ​​corresponding to the trading prices of each of the multiple stocks stored in the input memory 32.

[0090] The solver device 40 receives a combinatorial optimization problem from the problem generator 42 and solves the received combinatorial optimization problem. The solver device 40 then outputs a solution to the received combinatorial optimization problem. In this embodiment, the solver device 40 is a simulated bifurcation machine, which is an Ising machine, and is implemented in a dedicated hardware circuit. Note that the solver device 40 may solve the combinatorial optimization problem based on another algorithm instead of the simulated bifurcation machine.

[0091] Moreover, in this embodiment, the solver device 40 includes a weight memory 50 (first memory) and a pattern memory 52 (second memory). The weight memory 50 stores a plurality of weight values ​​included in a cost function of a combinatorial optimization problem. For example, the weight memory 50 stores a matrix (J) and a bias coefficient array (h) representing a plurality of weight values ​​included in the cost function shown in equation (7). The pattern memory 52 stores pattern information (first information) indicating the storage positions of the respective plurality of weight values ​​in the weight memory 50.

[0092] The problem generator 42 generates a combinatorial optimization problem based on the data acquired by the acquisition unit 36, and causes the solver device 40 to solve the generated combinatorial optimization problem. More specifically, the problem generator 42 generates a plurality of weight values ​​included in a cost function in the combinatorial optimization problem based on a plurality of input values ​​stored in the input memory 32, and writes the generated plurality of weight values ​​to the weight memory 50. In this embodiment, the solver device 40 is an Ising machine, and the combinatorial optimization problem is an Ising problem. Therefore, the problem generator 42 generates a matrix (J) and a bias coefficient array (h), and writes the generated matrix (J) and bias coefficient array (h) to the weight memory 50.

[0093] In this embodiment, the problem generator 42 generates a combinatorial optimization problem that minimizes the cost function shown in equation (7). More specifically, the problem generator 42 generates a plurality of weight values ​​included in the cost function of the combinatorial optimization problem shown in equation (7) based on a plurality of input values ​​stored in the input memory 32, and writes the generated plurality of weight values ​​to the weight memory 50. More specifically, the problem generator 42 generates a matrix (J) and a bias coefficient array (h) obtained by equation (7) based on values ​​corresponding to the trading prices of a plurality of stocks stored in the input memory 32, and writes the generated matrix (J) and bias coefficient array (h) to the weight memory 50.

[0094] Furthermore, the question generator 42 generates pattern information for identifying the storage locations of each of the multiple weight values ​​in the weight memory 50. Then, the question generator 42 writes the generated pattern information into the pattern memory 52.

[0095] Furthermore, the problem generator 42 generates a combinatorial optimization problem in response to acquiring data or at preset intervals, and causes the solver device 40 to solve the combinatorial optimization problem. In this embodiment, the problem generator 42 generates a combinatorial optimization problem in response to acquiring a market condition packet by the acquiring unit 36 ​​or at preset intervals, and causes the solver device 40 to solve the combinatorial optimization problem.

[0096] However, during the solution-seeking process period from when generation of a combinatorial optimization problem starts until a solution to the generated combinatorial optimization problem is output, the problem generator 42 does not generate a new combinatorial optimization problem even if the acquirer 36 acquires a new market packet. Furthermore, the preset period is longer than the time required from when generation of a combinatorial optimization problem starts until a solution to the generated combinatorial optimization problem is output. Furthermore, the preset period does not have to be at a fixed time interval and may vary over time.

[0097] The process execution unit 46 obtains a solution to the combinatorial optimization problem from the solver device 40. In this embodiment, the process execution unit 46 calculates the solution to the combinatorial optimization problem by solving a plurality of decision variables (b1 to bN ) as a solution. In response to receiving the solution from the solver device 40, the process execution unit 46 executes a process based on the received solution.

[0098] For example, when the processing execution unit 46 acquires a solution to a combinatorial optimization problem from the solver device 40, the processing execution unit 46 generates output data including output information indicating to perform a predetermined operation on at least one stock among the multiple stocks identified by the solution, based on the acquired solution. Then, the processing execution unit 46 outputs the output data to the first device.

[0099] In this embodiment, when the process execution unit 46 acquires a solution to a combinatorial optimization problem from the solver device 40, it generates an order packet, which is an example of output data. The order packet includes, as output information, a plurality of decision variables (b1 to b N The order packet includes transaction information indicating that a buy order or a sell order, which is a predetermined operation, is to be placed for the stock corresponding to the decision variable having the value (1) indicating that a transaction is to be placed among the values ​​of the decision variables (1) and (2), which indicates that a transaction is to be performed. Then, the process execution unit 46 outputs the generated order packet to the market server device 12, which is an example of the first device.

[0100] In this embodiment, the weights included in the cost function in the combinatorial optimization problem are identified by an index representing a position in a predetermined first region. For example, the weights included in the second term on the right side of the formula (7) are identified by an index (i, j) representing the row number (i) and column number (j) of a matrix (J) with N rows and N columns.

[0101] Furthermore, in this embodiment, a first partial weight group, which is a part of the multiple weight values, is the same as a second partial weight group, which is the other part. For example, a first partial weight group included in a first partial region, which is a part of a predetermined first region, is the same as a second partial weight group included in a second partial region, which is the other part of the predetermined first region. For example, N weight values ​​included in a first row of a matrix (J) with N rows and N columns are the same as N weight values ​​included in a second row of the matrix (J).

[0102] In this embodiment, the problem generator 42 writes the first partial weight group and the second partial weight group into a common area in the weight memory 50. Then, the solver device 40 reads each of the multiple weight values ​​from the weight memory 50 based on the pattern information stored in the pattern memory 52, and solves a solution.

[0103] 8 is a timing chart showing processing timing of the information processing device 20. The information processing device 20 executes processing, for example, according to the flow shown in FIG.

[0104] When the acquiring unit 36 ​​acquires a market condition packet from the market server device 12, the acquiring unit 36 ​​rewrites the value corresponding to the trading price of the stock related to the trading price included in the market condition packet, among the values ​​corresponding to the respective trading prices of the multiple stocks stored in the input memory 32. As a result, the values ​​corresponding to the respective trading prices of the multiple stocks stored in the input memory 32 are changed (t1 and t5 in FIG. 8).

[0105] The problem generator 42 generates a plurality of weight values ​​to be included in a cost function for a combinatorial optimization problem, based on values ​​corresponding to the respective trading prices of a plurality of stocks stored in the input memory 32. Then, the problem generator 42 writes the generated plurality of weight values ​​into the weight memory 50 of the solver device 40, and causes the solver device 40 to execute a solution-finding process (t2, t6 in FIG. 8). For example, the problem generator 42 and the solver device 40 execute problem generation every time they acquire a market condition packet from the market server device 12, or at predetermined time intervals.

[0106] The solver device 40 starts the solution-finding process after the multiple weight values ​​are written to the weight memory 50. When the solver device 40 completes the solution-finding process, it provides the solution of the combinatorial optimization problem to the process execution unit 46 (t3 and t7 in FIG. 8).

[0107] The process execution unit 46 generates an order packet in response to obtaining the solution to the combinatorial optimization problem from the solver device 40. Then, the process execution unit 46 outputs the generated order packet to the market server device 12 (t4 and t8 in FIG. 8).

[0108] FIG. 9 is a diagram showing pseudocode 60 for generating a Q matrix in QUBO from the second term on the right-hand side of equation (7).

[0109] For example, each of the N rows in the matrix (J) included in the second term on the right side of equation (7) is represented by one of two patterns, as described below.

[0110] First, consider generating an N-row × N-column Q matrix in QUBO from the second term on the right side of equation (7). When generating an N-row × N-column Q matrix in QUBO from the second term on the right side of equation (7), the problem generator 42 executes the pseudocode 60 shown in FIG.

[0111] Note that p_sgn(i) is sgn(p i (t) / p i (0)-1). Also, p_sgn(j) represents sgn(p j (t) / p j Represents (0)-1).

[0112] The N weight values ​​in the first row of the Q matrix (Q 1,1 ,Q 1,2 ,…,Q 1,N ,) is {β×p_sgn(1)×p_sgn(1), β×p_sgn(1)×p_sgn(2), …, β×p_sgn(1)×p_sgn(N)}.

[0113] p_sgn(i) and p_sgn(j) are either +1 or -1. Therefore, the N weight values ​​in the first row of the Q matrix (Q 1,1 ,Q 1,2 ,…,Q 1,N,) is {β×p_sgn(1),β×p_sgn(2),…,β×p_sgn(N)} when β×p_sgn(1) is +1. Also, the N weight values ​​(Q 1,1 ,Q 1,2 ,…,Q 1,N ,) is {-β×p_sgn(1),-β×p_sgn(2),...,-β×p_sgn(N)} when β×p_sgn(1) is -1. The other rows of the Q matrix other than the first row are the same as the first row.

[0114] That is, each of the N rows in the Q matrix is ​​one of the two patterns: {β×p_sgn(1), β×p_sgn(2), ..., β×p_sgn(N)} or {-β×p_sgn(1), -β×p_sgn(2), ..., -β×p_sgn(N)}.

[0115] Similarly, when the Q matrix is ​​converted into a matrix (J) in the Ising problem, each of the N rows becomes one of the two patterns.

[0116] That is, each of the N rows in the matrix (J) will be either a first pattern of {-0.5×β×p_sgn(1), -0.5×β×p_sgn(2), ..., -0.5×β×p_sgn(N)} or a second pattern of {0.5×β×p_sgn(1), 0.5×β×p_sgn(2), ..., 0.5×β×p_sgn(N)}.

[0117] In this embodiment, when generating a matrix (J) included in the second term on the right side of equation (7), the problem generator 42 generates a first pattern and a second pattern instead of generating all of the N rows. Then, the problem generator 42 writes the two patterns, the first pattern and the second pattern, i.e., 2×N weight values, into the weight memory 50.

[0118] For example, the weight memory 50 includes a first storage area and a second storage area. In this case, the question generator 42 writes the N weight values ​​of the first pattern into the first storage area, and writes the N weight values ​​of the second pattern into the second storage area.

[0119] Furthermore, the question generator 42 generates pattern information indicating whether each of the N rows in the matrix (J) included in the second term on the right side of the formula (7) is the first pattern or the second pattern. For example, the question generator 42 calculates β×p_sgn(i) for each of the first to Nth rows. Next, the question generator 42 generates pattern information indicating the value of β×p_sgn(i) (+1 or −1) for each of the first to Nth rows. Then, the question generator 42 writes the generated pattern information to the pattern memory 52.

[0120] When the solver device 40 reads out the N×N weight values ​​included in the matrix (J) from the weight memory 50 during the solution of a combinatorial optimization problem, the solver device 40 refers to the pattern information stored in the pattern memory 52 to determine whether the row of the target weight value to be read out is the first pattern or the second pattern. If the row of the target weight value is the first pattern, the solver device 40 reads out the weight value corresponding to the column of the target weight value among the N weight values ​​stored in the first storage area in the weight memory 50. If the row of the target weight value is the second pattern, the solver device 40 reads out the weight value corresponding to the column of the target weight value among the N weight values ​​stored in the second storage area in the weight memory 50. In this way, the solver device 40 can read out each of the N×N weight values ​​based on the N weight values ​​of the first pattern, the N weight values ​​of the second pattern, and the pattern information.

[0121] As described above, the information processing device 20 according to the first embodiment stores the first partial weight group and the second partial weight group having the same pattern among the multiple weight values ​​included in the cost function in the combinatorial optimization problem in a common area of ​​the weight memory 50. As a result, the information processing device 20 does not generate all of the multiple weight values, but only generates a part of the multiple weight values, and therefore can generate the combinatorial optimization problem in a short time compared to the generation time required to generate all of the multiple weight values. Therefore, the information processing device 20 can generate the combinatorial optimization problem quickly and cause the solver device 40 to start solving it early.

[0122] Furthermore, since the solver device 40 does not need to store all of the weight values, but only a portion of the weight values, it is possible to reduce the size of the weight memory 50. As a result, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0123] Second embodiment Next, a market system 10 according to a second embodiment will be described. The market system 10 according to the second embodiment has substantially the same functions and configurations as those of the first embodiment, so elements having substantially the same functions and configurations are given the same reference numerals and detailed descriptions are omitted except for the differences. The same applies to the third and subsequent embodiments.

[0124] FIG. 10 is a diagram illustrating an example of a plurality of weight values ​​included in a cost function for a combinatorial optimization problem according to the second embodiment.

[0125] For example, each of the weight values ​​is identified by an index representing a position in a predetermined first region. For example, when the weight values ​​are represented by a matrix, each of the weight values ​​is identified by an index represented by a pair of a row number and a column number in the matrix. In this embodiment, the number of any row in the matrix is ​​represented as i. Also, the number of any column in the matrix is ​​represented as j.

[0126] In this embodiment, the predetermined first region is a two-dimensional space represented by a matrix. However, the predetermined first region may be a one-dimensional space represented by an array, or a multidimensional space such as a three-dimensional space or a four-dimensional space represented by a tensor.

[0127] FIG. 11 is a diagram showing an example of M partial regions, K patterns, pattern information, region conversion information, and partial address conversion information.

[0128] In this embodiment, the predetermined first region in which the multiple weight values ​​are arranged is divided into M regions having the same shape, where M is an integer of 3 or more.

[0129] In the example of Fig. 11, the predetermined first region is divided into four partial regions in the row direction and into four partial regions in the column direction. That is, in the example of Fig. 11, the predetermined first region is divided into 16 partial regions of the same shape. Note that, when the predetermined first region is a multidimensional space such as a four-dimensional space, each of the M partial regions may be a multidimensional space.

[0130] Each of the M partial regions is identified by a block number (B_N). For example, in FIG. 11, each of the 16 partial regions is identified by a block number (B_N) from 1 to 16.

[0131] A partial weight group that is a part of a plurality of weight values ​​is arranged in each of the M partial regions. The partial weight group arranged in each of the M partial regions is represented by any one of K patterns (K is an integer equal to or greater than 2 and smaller than M). In other words, two or more partial regions that include the same pattern among the M partial regions include the same partial weight group.

[0132] Moreover, the pattern information indicates which of the K patterns the partial regions includes in its partial weight set. For example, the pattern information includes information (Pk) for identifying a pattern using a block number (B_N) as an index.

[0133] The region conversion information is information for converting an index indicating the position of the target weight value in a predetermined first region into a block number (B_N) that identifies a partial region including the target weight value among the M partial regions. For example, the region conversion information is a function {f(i,j)} that converts a pair of a row number (i) and a column number (j) into a block number (B_N).

[0134] The partial address conversion information is information for converting an index representing the position of a target weight value in a predetermined first region into a partial address (i',j') representing the position of the target weight value in the partial region. For example, the partial address conversion information may be a function {g(i,j)} that converts a pair of a row number (i) and a column number (j) into a partial address (i',j').

[0135] In this embodiment, the problem generator 42 generates such K patterns, pattern information, domain conversion information, and partial address conversion information in generating a combinatorial optimization problem. Then, the problem generator 42 provides the generated K patterns, pattern information, domain conversion information, and partial address conversion information to the solver device 40.

[0136] In addition, when the division positions of the M partial regions with respect to the predetermined first region are fixed, the problem generator 42 does not need to generate the region conversion information and the partial address conversion information. In this case, the solver device 40 has the region conversion information and the partial address conversion information preset.

[0137] FIG. 12 is a diagram showing the configuration of a solver device 40 according to the second embodiment.

[0138] The solver device 40 according to the second embodiment includes a search circuit 62, a partial region specifying circuit 64, a partial address specifying circuit 66, a weight memory 50, a pattern memory 52, and a selector 68.

[0139] The search circuit 62 reads out each of the multiple weight values ​​stored in the weight memory 50 and searches for a solution that minimizes the cost function. i,j ), the search circuit 62 reads the target weight value (J i,j ) in a predetermined first region. For example, the search circuit 62 may use the target weight value (J i,j ) row number (i) and column number (j).

[0140] The partial region identification circuit 64 receives the region conversion information (f(i, j)) from the question generator 42. When the division positions of the M partial regions for a predetermined first region are fixed, the partial region identification circuit 64 may have the region conversion information (f(i, j)) preset.

[0141] The partial region specification circuit 64 is a circuit for specifying the target weight value (J i,j When reading out the target weight value (J i,j The partial region specifying circuit 64 obtains the row number (i) and column number (j) of the region (i, j) as an index. Then, the partial region specifying circuit 64 obtains the region conversion information (f(i, j)) and the target weight value (J i,j ) based on the index of the M subregions, the target weight value (J i,j ) is output as a block number (B_N) that identifies the target subregion in which it is contained.

[0142] The partial address identification circuit 66 receives the partial address conversion information (g(i,j)) from the question generator 42. When the division positions of the M partial areas with respect to the predetermined first area are fixed, the partial address identification circuit 66 may have the partial address conversion information (g(i,j)) preset.

[0143] The partial address specification circuit 66 is a circuit for specifying the target weight value (J i,j When reading out the target weight value (J i,j The partial address specification circuit 66 then obtains the row number (i) and column number (j) of the partial address conversion information (g(i,j)) and the target weight value (Ji,j ) based on the index, the target weight value (J i,j ) and outputs the target part address (i', j') that indicates the position of the

[0144] Pattern information is written into the pattern memory 52 by the question generator 42. The pattern memory 52 receives a block number (B_N) from the partial area identification circuit 64. When the pattern memory 52 receives the block number (B_N), it outputs information (Pk) indicating a pattern identified by the received block number (B_N) in the stored pattern information.

[0145] The weight memory 50 includes K partial memories 70-1 to 70-K. The K partial memories 70-1 to 70-K correspond one-to-one to the K patterns. That is, the k-th partial memory 70-k (k is an integer greater than or equal to 1 and less than or equal to K) among the K partial memories 70-1 to 70-K corresponds to the k-th pattern among the K patterns. In each of the K partial memories 70-1 to 70-K, a partial weight group of a corresponding pattern among the K patterns is written by the question generator 42. That is, the partial weight group of the k-th pattern is written into the k-th partial memory 70-k.

[0146] Each of the K partial memories 70-1 to 70-K receives a target partial address (i', j') from the partial address identification circuit 66. When each of the K partial memories 70-1 to 70-K receives a target partial address (i', j'), it outputs a weight value identified by the target partial address (i', j') from the stored partial weight group.

[0147] The selector 68 receives information (Pk) indicating a pattern identified by the block number (B_N) from the pattern memory 52. ​​When the selector 68 receives the information (Pk) indicating a pattern, it selects one partial memory 70 specified by the received information (Pk) indicating a pattern from among the K partial memories 70-1 to 70-K. Then, the selector 68 calculates the weight value output from the selected partial memory 70 from the pattern memory 52 as the target weight value (J i,j ) to the search circuit 62.

[0148] In this way, when the solver device 40 reads out a target weight value from among a plurality of weight values, it identifies a target partial region, out of the M partial regions, in which the target weight value is included. Next, the solver device 40 identifies a target pattern in the target partial region out of the K patterns based on the pattern information. Next, the solver device 40 identifies a target partial address that indicates the position of the target weight value in the target partial region. Then, the solver device 40 reads out, from the weight memory 50, the weight value in the partial weight group of the target pattern that is identified by the target partial address as the target weight value. In this way, the solver device 40 can identify the target weight value (J i,j ) can be read out.

[0149] As described above, the information processing device 20 according to the second embodiment stores partial weight sets of K patterns in the weight memory 50. As a result, the information processing device 20 does not need to generate all of the multiple weight values, but only needs to generate partial weight sets of K patterns, and therefore can generate a combinatorial optimization problem in a short time compared to the generation time required to generate all of the multiple weight values. Therefore, the information processing device 20 can generate a combinatorial optimization problem at high speed and cause the solver device 40 to start solving the problem early.

[0150] Furthermore, since the solver device 40 does not need to store all of the weight values, but only needs to store a partial weight group of K patterns, it is possible to reduce the size of the weight memory 50. As a result, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0151] Third embodiment Next, a market system 10 according to a third embodiment will be described.

[0152] 13 is a diagram showing the configuration of a solver device 40 according to the third embodiment. The information processing device 20 according to the third embodiment includes the solver device 40 that executes a simulated bifurcation algorithm.

[0153] The solver device 40 includes an arithmetic circuit 71 , an input circuit 72 , an output circuit 73 , and a setting circuit 74 .

[0154] The arithmetic circuit 71 increases a parameter t representing time by unit time (Δt) from an initial time (for example, 0) to an end time. The arithmetic circuit 71 calculates a first variable (x i ) and the second variable (y i ) is calculated. The N virtual points correspond to the N spins in the Ising model. The i-th virtual point of the N virtual points corresponds to the i-th spin of the N spins in the Ising model.

[0155] The first variable (x i ) is a position variable that represents the position of the corresponding virtual point. i ) is the momentum variable that represents the momentum of the corresponding virtual point.

[0156] The calculation circuit 71 calculates N first variables (x i ) and N second variables (y i ) in sequence for each unit time and for the first variable (x i ) and the second variable (y i) alternately. More specifically, the arithmetic circuit 71 executes the arithmetic shown in the algorithms of equations (4-1) and (4-2) for each unit time from the initial time to the end time. The arithmetic circuit 71 may execute the arithmetic shown in the algorithms of equations (5-1), (5-2) and (5-3), or may execute the arithmetic shown in the algorithms of equations (6-1), (6-2) and (6-3). The arithmetic circuit 71 calculates the N first variables (x i ) (i.e., the positions of the N virtual points) are binarized to calculate a solution to the combinatorial optimization problem.

[0157] Prior to the arithmetic processing by the arithmetic circuit 71, the input circuit 72 receives N first variables (x i ) and N second variables (y i ) and provides them to the arithmetic circuit 71. After the arithmetic processing by the arithmetic circuit 71 is completed, the output circuit 73 acquires the solution to the combinatorial optimization problem from the arithmetic circuit 71. Then, the output circuit 73 outputs the acquired solution. The setting circuit 74 sets each parameter in the arithmetic circuit 71 prior to the arithmetic processing by the arithmetic circuit 71.

[0158] Fig. 14 is a diagram showing a block configuration of the arithmetic circuit 71. In the explanation of Fig. 14, the target time (second time) is any time when the time from the initial time to the end time is divided into unit times. In the explanation of Fig. 14, the immediately preceding time (first time) is represented as t1. Moreover, the target time (second time) is represented as t2.

[0159] The arithmetic circuit 71 includes an X memory 81, a Y memory 82, an action arithmetic circuit 83, a time evolution circuit 84 (first circuit), and a control circuit 85.

[0160] The X memory 81 stores the N first variables (x i As the time is updated, the X memory 81 stores the N first variables (x iThat is, the X memory 81 stores the N first variables (x i When the first variable (x i (t2)) is the new N first variables (x i Prior to the calculation, the setting circuit 74 writes the N first variables x i Write to X memory 81.

[0161] The Y memory 82 stores N second variables (y i As the time is updated, the Y memory 82 stores the N second variables (y i That is, the Y memory 82 stores N second variables (y i When the second variable (y i (t2)) is the N second variables (y i (t1)). Prior to the calculation, the setting circuit 74 writes the N second variables y i is written to Y memory 82.

[0162] The action calculation circuit 83 calculates the N first variables (x j (t1)) from the X memory 81. Then, the action calculation circuit 83 obtains the update value (z i (t1)) is calculated.

[0163] The time evolution circuit 84 calculates the update value (z i The time evolution circuit 84 obtains the first variable (x i (t1)) is obtained from the X memory 81, and the second variable (yi The time evolution circuit 84 then obtains the first variable (x i (t2)) is calculated, and the first variable (x i At the same time, the time evolution circuit 84 rewrites the second variable (y i (t2)) is calculated, and the second variable (y i Rewrite (t1).

[0164] The control circuit 85 sequentially updates the target time (t2) for each unit time (Δt) to provide the action calculation circuit 83 and the time evolution circuit 84 with a first variable (x i (t)) and the second variable (y i (t)) are calculated sequentially.

[0165] Furthermore, the control circuit 85 generates an index (i) for identifying the N virtual points by incrementing from 1 to N for each unit time. The control circuit 85 provides the index (i) to the action calculation circuit 83 and the time evolution circuit 84 to calculate the first variable (x i (t2)) and the second variable (y i The action calculation circuit 83 and the time evolution circuit 84 calculate a plurality of first variables (x i (t2)) and multiple second variables (y i (t2)) may be calculated in parallel.

[0166] 15 is a diagram showing the configuration of the action calculation circuit 83. The action calculation circuit 83 has a weight memory 50, a matrix calculation circuit 93, an α function circuit 94, and a first adder circuit 95. The weight memory 50 includes a J memory 91 and an H memory 92.

[0167] The J memory 91 stores a pattern for generating an N×N matrix (J) containing (N×N) weight values. i , j represents the weight value of the i-th row and j-th column in the matrix. i , j corresponds to the coupling coefficient between the i-th spin and the j-th spin in the Ising model. Prior to calculation, the setting circuit 74 writes a pattern for generating the matrix (J) generated by the problem generator 42 into the J memory 91.

[0168] The H memory 92 stores an array containing N bias coefficients. i represents the i-th bias coefficient in the array. i corresponds to the local magnetic field coefficient acting on the i-th spin in the Ising model. Prior to the calculation, the setting circuit 74 writes an array including N bias coefficients generated by the problem generator 42 into the H memory 92.

[0169] The matrix calculation circuit 93 reads from the X memory 81 the N first variables (x j The matrix calculation circuit 93 obtains the N weight values ​​J (t1) included in the target row from the J memory 91 for each of the N virtual points. i,j Then, the matrix calculation circuit 93 obtains the N first variables (x j (t1)) and the N weight values ​​J i,j Perform a multiply-and-accumulate operation with

[0170] The α function circuit 94 selects the target bias coefficient h from the H memory 92 for each of the N virtual points. i The α function circuit 94 obtains, for each of the N virtual points, i α(t1)} is calculated, where α(t) is a preset function.

[0171] The first adder circuit 95 adds the product-sum calculation result by the matrix calculation circuit 93 and the calculation result by the α function circuit 94 for each of the N virtual points. Through this calculation, the first adder circuit 95 calculates the update value (z i (t1)).

number

[0172] 16 is a diagram illustrating an example of a matrix (J). In the third embodiment, the matrix (J) including N×N weight values ​​is such that N weight values ​​included in each of N rows are arranged in a first pattern {J1(J1 ,1 ,J1 ,2 ,…,J1 ,N )} or second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N )}.

[0173] The question generator 42 according to the third embodiment generates a first pattern and a second pattern as a matrix (J) and stores them in a J memory 91. The question generator 42 also generates pattern information indicating whether each of the N rows in the matrix (J) is the first pattern or the second pattern, and provides the pattern information to a matrix calculation circuit 93.

[0174] FIG. 17 is a diagram showing the configuration of a matrix calculation circuit 93 according to the third embodiment, together with a J memory 91 and an X memory 81.

[0175] The J memory 91 includes a first partial memory 111 and a second partial memory 112 .

[0176] The first partial memory 111 stores N weight values ​​of the first pattern {J1(J1 ,1 ,J1 ,2 ,…,J1 ,N)}. The first partial memory 111 outputs the N weight values ​​one by one, starting from the first column, every time a clock is given. After outputting the weight value of the Nth column, the first partial memory 111 returns to the first column and outputs weight values ​​again from the first column for each clock. That is, the first partial memory 111 starts outputting weight values ​​from the first column for each N clock.

[0177] The second partial memory 112 stores the N weight values ​​of the second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N )}. The second partial memory 112 outputs the N weight values ​​one by one, starting from the first column, every time a clock is given. After outputting the weight value of the Nth column, the second partial memory 112 returns to the first column and outputs weight values ​​again from the first column for each clock. That is, the second partial memory 112 starts outputting weight values ​​from the first column for each N clock.

[0178] The X memory 81 stores the N first variables (x j The X memory 81 stores N first variables (x j (t1)) to the first variable (x1(t1)) and then the Nth first variable (x N The X memory 81 outputs the first variable (x j After outputting the first variable (x N The X memory 81 outputs the first variable (x N (t1)).

[0179] The matrix operation circuit 93 includes a pattern memory 52, a pattern selector 113 (first selector), a multiplication circuit 115, and an accumulation circuit .

[0180] The pattern memory 52 stores the pattern information generated by the question generator 42. The pattern memory 52 acquires an index (i) representing any one of 1 to N generated from the control circuit 85. The index (i) is incremented every N clocks. The timing at which the index (i) is incremented is synchronized with the timing at which the weight values ​​of the first column are output from the first partial memory 111 and the second partial memory 112. The pattern memory 52 outputs a selection value (0 or 1) indicating whether the row corresponding to the index (i) is the first pattern or the second pattern. In this example, the selection value 0 indicates the first pattern, and 1 indicates the second pattern.

[0181] The pattern selector 113 receives a selection value representing 0 or 1 from the pattern memory 52. ​​The pattern selector 113 selects and outputs a weight value output from either the first partial memory 111 or the second partial memory 112, whichever is specified by the selection value.

[0182] The multiplication circuit 115 multiplies the weight value output from the pattern selector 113 by the first variable (x j (t1)) and output the multiplication result.

[0183] The cumulative addition circuit 116 includes an adder 121, a reset selector 122, and a second latch circuit 123. The adder 121 adds the multiplication result output from the multiplication circuit 115 and the value stored in the second latch circuit 123. The reset selector 122 provides the value output from the adder 121 to the second latch circuit 123. Furthermore, the reset selector 122 provides 0 to the second latch circuit 123 instead of the value output from the adder 121 every N clocks, that is, in synchronization with the update of the index (i). The second latch circuit 123 takes in and stores the value output from the reset selector 122 for each clock.

[0184] The accumulating circuit 116 calculates an accumulating value by accumulating the multiplication results output from the multiplying circuit 115 for each clock. The accumulating circuit 116 resets the accumulating value to 0 every N clocks, that is, in synchronization with the update of the index (i). In addition, in the cycle immediately before resetting the accumulating value to 0, the accumulating circuit 116 multiplies the accumulating value by N weight values ​​(J i,1 ~J i,N ) and the first variable (x j (t1)) and output it as the result of multiplying and adding the result.

[0185] Such a matrix calculation circuit 93 calculates the sum-of-products result (Z' i (t1) (an example of the i-th second intermediate variable among the N second intermediate variables) can be calculated.

number

[0186] As described above, the information processing device 20 according to the third embodiment calculates the N weight values ​​{J1(J1 ,1 ,J1 ,2 ,…,J1 ,N )} and the N weight values ​​of the second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N )} is stored in the weight memory 50. As a result, the information processing device 20 does not need to generate all of the N×N weight values, but only needs to generate 2×N weight values, and therefore can generate a combinatorial optimization problem in a short time compared to the generation time required to generate all of the multiple weight values. Therefore, the information processing device 20 can generate a combinatorial optimization problem at high speed and cause the solver device 40 to start solving the problem early.

[0187] Furthermore, since the solver device 40 does not need to store all of the N×N weight values, but only needs to store 2×N weight values, it is possible to reduce the size of the weight memory 50. As a result, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0188] In this embodiment, the N weight values ​​included in the i row of the matrix (J) are either the first pattern or the second pattern. However, the N weight values ​​included in the i row of the matrix (J) may be any one of the K patterns. In this case, the weight memory 50 includes K partial memories 70-1 to 70-K. Then, the k-th partial memory 70-k (k is an integer of 1 to K) among the K partial memories 70-1 to 70-K stores the N weight values ​​of the k-th pattern of the K patterns. The N weight values ​​are read out from each of the K partial memories 70-1 to 70-K in the same manner as the first partial memory 111 and the second partial memory 112. Moreover, the pattern information indicates which of the K patterns each of the N rows included in the matrix (J) is.

[0189] Furthermore, when the weight memory 50 includes K partial memories 70-1 to 70-K, the pattern selector 113 selects and outputs N weight values ​​output from the partial memory 70 corresponding to the pattern in the i-th row indicated in the pattern information among the K partial memories 70-1 to 70-K. The accumulating circuit 116 multiplies each of the N weight values ​​output from the pattern selector 113 by x j The cumulative addition circuit 116 accumulates the accumulated result obtained by the cumulative addition as the product-sum operation result (Z' i (t1)).

[0190] (Fourth embodiment) Next, a market system 10 according to the fourth embodiment will be described. The market system 10 according to the fourth embodiment is the same as that of the third embodiment, except for the matrix calculation circuit 93. Below, the matrix calculation circuit 93 according to the fourth embodiment will be described, and detailed descriptions of the same configuration as that of the third embodiment will be omitted.

[0191] FIG. 18 is a diagram showing the configuration of a matrix calculation circuit 93 according to the fourth embodiment, together with a J memory 91 and an X memory 81.

[0192] The matrix operation circuit 93 includes a pattern memory 52 , a first multiplication circuit 131 , a second multiplication circuit 132 , a first accumulating and adding circuit 133 , a second accumulating and adding circuit 134 , and an output selector 137 .

[0193] The first multiplication circuit 131 multiplies the weight value output from the first partial memory 111 at each clock by the first variable (x i (t1)) and outputs the first multiplication result.

[0194] The second multiplication circuit 132 multiplies the weight value output from the second partial memory 112 for each clock by the first variable (x i (t1)) and outputs the second multiplication result.

[0195] The first cumulative addition circuit 133 has the same configuration as the cumulative addition circuit 116 according to the third embodiment. The first cumulative addition circuit 133 calculates a first cumulative addition value by cumulatively adding the first multiplication results output from the first multiplication circuit 131 for each clock. The first cumulative addition circuit 133 resets the first cumulative addition value to 0 for every N clocks, that is, in synchronization with the update of the index (i). Furthermore, the first cumulative addition circuit 133 outputs the first cumulative addition value in the cycle immediately before resetting the first cumulative addition value to 0.

[0196] The second cumulative addition circuit 134 has the same configuration as the cumulative addition circuit 116 according to the third embodiment. The second cumulative addition circuit 134 calculates a second cumulative addition value by cumulatively adding the second multiplication results output from the second multiplication circuit 132 for each clock. The second cumulative addition circuit 134 resets the second cumulative addition value to 0 for every N clocks, that is, in synchronization with the update of the index (i). In addition, the second cumulative addition circuit 134 outputs the second cumulative addition value in the cycle immediately before resetting the second cumulative addition value to 0.

[0197] The output selector 137 receives a selection value representing 0 or 1 from the pattern memory 52. ​​The output selector 137 selects an accumulated sum output from either the first accumulating circuit 133 or the second accumulating circuit 134, as specified by the selection value. Then, the output selector 137 outputs the selected accumulated sum as one of the N weight values ​​(J i,1 ~J i,N ) and the first variable (x j (t1)) and output it as the result of multiplying and adding the result.

[0198] As described above, the information processing device 20 according to the fourth embodiment calculates the N weight values ​​{J1(J1 ,1 ,J1 ,2 ,…,J1 ,N )} and the N weight values ​​of the second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N )} is stored in the weight memory 50. As a result, the information processing device 20 does not need to generate all of the N×N weight values, but only needs to generate 2×N weight values, and therefore can generate a combinatorial optimization problem in a short time compared to the generation time required to generate all of the multiple weight values. Therefore, the information processing device 20 can generate a combinatorial optimization problem at high speed and cause the solver device 40 to start solving the problem early.

[0199] Furthermore, since the solver device 40 does not need to store all of the N×N weight values, but only needs to store 2×N weight values, it is possible to reduce the size of the weight memory 50. As a result, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0200] The N weight values ​​included in the i row of the matrix (J) may be any one of the K patterns. In this case, the weight memory 50 includes K partial memories 70-1 to 70-K. Among the K partial memories 70-1 to 70-K, the k-th partial memory 70-k stores the N weight values ​​of the k-th pattern of the K patterns. Like the first partial memory 111 and the second partial memory 112, the N weight values ​​are read out from each of the K partial memories 70-1 to 70-K. The pattern information indicates which of the K patterns each of the N rows included in the matrix (J) is.

[0201] In the fourth embodiment, when the weight memory 50 includes K partial memories 70-1 to 70-K, the matrix calculation circuit 93 includes K multiplication circuits and K accumulating circuits. The k-th multiplication circuit among the K multiplication circuits multiplies each of the N weight values ​​output from the k-th partial memory 70-k among the K partial memories 70-1 to 70-K by x j Each of the K accumulating circuits has the same configuration as the first accumulating circuit 133 and the second accumulating circuit 134. The k-th accumulating circuit among the K accumulating circuits adds the multiplication results output from the k-th multiplier circuit for N cycles. That is, the k-th accumulating circuit multiplies each of the N weight values ​​output from the k-th partial memory 70-k by x j The output selector 137 selects the cumulative addition result output from the cumulative addition circuit corresponding to the i-th row pattern indicated in the pattern information among the K cumulative addition circuits as the product-sum operation result (Z' i (t1)).

[0202] Fifth embodiment Next, a control system 210 according to a fifth embodiment will be described.

[0203] In the first to fourth embodiments, an example in which the information processing device 20 is applied to the market system 10 has been described. The information processing device 20 can be applied to other systems as well as the market system 10, as long as the system executes processing using a combinatorial optimization problem on data that changes over time. For example, the information processing device 20 can be applied to a control system 210 that controls the movement of a moving object.

[0204] 19 is a diagram showing an example of the configuration of a control system 210 according to the fifth embodiment. The control system 210 controls a moving object that moves autonomously, such as a self-driving car, a drone, or a robot.

[0205] The control system 210 includes an object detection device 212 , an information processing device 20 , and a control device 214 .

[0206] The object detection device 212 acquires image data from, for example, a camera that captures an image of the surroundings of the moving object to be controlled. The object detection device 212 may acquire sensor data from other sensor devices in addition to image data. The object detection device 212 detects coordinate data representing three-dimensional coordinates for one or more objects around the moving object based on the acquired image data, sensor data, etc. Furthermore, the object detection device 212 may also detect the three-dimensional coordinates of the moving object itself to be controlled.

[0207] The object detection device 212 irregularly and repeatedly outputs data including identification information for identifying one of one or more objects, and coordinate data (input information) representing the coordinates of the object identified by the identification information, to the information processing device 20. Note that the input information may include, in addition to the coordinate data, other related information such as the moving speed, acceleration, moving direction, and type of the object identified by the identification information.

[0208] The control device 214 acquires output data including output information indicating a predetermined operation to be performed on the mobile object in order to control the mobile object from the information processing device 20. The control device 214 controls the mobile object based on the acquired output data.

[0209] The output information may also indicate that a predetermined operation is to be performed on any one of one or more objects around the moving body. For example, the output information may include information indicating that information indicating movement control, a predetermined instruction, a warning, or the like is to be given to any one of one or more objects around the moving body. In this case, the output data includes identification information for identifying any one of the one or more objects, and the output information. Furthermore, when such output data is received, the control device 214 executes a predetermined operation on the object identified by the identification information included in the output data.

[0210] The information processing device 20 has the same configuration as those described in the first to fourth embodiments.

[0211] The information processing device 20 generates a combinatorial optimization problem based on data irregularly provided by the object detection device 212, and causes the solver device 40 to solve the combinatorial optimization problem. Then, the information processing device 20 acquires a solution to the combinatorial optimization problem from the solver device 40, generates output data based on the solution in response to acquiring the solution, and outputs the generated output data to the control device 214, which is an example of a first device.

[0212] The information processing device 20 according to this embodiment can generate a combinatorial optimization problem at high speed and allow the solver device 40 to start solving the problem at an early stage. Furthermore, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0213] (Hardware configuration) Fig. 20 is a diagram showing an example of a hardware configuration of the information processing device 20. A partial configuration in the information processing device 20 not including the solver device 40 is realized by, for example, a computer having a hardware configuration as shown in Fig. 20. The information processing device 20 includes a CPU (Central Processing Unit) 301, a RAM (Random Access Memory) 302, a ROM (Read Only Memory) 303, a storage device 304, and a communication interface device 305. These components are connected by a bus.

[0214] The CPU 301 is one or more processors that executes arithmetic processing, control processing, etc. according to a program. The CPU 301 uses a predetermined area of ​​the RAM 302 as a working area and executes various processes in cooperation with programs stored in the ROM 303, the storage device 304, etc.

[0215] The RAM 302 is a memory such as a Synchronous Dynamic Random Access Memory (SDRAM), and functions as a work area for the CPU 301. The ROM 303 is a memory that stores programs and various information in a non-rewritable manner.

[0216] The storage device 304 is a device that writes and reads data to a semiconductor storage medium such as a flash memory, or a magnetically or optically recordable storage medium, etc. The storage device 304 writes and reads data to the storage medium in response to control from the CPU 301. The communication interface device 305 communicates with external devices via a network in response to control from the CPU 301.

[0217] A program executed by the computer causes the computer to function as the information processing device 20. This program is deployed on the RAM 302 by the CPU 301 (processor) and executed.

[0218] In addition, the program executed by the computer is provided as a file in a format that can be installed on the computer or in a format that can be executed by the computer, and is recorded on a computer-readable recording medium such as a CD-ROM, a flexible disk, a CD-R, or a DVD (Digital Versatile Disk).

[0219] The program may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. The program may be provided or distributed via a network such as the Internet. The program executed by the information processing device 20 may be provided by being pre-installed in the ROM 303 or the like.

[0220] The program for making the computer function as the information processing device 20 has a modular configuration including, for example, an acquisition module, a solver module, a problem generation module, and a process execution module. When this program is executed by the CPU 301, each module is loaded into the RAM 302, and the CPU 301 functions as the acquisition unit 36, the solver device 40, the problem generation unit 42, and the process execution unit 46. When the CPU 301 has multiple processors, these units may be divided among the multiple processors. In addition, this program causes the RAM 302 and the storage device 304 to function as the input memory 32. Note that these configurations may be partially or entirely configured by hardware.

[0221] The solver device 40 may be realized by one or more reconfigurable semiconductor devices such as a field-programmable gate array (FPGA). The solver device 40 may be realized by one or more CPUs, microprocessors, graphics processing units (GPUs), application specific integrated circuits (ASICs), or electronic circuits including these circuits.

[0222] The solver device 40 may be incorporated in the information processing device 20. For example, the solver device 40 may be incorporated as an accelerator in a part of the information processing device 20. The solver device 40 may also include a part of the functions of the information processing device 20, for example, a problem generator 42.

[0223] Furthermore, when the information processing device 20 is realized by a reconfigurable semiconductor device such as an FPGA, the circuit information (configuration data) to be written into the reconfigurable semiconductor device to operate the reconfigurable semiconductor device as the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Furthermore, the circuit information (configuration data) to be written into the reconfigurable semiconductor device to operate the reconfigurable semiconductor device as the information processing device 20 may be provided by being recorded on a computer-readable recording medium.

[0224] Furthermore, when the information processing device 20 is realized by a semiconductor device such as an ASIC, the circuit information representing the configuration of a circuit described in a hardware description language used in the design and manufacture of the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by downloading it via the network. Furthermore, the circuit information representing the configuration of a circuit described in a hardware description language used in the design and manufacture of the information processing device 20 may be provided by being recorded on a computer-readable recording medium.

[0225] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0226] (Additional Note) The above-described embodiments can be summarized as the following technical solutions.

[0227] [Technical proposal 1] An information processing device that executes processing on data, A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory that stores the plurality of weight values; The information processing circuit includes: generating the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writing the plurality of weight values ​​to the first memory; In writing the plurality of weight values, the first partial weight group and the second partial weight group are written into a common area in the first memory, and first information indicating storage positions of each of the plurality of weight values ​​in the first memory is provided to the solver device; The solver device reads the weight values ​​from the first memory based on the first information and solves the solution. Information processing device.

[0228] [Technical proposal 2] The information processing circuit further obtains a solution to the combinatorial optimization problem from the solver device and executes a process based on the solution. An information processing device according to technical proposal 1.

[0229] [Technical proposal 3] a first weight value of the plurality of weight values ​​is identified by an index representing a position in a predetermined first region; The predetermined first region is divided into M partial regions (M is an integer of 3 or more) having the same shape, a first sub-region among the M sub-regions includes a partial weight set that is a part of the plurality of weight values; the partial weight group arranged in each of the M partial regions is represented by any one of K patterns (K is an integer equal to or greater than 2 and smaller than M); the first memory stores the K patterns; The first information indicates which of the K patterns each of the M partial regions includes the partial weight set. An information processing device according to technical proposal 1 or 2.

[0230] [Technical proposal 4] the solver device further includes a second memory configured to store the first information; The information processing circuit, in generating the combinatorial optimization problem, generating the partial weight set of the K patterns based on the data and writing the partial weight set to the first memory; generating the first information based on the data and writing the first information to the second memory; An information processing device according to technical proposal 3.

[0231] [Technical proposal 5] When reading out the first weight value of the plurality of weight values, the solver device Identifying a partial region including the first weight value among the M partial regions; Identifying a pattern in the partial region that includes the first weight value among the K patterns based on the first information; identifying a first address representing a position of the first weight value in the partial region including the first weight value; A weight value in the partial weight group of the identified pattern, which is identified by the first address, is read out from the first memory as the first weight value. An information processing device described in Technical Proposal 4.

[0232] [Technical proposal 6] the cost function includes, as the plurality of decision variables, N decision variables (N is an integer equal to or greater than 2), and includes, as the plurality of weight values, a matrix including weight values ​​of N rows by N columns; The cost function is expressed as a quadratic function of the N decision variables. An information processing device described in any one of technical proposals 3 to 5.

[0233] [Technical proposal 7] Each of the plurality of decision variables is a binary discrete variable. An information processing device according to Technical Proposal 6.

[0234] [Technical proposal 8] The combinatorial optimization problem is a QUBO (Quadratic Unconstrained Binary Optimization) problem. An information processing device described in Technical Proposal 7.

[0235] [Technical proposal 9] The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes an Ising model. An information processing device according to Technical Proposal 8.

[0236] [Technical proposal 10] The solver device solves the Ising problem by a simulated bifurcation algorithm. An information processing device according to Technical Proposal 9.

[0237] [Technical proposal 11] the cost function is a cubic or higher function of the plurality of decision variables; The combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. An information processing device described in Technical Proposal 7.

[0238] [Technical proposal 12] The solver device comprises: a matrix calculation circuit that calculates N second intermediate variables at a first time by matrix multiplying N first intermediate variables at the first time by the matrix; a first circuit that calculates, based on the N second intermediate variables at the first time, N first variables at a second time after the first time and N second variables at the second time; a control circuit that causes the matrix calculation circuit and the first circuit to execute processing from a start time to an end time; an output circuit that generates and outputs the solution based on the N first variables at the end time; Equipped with An i-th spin (i is an integer between 1 and N) among N spins in the Ising model corresponds to an i-th point among N points, an i-th first variable among the N first variables corresponds to the i-th spin; an i-th second variable among the N second variables corresponds to the i-th spin; the i-th first variable represents a position of a point corresponding to the i-th spin; The i-th second variable represents the momentum of a point corresponding to the i-th spin, an i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable; the i-th first intermediate variable is the i-th first variable or a value obtained by multiplying the i-th first variable by a preset coefficient, The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. An information processing device according to technical proposal 10.

[0239] [Technical proposal 13] Each of the weight values ​​of the N rows and N columns included in the matrix is ​​J i,j is represented by The i represents a row number of the matrix, The j represents a column number of the matrix and is an integer equal to or greater than 1 and equal to or less than N, N weight values ​​included in the i row of the matrix are any one of the K patterns; the first information indicates which of the K patterns each of the N rows included in the matrix corresponds to; the first memory includes K partial memories; A k-th partial memory (k is an integer between 1 and K) among the K partial memories stores the k-th pattern among the K patterns. An information processing device according to technical proposal 12.

[0240] [Technical proposal 14] The matrix calculation circuit includes: a first selector that selects and outputs the N weight values ​​output from a partial memory corresponding to the i-th row pattern indicated in the first information, among the K partial memories; an accumulating circuit that accumulates and adds the results of multiplying each of the N weight values ​​output from the first selector by a j-th first intermediate variable among the N first intermediate variables, and outputs the accumulated result as an i-th second intermediate variable among the N second intermediate variables; An information processing device according to technical proposal 13, comprising:

[0241] [Technical proposal 15] The matrix calculation circuit includes: K accumulating circuits; An output selector; Including, a k-th accumulation circuit among the K accumulation circuits multiplies each of the N weight values ​​output from the k-th partial memory among the K partial memories by a j-th first intermediate variable among the N first intermediate variables, accumulates the results, and outputs an accumulation result; The output selector outputs an accumulation result output from an accumulation circuit corresponding to an i-th row pattern indicated in the first information, among the K accumulation circuits, as an i-th second intermediate variable among the N second intermediate variables. An information processing device according to technical proposal 13.

[0242] [Technical proposal 16] the information processing circuit, in acquiring the data, acquires a market condition packet as the data from a market server device which trades N objects (N is an integer of 2 or more); the market packet includes a trading price for at least one of the N objects; The cost function includes N decision variables as the plurality of decision variables; The n-th decision variable (n is an integer between 1 and N) among the N decision variables represents whether or not to trade the n-th object among the N objects. An information processing device according to any one of technical proposals 1 to 15.

[0243] [Technical proposal 17] The data includes coordinate data representing coordinates of at least one object. An information processing device according to any one of technical proposals 1 to 15.

[0244] [Technical proposal 18] An information processing method for executing processing on data by an information processing device, comprising: The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit, Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; each of a plurality of terms constituting the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory that stores the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides first information indicating storage positions of the plurality of weight values ​​in the first memory to the solver device; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. Information processing methods.

[0245] [Technical proposal 19] A program for causing a computer to function as an information processing circuit in an information processing device including a solver device for solving a combinatorial optimization problem and an information processing circuit, the program comprising: The information processing device executes processing on data, The computer, Obtaining the data, A combinatorial optimization problem is generated based on the data, and the combinatorial optimization problem is solved by the solver device. It functions like this, a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory that stores the plurality of weight values; the computer generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the computer, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group into a common area in the first memory, and provides the solver device with first information indicating storage positions of each of the plurality of weight values ​​in the first memory; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. program.

[0246] [Technical proposal 20] Circuit information describing a configuration of a circuit, the circuit information being written in a hardware description language, causing the circuit to function as an information processing device that performs processing on data; The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory that stores the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides first information indicating storage positions of the plurality of weight values ​​in the first memory to the solver device; The solver device reads the weight values ​​from the first memory based on the first information and solves the solution. Circuit information.

[0247] [Technical proposal 21] Circuit information to be written into a reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device, causing the reconfigurable semiconductor device to function as an information processing device that executes processing on data; The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory that stores the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides first information indicating storage positions of the plurality of weight values ​​in the first memory to the solver device; The solver device reads the weight values ​​from the first memory based on the first information and solves the solution. Circuit information. [Explanation of symbols]

[0248] 10. Market System 12 Market Server Equipment 14 Client Device 16 Receiving section 17 Matching section 18 Distribution Department 20 Information processing device 32 Input Memory 36 Acquisition Department 40 Solver Device 42 Problem generation part 46 Processing Execution Unit 50 weight memory 52 Pattern Memory 60 Pseudocode 62 Search circuit 64 Partial area identification circuit 66 Partial address specification circuit 68 Selector 70 Partial Memory 71 Arithmetic circuit 72 Input circuit 73 Output circuit 74 Setting circuit 81X Memory 82 Y Memory 83 Action calculation circuit 84 Time-evolving circuits 85 Control circuit 91 J Memory 92H Memory 93 Matrix calculation circuit 94 Alpha Function Circuit 95 First Adding Circuit 111 First Part Memory 112 Second Part Memory 113 Pattern Selector 115 Multiplication Circuit 116 Accumulation Addition Circuit 121 Adder 122 Reset Selector 123 Second latch circuit 131 First multiplier circuit 132 Second Multiplier Circuit 133 First accumulating circuit 134 Second Accumulation Addition Circuit 137 Output Selector 210 Control System 212 Object detection device 214 Control device

Claims

1. An information processing device that executes processing on data, A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables of the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory for storing the plurality of weight values; The information processing circuit includes: generating the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writing the plurality of weight values ​​to the first memory; In writing the plurality of weight values, the first partial weight group and the second partial weight group are written into a common area in the first memory, and first information indicating storage positions of the plurality of weight values ​​in the first memory is provided to the solver device; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. Information processing device.

2. The information processing circuit further obtains a solution to the combinatorial optimization problem from the solver device and executes a process based on the solution. The information processing device according to claim 1 .

3. a first weight value of the plurality of weight values ​​is identified by an index representing a position in a predetermined first region; The predetermined first region is divided into M partial regions (M is an integer of 3 or more) having the same shape, a first partial region among the M partial regions includes a partial weight set that is a part of the plurality of weight values; the partial weight group arranged in each of the M partial regions is represented by any one of K patterns (K is an integer equal to or greater than 2 and smaller than M); the first memory stores the K patterns; The first information indicates which of the K patterns each of the M partial regions includes the partial weight set. The information processing device according to claim 1 .

4. the solver device further includes a second memory for storing the first information; The information processing circuit, in generating the combinatorial optimization problem, generating the partial weight set of the K patterns based on the data and writing the partial weight set to the first memory; generating the first information based on the data and writing the first information to the second memory; The information processing device according to claim 3 .

5. When retrieving the first weight value of the plurality of weight values, the solver device Identifying a partial region including the first weight value among the M partial regions; Identifying a pattern in the partial region that includes the first weight value among the K patterns based on the first information; identifying a first address representing a position of the first weight value in the partial region including the first weight value; A weight value in the partial weight group of the identified pattern, which is identified by the first address, is read out from the first memory as the first weight value. The information processing device according to claim 4.

6. the cost function includes, as the plurality of decision variables, N decision variables (N is an integer equal to or greater than 2), and includes, as the plurality of weight values, a matrix including weight values ​​of N rows by N columns; The cost function is expressed as a quadratic function of the N decision variables. The information processing device according to claim 3 .

7. Each of the plurality of decision variables is a binary discrete variable. The information processing device according to claim 6.

8. The combinatorial optimization problem is a quadratic unconstrained binary optimization problem (QUBO). The information processing device according to claim 7.

9. The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes an Ising model. The information processing device according to claim 8.

10. The solver device solves the Ising problem by a simulated bifurcation algorithm. The information processing device according to claim 9.

11. the cost function is a cubic or higher function of the plurality of decision variables; The combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. The information processing device according to claim 7.

12. The solver device comprises: a matrix calculation circuit that calculates N second intermediate variables at a first time by matrix multiplying N first intermediate variables at the first time by the matrix; a first circuit that calculates, based on the N second intermediate variables at the first time, N first variables at a second time after the first time and N second variables at the second time; a control circuit that causes the matrix calculation circuit and the first circuit to execute processing from a start time to an end time; an output circuit that generates and outputs the solution based on the N first variables at the end time; Equipped with An i-th spin (i is an integer between 1 and N) among N spins in the Ising model corresponds to an i-th point among N points, an i-th first variable among the N first variables corresponds to the i-th spin; an i-th second variable among the N second variables corresponds to the i-th spin; The i-th first variable represents a position of a point corresponding to the i-th spin, The i-th second variable represents the momentum of a point corresponding to the i-th spin, an i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable; the i-th first intermediate variable is the i-th first variable or a value obtained by multiplying the i-th first variable by a preset coefficient, The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. The information processing device according to claim 10.

13. Each of the weight values ​​of the N rows and N columns included in the matrix is ​​J ｉ，ｊ is represented by The i represents a row number of the matrix, The j represents a column number of the matrix and is an integer equal to or greater than 1 and equal to or less than N, N weight values ​​included in the i row of the matrix are any one of the K patterns, the first information indicates which of the K patterns each of the N rows included in the matrix corresponds to; the first memory includes K partial memories; A k-th partial memory (k is an integer between 1 and K) among the K partial memories stores the k-th pattern of the K patterns. The information processing device according to claim 12.

14. The matrix calculation circuit includes: a first selector that selects and outputs the N weight values ​​output from a partial memory corresponding to an i-th row pattern indicated in the first information, among the K partial memories; an accumulating circuit that accumulates and adds the results of multiplying each of the N weight values ​​output from the first selector by a j-th first intermediate variable among the N first intermediate variables, and outputs the accumulated result as an i-th second intermediate variable among the N second intermediate variables; The information processing apparatus according to claim 13 .

15. The matrix calculation circuit includes: K accumulating circuits; An output selector; Including, a k-th accumulation circuit among the K accumulation circuits multiplies each of the N weight values ​​output from the k-th partial memory among the K partial memories by a j-th first intermediate variable among the N first intermediate variables, accumulates the results, and outputs an accumulation result; The output selector outputs an accumulation result output from an accumulation circuit corresponding to an i-th row pattern indicated in the first information, among the K accumulation circuits, as an i-th second intermediate variable among the N second intermediate variables. The information processing device according to claim 13.

16. the information processing circuit, in acquiring the data, acquires a market condition packet as the data from a market server device which trades N objects (N is an integer of 2 or more); the market packet includes a trading price for at least one of the N objects; The cost function includes N decision variables as the plurality of decision variables, The n-th decision variable (n is an integer between 1 and N) among the N decision variables represents whether or not to trade the n-th object among the N objects. The information processing device according to claim 1 .

17. The data includes coordinate data representing coordinates of at least one object. The information processing device according to claim 1 .

18. An information processing method for executing processing on data by an information processing device, comprising: The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit, Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; each of a plurality of terms constituting the cost function is expressed by multiplying one or more decision variables among the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory for storing the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides the solver device with first information indicating storage positions of the plurality of weight values ​​in the first memory; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. Information processing methods.

19. A program for causing a computer to function as an information processing circuit in an information processing device including a solver device for solving a combinatorial optimization problem and an information processing circuit, the program comprising: The information processing device executes processing on data, The computer, Obtaining the data, A combinatorial optimization problem is generated based on the data, and the combinatorial optimization problem is solved by the solver device. It functions like this, a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables of the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory for storing the plurality of weight values; the computer generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the computer writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides the solver device with first information indicating storage positions of the respective plurality of weight values ​​in the first memory; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. program.

20. Circuit information describing a configuration of a circuit, the circuit information being written in a hardware description language, causing the circuit to function as an information processing device that performs processing on data; The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables of the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory for storing the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides first information indicating storage positions of the plurality of weight values ​​in the first memory to the solver device; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. Circuit information.

21. Circuit information to be written into a reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device, causing the reconfigurable semiconductor device to function as an information processing device that executes processing on data; The information processing device includes: A solver device for solving a combinatorial optimization problem; An information processing circuit; Equipped with The information processing circuit includes: Obtaining the data, generating a combinatorial optimization problem based on the data, and causing the solver device to solve the combinatorial optimization problem; a cost function for the combinatorial optimization problem including a plurality of decision variables and a plurality of weight values; a term included in the cost function is expressed by multiplying one or more decision variables of the plurality of decision variables by any one of the plurality of weight values; A first partial weight group, which is a part of the plurality of weight values, is the same as a second partial weight group, which is another part of the plurality of weight values; the solver device includes a first memory for storing the plurality of weight values; the information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory; the information processing circuit writes the first partial weight group and the second partial weight group into a common area in the first memory in writing the plurality of weight values, and provides first information indicating storage positions of the plurality of weight values ​​in the first memory to the solver device; The solver device reads the weight values ​​from the first memory based on the first information to solve the problem. Circuit information.

Images