Infrared LED element

Abstract

To provide an infrared LED element capable of securing high light extraction efficiency and further improving light distribution of emitted light while having a predetermined thickness.SOLUTION: There is provided an infrared LED element including: an InP substrate having a thickness of 30 μm or more, one main surface thereof being a light emitting surface; and a laminate disposed on a main surface side different from the light emitting surface of the InP substrate. The laminate includes: a first semiconductor layer of a first conductive type that is p-type or n-type; an active layer formed on the upper layer of the first semiconductor layer; and a second semiconductor layer of a second conductive type different from the first conductive type, the second semiconductor layer being formed on the upper layer of the active layer. When a peak wavelength is λp, the surface roughness of the light emission surface of the InP substrate is Ra1, the surface roughness of the side surface of the InP substrate is Ra2, and the refractive index of the InP substrate corresponding to the peak wavelength λp is n (λp), a predetermined expression is satisfied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an infrared LED element, and in particular to an infrared LED element with an emission wavelength of 1,000 nm or more. [Background technology]

[0002] In recent years, semiconductor light-emitting elements that emit light in the infrared region with wavelengths of 1,000 nm or more have been widely used in a variety of applications, including security and surveillance cameras, gas detectors, medical sensors, and industrial equipment.

[0003] Semiconductor light-emitting devices with an emission wavelength of 1,000 nm or more are generally manufactured by the following procedure. A first conductivity type semiconductor layer, an active layer (sometimes called an "emitting layer"), and a second conductivity type semiconductor layer are epitaxially grown in this order on an InP substrate used as a growth substrate, and then electrodes for current injection are formed on the semiconductor wafer. The device is then cut into chips.

[0004] In the past, semiconductor laser elements have been the leading semiconductor light-emitting element with an emission wavelength of 1,000 nm or more, but LED elements have not seen as much development as laser elements, due in part to the lack of applications for these elements.

[0005] However, in recent years, with the spread of applications, there is an increasing demand for high efficiency infrared LED elements. For example, Patent Document 1 discloses an infrared LED element in which electrodes are formed on the top and bottom surfaces of a wafer in which an LED structure is crystal-grown on an InP substrate, and a voltage is applied between the two electrodes to inject a current into the active layer, causing light to be emitted. Patent Document 2 discloses a structure in which a wafer in which an epitaxial semiconductor film of an LED structure is crystal-grown on a growth substrate is bonded to a conductive support substrate, and then the growth substrate is removed to increase the light extraction efficiency.

[0006] Furthermore, in recent years, the spread of applications for the relevant wavelength band has led to a demand for smaller, lower-profile LEDs with higher luminous efficiency. As a configuration that meets this demand, Patent Document 3 discloses a structure called flip-chip mounting, in which the main surface of the substrate is used as the light-emitting surface, and a pair of electrodes formed on the opposite surface of the substrate are bonded to a submount, eliminating the need for wire bonding. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 4-282875 [Patent Document 2] JP 2013-30606 A [Patent Document 3] JP 2000-114595 A [Patent Document 4] Patent No. 6587765 Summary of the Invention [Problem to be solved by the invention]

[0008] The growth substrate and semiconductor layer of an infrared LED element with an emission wavelength of 1,000 nm or more are made of a material consisting of a combination of multiple elements selected from Al, Ga, In, As, and P. Many of these materials are known to have a high refractive index. For example, InP has a refractive index of about 3.1 to 3.3 for light with a wavelength of 1,000 nm or more and 2,000 nm or less. For this reason, when extracting light from the InP substrate side, if no treatment is applied to the InP substrate, most of the light generated in the semiconductor layer is totally reflected at the boundary between the InP substrate and air. It is expected that the light reflected at the interface with the InP substrate and returned to the active layer side is extracted to the outside after repeated reflections, but part of the light is absorbed during the process of traveling through the InP substrate and the semiconductor layer, resulting in a decrease in extraction efficiency.

[0009] Conventionally, in order to extract more light, semiconductor light-emitting elements have been subjected to a process for forming a scattering structure on a light emission surface, which emits light in a desired emission direction, and on the side surfaces of the semiconductor light-emitting element, as shown in Patent Document 4, for example.

[0010] In addition, in the above-mentioned Patent Document 4, the side surface that has been treated to form a scattering structure is depicted as having projections and recesses, and the side surface that has not been treated to form a scattering structure is depicted as a flat surface. This representation is a schematic representation to show the difference between the extremely fine projections and recesses on the surface on which the scattering structure is formed.

[0011] However, as will be described later with reference to FIG. 3I in the section "Description of Embodiments," in reality, unevenness is inevitably formed on the side surface of an InP substrate during the process of separating elements (here, the dicing process).

[0012] When designing devices that incorporate LEDs, it is often assumed that the light distribution of the emitted light will be a Lambertian distribution that is proportional to cosθ for the emission angle θ. For this reason, it is considered ideal for the light distribution of light emitted from an infrared LED element to be close to a Lambertian distribution.

[0013] Conventional infrared LED elements have a sufficiently small side surface area compared to the light-emitting surface area, so the light distribution of the light emitted from an infrared LED element could be controlled to some extent by adjusting the light emitted from the light-emitting surface without being too concerned about the influence of the light emitted from the side surfaces.

[0014] However, in recent years, there has been a demand for smaller infrared LED elements, and the ratio of the area of ​​the entire side surface to the area of ​​the light emitting surface has gradually increased. As a result, the influence of light emitted from the side surface of the element has become more pronounced in the light distribution of the light emitted from the infrared LED element.

[0015] Under these circumstances, if a scattering structure is simply provided on the light exit surface and side surfaces of an infrared LED element as in the past in order to increase the light extraction efficiency, the light distribution of the light emitted from the infrared LED element will deviate significantly from the ideal Lambertian distribution.

[0016] Therefore, an object of the present invention is to provide an infrared LED element having a predetermined thickness that ensures high light extraction efficiency and has an improved light distribution of emitted light. [Means for solving the problem]

[0017] The semiconductor light-emitting element of the present invention comprises: An infrared LED element that emits infrared light having a peak wavelength in the range of 1,000 nm or more and 2,000 nm or less, An InP substrate having a thickness of 30 μm or more and a light emitting surface as one principal surface; a laminate disposed on a main surface side of the InP substrate different from the light emission surface, The laminate comprises: A first semiconductor layer of a first conductivity type, which is p-type or n-type; an active layer formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type different from the first conductivity type formed on the active layer; The present invention is characterized in that, when the peak wavelength is λp, the surface roughness of the light emitting surface of the InP substrate is Ra1, the surface roughness of the side surface of the InP substrate is Ra2, and the refractive index of the InP substrate corresponding to the peak wavelength λp is n(λp), the following formula (1) and formula (2) are satisfied. Ra1 ≧ λp / n(λp) (1) Ra2 ≦ λp / (2×n(λp)) (2)

[0018] The infrared LED element is The light distribution of the emitted infrared light may be substantially a Lambertian distribution.

[0019] In this specification, unless otherwise specified, the term "surface roughness" refers to the "arithmetic mean roughness (Ra)" of the surface. The "arithmetic mean roughness (Ra)" conforms to JIS B 0601 (2001).

[0020] In addition, in this specification, "substantially a Lambertian distribution" means that the minimum value of the residual sum of squares E between an ideal Lambertian distribution and the light distribution of the infrared light emitted from the actual infrared LED element is 0.05 or less. The residual sum of squares E is calculated by taking the emission angle of the infrared light emitted from the infrared LED element when the normal direction of the light emission surface is 0° and expressing it as θ i (-90°≦θ i ≦90°: i = 1, , N), and i The light intensity value at I i and the light intensity value I i When the normalization constant of is α, it is derived by the following formula (3). The normalization coefficient α is a constant that minimizes the residual sum of squares E, and is obtained by numerical analysis (for example, the steepest descent method).

[0021]

number

[0022] Conventional infrared LED elements are generally fabricated so that the main surface of the InP substrate, i.e., the light emitting surface, is 1 mm x 1 mm in size. However, as mentioned above, in recent years, there has been a demand for smaller elements, and infrared LED elements have been fabricated with a light emitting surface of 200 μm x 200 μm to 400 μm x 400 μm, or a rectangular light emitting surface with a long side length of 200 μm to 400 μm. Further miniaturization of infrared LED elements is still being considered.

[0023] As an example, in an infrared LED element with a light exit surface of 300 μm×300 μm and an InP substrate with a thickness of 30 μm, we check the ratio of the area of ​​the light exit surface of the InP substrate to the area of ​​the side surface. The area of ​​the light exit surface is 300 μm×300 μm=90,000 μm. 2The side area of ​​the InP substrate is 30μm×300μm×4 sides=36,000μm 2 In other words, in this configuration example, the ratio of the side surface area of ​​the InP substrate to the area of ​​the light emitting surface is about 40%. In a conventional 1 mm x 1 mm infrared LED element, this ratio was 4% or less, which was sufficiently small.

[0024] Most of the infrared light emitted from the side of the InP substrate is emitted in a direction parallel to the light emission surface. Therefore, in the light distribution of the infrared light emitted from the infrared LED element, the influence of the infrared light emitted from the side of the InP substrate is likely to appear especially in the region where the emission angle θ with respect to the light emission surface is close to 90°.

[0025] Specifically, when the ratio of the side surface area to the light exit surface area increases, the amount of infrared light emitted from the side surface of the InP substrate increases. In this case, the light distribution of the infrared light emitted from the infrared LED element shows a tendency for the intensity of the infrared light to increase sharply in the region where the exit angle θ relative to the light exit surface is close to 90°.

[0026] As described above, the Lambertian distribution is a distribution in which the light distribution of emitted light is proportional to cos θ with respect to the emission angle θ. In other words, the Lambertian distribution is a distribution in which the light intensity is maximum when the emission angle θ is 0° when the light emission surface is used as the reference, and gradually decreases as the angle approaches 90°.

[0027] Therefore, in order to bring the light distribution of light emitted from an infrared LED element of a certain thickness closer to a Lambertian distribution, it is necessary to reduce the amount of infrared light emitted from the side surface of the InP substrate and create a distribution in which the light intensity gradually decreases as the emission angle θ approaches 90°.

[0028] With the infrared LED element having the above configuration, the amount of light emitted from the light exit surface is increased, and the amount of light emitted from the side surface of the InP substrate is reduced. Therefore, the light distribution of the infrared light emitted from the infrared LED element is less affected by the infrared light emitted from the side surface of the InP substrate, and becomes a light distribution based on the infrared light emitted from the light exit surface, i.e., a substantially Lambertian distribution.

[0029] In the infrared LED element, The surface roughness Ra1 is preferably 3 μm or less.

[0030] If Ra is extremely large, the ratio of the height of the projections and recesses to the thickness of the board becomes very large, which can lead to a decrease in mechanical strength and make the LED elements more susceptible to breakage, which can make handling during mounting difficult.

[0031] In the infrared LED element, The surface roughness Ra2 is preferably 0.03 μm or more.

[0032] Depending on the application, LED elements may be used in a state where they are sealed with resin, etc. In such cases, by having a minimum Ra within the range that satisfies the above formula (2), it is possible to increase the surface area and improve the adhesion between the LED element and the resin due to the anchor effect, resulting in an LED element with higher added value.

[0033] If the surface roughness Ra1 of the light exit surface becomes too large, the durability of the element itself may deteriorate and unevenness may occur in the light distribution, and the light distribution of the infrared light emitted from the light exit surface may deviate significantly from a Lambertian distribution.

[0034] Furthermore, taking into consideration the processing accuracy of the surface treatment of the InP substrate, the surface roughness Ra1 is preferably 3 μm or less as described above.

[0035] Furthermore, although it is possible to make the unevenness formed in the dicing process closer to a flat surface by polishing, etching, or the like, it is preferable that the surface roughness Ra2 be 0.03 μm or more from the viewpoints of improving the processing accuracy of the surface treatment of the InP substrate and the light extraction efficiency even if only slightly.

[0036] The infrared LED element is The semiconductor device may include a first electrode formed on the first semiconductor layer in a region where the active layer is not formed, and a second electrode formed on the second semiconductor layer at a position spaced apart from the first electrode in a direction parallel to the light emitting surface of the InP substrate.

[0037] According to the above configuration, one main surface of the InP substrate is used as the light-emitting surface, and the electrodes formed on the opposite main surface are connected to current-carrying pattern electrodes mounted on the stem, thereby realizing a flip-chip type infrared LED element with an increased light extraction area and improved extraction efficiency.

[0038] The infrared LED element is the first semiconductor layer is formed on the InP substrate; The concentration of the first conductive type dopant in the InP substrate is 1×10 18 / cm 3 It is acceptable if it is less than that.

[0039] When light generated in an infrared LED element and traveling through an InP substrate collides with free carriers present in the InP substrate, it is absorbed by the free carriers. Therefore, the concentration of free carriers in the InP substrate affects the light extraction efficiency of an infrared LED element. The concentration of free carriers in the InP substrate is proportional to the concentration of the first conductivity type dopant doped into the InP substrate.

[0040] According to the above configuration, light absorption by free carriers in the InP substrate is suppressed, and the light extraction efficiency is further improved.

[0041] In the infrared LED element, The InP substrate may be doped with a transition metal capable of forming a deep level.

[0042] In the manufacture of InP substrates, even in substrates to which no dopants are added (sometimes called "undoped substrates"), some amount of carriers may still be generated due to impurity diffusion and lattice defects, although this is generally lower than in the case of doping.

[0043] Transition metals such as Fe and W form deep levels in the InP substrate and capture carriers generated due to impurity diffusion and lattice defects. As a result, the generation of free carriers is suppressed. Therefore, by using an infrared LED element with the above configuration, it is possible to further reduce free carrier absorption and further increase the light extraction efficiency.

[0044] In the infrared LED element, The InP substrate has an intermediate refractive index film on the light emitting surface, the intermediate refractive index film having a refractive index lower than that of the InP substrate and higher than that of air, and may not have the intermediate refractive index film on the side surface.

[0045] By using the infrared LED element having the above configuration, a region where the refractive index changes stepwise between the light emitting surface and the air is formed, and the large change in the refractive index between the InP substrate and the air is mitigated. Therefore, with this configuration, the infrared light generated in the element is more easily extracted from the InP substrate than in an infrared LED element that does not have an intermediate refractive index film layer. As a result, the light extraction efficiency of the infrared LED element is further improved.

[0046] In addition, the above configuration improves the light extraction efficiency of the infrared light at the light exit surface, so that the influence of the infrared light emitted from the side surface of the InP substrate on the light distribution of the infrared light emitted from the infrared LED element is reduced. Therefore, the infrared LED element of the above configuration can make the light distribution of the emitted infrared light closer to a Lambertian distribution. Effect of the Invention

[0047] According to the present invention, an infrared LED element is realized which ensures high light extraction efficiency and has a given thickness while improving the light distribution of emitted light. [Brief description of the drawings]

[0048] [Figure 1] 1 is a cross-sectional view showing a schematic structure of an infrared LED element according to one embodiment. [Figure 2A] 2 is a cross-sectional view of the state shown in FIG. 1 with the submount and the pattern electrode omitted. [Figure 2B] 2B is a schematic plan view of the state of FIG. 2A as viewed from the opposite side to the InP substrate. FIG. [Figure 3A] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3B] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3C] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3D] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3E] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3F] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3G] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3H] 1A to 1C are cross-sectional views illustrating a process for producing an infrared LED element. [Figure 3I] This is an image taken of the side of the InP substrate immediately after dicing. [Figure 4] FIG. 13 is a schematic cross-sectional view for explaining the structure of a stem used in verification. [Diagram 5]1A to 1C are schematic diagrams illustrating a method for measuring the light distribution of infrared light emitted from a verification sample. [Figure 6A] 11 is a graph showing an example of a radiation intensity distribution of a verification sample. [Figure 6B] 11 is a graph showing an example of a radiation intensity distribution of a verification sample. [Figure 7] 13 is a graph showing an example of the correlation between the surface roughness Ra1 of the light exit surface and the surface roughness Ra2 of the side surfaces, and the residual sum of squares E in a verification sample. [Figure 8] 13 is a graph showing an example of the correlation between the surface roughness Ra1 of the light exit surface and the surface roughness Ra2 of the side surfaces, and the residual sum of squares E in a verification sample. [Figure 9] FIG. 4 is a cross-sectional view showing a schematic structure of an infrared LED element according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] The infrared LED element of the present invention will be described below with reference to the drawings. Note that the following drawings of the infrared LED element are all schematic illustrations, and the dimensional ratios and numbers in the drawings do not necessarily match the actual dimensional ratios and numbers.

[0050] In this specification, the expression "layer B is formed on layer A" is intended to include not only the case where layer B is formed directly on the surface of layer A, but also the case where layer B is formed on the surface of layer A via a thin film. Note that "thin film" here refers to a layer having a thickness of 1 μm or less, preferably a layer having a thickness of 50 nm or less, and more preferably a layer having a thickness of 10 nm or less. In addition, the upper layer here refers to the layer in the direction away from the InP substrate.

[0051] Fig. 1 is a cross-sectional view showing a schematic structure of this embodiment of an infrared LED element 1. As shown in Fig. 1, the infrared LED element 1 includes an InP substrate 3 and a semiconductor layer 10 formed on the InP substrate 3. Fig. 1 shows, as an example, a state in which the infrared LED element 1 is flip-chip mounted on a submount 35. In the example shown in Fig. 1, the infrared LED element 1 is fixed on the submount 35 via pattern electrodes 37a and 37b.

[0052] Fig. 2A is a cross-sectional view in which the submount 35 and the pattern electrodes (37a, 37b) are omitted from the state shown in Fig. 1, and is upside down for convenience of explanation. Fig. 2B is a schematic plan view of the state shown in Fig. 2A as viewed from the opposite side to the InP substrate 3.

[0053] 1, infrared light L1 generated in the semiconductor layer 10 (more specifically, in the active layer 13 described below) is extracted from the surface of the InP substrate 3 opposite the submount 35, i.e., the light emission surface 3a. The infrared light L1 has a peak wavelength λp of 1,000 nm or more and 2,000 nm or less.

[0054] [Element structure] The structure of the infrared LED element 1 will be described in detail below.

[0055] (InP substrate 3) The infrared LED element 1 includes an InP substrate 3. As will be described later in the description of the manufacturing method, the InP substrate 3 is also used as a growth substrate for growing the semiconductor layer 10. The InP substrate 3 has a thickness of 30 μm or more.

[0056] In this embodiment, the InP substrate 3 has a thickness of 150 μm and is doped with Fe. Fe is a type of transition metal that forms a deep level in InP, and the InP substrate 3 exhibits semi-insulation properties by being doped with such a metal at an extremely low concentration. More specifically, the InP substrate 3 is doped with Fe at a concentration of 1×10 7A substrate with a resistivity of Ω·cm or more was used. As a transition metal that forms such a deep level, W, etc., can be used in addition to Fe.

[0057] The InP substrate 3 may be an undoped substrate. Even if the substrate is undoped, impurities are inevitably mixed in during the growth of the substrate, resulting in a doping rate of 1×10 17 / cm 3 The impurities are doped at a dopant concentration of less than 1000 nm.

[0058] The thickness of the InP substrate 3 is preferably 1,000 μm or less, and more preferably 700 μm or less.

[0059] In the infrared LED element 1 of this embodiment, uneven portions (6a, 6b) are formed on the light emitting surface 3a and the side surface 3b of the InP substrate 3. The arithmetic mean roughness of the uneven portion 6a corresponds to the surface roughness Ra1 of the light emitting surface 3a, and the arithmetic mean roughness of the uneven portion 6b corresponds to the surface roughness Ra2 of the side surface 3b.

[0060] The light exit surface 3a has an uneven portion 6a formed thereon so that the surface roughness Ra1 satisfies the above formula (1). The side surface 3b has an uneven portion 6b formed thereon so that the surface roughness Ra2 satisfies the above formula (2). For completeness, the above formulas (1) and (2) are presented again. Ra1 ≧ λp / n(λp) (1) Ra2 ≦ λp / (2×n(λp)) (2)

[0061] As described above, λp is the peak wavelength of the infrared light L1, and n(λp) is the refractive index of the InP substrate 3 corresponding to the peak wavelength λp.

[0062] Furthermore, the infrared LED element 1 of this embodiment is provided with an intermediate refractive index film 31 made of a material with high transmittance for infrared light L1 on the light emission surface 3a of the InP substrate 3. The intermediate refractive index film 31 is selected from materials whose refractive index is between that of InP and air. Examples of materials constituting the intermediate refractive index film 31 include SiOx , SiON, SiN x , TiO x , MgO x or a combination of two or more of these materials may be employed.

[0063] From the viewpoint of bringing the overall light distribution of the infrared light L1 emitted from the infrared LED element 1 closer to a Lambertian distribution, it is preferable that the ratio of the area of ​​the light emitting surface 3a to the overall area of ​​the side surfaces 3b of the InP substrate 3 be 0.1 or more, assuming that the thickness of the InP substrate 3 is 30 μm or more. Also, from the viewpoint of stably controlling the light distribution, it is preferable that the ratio of the area of ​​the light emitting surface 3a to the overall area of ​​the side surfaces 3b of the InP substrate 3 be 1.0 or less.

[0064] (Semiconductor layer 10) The infrared LED element 1 has a semiconductor layer 10 formed on an InP substrate 3. The semiconductor layer 10 is composed of a laminate of multiple layers. Specifically, the semiconductor layer 10 includes a first semiconductor layer 11, an active layer 13, and a second semiconductor layer 15.

[0065] The first semiconductor layer 11 is formed on the upper surface of the InP substrate 3. In this embodiment, the first semiconductor layer 11 is made of n-type (corresponding to the first conductivity type) InP. The thickness of the first semiconductor layer 11 is not limited, but is, for example, 1,000 nm or more and 20,000 nm or less, and preferably 3,000 nm or more and 10,000 nm or less. The dopant concentration of the first semiconductor layer 11 is preferably 1×10 17 / cm 3 That's it, 5 x 10 18 / cm 3 More preferably, it is 5×10 or less. 17 / cm 3 That's it, 4 x 10 18 / cm 3 The n-type dopant material contained in the first semiconductor layer 11 may be Sn, Si, S, Ge, Se, or the like, with Si being particularly preferred.

[0066] As shown in FIGS. 1 and 2A, the first semiconductor layer 11 is formed over almost the entire surface of the InP substrate 3.

[0067] The active layer 13 is composed of a semiconductor layer formed on the first semiconductor layer 11. More specifically, the active layer 13 is formed on a portion of the first semiconductor layer 11, as shown in Figures 1 and 2A.

[0068] The active layer 13 is appropriately selected from materials capable of generating light of a target wavelength and capable of being epitaxially grown on the InP substrate 3. For example, the active layer 13 may have a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or may have an MQW (Multiple Quantum Well) structure including a well layer made of GaInAsP, AlGaInAs, or InGaAs, and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP having a larger band gap energy than the well layer.

[0069] The film thickness of the active layer 13 is 50 nm to 2,000 nm, preferably 100 nm to 1,000 nm, when the active layer 13 has a single layer structure. When the active layer 13 has an MQW structure, the active layer 13 is formed by stacking well layers and barrier layers having a film thickness of 5 nm to 20 nm in the range of 2 to 50 periods.

[0070] The active layer 13 may be doped to n-type or p-type, or may be undoped. When doped to n-type, for example, Si can be used as a dopant.

[0071] The second semiconductor layer 15 is formed on the active layer 13. In this embodiment, the second semiconductor layer 15 is composed of a p-type (corresponding to the second conductivity type) semiconductor layer, and includes a p-type cladding layer and a p-type contact layer.

[0072] In the second semiconductor layer 15, the p-type cladding layer is made of p-type InP. The thickness of this p-type cladding layer is not limited, but is, for example, 1,000 nm or more and 10,000 nm or less, and preferably 2,000 nm or more and 5,000 nm or less. The p-type dopant concentration of the p-type cladding layer is preferably 1×10 17 / cm 3 That's it, 5 x 10 18 / cm 3 More preferably, it is 5×10 or less. 17 / cm 3 That's it, 3 x 10 18 / cm 3 The following is the result.

[0073] In the second semiconductor layer 15, the p-type contact layer is made of p-type GaInAsP. The thickness of this p-type contact layer is not limited, but is, for example, 10 nm or more and 1,000 nm or less, and preferably 50 nm or more and 500 nm or less. The p-type dopant concentration of the p-type contact layer is preferably 5×10 17 / cm 3 That's it, 3 x 10 19 / cm 3 More preferably, it is 1×10 18 / cm 3 That's it, 2 x 10 19 / cm 3 The following is the result.

[0074] As the p-type dopant material contained in the p-type cladding layer and the p-type contact layer constituting the second semiconductor layer 15, Zn, Mg, Be, etc. can be used, with Zn or Mg being preferred, and Zn being particularly preferred.

[0075] The first semiconductor layer 11 and the second semiconductor layer 15 are appropriately selected from materials that do not absorb the infrared light L1 generated in the active layer 13 and that can be epitaxially grown by lattice matching with the InP substrate 3. For example, the first semiconductor layer 11 and the second semiconductor layer 15 can be made of materials such as GaInAsP and AlGaInAs in addition to InP.

[0076] In this embodiment, the second semiconductor layer 15 has a laminated structure of a cladding layer and a contact layer, but the present invention does not exclude a case where the cladding layer and the contact layer are made of the same material. Also, the present invention does not exclude a case where the first semiconductor layer 11 is composed of a laminated body of a cladding layer and a contact layer made of different materials.

[0077] (first electrode 21) 1 and 2A, an active layer 13 is formed on a partial region of the first semiconductor layer 11. The infrared LED element 1 includes a first electrode 21 formed on the first semiconductor layer 11 in a region where the active layer 13 is not formed.

[0078] The first electrode 21 forms an ohmic connection with the first semiconductor layer 11. The first electrode 21 is made of, for example, Au / Ge / Au, Au / Ge / Ni / Au, AuGe, AuGeNi, or the like, and may include a plurality of these materials. The thickness of the first electrode 21 is not limited, but is, for example, 50 nm or more and 1000 nm or less, and preferably 100 nm or more and 500 nm or less.

[0079] (Insulating layer 19) 1 and 2A, the infrared LED element 1 includes an insulating layer 19 formed so as to cover part of the sidewall and upper surface of the semiconductor layer 10. The insulating layer 19 is made of a material that exhibits electrical insulation and has high transmittance to infrared light L1. The transmittance of the insulating layer 19 to infrared light L1 is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more. When the peak wavelength λp of the infrared light L1 is 1,000 nm or more and 2,000 nm or less, the insulating layer 19 can be made of a material such as SiO2, SiN, or Al2O3.

[0080] The thickness of the insulating layer 19 is arbitrary, but is, for example, 50 nm or more and 5,000 nm or less, and preferably 100 nm or more and 1,000 nm or less.

[0081] (Second electrode 22) 1 and 2A, the infrared LED element 1 includes a second electrode 22 formed on the second semiconductor layer 15. This second electrode 22 is disposed at a position spaced apart from the first electrode 21 in a direction parallel to the surface of the InP substrate 3 (see also FIG. 2B).

[0082] The second electrode 22 in this embodiment constitutes a partial electrode that is discretely arranged on a part of the second semiconductor layer 15. In the example shown in Fig. 2B, a plurality of second electrodes 22 are discretely arranged on a plane when viewed from above. In reality, when the infrared LED element 1 is viewed from the side opposite the InP substrate 3, the second electrode 22 is hidden by the second pad electrode 27 described below and cannot be seen, but from the viewpoint of facilitating understanding, the second electrode 22 is illustrated by a dashed line in Fig. 2B.

[0083] The second electrode 22 is made of a material capable of making ohmic contact with the second semiconductor layer 15, such as Au / Zn / Au, AuZn, AuBe, or the like. The second electrode 22 may include a plurality of partial electrodes made of these materials. As described above, when the second semiconductor layer 15 includes a contact layer, an ohmic contact is formed between the contact layer and the second electrode 22. The thickness of the second electrode 22 is not limited, but is, for example, 50 nm or more and 500 nm or less, and preferably 100 nm or more and 300 nm or less.

[0084] As shown in FIGS. 1 and 2A, an insulating layer 19 is formed in an area of ​​the upper layer of the second semiconductor layer 15 where the second electrode 22 is not formed.

[0085] (Reflecting electrode 26) As shown in Fig. 1 and Fig. 2A, the infrared LED element 1 of this embodiment includes a reflective electrode 26 on the second electrode 22. The reflective electrode 26 serves to return the infrared light L1 generated in the active layer 13, which has traveled toward the second semiconductor layer 15 and passed through the insulating layer 19, to the InP substrate 3. The reflective electrode 26 is made of a conductive material that exhibits high reflectance to the infrared light L1. The reflectance of the reflective electrode 26 to the infrared light L1 is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more. When the peak wavelength λp of the infrared light L1 is 1,000 nm or more and 2,000 nm or less, the reflective electrode 26 can be made of a metal material such as Ag, an Ag alloy, Au, Al, or Cu.

[0086] The thickness of the reflective electrode 26 is not particularly limited, but is, for example, not less than 10 nm and not more than 2,000 nm, and preferably not less than 100 nm and not more than 1,000 nm.

[0087] Since the second electrode 22 needs to achieve ohmic contact with the second semiconductor layer 15, it is made of a material that can be easily alloyed with the second semiconductor layer 15 (more specifically, the contact layer) to achieve low contact resistance. For this reason, as described above, AuZn, AuBe, an Au / Zn / Au layer structure, or the like is used for the second electrode 22. However, these materials have a relatively low reflectance for the infrared light L1. Therefore, if the second electrode 22 is formed on the entire surface of the second semiconductor layer 15, the proportion of the infrared light L1 that is absorbed by the second electrode 22 out of the infrared light L1 that is generated in the active layer 13 and travels toward the second semiconductor layer 15 will be high.

[0088] In contrast, as described above, in the infrared LED element 1 of this embodiment, the second electrodes 22 are arranged discretely on the upper layer of the second semiconductor layer 15, and the insulating layer 19 made of a material exhibiting high transmittance to the infrared light L1 is formed in the region of the upper layer of the second semiconductor layer 15 where the second electrodes 22 are not formed. Then, the reflective electrode 26 made of a material having a higher reflectance to the infrared light L1 than the second electrode 22 is formed on the upper layer of this insulating layer 19. As a result, a part of the infrared light L1 generated in the active layer 13 and proceeding toward the second semiconductor layer 15 proceeds through the insulating layer 19 without being absorbed by the second electrode 22, enters the reflective electrode 26, and is then reflected by the surface of the reflective electrode 26 and guided toward the InP substrate 3. This increases the light extraction efficiency of the infrared light L1 in the infrared LED element 1. The reflective electrode 26 does not contact the second semiconductor layer 15, and therefore does not need to be made of a material capable of realizing ohmic contact with the second semiconductor layer 15. Therefore, the material of the reflective electrode 26 can be selected from metal materials having a higher reflectance than the second electrode 22, such as Al, Au, and Al / Au.

[0089] The reflective electrode 26 may be formed integrally with a second pad electrode 27, which will be described later.

[0090] (First pad electrode 25, second pad electrode 27) 1 to 2B, the infrared LED element 1 includes a first pad electrode 25 formed on the first electrode 21, and a second pad electrode 27 formed on the second electrode 22. In the example of Fig. 1 and Fig. 2A, the second pad electrode 27 is formed on the reflective electrode 26, but if the second pad electrode 27 has a high reflectance for infrared light L1, the second pad electrode 27 may also function as the reflective electrode 26.

[0091] The first pad electrode 25 and the second pad electrode 27 are made of, for example, Ti / Au, Ti / Pt / Au, etc. The thickness of the first pad electrode 25 and the second pad electrode 27 is not particularly limited, but is, for example, 500 nm or more and 5,000 nm or less, and preferably 1,000 nm or more and 4,000 nm or less.

[0092] (Height adjustment electrode 29) As shown in Figs. 1 to 2B, the infrared LED element 1 includes a height-adjusting electrode 29 formed on the upper layer of the first pad electrode 25. The height-adjusting electrode 29 is provided for flip-chip mounting the infrared LED element 1 as shown in Fig. 1. As shown in Figs. 1 and 2A, the first pad electrode 25 is formed closer to the InP substrate 3 than the second pad electrode 27, so that a difference in height occurs between the first pad electrode 25 and the second pad electrode 27. When flip-chip mounting the infrared LED element 1, as shown in Fig. 1, it is necessary to secure an electrical connection between the pattern electrode 37a formed on the submount 35 and the first pad electrode 25 while forming an electrical connection between the pattern electrode 37b formed on the submount 35 and the second pad electrode 27.

[0093] From this viewpoint, the height adjustment electrode 29 is formed for the purpose of compensating for the difference in height between the first pad electrode 25 and the second pad electrode 27. The material of the height adjustment electrode 29 is not limited, but for example, Au plating, Ni plating, Cu plating, etc. can be used, and a combination of a plurality of these materials may be used. However, from the viewpoint of oxidation resistance, it is preferable that at least a region having a thickness of several tens to several hundreds of nm near the surface of the height adjustment electrode 29 is formed of Au plating.

[0094] [Manufacturing method] An example of a method for manufacturing the above-mentioned infrared LED element 1 will be described with reference to Figures 3A to 3I. Figures 3A to 3H are all cross-sectional views of a single step in the manufacturing process.

[0095] (Step S1) An InP substrate 3 is prepared. As described above, the InP substrate 3 may be a substrate doped with a transition metal that forms a deep level, such as Fe, or an undoped substrate may be used. For example, the InP substrate 3 is a 2-inch substrate, 370 μm thick, doped with Fe, and has a 1×10 7 Substrates with resistivity of Ω·cm or higher can be used.

[0096] (Step S2) The InP substrate 3 is transferred into an MOCVD (Metal Organic Chemical Vapor Deposition) device, and as shown in Fig. 3A, a first semiconductor layer 11, an active layer 13, and a second semiconductor layer 15 are epitaxially grown in sequence on the InP substrate 3 to form a semiconductor layer 10. In this step S2, the type and flow rate of the source gas, the processing time, the environmental temperature, and the like are appropriately adjusted according to the material and film thickness of the layer to be grown. Examples of materials for each semiconductor layer 10 are as described above.

[0097] (Step S3) The epitaxial wafer is removed from the MOCVD apparatus, and as shown in Fig. 3B, the second semiconductor layer 15 and the active layer 13 in a partial region are removed by etching to expose the first semiconductor layer 11. In detail, this can be performed, for example, by the following procedure.

[0098] First, a mask layer (here, a SiO2 layer) is formed to a predetermined thickness by plasma CVD on the upper surface of the second semiconductor layer 15, which is the outermost surface of the semiconductor layer 10, and then a resist opening is formed by photolithography. Next, the mask layer in the resist opening is etched away using buffered hydrofluoric acid, and then the resist is removed. The semiconductor layer 10 is etched by dry etching using Cl2 gas using the mask layer as a mask, thereby removing the second semiconductor layer 15, the active layer 13, and a part of the first semiconductor layer 11 in a certain region. Then, the remaining mask layer is removed using buffered hydrofluoric acid.

[0099] (Step S4) As shown in FIG. 3C, an insulating layer 19 is formed on the entire surface of the semiconductor layer 10 by using a plasma CVD method.

[0100] (Step S5) 3D, the second electrode 22 is formed in a partial region of the second semiconductor layer 15. In detail, for example, the following procedure can be used.

[0101] First, a resist opening is formed in a portion of the insulating layer 19 by photolithography, and then the insulating layer 19 in the resist opening is removed by using buffered hydrofluoric acid. Next, a material film for the second electrode 22 is formed by using an electron beam (EB) deposition device, and then the resist is removed, and the material film formed in the portion outside the region where the second electrode 22 is to be formed is lifted off.

[0102] Thereafter, an alloying process (annealing process) is performed by heating at 450° C. for 10 minutes, for example, to realize ohmic contact between the second semiconductor layer 15 and the second electrode 22.

[0103] (Step S6) 3E, a reflective electrode 26 is formed on the second electrode 22, and a second pad electrode 27 is further formed on the reflective electrode 26. In detail, for example, the following procedure can be used.

[0104] After forming a resist opening in the upper layer of the second electrode 22 by photolithography, a material film of the reflective electrode 26 and a material film of the second pad electrode 27 are formed by using an EB deposition apparatus. The reflective electrode 26 and the second pad electrode 27 may be formed continuously. For example, a laminate of Al / Au / Ti / Pt / Au is formed to continuously form the laminate structure of the reflective electrode 26 and the second pad electrode 27.

[0105] (Step S7) 3F, a first electrode 21 is formed on the first semiconductor layer 11 in a portion of the region where the active layer 13 is not formed. In detail, this can be performed, for example, by the following procedure.

[0106] First, a resist opening is formed in a portion of the insulating layer 19 by photolithography, and then the insulating layer 19 in the resist opening is removed by using buffered hydrofluoric acid. Next, a material film for the first electrode 21 is formed by using an electron beam (EB) deposition device, and then the resist is removed, and the material film formed in the portion outside the region where the first electrode 21 is to be formed is lifted off.

[0107] Thereafter, an alloying process (annealing process) is performed by heating at 350° C. for 10 minutes, for example, to realize ohmic contact between the first semiconductor layer 11 and the first electrode 21.

[0108] (Step S8) 3G, a first pad electrode 25 is formed on the first electrode 21, and a height adjustment electrode 29 is further formed on the first pad electrode 25. In detail, for example, the following procedure can be used.

[0109] After a resist opening is formed in the upper layer of the first electrode 21 by using a photolithography method, an EB deposition apparatus is used to deposit a material film of the first pad electrode 25. For example, a Ti / Pt / Au film is deposited as the first pad electrode 25.

[0110] Next, a resist opening is formed on the upper layer of the first electrode 21 by photolithography, and then a height adjustment electrode 29 made of Au plating is grown on the upper layer of the first pad electrode 25 in the resist opening by electroless Au plating. This adjusts the height adjustment electrode 29 and the second pad electrode 27 to be substantially the same height. The height adjustment electrode 29 may also be grown by electrolytic plating or EB deposition.

[0111] (Step S9) 3H, the main surface of the InP substrate 3 opposite to the side on which the semiconductor layer 10 is formed is thinned. In detail, this can be performed, for example, by the following procedure.

[0112] With the surface of the InP substrate 3 on the epitaxial layer side attached to a support member with wax, the InP substrate 3 is ground to a desired thickness by a surface grinder using a grindstone. After grinding, powdery debris generated by grinding is removed with an alkaline cleaning solution, and then the InP substrate 3 is removed from the support member and the wax is washed away. The thickness of the InP substrate 3 after grinding can be adjusted between 50 μm and 350 μm, and is selected depending on the application and subsequent processes. In this embodiment, the thickness of the InP substrate 3 after grinding is set to 300 μm. The Ra1 of the ground surface that becomes the light emitting surface can be changed by selecting the grit of the grindstone.

[0113] By this step S9, the uneven portion 6a is formed on the main surface of the InP substrate 3 opposite to the side on which the semiconductor layer 10 is formed, that is, on the light emitting surface 3a.

[0114] (Step S10) Next, as shown in Fig. 2A, an intermediate refractive index film 31 is formed by using a plasma CVD method on the light emission surface 3a of the InP substrate 3 on which the uneven portion 6a is formed. Note that, in Fig. 2A, the intermediate refractive index film 31 is illustrated as having unevenness on its surface so as to follow the shape of the uneven portion 6a provided on the light emission surface 3a of the InP substrate 3, but the surface of the intermediate refractive index film 31 may be configured as a flatter surface than the InP substrate 3.

[0115] (Step S11) Next, the InP substrate 3 attached to the dicing tape is diced by blade dicing to be formed into chips.

[0116] Fig. 3I is an image obtained by photographing the side surface 3b of the InP substrate 3 immediately after dicing. When dicing by this blade dicing, as shown in Fig. 3I, an uneven portion 6b is formed on the side surface 3b of the InP substrate 3. In the process of dicing the InP substrate 3, the surface roughness Ra2 of the side surface 3b is adjusted by adjusting the roughness (grit) of the abrasive grains used in the blade, the rotation speed, and the feed speed of the InP substrate 3.

[0117] The surface roughness Ra1 of the uneven portion 6a on the light emission surface 3a of the InP substrate 3 is adjusted by the grit size and rotation speed of the grindstone used during grinding, and the feed speed of the InP substrate 3. If necessary, the surface roughness Ra1 may be adjusted by immersing the wafer in an etching solution after grinding. The surface roughness Ra2 of the uneven portion 6b on the side surface 3b is adjusted by changing the grit size of the blade, the rotation speed and feed speed of the blade during cutting, and further by immersing the chip in an etching solution after dicing. The surface roughness Ra1 is preferably 3 μm or less, and more preferably 1 μm or less, while satisfying the above formula (1). The surface roughness Ra2 is preferably 0.03 μm or more, and more preferably 0.05 μm or more, while satisfying the above formula (2).

[0118] Here, we will check the actual shape of the side surface 3b of the InP substrate 3 that has not been subjected to any processing after dicing. As shown in Fig. 3I, the side surface 3b of the InP substrate 3 immediately after dicing is not a flat surface, and streaky irregularities are inevitably formed by the blade.

[0119] If the unevenness formed in such a dicing process causes the surface roughness Ra2 of the side surface 3b to fall within a range that does not satisfy the condition of the above formula (2), the side surface 3b of the InP substrate 3 may be subjected to processing such as polishing or etching in order to reduce the surface roughness Ra2.

[0120] (Step S12) After step S11 is performed, the infrared LED element formed as a chip is mounted on the submount 35 as shown in Fig. 1. More specifically, a submount 35 having a pattern electrode 37a and a pattern electrode 37b formed on the upper surface is prepared, and the pattern electrode 37a and the height adjustment electrode 29, and the pattern electrode 37b and the second pad electrode 27 are ultrasonically bonded, respectively. In this way, a flip-chip mounted infrared LED element 1 is manufactured.

[0121] [verification] Infrared LED elements 1 were manufactured by varying the surface roughness Ra1 of the light emitting surface 3a of the InP substrate 3 and the surface roughness Ra2 of the side surface 3b, but otherwise by the same method as in steps S1 to S12 above, and the light distribution of the emitted infrared light was measured.

[0122] Nine samples were prepared with different surface roughnesses Ra1 and Ra2, and it was confirmed whether the light distribution at the peak wavelength λp emitted from each sample substantially exhibited a Lambertian distribution.

[0123] The samples used were an infrared LED element in which the peak wavelength λp of the emitted infrared light L1 was 1300 nm, and an infrared LED element in which the peak wavelength λp of the emitted infrared light L1 was 1,650 nm.

[0124] (Measurement method) Fig. 4 is a schematic cross-sectional view for explaining the structure of the stem 40 used in the verification. Each sample of the infrared LED element was mounted on the stem 40 as shown in Fig. 4, and emitted light by supplying current from a power source (not shown).

[0125] The specific structure of the stem 40 shown in Fig. 4 will be described. A pair of power supply pins (43a, 43b) electrically insulated from each other by an insulating member 42 is inserted into the stem 40. The submount 35 of the infrared LED element 1 is fixed to the upper surface of the stem 40 by silver paste 41. The power supply pin 43a and the pattern electrode 37a are connected by a bonding wire 44a, and the power supply pin 43b and the pattern electrode 37b are connected by a bonding wire 44b.

[0126] 5 is a schematic diagram showing a method for measuring the light distribution of infrared light emitted from a test sample. As shown in FIG. 5, the light distribution of the light of wavelength λp emitted from the test sample is in the range of −90°≦θ around the center of the light emission surface 3a. iThe data was obtained based on the current value measured by the ammeter 51 connected to the photodiode 50 when the photodiode 50 was moved in the range of ≦90°. The radiation intensity data was obtained at intervals of 0.36° within the range of -90° to 90°, and the total number of data N in one sample was 501.

[0127] (Evaluation method) From the light distribution of each sample obtained by the above measurement method, the residual sum of squares E is derived based on the above formula (3).Then, for samples whose value of the residual sum of squares E is 0.05 or less, the light distribution of infrared light with wavelength λp has a sufficiently small error from the actual Lambertian distribution, and the sample is evaluated as being substantially a Lambertian distribution.Just to be sure, the above formula (3) is presented again.

[0128]

number

[0129] Here, I(θ i ) is the radiation intensity distribution obtained for each sample, and α is a normalization coefficient. The normalization coefficient α is a coefficient obtained by performing a numerical analysis to minimize E with α as a variable. As a minimization method, any numerical analysis method such as the steepest descent method can be used.

[0130] (result) Figures 6A and 6B are graphs showing an example of the radiation intensity distribution of a verification sample with a wavelength λp of 1,300 nm. The graph shown in Figure 6A is the radiation intensity distribution of a sample with a residual sum of squares E of 0.096 (>0.05), and the graph shown in Figure 6B is the radiation intensity distribution of a sample with a residual sum of squares E of 0.019 (≦0.05). Note that the radiation intensities in the graphs shown in Figures 6A and 6B are relative radiation intensities normalized with the maximum value set to 1.

[0131] In the sample from which the relative intensity distribution in FIG. 6A was obtained, the surface roughness Ra1 on the light emitting surface 3a was 0.02 μm, and the surface roughness Ra2 on the side surface 3b was 0.34 μm.

[0132] In the sample from which the relative intensity distribution in FIG. 6B was obtained, the surface roughness Ra1 on the light emitting surface 3a was 0.71 μm, and the surface roughness Ra2 on the side surface 3b was 0.08 μm.

[0133] Fig. 7 is a graph showing an example of the correlation between the surface roughness Ra1 of the light exit surface 3a and the surface roughness Ra2 of the side surface 3b, and the residual sum of squares E, for a verification sample having a peak wavelength λp of 1,300 nm. As shown in Fig. 7, plots shown with "◯" indicate samples whose residual sum of squares E is smaller than 0.05, and plots shown with "×" indicate samples whose residual sum of squares E is larger than 0.05.

[0134] As can be seen from the results shown in FIG. 7, in the samples belonging to region C1 where the surface roughness Ra1 is large and the surface roughness Ra2 is small, the residual sum of squares E is smaller than 0.05, which confirms that the emitted infrared light substantially has a Lambertian distribution.

[0135] 8 is a graph showing an example of the correlation between the surface roughness Ra1 of the light exit surface 3a and the surface roughness Ra2 of the side surface 3b of the verification sample emitting infrared light with a peak wavelength λp of 1,650 nm, and the residual sum of squares E. As shown in FIG 8, it is confirmed that the verification sample emitting infrared light with a peak wavelength λp of 1,650 nm also provides results similar to those of the verification sample emitting infrared light with a peak wavelength λp of 1,300 nm.

[0136] As described above, the refractive index of InP for infrared light with a wavelength of 1,000 nm or more and 2,000 nm or less is about 3.1 to 3.3, and the refractive index of InP for infrared light with a wavelength of 1,300 nm is 3.19. Therefore, λp / n(λp) in the above formula (1) is 0.41 μm, and λp / (2×n(λp)) in the above formula (2) is 0.20 μm.

[0137] That is, the area that satisfies both the above formula (1) and the above formula (2) corresponds to the area C1 (area where Ra1>0.41 μm and Ra2<0.20 μm) surrounded by the dashed line in the graph shown in Fig. 7. As shown in Fig. 7, it is confirmed that the samples belonging to the area C1 have a residual sum of squares E value smaller than 0.05.

[0138] 7 and 8, region C1 is a region that is defined to ensure a margin around the outer edge of the region in which the plots of samples with a residual sum of squares E value of 0.05 or less are dispersed. In other words, an infrared LED element 1 manufactured to belong to region C1 will emit light that is essentially a Lambertian distribution.

[0139] From the above, in an infrared LED element in which the uneven portions (6a, 6b) are formed so as to satisfy the above formulas (1) and (2), the light distribution of the emitted infrared light L1 substantially exhibits a Lambertian distribution. In other words, a configuration that satisfies the above formulas (1) and (2) brings the light distribution of the infrared light emitted from the infrared LED element 1 closer to a Lambertian distribution, which leads to an improvement in the light distribution of the infrared light emitted from the infrared LED element 1.

[0140] Furthermore, by providing the infrared LED element 1 with the intermediate refractive index film 31 that exhibits a refractive index between air and InP, the amount of change in refractive index of the infrared light L1 as it travels from the InP substrate 3 to the air is mitigated. This further reduces the proportion of the infrared light L1 that is totally reflected at the surface of the InP substrate 3, and the light extraction efficiency is further improved. In particular, the refractive index of InP for infrared light L1 with a wavelength of 1,000 nm or more and 2,000 nm or less is about 3.1 to 3.3, which is significantly different from the refractive index of air (=1), so that the light extraction efficiency can be significantly improved by providing the intermediate refractive index film 31 on the upper layer of the InP substrate 3.

[0141] [Another embodiment] Another embodiment will be described below.

[0142] <1> In the above embodiment, the case where the infrared LED element 1 is flip-chip mounted has been described with reference to Fig. 1. However, although not shown, using the respective symbols of the above embodiment shown in Fig. 1, the scope of the present invention also includes an infrared LED element 1 in which an InP substrate 3 is placed on a mounting surface, a semiconductor layer 10 such as an active layer 13 is formed on the InP substrate 3, and a bonding wire is connected to each of a first pad electrode 25 and a second pad electrode 27 formed thereon to conduct electricity to the semiconductor layer 10 (so-called face-up mounting). In this case, the infrared LED element 1 does not necessarily need to include a height adjustment electrode 29 or a reflective electrode 26.

[0143] However, in the case of face-up mounting, the electrodes (21, 22) side becomes the light emitting surface, so the electrodes (21, 22) and bonding wires reduce the light extraction area compared to flip-chip mounting, and the thickness of the infrared LED element 1 itself increases. For this reason, from the viewpoint of achieving a higher light extraction efficiency and a low-profile element, an infrared LED element 1 intended for flip-chip mounting, as shown in Fig. 1, is preferable.

[0144] <2> Fig. 9 is a cross-sectional view showing a schematic structure of an infrared LED element 1 according to another embodiment. As shown in Fig. 9, the electrodes (23, 24) of the infrared LED element 1 may be arranged at positions spaced apart in a direction perpendicular to the light emission surface 3a of the InP substrate 3. The infrared LED element 1 shown in Fig. 9 includes a passivation film 28 that covers the side surface of the semiconductor layer 10. The passivation film 28 is made of an insulator such as SiO2.

[0145] In this embodiment, the second electrode 24 is wire-bonded, and therefore a second pad electrode 27 is formed on the surface of the second electrode 24.

[0146] Furthermore, as shown in FIG. 9, the infrared LED element 1 of this embodiment is formed with a reflective layer 33 that reflects light that is generated in the active layer 13 and travels toward the opposite side to the light emitting surface 3a, so that the light travels toward the light emitting surface 3a.

[0147] In the infrared LED element 1 of this embodiment, the InP substrate 3 and the first semiconductor layer 11 are doped with n-type impurities, and the second semiconductor layers (14, 15) are doped with p-type impurities so that a current flows between the electrodes (23, 24) via the InP substrate 3.

[0148] In this embodiment, the dopant concentration of the InP substrate 3 is 1×10 18 / cm 3 By adjusting the dopant concentration of the InP substrate 3 in this manner, the amount of light absorbed in the InP substrate 3 is suppressed, and the light extraction efficiency of the infrared LED element 1 is improved. Note that the present invention does not exclude configurations in which the dopant concentration of the InP substrate 3 is outside the above range.

[0149] The second semiconductor layer 15 constitutes a p-type cladding layer in the infrared LED element 1, and the second semiconductor layer 14 constitutes a p-type contact layer in the infrared LED element 1. The second semiconductor layer 14 is a highly doped layer to ensure electrical connection with the first electrode 23. However, if sufficient electrical connection is ensured, the second semiconductor layer 14 may be omitted and the first electrode 23 may be directly in contact with the second semiconductor layer 15 that constitutes the p-type cladding layer.

[0150] Furthermore, in this embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type. That is, in the infrared LED element 1 shown in Fig. 1, the InP substrate 3 may be InP doped with a p-type dopant, the first semiconductor layer 11 may be a p-type semiconductor layer, and the second semiconductor layer (14, 15) may be an n-type semiconductor layer. In this case, the infrared LED element 1 may not include the second semiconductor layer 14 as an n-type contact layer.

[0151] In the infrared LED element 1 of this embodiment, the surface roughness Ra1 of the light emitting surface 3a of the InP substrate 3 also satisfies the condition of formula (1) above, and the surface roughness Ra2 of the side surface 3b satisfies the condition of formula (2) above.

[0152] However, in this configuration, the surface on which one electrode is provided becomes the light emitting surface 3a, and the electrodes and bonding wires reduce the light extraction area compared to the configuration of the above embodiment, and the thickness of the infrared LED element 1 itself becomes thicker. For this reason, from the viewpoint of realizing a low-profile element that exhibits higher light extraction efficiency, an infrared LED element 1 that is intended for flip-chip mounting, as shown in Figure 1, is preferable.

[0153] <3> In the above embodiment, the infrared LED element 1 has been described as having the intermediate refractive index film 31 on the light emission surface 3a of the InP substrate 3, but in the present invention, it is optional whether or not the infrared LED element 1 has the intermediate refractive index film 31. However, from the viewpoint of further increasing the light extraction efficiency, it is preferable for the infrared LED element 1 to have the intermediate refractive index film 31.

[0154] Furthermore, in the above embodiment, the second electrode 22 is described as constituting a partial electrode, but in the present invention, it is optional whether the second electrode 22 is a partial electrode or not. However, from the viewpoint of further increasing the light extraction efficiency, it is preferable that the second electrode 22 is a partial electrode and the infrared LED element 1 is provided with a reflective electrode 26 on the second electrode 22.

[0155] <4> In the above embodiment, the first semiconductor layer 11 is n-type and the second semiconductor layer 15 is p-type. However, these conductivity types may be reversed.

[0156] <5> Among the steps constituting the above-mentioned manufacturing method, the order of some steps may be reversed. For example, the order of step S6 of forming the second electrode 22 and step S7 of forming the first electrode 21 may be reversed. Also, for example, step S9 of thinning the InP substrate 3 may be performed before the step of forming the electrodes (21, 22).

[0157] <6> The configuration of the infrared LED element 1 and the manufacturing method of the infrared LED element 1 described above are merely examples, and the present invention is not limited to the illustrated configurations and the above-described method. [Explanation of symbols]

[0158] 1: Infrared LED element 3: InP substrate 3a: Light exit surface 3b: Side 6a: Uneven part 6b: Uneven part 10: Semiconductor layer 11: First semiconductor layer 13: Active layer 14: Second semiconductor layer 15: Second semiconductor layer 19: Insulating layer 21 : First electrode 22: Second electrode 23: First electrode 24: Second electrode 25: First pad electrode 26 : Reflective electrode 27: Second pad electrode 28: Passivation layer 29: Height adjustment electrode 30: Dielectric layer 31: Intermediate refractive index film 33 : Reflective layer 35: Submount 37a: Pattern electrode 37b: Pattern electrode 40: Stem 41: Silver paste 42: Insulating material 43a: Power pin 43b: Power pin 44a: Bonding wire 44b: Bonding wire 50: Photodiode 51 : Ammeter

Claims

1. An infrared LED element that emits infrared light having a peak wavelength in the range of 1,000 nm or more and 2,000 nm or less, An InP substrate having a thickness of 30 μm or more and a light emitting surface as one principal surface; a laminate disposed on a main surface side of the InP substrate different from the light emission surface, The laminate comprises: a first semiconductor layer of a first conductivity type, which is p-type or n-type; an active layer formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type different from the first conductivity type formed on the active layer; an infrared LED element characterized in that, when the peak wavelength is λp, the surface roughness of the light exit surface of the InP substrate is Ra1, the surface roughness of the side surface of the InP substrate is Ra2, and the refractive index of the InP substrate corresponding to the peak wavelength λp is n(λp), the following formula (1) and formula (2) are satisfied: Ra1 ≧ λp / n(λp) (1) Ra2 ≦ λp / (2×n(λp)) (2)

2. 2. The infrared LED element according to claim 1, wherein the light distribution of the emitted infrared light is substantially a Lambertian distribution.

3. 2. The infrared LED element according to claim 1, wherein the surface roughness Ra1 is 3 μm or less.

4. 2. The infrared LED element according to claim 1, wherein the surface roughness Ra2 is 0.03 μm or more.

5. 2. An infrared LED element according to claim 1, further comprising: a first electrode formed on the first semiconductor layer in a region where the active layer is not formed; and a second electrode formed on the second semiconductor layer at a position spaced apart from the first electrode in a direction parallel to the light-emitting surface of the InP substrate.

6. the first semiconductor layer is formed on the InP substrate; The concentration of the first conductive type dopant in the InP substrate is 1×10 18 / cm 3 2. The infrared LED element according to claim 1, wherein the infrared LED element has a capacitance of 100 nm or less.

7. 2. The infrared LED element according to claim 1, wherein the InP substrate is doped with a transition metal capable of forming a deep level.

8. 2. The infrared LED element according to claim 1, wherein the InP substrate has an intermediate refractive index film on the light exit surface, the intermediate refractive index film having a refractive index lower than that of the InP substrate and higher than that of air, and the side surfaces are not provided with the intermediate refractive index film.

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