Stacking single-photon avalanche diodes and high voltage devices

Abstract

To achieve active pixel quenching and minimize package size while ensuring connection reliability of an array of single-photon avalanche diodes (SPADs) and high voltage switches formed on separate chips or packages.SOLUTION: In SPAD circuitry 100, a second die 104 may have a front side facing a third die 106, and a back side facing a first die 102. The third die has a plurality of SPADs. The second die includes a plurality of switches coupled to cathode terminals 154 of the plurality of SPADs in the third die. The first die includes digital readout logic coupled to the plurality of switches in the second die. The plurality of switches in the second die can be powered using a high voltage and referred to as analog high voltage switches. The digital readout logic in the first die is powered using a voltage that is lower than the high voltage being used to power the second die.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] This application relates generally to imaging systems, and more particularly to imaging systems having single-photon avalanche diodes (SPADs). [Background technology]

[0002] A SPAD is a type of PN junction diode biased above its breakdown voltage with a high voltage. In this state, the SPAD can be sensitive to a single impinging photon. The SPAD can be coupled to an associated high voltage switch and a digital readout circuit. The high voltage switch can include pull-up and pull-down transistors. The digital readout circuit can include a comparator, a level shifter, and a pulse generator.

[0003] Conventionally, the array of SPADs and high voltage switches are formed on separate chips or packages. In such configurations, it can be difficult to achieve active pixel quenching and minimize package size while ensuring connection reliability. It is within this context that the embodiments described herein arise. [Brief description of the drawings]

[0004] [Figure 1] 1 is a functional block diagram of an exemplary SPAD-based imaging sensor in accordance with some embodiments. [Diagram 2] 2 is a diagram of an example vehicle having an imaging system of the type shown in FIG. 1, in accordance with some embodiments. [Diagram 3] 1 is a schematic diagram of an exemplary SPAD pixel, according to some embodiments. [Figure 4] FIG. 2 is a cross-sectional side view of a sensor die, an analog high voltage die, and a digital readout logic die stacked vertically relative to one another in accordance with some embodiments. [Diagram 5]1 is a cross-sectional side view of an exemplary n-type high voltage transistor according to some embodiments. [Figure 6] 1 is a cross-sectional side view of an exemplary p-type high voltage transistor according to some embodiments. [Figure 7A] 1A-1C are cross-sectional side views illustrating front side processing of a digital readout logic wafer and an analog high voltage wafer according to some embodiments. [Figure 7B] FIG. 1 is a cross-sectional side view illustrating wafer bonding between a digital readout logic wafer and an analog high voltage wafer according to some embodiments. [Figure 7C] FIG. 13 is a cross-sectional side view illustrating removal of a handling wafer on the backside of an analog high voltage wafer according to some embodiments. [Figure 7D] 1A-1C are cross-sectional side views illustrating additional backside processing for an analog high voltage wafer according to some embodiments. [Figure 7E] 1A-1D are cross-sectional side views illustrating front side processing of a sensor wafer according to some embodiments. [Figure 7F] FIG. 13 is a cross-sectional side view illustrating wafer bonding between a sensor wafer and a processed backside of an analog high voltage wafer according to some embodiments. [Figure 7G] 1A-1D are cross-sectional side views illustrating backside processing of a sensor wafer according to some embodiments. [Figure 8] 8 is a flow chart of illustrative steps for manufacturing circuits of the type shown in FIGS. 4-7, according to some embodiments. [Figure 9] 1 is a cross-sectional side view of a sensor die, an analog high voltage die without n-type transistors, and a digital readout logic die stacked vertically relative to one another in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The imaging system or device may include a single photon avalanche diode (SPAD) forming a SPAD-based imaging system or device (sometimes referred to herein simply as a SPAD device), which may also be referred to as a silicon photomultiplier (SiPM).

[0006] Some imaging systems include image sensors that detect light by converting impinging photons into electrons or holes that are integrated (collected) at pixel photodiodes in a sensor array. After the integration cycle is complete, the collected charge is converted into a voltage that is supplied to the output terminals of the sensor. In complementary metal-oxide semiconductor (CMOS) image sensors, the charge-to-voltage conversion is accomplished directly in the pixel itself, and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage can also be later converted to a digital equivalent on-chip and processed in various ways in the digital domain.

[0007] On the other hand, SPAD devices use a different photon detection mechanism. In some exemplary configurations, as sometimes described herein as an example, the SPAD device may form a light detection and ranging (LIDAR) device or imaging system. The LIDAR device may include a light source that emits light toward a target object or scene. When a light-sensing diode (SPAD) in the LIDAR device can be biased above its breakdown point and an incident photon from the light source (e.g., light reflected from the target object / scene) generates an electron-hole pair, these carriers initiate an avalanche breakdown and additional carriers are generated. Since avalanche multiplication is a self-sustaining process, a current signal can be generated and can be easily detected by a readout circuit associated with the SPAD. The avalanche breakdown process needs to be stopped (quenched) in order to detect new photons by lowering the voltage bias across the diode below its breakdown point. In a LIDAR device, SPAD pixels may be used to measure the time-of-flight (ToF) of photons from a synchronized light source to a scene object point and back to a sensor, which can be used (as one example) to obtain a three-dimensional image of the scene.

[0008] Figure 1 is a functional block diagram of an example imaging system, such as imaging system 10. Imaging system 10 of Figure 1 may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), a surveillance system, a medical imaging system, a general machine vision system, or any other desired type of system.

[0009] The imaging system 10 may include or implement a LIDAR-based device (sometimes referred to as a LIDAR module) with a SPAD device. The LIDAR module may use the SPAD device to capture images of a scene and measure distances to obstacles (sometimes referred to as targets) in the scene. As an example, in a vehicle safety system, information from the LIDAR module may be used by the vehicle safety system to determine environmental conditions surrounding the vehicle. As an example, the vehicle safety system may include systems such as parking assistance systems, automatic or semi-automatic cruise control systems, automatic braking systems, collision avoidance systems, lane keeping systems (sometimes referred to as lane drift avoidance systems), pedestrian detection systems, and the like. In at least some instances, the LIDAR module may form part of a semi-automatic or autonomous vehicle.

[0010] An illustrative example of a vehicle, such as an automobile 8, is shown in FIG. 2. As shown in the illustrative example of FIG. 2, the automobile 8 may include one or more SPAD-based imaging systems 10. The imaging systems may be vehicle safety systems as discussed above. In the illustrative example of FIG. 2, a first imaging system 10 is shown mounted at the front of the vehicle 8 (e.g., to capture images of the surroundings ahead of the vehicle) and a second imaging system 10 is shown mounted inside the vehicle 8 (e.g., to capture images of the driver of the vehicle). If desired, the imaging system 10 may be mounted at the rear end of the vehicle 8 (i.e., the end of the vehicle opposite where the first imaging system 10 of FIG. 2 is mounted). The imaging system at the rear end of the vehicle may capture images of the surroundings behind the vehicle. These examples are merely illustrative. One or more imaging systems 10 may be mounted at any desired location or within the vehicle 8.

[0011] Referring back to FIG. 1 , imaging system 10 may include one or more SPAD-based (semiconductor) devices 12. One or more lenses 14 may cover each SPAD-based device 12. In operation, lenses 14 (sometimes referred to as optical elements) may focus light onto a corresponding SPAD-based semiconductor device 12. SPAD-based devices 12 may each include (an array of) SPAD pixels that convert light into digital data or analog signals in the case of SiPMs. SPAD-based devices 12 may have any number of SPAD pixels (e.g., hundreds, thousands, millions, or more). In some SPAD-based devices, each SPAD pixel may be covered by a respective color filter element and / or microlens.

[0012] The SPAD-based device 12 may include control circuitry. The control circuitry for the SPAD-based device 12 may be formed either on-chip (e.g., on the same semiconductor substrate as the SPAD-based device 12) or off-chip (e.g., on a different semiconductor substrate than the SPAD-based device 12). The control circuitry may control the operation of the SPAD-based device 12. For example, the control circuitry may operate active quenching circuits or other adjustable (transistor) circuits within each SPAD pixel, may control one or more bias voltages provided to each SPAD pixel, and may control / monitor readout circuitry associated with each SPAD pixel.

[0013] The SPAD-based semiconductor device 12 may optionally include additional circuitry, such as logic gates, digital counters, time-to-digital converters, biasing circuits (e.g., source follower load circuits), sample and hold circuits, amplifier circuits, analog-to-digital (ADC) circuits, data output circuits, memory (e.g., buffer circuits), address circuits, etc. Any of the foregoing circuits may form part of a control circuit or, when provided on a pixel basis, may form part of a SPAD pixel.

[0014] If desired, the 3D image data output from the SPAD-based device 12 may be provided to downstream image processing circuitry. The image processing circuitry may process the data collected by the SPAD pixels and use the time-of-flight data to determine (as another example) a depth map of the scene. Complete 3D image data of a particular scene may be obtained by combining the depth map of the scene with an intensity map. An intensity map may refer to a spatial representation of photon intensities or photon counts obtained from detected photons and may provide information regarding the spatial distribution of photon intensities / counts over a two-dimensional region or even a three-dimensional volume in a particular application. In some cases, some or all of the control circuitry of the SPAD device 12 may be formed integrally (e.g., on the same die or package) with the image processing circuitry.

[0015] The imaging system 10 may provide a number of high-level functions to a user. For example, the imaging system 10 may provide a user with the ability to run user applications on the system 10. To implement these functions, the imaging system 10 may include input / output devices 16, such as a keypad, buttons, input / output ports, a joystick, and a display. Other functional modules and / or additional storage and processing circuitry (e.g., other components 20) may also be included in the imaging system 10 as desired. Such other modules or circuitry may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard drives, solid state drives, etc.), microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, and / or other processing circuitry for other (non-imaging) functional modules, etc.

[0016] The input / output device 16 may include an output device that works in combination with the SPAD-based device 12. For example, one or more light emitting components 18 may be included in the imaging system 10 to emit light (e.g., infrared light or any other desired type of light). The light emitting components 18 may be lasers, light emitting diodes, or any other desired type of light emitting components. The SPAD-based device 12 may measure the reflection of light from an object to measure the distance to the object in a LIDAR scheme (e.g., in a scenario where the imaging system 10 implements or includes a LIDAR module). The control circuitry used to control the operation of the SPAD-based device 12 may also be used to, optionally, control the operation of the light emitting components 18 for a coordinated sensing scheme.

[0017] Figure 3 is a schematic diagram of an exemplary SPAD pixel, such as SPAD pixel 30. Such SPAD pixels may be formed in a plurality or array in SPAD device 12, as shown in Figure 1. As shown in Figure 3, SPAD pixel 30 has an anode terminal connected to a voltage supply terminal 32, a cathode terminal 34 connected to a power supply line 38 (e.g., a high voltage V H The anode terminal 32 can be connected to a power supply terminal capable of supplying a voltage V BS In preparation for a detection operation using the SPAD pixel 30, the SPAD 24 may be biased to a voltage (e.g., a voltage across the SPAD 24) higher than the breakdown voltage of the SPAD 24 using the supply voltage terminals 32 and 38. The breakdown voltage may be defined as the reverse bias voltage that can be applied across the SPAD 24 without causing an exponential increase in the reverse forward current in the SPAD 24. Thus, when the SPAD 24 is reverse biased above the breakdown voltage, the absorption of a single photon may trigger a short-lived but relatively large avalanche current through impact ionization, thereby providing a single photon.

[0018] A quenching circuit can be used to reduce the bias voltage of the SPAD 24 below the level of the breakdown voltage. Reducing the bias voltage of the SPAD 24 below the breakdown voltage stops the avalanche process and the corresponding avalanche current. There are many ways to form a quenching circuit. As an example, the quenching circuit can be a passive quenching circuit or an active quenching circuit. A passive quenching circuit can automatically quench the avalanche current when initiated without external control or monitoring. As an example, a resistor (e.g., a passive resistive component) coupled between the cathode terminal of the SPAD and the corresponding voltage supply terminal can act as a passive quenching circuit. On the other hand, an active quenching circuit may require external control or monitoring to apply a voltage to the cathode terminal of the SPAD.

[0019] In the example of FIG. 3, pixel 30 includes an active quenching circuit. The active quenching circuit may reduce the time it takes for SPAD 24 to be quenched and reset (e.g., dead time). This reduction in dead time may allow SPAD 24 to detect incident light at a faster rate than if a passive quenching circuit were used, thereby improving the count rate of the SPAD device. As shown in FIG. 3, the (active) quenching circuit of pixel 30 couples cathode terminal 34 to a ground power line 42 (e.g., ground voltage V -SS 1. When the switch 40 is turned on, it couples a ground voltage V at a terminal 42 to a ground line that can provide a SS may be provided to the cathode terminal 34 of the SPAD 24. A switch 40 configured in this manner is sometimes referred to as a pull-down transistor or a disable transistor.

[0020] To control the state of the switch 40, the quenching circuit of the pixel 30 may also include a control circuit 50 that provides a control signal along path 52 that controls the state of the switch 40. For example, the control circuit 50 may assert or deassert the control signal to switch the switch 40 between an on state and an off state, or may otherwise control the switch 40 in any suitable manner. In the example of FIG. 3, an output signal from a delay circuit 44 coupled along the SPAD readout path (e.g., the signal along path 48) may be used to generate the control signal on path 52. In other words, in this active quenching scheme, the active quenching circuit may modulate the SPAD quench resistance based on the SPAD operation. For example, before a photon is detected, the quench resistance is set high, and then when a photon is detected, the quench resistance is minimized to quench the avalanche and reduce the recovery time. In the example of FIG. 3, the control circuit 50 can control the switch 40 to an open or high resistance state to set the SPAD quench resistance high before a photon is detected, and control the switch 40 to a closed or low resistance state to quench the avalanche once a photon is detected.

[0021] Similarly, delay circuit 44 may provide a control signal on path 46 (e.g., based on the introduced delay) to control switch 36 to an open or closed state at a corresponding time. As an example, at a suitable period after a quenching operation of SPAD 24 (e.g., assertion of a control signal on path 52 to close switch 40), delay circuit 44 may provide an asserted control signal to close switch 36 and reset or recharge SPAD 24 to prepare for detection of a subsequent photon. The period after the quenching and reset / recharge operations of SPAD 24 may have a duration equal to tens or hundreds of nanoseconds (ns), less than 100 ns, less than 10 ns, less than 1 ns, or more than 1 microsecond. Thus, switch 36 may also be referred to as a pull-up transistor or a recharge transistor.

[0022] In the example of FIG. 3, the readout path of pixel 30 may include a delay circuit 44 and a driver circuit 54. The delay circuit 44 and the driver circuit 54 may pass a detection signal from the cathode terminal 34 to a pixel output terminal 56 in response to a detected impinging photon. If desired, specific functional circuits may be coupled along the readout path of pixel 30 between terminal 34 and terminal 56 instead of or in addition to the delay circuit 44 and / or the driver circuit 54. For example, such functional circuits may include, among others, a variable or constant hold-off timer circuit, a variable or constant reset timer circuit, and / or a reset timeout circuit. The detection signal leaving pixel 30 at output terminal 56 may be processed by downstream digital processing circuitry.

[0023] To provide additional functionality to the SPAD pixel 30, the control circuit 50 may receive additional input signals, such as DIS and TST. In particular, the input signal DIS may be a disable signal that, when asserted, enables the control circuit 50 to use (assert) a control signal on path 52 to keep the switch 40 in a closed or actuated state, thereby preventing a SPAD avalanche, thereby actively disabling the pixel 30 from performing a sensing operation. The input signal TST may be a test signal that, when asserted, enables the control circuit 50 to control the switch 40 and / or other pixel elements to respond to test inputs, thereby providing testability for the pixel 30.

[0024] The delay circuit 44, the control circuit 50, the driver 54, and / or any other circuitry associated with reading out the SPAD pixel 30 may be collectively defined herein as "digital readout logic." For example, the other circuitry may include one or more comparators, one or more pulse generators, one or more level shifters, one or more inverters, etc. The digital readout logic operates on a power supply voltage V H As an example, the low power supply voltage for powering the digital read logic may be 1.8V, 1-2V, 2-3V, 3.3V, 3-4V, or V HIt may be equal to another voltage lower than

[0025] On the other hand, high voltage V H The switches 36 and 40, which are powered using a high voltage V H may be equal to 5V, 6V, 7V, 5-7V, 4-6V, 6-8V, 4-8V, over 8V, or other voltages greater than the low voltage that powers the digital readout logic. Meanwhile, the bias voltage V at the anode terminal 32 BS can be set equal to at least 17V, 18V, 19V, 20V, 17-20, greater than 10V, greater than 12V, greater than 14V, greater than 16V, or other suitable level that ensures that the SPAD 24 is biased in the destructive operating regime.

[0026] According to some embodiments, the SPAD pixel circuit can be implemented using a stacked die arrangement, sometimes referred to as a three-dimensional (3D) stack. The stacked die arrangement may include two or more dies having different components and circuits that form a SPAD pixel circuit when stacked vertically on one another. FIG. 4 is a cross-sectional side view of an exemplary SPAD circuit 100 implemented using a first die, such as die 102, a second die, such as die 104, and a third die, such as die 106, stacked vertically on one another. Die 106 may include only a SPAD (e.g., an array of SPADs) and may be referred to and defined herein as a sensor die 106. The sensor die 106 may be configured as a backside illuminated (BSI) sensor die. Die 104 is a high-voltage V HThe die 102 may include analog high voltage (HV) transistors powered using a V H 4. The BSI sensor die 106 may include digital readout logic that is powered using a lower supply voltage of less than 10 V and is therefore sometimes referred to and defined herein as the digital readout logic (low voltage) die or digital die 102. The analog high voltage die 104 may be stacked on the front side of the digital readout logic die 102 as shown in FIG. 4. In other words, the analog high voltage die 104 may be interposed or sandwiched between the BSI sensor die 106 and the digital readout logic (low voltage) die 102.

[0027] 4, the digital readout logic die 102 may include a semiconductor substrate, such as a silicon substrate 110. The digital readout logic, which may include the delay circuit 44 (see FIG. 3), the control circuit 50, the driver 54, and / or any other circuitry associated with reading out each SPAD pixel 30, may be formed in or on the semiconductor substrate 110. The digital readout logic may have one or more gate conductors, such as exemplary gate conductor 114, formed on the semiconductor substrate 110.

[0028] An interconnect stack, such as interconnect stack 112, may be formed on semiconductor substrate 110. Interconnect stack 112 may include alternating routing layers and via layers. If desired, interconnect stack 112 may optionally include only one routing layer and only one via layer. Each routing layer may include a conductive (metal) routing path, such as metal routing structure 116, formed in a layer of dielectric material. Each via layer may include a conductive (metal) via, such as metal via structure 118, formed in a layer of dielectric material. Thus, interconnect stack 112 may also be referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed in a dielectric material such as silicon dioxide). Conductive routing structure 116 and conductive via structure 118 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal routing structures 116 and metal via structures 118 can form an electrical network for interconnecting various components within die 102 and coupling the digital readout logic on die 102 to other off-chip components (e.g., components on die 104, die 106, and / or other external components).

[0029] The analog high voltage die 104 may be stacked on the digital readout logic die 102. The analog high voltage die 104 may include a semiconductor substrate, such as a silicon substrate 120. High voltage devices, such as an n-type transistor N1 and a p-type transistor P1, may be formed in the semiconductor substrate 120. The n-type transistor N1 may represent the high voltage pull-down switch 40 of FIG. 3, and the p-type transistor P1 may represent the high voltage pull-up transistor 36 of FIG. 3. As shown in FIG. 4, each SPAD pixel 30 may include an n-type HV transistor N1 and a p-type HV transistor P1. This is exemplary. As another example, the SPAD pixel 30 may include only one n-type HV transistor without including a p-type transistor. As another example, the SPAD pixel 30 may include only one p-type HV transistor without including an n-type transistor. As another example, the SPAD pixel 30 may include one or more n-type HV transistors. As another example, the SPAD pixel 30 may include one or more p-type HV transistors. As another example, the SPAD pixel 30 can include one or more n-type HV transistors and one or more p-type HV transistors.

[0030] A more detailed view of an n-type high voltage (HV) transistor N1 is shown in FIG. 5. As shown in FIG. 5, the transistor N1 can include an n-type drift region 200, an n+ layer 202 formed on a backside of the n-type drift region 200, and an n++ contact 204 formed in a respective p-body (implant) region 206 on a front side of the n-type drift region 200. The n+ layer 202 may be configured as the drain terminal of the transistor N1, and the n++ contact 204 may be collectively configured as the source terminal of the transistor N1. An N-type transistor N1 having source and drain terminals formed on or near opposite sides or faces of the substrate 120 in this manner may be referred to and defined herein as a "vertical transistor." The terms "source" and "drain" may be used interchangeably when referring to the current conducting terminals of a transistor. Thus, the source and drain terminals may be referred to as "source-drain" terminals (e.g., the source terminal may be referred to as a first source-drain terminal and the drain terminal may be referred to as a second source-drain terminal, or vice versa). Transistor N1 may be formed on one side of a semiconductor substrate 120 and may have a gate conductor 124 connecting the source terminal 204. The side of the substrate 120 on which the gate conductor 124 is formed is typically referred to as the "front side" of the substrate or die.

[0031] A more detailed view of a p-type high voltage (HV) transistor P1 is shown in FIG. 6. As shown in FIG. 6, the transistor P1 can include a p-type substrate region 210, a p+ layer 212 formed on a backside of the p-type substrate region 210, and a p++ contact 214 formed in a respective n-body (implant) region 216 on a front side of the p-type substrate region 210. The p+ layer 212 may be configured as the drain terminal of the transistor P1, and the p++ contact 214 may be collectively configured as the source terminal of the transistor P1. A P-type transistor P1 having source and drain terminals formed on or near opposite sides or faces of the substrate 120 in this manner may be referred to and defined herein as a "vertical transistor." The terms "source" and "drain" may be used interchangeably when referring to the current conducting terminals of a transistor, and thus may be referred to as "source-drain" terminals. The transistor P1 may have a gate conductor 124 formed on the front side of the semiconductor substrate 120 and connecting the source terminal 214.

[0032] Referring again to FIG. 4, an interconnect stack, such as interconnect stack 122, may be formed on a front side (surface) of semiconductor substrate 120. Interconnect stack 122 may include alternating routing layers and via layers. Each routing layer in interconnect stack 122 may include a conductive (metal) routing path, such as metal routing structure 126, formed in a layer of dielectric material. Each via layer in interconnect stack 122 may include a conductive (metal) via, such as metal via structure 128, formed in a layer of dielectric material. Thus, interconnect stack 122 may be referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed in a dielectric material such as silicon dioxide). Conductive routing structure 126 and conductive via structure 128 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal routing structures 126 and metal via structures 128 can interconnect various components within die 104 to each other and form an electrical network for coupling high voltage devices (e.g., transistors N1 and P1) to digital readout logic within die 102.

[0033] The interconnect stack 122 of the die 104 may be bonded to the interconnect stack 112 at a wafer bonding interface 103. The bonding interface 103 may be formed to ensure that the dielectric materials in the interconnect stacks 112 and 122 are properly attached and also to ensure that the conductive routing structures 116 and 126 at the bonding interface 103 are properly connected (bonded). Such bonding at the interface 103 that ensures both a physical bond and an electrical bond may be referred to herein as a hybrid bond.

[0034] The interconnect stack 122 formed on the front side of the semiconductor substrate 120 is exemplary. Additionally, an interconnect stack, such as the interconnect stack 142, may be formed on the back side of the semiconductor substrate 120. The interconnect stack 142 may include alternating routing layers and via layers. Each routing layer in the interconnect stack 142 may include a conductive (metal) routing path, such as the metal routing structure 146, formed in a layer of dielectric material. Each via layer in the interconnect stack 142 may include a conductive (metal) via, such as the metal via structure 148, formed in a layer of dielectric material. Thus, the interconnect stack 142 may be referred to as a dielectric stack (e.g., an interconnect stack having a conductive routing path formed in a dielectric material such as silicon dioxide). The conductive routing structure 146 and the conductive via structure 148 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal routing structures 146 and metal via structures 148 can form an electrical network to interconnect various components within the die 104 and couple high voltage devices (e.g., transistors N1 and P1) to the SPADs within the sensor die 106.

[0035] One or more through silicon via (TSV) structures, such as TSV 130, may be formed in the analog high voltage die 104. In the example of FIG. 4, the TSV structure 130 may extend through the entire depth of the semiconductor substrate 120 (e.g., from the backside of the substrate 120 to at least the frontside of the substrate 120). In some implementations, the TSV structure 130 may extend at least partially into the frontside interconnect stack 122 and may be electrically connected to one of the metal routing structures 126 or a conductive via. If desired, the TSV structure 130 may additionally or alternatively extend at least partially into the backside interconnect stack 142. The TSV structure 130 may be electrically connected to a metal routing structure 146 in the backside interconnect stack 142, either directly or using a conductive via 148 as shown in FIG. 4. The TSV structure 130 may be lined with an insulating layer 132 and filled with a conductive material 134. The insulating layer 132 may be formed from silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials. The fill material 134 may be formed from tungsten, aluminum, copper, copper tungsten, titanium, tantalum, combinations of these materials, or other conductive materials suitable for via structures.

[0036] The sensor die 106 may be stacked on the backside of the analog high voltage die 104. The sensor die 106 may include a semiconductor substrate, such as a silicon substrate 150. An array of SPADs may be formed in the semiconductor substrate 150. Each SPAD pixel 30 may include a respective SPAD (see, e.g., SPAD1 and adjacent SPAD2, etc.). Each SPAD may include an n+ contact 154 formed in a p-type region 155 (e.g., a p-substrate). The n+ contact 154 may function as a cathode terminal at which the SPAD output voltage is generated, and the p-type region 155 may be coupled to a bias voltage V BS In the example of FIG. 4, the first SPAD1 can function as an anode terminal configured to receive a corresponding voltage V SPAD1 , and a second (adjacent) SPAD2 can be configured to output a corresponding voltage VSPAD2 The output voltage of each SPAD may be provided to downstream image processing circuitry, such as digital readout logic on die 102 or other image processing circuitry in imaging system 10 of FIG. 1. The image processing circuitry processes the data collected by the SPAD pixels and can use the time-of-flight data to determine a depth map of the scene. The depth map can be combined with an intensity map to obtain a complete 3D image of the physical scene or environment.

[0037] An interconnect stack, such as interconnect stack 152, may be formed on the front side (surface) of semiconductor substrate 150. Interconnect stack 152 may include alternating routing layers and via layers. Each routing layer in interconnect stack 152 may include a conductive (metal) routing path, such as metal routing structure 156, formed in a layer of dielectric material. Each via layer in interconnect stack 152 may include a conductive (metal) via, such as metal via structure 158, formed in a layer of dielectric material. Thus, interconnect stack 152 may be referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed in a dielectric material such as silicon dioxide). Conductive routing structure 156 and conductive via structure 158 may be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, metal alloys, combinations of metals, and / or other types of conductive materials. Metal routing structures 156 and metal via structures 158 can interconnect various components within die 106 and form an electrical network for coupling the array of SPADs to analog high voltage die 104. Metal routing structures 156 may be coupled to the SPAD cathode terminals (e.g., for reading out the SPAD output voltages) and may couple to the voltages V BS ) may be coupled to the SPAD anode terminal.

[0038] The interconnect stack 152 of the die 104 may be bonded to the interconnect stack 142 at a wafer bonding interface 105. The bonding interface 105 may be formed to ensure that the dielectric materials in the interconnect stacks 142 and 152 are properly attached and also to ensure that the conductive routing structures 146 and 156 at the bonding interface 105 are properly connected (bonded). Such bonding at the interface 105 that ensures both a physical bond and an electrical bond may be referred to herein as a hybrid bond.

[0039] One or more through silicon via (TSV) structures, such as TSV 160, may be formed in the sensor die 106. In some embodiments, the TSV structure 160 may extend through the entire depth of the semiconductor substrate 150 (e.g., the through silicon via 160 may extend from the backside of the substrate 150 to at least the frontside of the substrate 150). The TSV structure 160 may extend at least partially into the interconnect stack 152 and may be electrically connected to one of the metal routing structures 156 or a conductive via. If desired, an additional interconnect stack may be formed between the substrate layer 150 and the passivation layer 170 in the wafer 106, and the TSV structure 160 may additionally or alternatively extend at least partially into or completely through the additional interconnect stack. The TSV structure 160 may be lined with an insulating layer 162 and filled with a conductive material 164. Insulating layer 162 may be formed from silicon dioxide, silicon nitride, silicon oxynitride, or other insulating materials. Conductive fill material 164 may be formed from tungsten, aluminum, copper, copper tungsten, titanium, tantalum, combinations of these materials, or other conductive materials suitable for via structures.

[0040] A passivation layer, such as passivation layer 170, may be formed along the backside (rear side) of substrate 150. Passivation layer 170 may be formed using silicon dioxide, silicon nitride, silicon oxynitride, polyimide, other polymers, or other passivation materials. A contact pad, such as contact pad 172 (e.g., a wire bond pad or other type of metal pad), may be formed on passivation layer 170. Contact pad 172 may be coupled to through-silicon via 160 that traverses substrate layer 150 of sensor die 106. During operation of SPAD circuit 100, incident light 174 may be incident through the backside of sensor die 106 (i.e., the backside of sensor die substrate 150). A SPAD circuit 100 operating in this manner may be referred to as a backside illuminated (BSI) SPAD-based sensor.

[0041] The imaging system described herein may have SPAD pixels vertically stacked with HV devices and corresponding readout logic. The SPADs may be connected to the HV devices through an interconnect stack including TSVs and conductive vias. The HV devices may be further connected to external contact pads using another such interconnect stack. In some implementations, the HV devices are vertically stacked with corresponding readout logic for the SPADs through another interconnect stack, and the readout logic is then connected to external contact pads through yet another interconnect stack. A vertically stacked SPAD circuit 100 arranged in the manner shown in FIG. 4 is technically advantageous and beneficial since the HV devices are vertically stacked with the SPAD pixels and the readout logic on the wafer 102 is coupled to the external contact pads using TSVs 130 that traverse the substrate layer 120 in the wafer 104 and TSVs 160 that traverse the substrate layer 150 in the wafer 106, providing active in-pixel quenching, a smaller overall form factor, and improved reliability due to reduced need for wire bonding between stacked dies. For example, compared to a non-stacked configuration in which the SPAD pixels and HV devices are formed within the same wafer, vertically stacked SPAD circuits can help reduce the overall footprint of the package by at least 30% or more, at least 40% or more, or at least 50% or more.

[0042] The process of fabricating the SPAD circuit 100 of FIG. 4 may be illustrated in a series of snapshots shown in FIGS. 7A-7G. FIG. 7A is a side cross-sectional view showing front side processing of the digital readout logic wafer 102 and the analog high voltage wafer 104. As shown in FIG. 7A, an interconnect stack 112 may be formed on the front side (surface) of the semiconductor substrate 110. The digital readout logic wafer 102 may also be called a digital readout logic layer, and may later be separated or diced into a plurality of digital readout logic dies 102. Meanwhile, an interconnect stack 122 may be formed on the front side (surface) of the semiconductor substrate 120 for the wafer 104. The analog HV wafer 104 may also be called an analog high voltage layer, and may later be separated or cut into a plurality of analog high voltage dies 104. Prior to front side processing of the wafer 104, the semiconductor substrate 120 may be attached to an oxide layer, such as a buried oxide (BOX) layer 300. The buried oxide layer 300 may be formed from silicon dioxide, aluminum oxide, zinc oxide, indium tin oxide, titanium oxide, or gallium oxide (for example). The buried oxide layer 300 may be formed on a handling wafer, such as a carrier wafer 302. The stacking of the buried oxide layer 300 and the semiconductor substrate 120 onto the carrier wafer 302 may be referred to as a silicon-on-insulator (SOI) configuration. The surface of the wafer 102 may be applied to the surface of the wafer 104, as indicated by arrow 304, in preparation for the subsequent bonding process in FIG. 7B.

[0043] 7B is a cross-sectional side view showing wafer bonding between the digital readout logic wafer 102 and the analog high voltage wafer 104. As shown in FIG. 7B, the wafers 102 and 104 can be bonded at an interface 103. The bonding interface 103 can be formed to ensure that the dielectric materials in the interconnect stacks 112 and 122 are properly attached and also ensure that the conductive routing structures 116 and 126 at the bonding interface 103 are electrically connected (bonded). Such bonding at the interface 103 that ensures both physical and electrical bonding may be referred to herein as hybrid bonding.

[0044] 7C is a cross-sectional side view showing removal of the carrier wafer 302 from the backside of the analog high voltage wafer 104. Removal of the carrier (handling) wafer 302 can be accomplished by a mechanical grinding process and / or a wet etching process and chemical-mechanical polishing (CMP). A wet etching process can include using an etchant that can selectively remove the carrier wafer 302 while stopping on the buried oxide layer 300 (e.g., the wet etchant only minimally removes silicon dioxide).

[0045] 7D is a cross-sectional side view illustrating additional backside processing of the analog high voltage wafer 104. As shown in FIG. 7D, an interconnect stack 142 may be formed on the backside (rear surface) of the semiconductor substrate 120. The interconnect stack 142 may be formed from a buried oxide layer 300. Metal routing structures 146 within the interconnect stack 142 may be connected to one or more TSV structures 130 (e.g., vias 148). *148'', to a drain terminal of one or more high voltage devices N1 (e.g., using vias 148'), and to a drain terminal of one or more high voltage devices P1 (e.g., using vias 148''). This example in which the interconnect stack 142 is formed from a buried oxide layer 300 is illustrative. In other embodiments, the interconnect stack 142 can be formed separately on the backside of the substrate 120 without first forming the buried oxide layer 300.

[0046] FIG. 7E is a side cross-sectional view illustrating front side processing of the sensor wafer 106. As shown in FIG. 7E, an interconnect stack 152 may be formed on the front side (surface) of a semiconductor substrate 150. The sensor wafer 106 may also be referred to as a sensor or SPAD layer and may later be separated or diced into multiple sensor dies 106. Prior to front side processing of the wafer 106, the semiconductor substrate 150 may be attached to a p+ silicon layer 310. The substrate layer 150 may be an epitaxial silicon layer. A TSV structure 160 may be formed at least partially through the epitaxial silicon layer 150 and the interconnect stack 152. The front side of the wafer 106 may be applied to the back side of the wafer 104, as indicated by arrow 312, in preparation for the subsequent bonding process of FIG. 7F.

[0047] 7F is a cross-sectional side view illustrating wafer bonding between the sensor wafer 106 and the processed backside of the analog high voltage wafer 104. As shown in FIG. 7F, the wafers 106 and 104 may be bonded at interface 105. The bonding interface 105 may be formed to ensure that the dielectric materials in the interconnect stacks 152 and 142 are properly attached and also to ensure that the conductive routing structures 156 and 146 at the bonding interface 105 are electrically connected (bonded). Such bonding at interface 105 that ensures both a physical bond and an electrical bond may be referred to herein as hybrid bonding.

[0048] FIG. 7G is a cross-sectional side view illustrating additional backside processing of the sensor wafer 106. As shown in FIG. 7G, the p+ silicon layer 310 of FIG. 7F can be removed by mechanical grinding and / or wet etching processes. A planarization process, such as a chemical mechanical polishing (CMP) process, can then be used to polish the backside of the substrate layer 150 and expose the TSV structures 160 (e.g., such that the TSVs 160 are exposed at the backside of the substrate layer 150). After the CMP or other planarization process, a passivation layer 170 can be formed on the backside of the substrate layer 150. The passivation layer 170 can be formed using silicon dioxide, silicon nitride, silicon oxynitride, polyimide, other polymers, or other passivation materials. Additional processing steps can then be performed to selectively pattern the passivation layer 170 to form contact pads 172 coupled to one or more TSV structures 160 (see, e.g., the completed die stack of FIG. 4).

[0049] FIG. 8 is a flow chart of exemplary steps for fabricating a SPAD circuit of the type shown in FIGS. 4-7. During the operation of block 400, the front side of the digital readout logic wafer 102 may be processed. For example, digital readout logic may be formed in the front side of the semiconductor substrate 110, and interconnects 112 may be formed on the front side of the semiconductor substrate 110. During the operation of block 402, the front side of the analog high voltage wafer 104 may be processed. For example, high voltage switches N1 and P1 may be formed in the front side of the semiconductor substrate 120, and interconnects 122 may be formed on the front side of the semiconductor substrate 120. The results of blocks 400 and 402 may be shown in FIG. 7A. Although the operation of block 402 is shown as occurring after the operation of block 400, block 402 may alternatively occur before or in parallel (concurrently) with block 400.

[0050] During the operation of block 404, the digital readout logic wafer 102 may be bonded to the analog high voltage wafer 104. The result of block 404 may be shown in FIG.

[0051] During the operation of block 406, the handle wafer 302 may be removed from the backside of the analog high voltage wafer 104. For example, the handle (carrier) wafer 302 may be removed using mechanical grinding and / or a wet etching process. The wet etching process may include using an etchant that can selectively remove the carrier wafer 302 while stopping on the buried oxide layer 300 (e.g., the wet etchant only minimally removes silicon dioxide). The result of block 406 may be shown in FIG. 7C.

[0052] During the operation of block 408, the backside of the analog high voltage wafer 104 may be processed. For example, an interconnect stack 142 may be formed on the backside (rear surface) of the semiconductor substrate 120 (see, e.g., FIG. 7D). The interconnect stack 142 may be formed from a buried oxide layer 300. Metal routing structures 146 in the interconnect stack 142 may be connected to one or more TSV structures 130 (e.g., vias 148). * vias 148 ′), to the drain terminals of one or more high voltage devices N1 (e.g., using vias 148 ′), and to the drain terminals of one or more high voltage devices P1 (e.g., using vias 148 ″). * , 148', and 148'' may be referred to as backside vias. The metal routing structures 146 exposed on the surface of the interconnect stack 142 may also be referred to as backside bond pads.

[0053] During the operation of block 410, the front side of the sensor wafer 106 may be processed. For example, an interconnect stack 152 may be formed on the front side (surface) of the semiconductor substrate 150 (see, e.g., FIG. 7E). Prior to front side processing of the wafer 106, the semiconductor substrate 150 may be attached to a p+ silicon layer 310. The substrate layer 150 may be an epitaxial silicon layer. A TSV structure 160 may be formed at least partially through the epitaxial silicon layer 150 and the interconnect stack 152. Although the operation of block 410 is shown as occurring after the operations of blocks 400-408, block 410 may alternatively be performed before or in parallel (concurrently) with any of blocks 400-408.

[0054] During the operation of block 412, the sensor wafer 106 may be bonded to the backside of the analog high voltage wafer 104. The result of block 412 may be shown in FIG.

[0055] During the operation of block 414, the backside of the sensor wafer 106 may be processed. For example, the p+ silicon layer 310 of FIG. 7F may be removed by mechanical grinding and / or wet etching processes. A planarization process, such as a chemical mechanical polishing (CMP) process, may then be used to polish the backside of the substrate layer 150 to expose the TSV structures 160. After the CMP or other planarization process, a passivation layer 170 may be formed on the backside of the substrate layer 150 (see operation of block 416). The passivation layer 170 may also be referred to as a BSI passivation layer. Additional processing steps may then be performed to selectively pattern the passivation layer 170 to form contact pads 172 coupled to one or more TSV structures 160 (see operation of block 418).

[0056] This example in FIG. 8 is illustrative. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processes may be added or inserted between the described operations. If desired, the order of some operations may be reversed or changed, and / or the timing of the described operations may be adjusted so that they occur at slightly different times.

[0057] The embodiment described above in connection with FIGS. 3-8, in which the high voltage devices in the analog die 104 include both n-type device N1 and p-type device P1, is an example. FIG. 9 shows another embodiment of a SPAD circuit 100' that includes a high voltage p-type device P1 but does not include a high voltage n-type device N1. As shown in FIG. 9, the analog high voltage wafer 104 has a p-type vertical transistor P1 formed as part of each SPAD pixel 30, but does not include an n-type vertical transistor N1 (see the absence of transistor N1). This may help to save one or more processing steps in manufacturing the wafer 104. The remaining structure of the entire wafer stack is similar or identical to that already described in connection with FIGS. 4-8 and need not be repeated in detail to avoid obscuring the present embodiment.

[0058] Various embodiments of SPAD circuits are included. One aspect of the present disclosure provides a circuit including a first die having a plurality of single photon avalanche diodes (SPADs), each SPAD in the plurality of SPADs having an anode terminal and a cathode terminal configured to receive a bias voltage, and a second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die. The first die may be stacked on a backside of the second die. The first die may include a first semiconductor substrate layer having a plurality of SPADs formed therein, a first interconnect stack of alternating routing layers and via layers on a surface of the first semiconductor substrate layer, and a first through silicon via (TSV) extending from a backside of the first semiconductor substrate layer to a surface of the first semiconductor substrate layer and at least partially within the first interconnect stack. The second die may include a second semiconductor substrate layer having a plurality of switches formed therein, a second interconnect stack of alternating routing and via layers on a back surface of the second semiconductor substrate layer, a second through-silicon via (TSV) extending from the back surface of the second semiconductor substrate layer to a front surface of the second semiconductor substrate layer, and a third interconnect stack of alternating routing and via layers on the front surface of the second semiconductor substrate layer, wherein the second TSV extends at least partially within the third interconnect stack.

[0059] The plurality of switches may include a p-type transistor having a drain terminal coupled to a routing structure in the second interconnect stack and having a source terminal and a gate terminal coupled to a routing structure in the third interconnect stack, and optionally an n-type transistor having a drain terminal coupled to a routing structure in the second interconnect stack and having a source terminal and a gate terminal coupled to a routing structure in the third interconnect stack. The circuit may include a third die having digital readout logic coupled to the plurality of switches in the second die, the second die being stacked on a front side of the third die. The third die may further include a third semiconductor substrate layer having the digital readout logic formed thereon, and a fourth interconnect stack of alternating routing and via layers on a surface of the third semiconductor substrate layer.

[0060] One aspect of the disclosure provides a method including forming a first wafer including a plurality of single photon avalanche diodes (SPADs), each SPAD in the plurality of SPADs having an anode terminal and a cathode terminal configured to receive a bias voltage, forming a second wafer including a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first wafer, and bonding the first wafer to the second wafer. The method may further include forming a third wafer including digital readout logic coupled to the plurality of switches in the second wafer, and bonding the third wafer to the second wafer. The method may further include forming a through silicon via (TSV) structure through a semiconductor substrate layer in the first wafer, and forming a through silicon via (TSV) structure through a semiconductor substrate layer in the second wafer.

[0061] One aspect of the disclosure provides an apparatus including a sensor die having a plurality of single photon avalanche diodes (SPADs), a digital die having digital readout logic powered by a first positive voltage, and an analog die having a switch powered by a second positive voltage greater than the first positive voltage, stacked vertically between the sensor die and the digital die. The analog die can have a front side configured to face the digital die and can have a back side configured to face the sensor die. The apparatus can include a first through silicon via (TSV) structure in the sensor die and a second through silicon via (TSV) structure in the analog die. At least some of the second TSV structures can be coupled to routing structures in the sensor die and routing structures in the digital die.

[0062] According to one embodiment, a circuit is provided that includes a first die having a plurality of single photon avalanche diodes (SPADs), each SPAD in the plurality of SPADs having an anode terminal and a cathode terminal, and a second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die, the first die being stacked on the second die.

[0063] According to another embodiment, the first die may further include a first semiconductor substrate layer having a plurality of SPADs formed therein, a first interconnect stack of alternating routing layers and via layers on a surface of the first semiconductor substrate layer, and a first through-silicon via (TSV) extending from a back surface of the first semiconductor substrate layer to the surface of the first semiconductor substrate layer and at least partially within the first interconnect stack.

[0064] According to another embodiment, the first die may further include a passivation layer on a back side of the first semiconductor substrate layer and conductive pads on the passivation layer.

[0065] According to another embodiment, the multiple SPADs can be configured to receive incident light from a backside of the first semiconductor substrate layer.

[0066] According to another embodiment, the second die may further include a second semiconductor substrate layer having a plurality of switches formed therein, a second interconnect stack of alternating routing layers and via layers on a back surface of the second semiconductor substrate layer, and a second through-silicon via (TSV) extending from the back surface of the second semiconductor substrate layer to the front surface of the second semiconductor substrate layer.

[0067] According to another embodiment, the second die may further include a third interconnect stack of alternating routing layers and via layers on a surface of the second semiconductor substrate layer, the second TSV extending at least partially within the third interconnect stack.

[0068] According to another embodiment, the plurality of switches can include a p-type transistor having a drain terminal coupled to a routing structure in the second interconnect stack and having source and gate terminals coupled to routing structures in the third interconnect stack.

[0069] According to another embodiment, the plurality of switches may further include an n-type transistor having a drain terminal coupled to a routing structure in the second interconnect stack and having source and gate terminals coupled to routing structures in the third interconnect stack.

[0070] According to another embodiment, the circuit may further include a third die having digital readout logic coupled to the plurality of switches in the second die, the second die being stacked on the third die.

[0071] According to another embodiment, the third die may further include a third semiconductor substrate layer having digital readout logic formed therein, and a fourth interconnect stack of alternating routing layers and via layers on a surface of the third semiconductor substrate layer.

[0072] According to one embodiment, a method is provided that includes forming a first wafer including a plurality of single photon avalanche diodes (SPADs), each SPAD in the plurality of SPADs having an anode terminal and a cathode terminal; forming a second wafer including a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first wafer; and bonding the first wafer to the second wafer.

[0073] According to another embodiment, the method may further include forming a third wafer including digital readout logic coupled to the plurality of switches in the second wafer, and bonding the third wafer to the second wafer.

[0074] According to another embodiment, the method may further include forming a through-silicon via (TSV) structure through a semiconductor substrate layer in the first wafer, the TSV structure extending at least partially into an interconnect stack on the semiconductor substrate layer in the first wafer.

[0075] According to another embodiment, the method may further include forming a through-silicon via (TSV) structure through a semiconductor substrate layer in the second wafer, the TSV structure extending at least partially into the interconnect stack on the semiconductor substrate layer in the second wafer.

[0076] According to another embodiment, the method may further include forming a p-type vertical transistor in the semiconductor substrate layer of the second wafer.

[0077] According to another embodiment, the method may further include forming an n-type vertical transistor in the semiconductor substrate layer of the second wafer.

[0078] According to one embodiment, an apparatus is provided that includes a sensor die having a plurality of single photon avalanche diodes (SPADs), a digital die having digital readout logic powered by a first positive voltage, and an analog die having a switch powered by a second positive voltage greater than the first positive voltage, the analog die vertically stacked between the sensor die and the digital die.

[0079] According to another embodiment, the apparatus may further include first through-silicon-via (TSV) structures in the sensor die, at least one of the first TSV structures having a first end coupled to the contact pad and a second end coupled to a routing structure in the sensor die.

[0080] According to another embodiment, the apparatus may further include second through-silicon-via (TSV) structures in the analog die, at least one of the second TSV structures having a first end coupled to a routing structure in the sensor die and a second end coupled to a routing structure in the digital die.

[0081] According to another embodiment, at least one of the switches in the analog die can have a gate terminal and a source terminal coupled to the routing structure in the digital die and a drain terminal coupled to the routing structure in the sensor die.

[0082] The above is merely illustrative and various modifications can be made to the described embodiments. The above embodiments can be implemented individually or in any combination.

Claims

1. 1. A circuit comprising: a first die having a plurality of single photon avalanche diodes (SPADs), each SPAD in the plurality of SPADs having an anode terminal and a cathode terminal; a second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die, the first die being stacked on the second die; A circuit comprising:

2. The first die includes: a first semiconductor substrate layer having the plurality of SPADs formed thereon; a first interconnect stack of alternating routing and via layers on a surface of the first semiconductor substrate layer; a first through-silicon via (TSV) extending from a back surface of the first semiconductor substrate layer to the front surface of the first semiconductor substrate layer and extending at least partially into the first interconnect stack; The circuit of claim 1 further comprising:

3. The first die includes: a passivation layer on the back surface of the first semiconductor substrate layer; a conductive pad on the passivation layer; The circuit of claim 2 further comprising:

4. The circuit of claim 2 , wherein the plurality of SPADs are configured to receive incident light from the backside of the first semiconductor substrate layer.

5. The second die includes: a second semiconductor substrate layer having the plurality of switches formed therein; a second interconnect stack of alternating routing and via layers on a backside of the second semiconductor substrate layer; a second through-silicon via (TSV) extending from the back surface of the second semiconductor substrate layer to a front surface of the second semiconductor substrate layer; a third interconnect stack of alternating routing and via layers on the surface of the second semiconductor substrate layer, the second TSV extending at least partially within the third interconnect stack; and The circuit of claim 2 further comprising:

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