Single photon avalanche diode, photoelectric detection device and electronic equipment

Abstract

The utility model provides a single-photon avalanche diode, a photoelectric detection device and electronic equipment. The single-photon avalanche diode comprises a substrate layer, a first doped region, a second doped region, an isolation region, a first electrode and a second electrode, the first doped region is located above the substrate layer, the second doped region is located above the first doped region, and the net doping type of the first doped region is opposite to that of the second doped region, so that a PN junction is formed between the first doped region and the second doped region, and depletion regions are formed on two sides of an interface of the PN junction; the isolation region is attached to the outer sides of the first doped region and the second doped region in the horizontal direction, and is constructed to at least cover the region between the upper interface of the second doped region and the lower interface of the first doped region in the height direction; the first electrode and the second electrode are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. According to the single-photon avalanche diode, the size of a middle strong longitudinal electric field region cannot be affected when the overall size is reduced.

Description

Technical Field

[0001] The present application relates to the field of photoelectric detection devices, and in particular to a single-photon avalanche diode, a photoelectric detection device, and an electronic device. Background Art

[0002] Single-photon avalanche diodes (SPADs) can detect extremely weak light, even single photons. By performing time-correlated single photon counting (TCSPC) on the emitted photons and the photons reflected by the detected target, they can measure the photons' time of flight (ToF), thereby enabling the detection of the target's distance. In recent years, LiDAR (Light Detection and Ranger) technology, which utilizes the ToF principle for ranging, has been widely used in consumer products for 3D imaging, modeling, and recognition of objects, particularly in assisted and autonomous driving systems, as well as in 3D machine vision.

[0003] To achieve two-dimensional imaging or depth detection, one approach is scanning; another is to directly utilize a two-dimensional array light source and a two-dimensional array detector to detect optical signals within a specific two-dimensional angle. For two-dimensional array detection, the imaging resolution can be increased by reducing the size of the single-photon avalanche diode (SPAD) unit in the two-dimensional array detector.

[0004] The most basic structure of an existing single-photon avalanche diode (SPAD) consists of a P-region and an N-region, which form a PN junction. While the P-region and N-region form a longitudinal electric field along the stacking direction, they also form a transverse electric field. This transverse electric field can easily lead to premature avalanche breakdown, preventing the normal output of electrical signals when signal photons are incident. This reduces the probability of detecting the incident signal light and, in turn, the signal-to-noise ratio of the SPAD's output signal. Therefore, it is necessary to suppress the transverse electric field formed by the P-region and N-region.

[0005] There are many ways to suppress the lateral electric field. However, in existing technologies, while maintaining the overall size of the SPAD unit, these methods often involve reducing the size of the intermediate avalanche region or employing charge focusing. A smaller intermediate avalanche region reduces the probability of edge carriers entering the region, leading to lower photoelectric detection efficiency. Charge focusing requires a complex ion implantation process, which increases device variability and timing jitter, leading to poor performance of the single-photon avalanche diode. Utility Model Content

[0006] In view of this, the embodiments of the present application are dedicated to providing a single-photon avalanche diode to solve the problem of poor performance of single-photon avalanche diodes in the prior art.

[0007] A first aspect of the present application provides a single-photon avalanche diode, comprising:

[0008] basal layer;

[0009] a first doping region and a second doping region, wherein the first doping region is located above the base layer, the second doping region is located above the first doping region, and the first doping region and the second doping region have opposite net doping types, so as to form a PN junction therebetween and form depletion regions on both sides of the PN junction interface;

[0010] an isolation region, the isolation region being attached to the outer sides of the first doping region and the second doping region in a horizontal direction and being configured to cover at least a region between an upper interface of the second doping region and a lower interface of the first doping region in a height direction;

[0011] A first electrode and a second electrode, wherein the first electrode is electrically connected to the first doped region, the second electrode is electrically connected to the second doped region, a connection region between the first electrode and the first doped region and a connection region between the second electrode and the second doped region form a heavily doped region, and the first electrode and the second electrode are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region.

[0012] In one embodiment of the present application, the isolation region is configured to be filled with polysilicon.

[0013] In one embodiment of the present application, the single-photon avalanche diode further includes a third electrode, wherein the third electrode is electrically connected to the isolation region to apply a voltage to the isolation region.

[0014] In one embodiment of the present application, the isolation region is configured to be filled with a dielectric.

[0015] In one embodiment of the present application, the isolation region includes a high dielectric constant material film located on the sidewalls and bottom wall of the isolation region and a dielectric filling the rest of the isolation region.

[0016] In one embodiment of the present application, it further includes:

[0017] An oxide layer is configured to be located at least between the isolation region and interfaces between the first doping region, the second doping region, and the base layer.

[0018] In one embodiment of the present application, the first doping region and the second doping region are configured to have equal dimensions extending in a horizontal direction.

[0019] In one embodiment of the present application, the second doping region is configured such that edges thereof extend beyond horizontal edges of the first doping region so as to respectively align with the isolation regions on the outside in the horizontal direction.

[0020] In one embodiment of the present application, the first doping region includes a first central doping region and a first edge doping region located at a horizontal outer edge of the first central doping region adjacent to the PN junction interface, and the net doping concentration of the first edge doping region is configured to be less than the net doping concentration of the first central doping region;

[0021] and / or,

[0022] The second doping region includes a second central doping region and a second edge doping region located at the horizontal outer edge of the second central doping region adjacent to the PN junction interface, and the net doping concentration of the second edge doping region is constructed to be less than the net doping concentration of the second central doping region.

[0023] In one embodiment of the present application, the third doping region is further provided around the outer side of the isolation region in a horizontal direction, wherein the impurity concentration of the third doping region is higher than the impurity concentration of the base layer, and the net doping type of the third doping region is the same as the net doping type of the first doping region;

[0024] The first electrode is configured to be electrically connected to the third doping region.

[0025] In one embodiment of the present application, a fourth doping region is further included below the base layer, wherein the impurity concentration of the fourth doping region is higher than the impurity concentration of the base layer, and the net doping type of the fourth doping region is the same as the net doping type of the first doping region;

[0026] The first electrode is configured to be electrically connected to the fourth doping region.

[0027] In one embodiment of the present application, the net doping type of the first doping region is P-type, the net doping type of the second doping region is N-type, and the base layer is a P-type substrate.

[0028] In one embodiment of the present application, the net doping type of the first doping region is N-type, the net doping type of the second doping region is P-type, and the base layer includes an N-type buried layer and a P-type substrate located below the N-type buried layer.

[0029] A second aspect of the present application provides a photoelectric detection device, comprising the single-photon avalanche diode, wherein the photoelectric detection device is configured to obtain relevant information by sensing an electrical signal generated corresponding to an optical signal received by the single-photon avalanche diode.

[0030] A third aspect of the present application provides an electronic device, comprising the photoelectric detection device, wherein the electronic device is configured to execute a corresponding function according to relevant information acquired by sensing an electrical signal by the photoelectric detection device.

[0031] During the operation of the single-photon avalanche diode of the present application, the first electrode and the second electrode can apply a reverse bias voltage to the PN junction between the first doped region and the second doped region, thereby forming a strong longitudinal electric field in the depletion region of the PN junction. The reverse bias voltage is higher than the avalanche breakdown voltage of the single-photon avalanche diode, thereby forming an avalanche region in the depletion region. At this time, the single-photon avalanche diode is in Geiger mode. When an incident photon is absorbed in the depletion region, an electron-hole carrier pair is generated in the depletion region. The carriers gain energy under the action of the strong longitudinal electric field in the depletion region and generate more carriers by collision ionization with lattice atoms, thereby triggering an avalanche multiplication effect, which causes the reverse current of the single-photon avalanche diode of the present application to rise sharply, and eventually form an avalanche current.

[0032] In the single-photon avalanche diode of the present application, since an isolation region is formed on the outside of the first doped region and the second doped region in the horizontal direction, and the isolation region covers at least the area between the upper interface of the second doped region and the lower interface of the first doped region in the height direction, the isolation region is attached to the second doped region and the outer area of ​​the depletion region of the PN junction between the first doped region and the second doped region, and is used to suppress the lateral electric field generated on the lateral outer side of the second doped region, so that the carrier avalanche generated by the incident light occurs as much as possible in the strong longitudinal electric field area rather than in the lateral electric field area, effectively avoiding edge breakdown of the single-photon avalanche diode, thereby improving the performance and reliability of the single-photon avalanche diode of the present application, and extending the service life of the single-photon avalanche diode of the present application.

[0033] Therefore, by setting up an isolation region, it is possible to effectively suppress the lateral electric field generated on the lateral outside of the second doped region without setting up a depletion region with a larger width on the outside of the second doped region, and it will not affect the middle strong longitudinal electric field region; this enables the single-photon avalanche diode of the present application to reduce the overall size without affecting the size of the middle strong longitudinal electric field region, so that when the single-photon avalanche diode of the present application is applied to a photoelectric detection device, it can improve the imaging resolution by reducing the overall size and increasing the overall density while ensuring the high photoelectric detection efficiency of a single single-photon avalanche diode, thereby effectively improving the overall performance of the photoelectric detection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a schematic diagram of the cross-sectional structure of an existing avalanche diode.

[0035] Figure 2 Shown is a schematic cross-sectional structure diagram of the single-photon avalanche diode of the present application.

[0036] Figure 3 Shown is a schematic diagram of the top surface structure of the single-photon avalanche diode of the present application.

[0037] Figure 4 Shown is a schematic cross-sectional structure diagram of another single-photon avalanche diode of the present application.

[0038] Figure 5 Shown is a schematic cross-sectional structure diagram of another single photon avalanche diode of the present application.

[0039] Figure 6 Shown is a schematic cross-sectional structure diagram of another single photon avalanche diode of the present application.

[0040] Figure 7 Shown is a schematic cross-sectional structure diagram of another single photon avalanche diode of the present application.

[0041] Figure 8 Shown is a schematic cross-sectional structure diagram of another single-photon avalanche diode of the present application.

[0042] Figure 9 Shown is a schematic cross-sectional structure diagram of another single-photon avalanche diode of the present application.

[0043] Figure 10 Shown is a schematic cross-sectional structure diagram of another single-photon avalanche diode of the present application.

[0044] Figures 11A-11E Shown Figure 4 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0045] Figures 12A-12E Shown Figure 5 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0046] Figures 13A-13E Shown Figure 6 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0047] Figures 14A-14F Shown Figure 7 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0048] Figures 15A-15E Shown Figure 8Schematic diagram of the preparation process of another single-photon avalanche diode.

[0049] Figures 16A-16F Shown Figure 9 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0050] Figures 17A-17I Shown Figure 10 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0051] Figure 18 Shown is a schematic diagram of the steps of the method for preparing the single-photon avalanche diode of the present application.

[0052] Figure markings: 10, base layer; 11, P-type substrate; 12, N-type buried layer; 20, first doped region; 21, first middle doped region; 22, first edge doped region; 30, second doped region; 31, second middle doped region; 32, second edge doped region; 40, isolation region; 41, polysilicon; 42, dielectric; 43, high dielectric constant material film; 44, deep trench; 50, oxide layer; 61, first electrode; 62, second electrode; 63, third electrode; 70, third doped region; 80, fourth doped region; 91, strong longitudinal electric field; 92, transverse electric field. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0054] Should be noted that: unless otherwise specifically stated, otherwise the relative arrangement, numerical expression and numerical value of the parts and steps set forth in these embodiments do not limit the scope of the application. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, rather than as a restriction. Therefore, other examples of exemplary embodiments can have different values.

[0055] The following description sets forth numerous specific details to facilitate a thorough understanding of this application. However, this application can be implemented in many other ways than those described herein, and those skilled in the art may make similar generalizations without violating the scope of this application. Therefore, this application is not limited to the specific implementations disclosed below. Techniques, methods, and apparatus known to persons of ordinary skill in the relevant art may not be discussed in detail, but, where appropriate, should be considered part of the specification.

[0056] The terms used in one or more embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of the present application. The singular forms "a", "an", "the" and "the" used in one or more embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of the present application refers to and includes any or all possible combinations of one or more associated listed items.

[0057] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of the present application, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to a determination". In this article, "upper", "lower", "front", "back", "left", "right", etc. are only used to indicate the relative positional relationship between the relevant parts, rather than to limit the absolute position of these relevant parts. In this article, "equal", "same", etc. are not strict mathematical and / or geometric limitations, but also include errors that can be understood by those skilled in the art and are allowed by manufacturing or use. Unless otherwise specified, the numerical ranges herein include not only the entire range within its two endpoints, but also several sub-ranges contained therein.

[0058] Figure 1 It is a cross-sectional structural diagram of an NP-type single-photon avalanche diode in the prior art. It is understandable that single-photon avalanche diodes can be divided into NP-type single-photon avalanche diodes and PN-type single-photon avalanche diodes. Figure 1 The single-photon avalanche diode in the invention is an NP-type single-photon avalanche diode. The PN-type single-photon avalanche diode has a similar principle and structure to the NP-type single-photon avalanche diode.

[0059] The single-photon avalanche diode includes a P region and an N region, which form a PN junction between each other; in order to facilitate avalanche multiplication, additional doping is usually performed near the PN junction region to facilitate avalanche multiplication under relatively low bias voltage.

[0060] Among them, Figure 1 As shown, the P and N regions generate a longitudinal electric field and a transverse electric field 92 simultaneously. The longitudinal electric field can drift carriers generated by incident photons into the avalanche region. Simultaneously, the strong longitudinal electric field 91 in the avalanche region causes the carriers to collide and ionize with the crystal lattice. When the width of the strong longitudinal electric field 91 is sufficiently large, a self-sustaining avalanche effect can occur, leading to avalanche breakdown.

[0061] Due to the presence of the transverse electric field, premature avalanche breakdown is likely to occur, making it impossible to output an electrical signal normally when a signal photon is incident, thereby reducing the probability of detecting the incident signal light and further reducing the signal-to-noise ratio of the output signal of the single-photon avalanche diode. Therefore, it is necessary to suppress the transverse electric field formed by the P region and the N region.

[0062] Therefore, if Figure 2 and Figure 3 As shown, the present application provides a single-photon avalanche diode, comprising a base layer 10, a first doped region 20, a second doped region 30, an isolation region 40, a first electrode 61, and a second electrode 62. The first doped region 20 is located above the base layer 10, and the second doped region 30 is located above the first doped region 20. The first doped region 20 and the second doped region 30 have opposite net doping types, so as to form a PN junction therebetween, and a depletion region is formed on both sides of the PN junction interface.

[0063] The isolation region 40 is laminated to the horizontal outer sides of the first doped region 20 and the second doped region 30, and is configured to cover at least the region between the upper interface of the second doped region 30 and the lower interface of the first doped region 20 in the height direction. It will be understood that the horizontal direction refers to the extension direction of the wafer on which the single-photon avalanche diode of the present application is located, and the isolation region 40 is laminated to the horizontal outer sides of the first doped region 20 and the second doped region 30, which means that the isolation region 40 is located outside the horizontal outer sides of the first doped region 20 and the second doped region 30, and is directly laminated to the horizontal outer side surfaces of the first doped region 20 and the second doped region 30. Figure 2 is a cross-sectional view of the single-photon avalanche diode of this application, Figure 3 For ease of processing, the first doped region 20 and the second doped region 30 may both be rectangular regions, and the isolation region 40 may be an annular region disposed horizontally outside the first doped region 20 and the second doped region 30 .

[0064] Of the first electrode 61 and the second electrode 62, the first electrode 61 is electrically connected to the first doped region 20, and the second electrode 62 is electrically connected to the second doped region 30. The first electrode 61 and the second electrode 62 are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. The electrical connection between the first electrode 61 and the first doped region 20 refers to an indirect electrical connection through other structures or a direct electrical connection. The second electrode 62 is directly electrically connected to the second doped region 30. As mentioned above, the portion of the region directly electrically connected between the second doped region 30 and the second electrode 62 can be heavily doped, which is not shown in the figure.

[0065] It can be understood that in the single-photon avalanche diode of the present application, the areas where the first electrode 61 and the second electrode 62 contact the corresponding structures can be heavily doped to achieve ohmic contact and reduce the on-resistance. This heavily doped area is not shown in the drawings.

[0066] During the operation of the single-photon avalanche diode of the present application, the first electrode 61 and the second electrode 62 can apply a reverse bias voltage to the PN junction between the first doped region 20 and the second doped region 30, thereby forming a strong longitudinal electric field 91 in the depletion region of the PN junction. The reverse bias voltage is higher than the avalanche breakdown voltage of the single-photon avalanche diode, thereby forming an avalanche region in the depletion region. At this time, the single-photon avalanche diode is in Geiger mode. When an incident photon is absorbed in the depletion region, an electron-hole carrier pair is generated in the depletion region. The carriers gain energy under the action of the strong longitudinal electric field 91 in the depletion region and generate more carriers by colliding and ionizing with lattice atoms, thereby triggering an avalanche multiplication effect, which causes the reverse current of the single-photon avalanche diode of the present application to rise sharply, and eventually form an avalanche current.

[0067] In the single-photon avalanche diode of the present application, since an isolation region 40 is formed on the outside of the first doped region 20 and the second doped region 30 in the horizontal direction, and the isolation region 40 covers at least the area between the upper interface of the second doped region 30 and the lower interface of the first doped region 20 in the height direction, the isolation region 40 is attached to the second doped region 30 and the outer area of ​​the depletion region of the PN junction between the first doped region 20 and the second doped region 30, and is used to suppress the lateral electric field generated on the lateral outer side of the second doped region 30, so that the carrier avalanche generated by the incident light occurs as much as possible in the strong longitudinal electric field 91 area, rather than in the lateral electric field area, effectively avoiding edge breakdown of the single-photon avalanche diode, thereby improving the performance and reliability of the single-photon avalanche diode of the present application, and extending the service life of the single-photon avalanche diode of the present application.

[0068] Therefore, by setting the isolation region 40, it is possible to effectively suppress the lateral electric field generated on the lateral outer side of the second doped region 30 without setting a depletion region with a larger width on the outer side of the second doped region 30, and will not affect the middle strong longitudinal electric field 91 region; this enables the single-photon avalanche diode of the present application to reduce the overall size without affecting the size of the middle strong longitudinal electric field 91 region, so that when the single-photon avalanche diode of the present application is applied to the photoelectric detection device, it can improve the imaging resolution by reducing the overall size and increasing the overall density while ensuring the high photoelectric detection efficiency of a single single-photon avalanche diode, thereby effectively improving the overall performance of the photoelectric detection device.

[0069] It is understood that single-photon avalanche diodes can be divided into NP-type single-photon avalanche diodes and PN-type single-photon avalanche diodes.

[0070] That is Figure 2 As shown, in one embodiment of the present application, the net doping type of the first doping region 20 is P type, the net doping type of the second doping region 30 is N type, and the base layer 10 is a P type substrate 11, that is, Figure 2 The single-photon avalanche diode shown is an NP-type single-photon avalanche diode.

[0071] And as Figure 5 As shown, in another embodiment of the present application, the net doping type of the first doping region 20 is N-type, the net doping type of the second doping region 30 is P-type, and the base layer 10 includes an N-type buried layer 12 and a P-type substrate 11 located below the N-type buried layer 12, that is, Figure 5 The single-photon avalanche diode shown is a PN-type single-photon avalanche diode. The operating principle of a PN-type single-photon avalanche diode is similar to that of an NP-type single-photon avalanche diode.

[0072] Since in the semiconductor field, P-type substrate 11 has more advantages than N-type substrate and has a wider range of applications, Figure 2 Compared to the NP-type single-photon avalanche diode shown in Figure 5 An N-type buried layer 12 is added to the PN-type single-photon avalanche diode shown in the figure to isolate the N-type first doped region 20 from the P-type substrate 11; it can be understood that the electric field strength between the N-type buried layer 12 and the P-type substrate 11 is small and an avalanche region cannot be formed.

[0073] Of course, if Figure 4 As shown, in another embodiment of the present application, an N-type substrate may also be directly used. The principle is similar and will not be described in detail here.

[0074] It can be understood that the isolation region 40 can also extend from the upper interface of the second doping region 30 to a position lower than the lower interface of the first doping region 20, thereby covering the area from the upper interface of the second doping region 30 to a certain distance below the lower interface of the first doping region 20 in the height direction. The effect is similar to extending to a position flush with the lower interface of the first doping region 20, and will not be repeated here.

[0075] In a specific embodiment of the present application, the width of the isolation region 40 is in the range of 0.1 μm to 1 μm, and the depth is in the range of 0.5 μm to 5 μm, to ensure the isolation effect of the isolation region 40. It is understood that the specific width and depth of the isolation region 40 can be selected according to the specific device structure and are not limited here.

[0076] It is understood that in the single-photon avalanche diode of the present application, in order to form the isolation region 40, it is necessary to etch a corresponding deep trench 44 on the substrate, and then deposit the corresponding material within the isolation region 40. Lattice defects may occur at the side interfaces of the deep trench 44 region, which in turn may generate composite carriers. These carriers may drift to the central strong longitudinal electric field region 91 under the influence of the weak electric field at the side interfaces, triggering an avalanche, thereby increasing the dark count rate of the single-photon avalanche diode of the present application.

[0077] Therefore, if Figure 2 As shown, in one embodiment of the present application, the isolation region 40 is constructed to be filled with polysilicon 41. Compared with other materials, polysilicon 41 can effectively reduce lattice defects at the side interfaces of the deep trench 44, thereby reducing premature breakdown at the side interfaces of the deep trench 44.

[0078] Further, such as Figure 2 As shown, in one embodiment of the present application, the single-photon avalanche diode further includes a third electrode 63 , which is electrically connected to the isolation region 40 to apply a voltage to the isolation region 40 .

[0079] It is understandable that the third electrode 63 can apply a voltage of the same polarity as the first electrode 61 to the isolation area 40, or a voltage of the opposite polarity to the first electrode 61. The voltage polarity is not limited here; and the voltage magnitude can also be adjusted as needed.

[0080] Among them, the third electrode 63 applies a voltage of the same polarity as the first electrode 61 to the isolation region 40, which means that when the first electrode 61 applies positive electricity to the first doped region 20, the third electrode 63 applies positive electricity to the isolation region 40; when the first electrode 61 applies negative electricity to the first doped region 20, the third electrode 63 applies negative electricity to the isolation region 40.

[0081] It can be understood that the third electrode 63 is electrically connected to the polysilicon 41 of the isolation region 40 to apply the same voltage as the first electrode 61 to the isolation region 40, thereby modulating the electric field on the side of the isolation region 40, that is, forming an electric field at the side interface of the deep trench 44 to attract electrons to move to the side interface of the deep trench 44, further repairing the lattice defects at the side interface of the deep trench 44, thereby avoiding lateral breakdown caused by the formation of a lateral electric field on the side of the second doped region 30, and after the third electrode 63 is applied to the isolation region 40, it can modulate the surface potential, thereby reducing the dark counts generated by the single-photon avalanche diode of the embodiment of the present application during operation.

[0082] It is understandable that in the single-photon avalanche diode of the present application, the area where the third electrode 63 contacts the polysilicon 41 can be heavily doped to achieve ohmic contact and reduce on-resistance. This heavily doped area is not shown in the drawings.

[0083] And as Figure 8 As shown, in another embodiment of the present application, the isolation region 40 is constructed to be filled with a dielectric 42. Because the dielectric 42 has good insulation properties, the dielectric 42 within the isolation region 40 can effectively suppress the lateral electric field generated laterally outside the second doped region 30, ensuring that the edge region of the second doped region 30 is unlikely to generate a large lateral electric field, thereby ensuring that the carrier avalanche generated by the incident light occurs in the strong longitudinal electric field 91 region formed by the depletion region between the first doped region 20 and the second doped region 30. The dielectric 42 material may include silicon oxide, silicon nitride, and other materials, which are not limited here.

[0084] Further, such as Figure 9 As shown, in one embodiment of the present application, the isolation region 40 includes a high dielectric constant material film 43 located on the sidewalls and bottom wall of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40 .

[0085] Because the high-k dielectric film 43 is formed on the sidewalls and bottom of the isolation region 40, it can form fixed charges on the sidewalls and bottom of the isolation region 40. These fixed charges can also form an electric field at the side interface of the deep trench 44, repairing lattice defects at the side interface of the deep trench 44, thereby preventing the formation of a lateral electric field on the side of the second doped region 30 and causing lateral breakdown. The remaining isolation region 40 is then filled with dielectric 42, which can effectively suppress the generation of a lateral electric field laterally outside the second doped region 30.

[0086] It is understandable that the high dielectric constant material may include various materials and combinations such as aluminum oxide, hafnium oxide, and tantalum oxide, and is not limited here.

[0087] like Figure 2 As shown, in one embodiment of the present application, the single-photon avalanche diode of the present application further includes an oxide layer 50 , which is constructed to be located at least between the isolation region 40 and the interface between the first doped region 20 , the second doped region 30 , and the base layer 10 .

[0088] It is understood that to facilitate the deposition of polysilicon 41, high-k dielectric film 43, or dielectric 42 within deep trench 44, after etching deep trench 44 during the fabrication of the single-photon avalanche diode of the present application, a thin oxide layer can first be grown on the sides, bottom, and substrate of deep trench 44 using thermal oxidation or atomic layer deposition (ALD) to form a favorable interface state. Polysilicon 41, high-k dielectric film 43, or dielectric 42 can then be deposited on the oxide layer, and the excess removed to form the desired isolation region 40. The oxide layer has fewer interface defects with the polysilicon 41, high-k dielectric film 43, or substrate layer 10, helping to reduce the generation of recombination carriers due to interface defects, thereby effectively lowering the dark count rate of the single-photon avalanche diode of the present application. Furthermore, the oxide layer 50 also provides a certain insulating effect, helping to effectively suppress the lateral electric field generated laterally outside the second doped region 30.

[0089] like Figure 2 As shown, in one embodiment of the present application, the first doping region 20 and the second doping region 30 are configured to have equal dimensions along the horizontal direction. The equal horizontal dimensions of the first doping region 20 and the second doping region 30 refer to the first doping region 20 and the second doping region 30 having equal horizontal dimensions in all horizontal extension directions of the wafer where the single photon avalanche diode of the present application is located.

[0090] Since the horizontal extension dimensions of the first doped region 20 and the second doped region 30 are equal, an avalanche region with an area equal to the interface area between the first doped region 20 and the second doped region 30 can be formed between the first doped region 20 and the second doped region 30. The area of ​​the avalanche region can be expanded as much as possible while keeping the dimensions of other regions unchanged, thereby effectively improving the photoelectric detection efficiency of the single-photon avalanche diode of the present application.

[0091] like Figure 6As shown, in another embodiment of the present application, the second doped region 30 is constructed so that its edges extend beyond the horizontal edges of the first doped region 20, so as to align with the isolation region 40 located horizontally outward. That is, compared to the second doped region 30, the first doped region 20 has a smaller extension, with the central portion of the second doped region 30 aligning vertically with the first doped region 20, while the edge portion directly aligns with the base layer 10. Thus, compared to the PN junction between the first doped region 20 and the central region of the second doped region 30, the potential difference of the built-in electric field of the PN junction between the edge region of the second doped region 30 and the base layer 10 is smaller, and the internal electric field strength is also relatively low. As a result, composite carriers generated by lattice defects at the side interfaces of the isolation region 40 are less likely to drift to the central strong longitudinal electric field 91 region under the action of the small electric field at the edge. This significantly reduces the probability of composite carriers generated by lattice defects at the side interfaces of the isolation region 40 reaching the central avalanche region and triggering avalanche multiplication, thereby reducing the dark count rate of the single-photon avalanche diode of the present application.

[0092] During the fabrication of the single-photon avalanche diode of the present application, the above structure can be achieved by reducing the size of the first doping region 20 relative to the edge of the second doping region 30 during ion implantation. In one embodiment, the first doping region 20 can be reduced by 0.1 μm to 0.5 μm relative to the edge of the second doping region 30.

[0093] Similar, such as Figure 7 As shown, in one embodiment of the present application, the first doping region 20 includes a first central doping region 21 and a first edge doping region 22 located at the horizontal outer edge of the first central doping region 21 adjacent to the PN junction interface, and the net doping concentration of the first edge doping region 22 is constructed to be less than the net doping concentration of the first central doping region 21.

[0094] Since the net doping concentration of the first edge doping region 22 is less than the net doping concentration of the first middle doping region 21, the built-in potential difference in the edge region of the PN junction between the first doping region 20 and the second doping region 30 can be made smaller than the built-in potential difference in the middle region of the PN junction between the first doping region 20 and the second doping region 30, thereby making it difficult for the composite carriers generated by lattice defects at the side interface of the isolation region 40 to drift to the central strong longitudinal electric field 91 region under the action of the small electric field at the edge, thereby greatly reducing the probability of the composite carriers generated by lattice defects at the side interface of the isolation region 40 reaching the central avalanche region and causing avalanche multiplication, thereby reducing the dark count rate of the single-photon avalanche diode of the present application.

[0095] Similarly, the second doping region 30 includes a second central doping region 31 and a second edge doping region 32 located at the horizontal outer edge of the second central doping region 31 adjacent to the PN junction interface. The net doping concentration of the second edge doping region 32 is constructed to be less than the net doping concentration of the second central doping region 31. The principle is similar and is not limited here.

[0096] It can be understood that, since the built-in potential difference of the PN junction is proportional to the product of the net doping concentrations of the doping regions on both sides, in the following three cases, the net doping concentration of the first edge doping region 22 is less than the net doping concentration of the first central doping region 21 and the net doping concentration of the second edge doping region 32 is less than the net doping concentration of the second central doping region 31; or, the net doping concentration of the first edge doping region 22 is less than the net doping concentration of the first central doping region 21 and the net doping concentration of the second doping region 30 is uniform; or, the net doping concentration of the second edge doping region 32 is less than the net doping concentration of the second central doping region 31 and the net doping concentration of the first doping region 20 is uniform, in these three cases, the product of the net doping concentration of the first edge doping region 22 and the net doping concentration of the second edge doping region 32 is less than the product of the net doping concentration of the second central doping region 31 and the net doping concentration of the second central doping region 31.

[0097] The net doping concentration in the first edge doping region 22 is greater than the net doping concentration in the first central doping region 21, but the net doping concentration in the second edge doping region 32 is less than the net doping concentration in the second central doping region 31. The product of the net doping concentration in the first edge doping region 22 and the net doping concentration in the second edge doping region 32 can also be made smaller than the product of the net doping concentration in the second central doping region 31 and the net doping concentration in the second central doping region 31.

[0098] Similarly, the net doping concentration of the first edge doping region 22 is less than the net doping concentration of the first central doping region 21, but the net doping concentration of the second edge doping region 32 is greater than the net doping concentration of the second central doping region 31. The product of the net doping concentration of the first edge doping region 22 and the net doping concentration of the second edge doping region 32 can also be made less than the product of the net doping concentration of the second central doping region 31 and the net doping concentration of the second central doping region 31.

[0099] For the above two cases, it is only necessary to obtain Figure 2 After forming the first doping region 20 and the second doping region 30 shown in the figure, secondary doping is performed on the first edge doping region 22 and the second edge doping region 32 at the same time, wherein the doping type is the same as the one with higher net doping concentration in the first middle doping region 21 and the second middle doping region 31, thereby obtaining the above structure.

[0100] It is understandable that the existing detection units with single photon avalanche diodes are mostly lateral devices. For lateral devices, in order to facilitate the first electrode 61 and the second electrode 62 to conduct outward, the first electrode 61 and the second electrode 62 are both arranged at Figure 2 The upper side of the middle.

[0101] Therefore, if Figure 2 As shown, the single-photon avalanche diode of the present application further includes a third doped region 70 disposed horizontally outside the isolation region 40. The impurity concentration of the third doped region 70 is higher than the impurity concentration of the base layer 10, and the net doping type of the third doped region 70 is the same as the net doping type of the first doped region 20. The first electrode 61 is configured to be electrically connected to the third doped region 70. Because the impurity concentration of the third doped region 70 is higher than the impurity concentration of the base layer 10, and the net doping type of the third doped region 70 is the same as the net doping type of the first doped region 20, the on-resistance of the third doped region 70 can be effectively reduced, effectively ensuring the conduction performance of the single-photon avalanche diode of the present application.

[0102] It can be understood that the net doping concentration of the third doping region 70 can be lower than the net doping concentration of the base layer 10 to minimize the generation of a lateral electric field between the third doping region 70 and the side of the second doping region 30; of course, in one embodiment of the present application, the net doping concentration of the third doping region 70 can also be higher than the net doping concentration of the base layer 10.

[0103] It is understandable that Figure 2 The single-photon avalanche diode photoelectric detection device shown in the figure is formed on the same wafer as the quenching, reset, and protection devices. During the operation of the photoelectric detection device, photons are generated from Figure 2 The light is emitted downward from above into the single-photon avalanche diode to induce avalanche multiplication in the single-photon avalanche diode.

[0104] In order to improve the distribution efficiency of single photon avalanche diodes on the wafer, in one embodiment of the present application, as shown in FIG. Figure 10 As shown, the single-photon avalanche diode of the present application also includes a fourth doping region 80 located below the substrate layer 10, the impurity concentration of the fourth doping region 80 is higher than the impurity concentration of the substrate layer 10, and the net doping type of the fourth doping region 80 is the same as the net doping type of the first doping region 20; the first electrode 61 is configured to be directly electrically connected to the fourth doping region 80.

[0105] Right now Figure 10 The single photon avalanche diode is a vertical device, and the first electrode 61 and the second electrode 62 are respectively Figure 10A reverse bias voltage is applied to the PN junction at the upper and lower sides of the depletion region to form an avalanche region in the depletion region. Because the impurity concentration of the fourth doping region 80 is higher than the impurity concentration of the base layer 10, the on-resistance of the fourth doping region 80 can be effectively reduced. Specifically, because the fourth doping region 80 is located below the base layer 10, the net doping concentration of the fourth doping region 80 can be higher than the net doping concentration of the first doping region 20, or lower than the net doping concentration of the first doping region 20.

[0106] It is understandable that when Figure 10 When the single-photon avalanche diode is a vertical device, the single-photon avalanche diode array can be formed separately on a single wafer, and the active quenching structure, reset structure, and peripheral drive, control, signal processing and other circuits are located on another logic circuit wafer. The two are bonded to achieve pixel-level signal interconnection; each single-photon avalanche diode still requires a separate quenching resistor or protective resistor to quench or limit the avalanche current.

[0107] After bonding, the logic wafer is located Figure 10 In the single photon avalanche diode, during the operation of the photoelectric detection device, photons are generated from Figure 10 It is understood that in order to ensure that photons can pass through the substrate upward, the substrate can be thinned to a set thickness during the preparation process of the single-photon avalanche diode of the present application, so as to ensure that photons can pass through the substrate upward. Figure 10 The lower portion in the middle is injected upward into the single-photon avalanche diode to induce avalanche multiplication in the single-photon avalanche diode.

[0108] Combined with the above Figures 2 to 10 , describes in detail the device embodiment of the single photon avalanche diode of the present application, and the following is combined with Figures 11A to 17I , describes in detail the embodiment of the method for preparing the single photon avalanche diode of the present application. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, so the parts not described in detail can be referred to the previous device embodiment. Specifically, Figures 11A-11E Shown Figure 2 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 12A-12E Shown Figure 5 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 13A-13E Shown Figure 6 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 14A-14F Shown Figure 7 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 15A-15E Shown Figure 8 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 16A-16F Shown Figure 9 Schematic diagram of the preparation process of another single-photon avalanche diode; Figures 17A-17I Shown Figure 10 Schematic diagram of the preparation process of another single-photon avalanche diode.

[0109] like Figure 18 As shown, the present application also provides a method for preparing a single-photon avalanche diode, comprising:

[0110] Step S101: providing a substrate, and etching corresponding positions of the isolation regions 40 on the substrate to obtain a substrate having an annular deep groove 44.

[0111] It is understood that the substrate can be a silicon-based substrate, a germanium-based substrate, or a substrate formed of other materials. The semiconductor substrate can be a high-purity substrate or a doped substrate. For example, the semiconductor substrate can be an N-type substrate or a P-type substrate 11 formed by doping. The doping concentration of the semiconductor substrate can be various, and can be a lightly doped semiconductor substrate with a relatively low doping concentration, a medium-doped semiconductor substrate with a medium doping concentration, or a heavily doped semiconductor substrate with a relatively high doping concentration, without limitation herein.

[0112] Step S102: depositing corresponding materials at least in the annular deep trench 44 to form a substrate having an isolation region 40.

[0113] It is understandable that the corresponding material can be uniformly deposited on the substrate having the annular deep groove 44 , and then excess material can be removed by chemical mechanical polishing (CMP) or etch back to obtain the desired substrate having the isolation region 40 .

[0114] Step S103: performing ion implantation on the inner region of the isolation region 40 of the substrate to form at least a first doping region 20 and a second doping region 30.

[0115] Among them, the second doping region 30 is located above the first doping region 20, and the net doping types of the first doping region 20 and the second doping region 30 are opposite to each other, so as to form a PN junction between the two, and form depletion regions on both sides of the PN junction interface. The isolation region 40 is located outside the first doping region 20 and the second doping region 30 in the horizontal direction, and covers at least the area between the upper interface of the second doping region 30 and the lower interface of the first doping region 20 in the height direction.

[0116] Step S104: forming at least a first electrode 61 and a second electrode 62, wherein the first electrode 61 is electrically connected to the first doping region 20, and the second electrode 62 is directly electrically connected to the second doping region 30.

[0117] It is understandable that if Figures 11A-11C As shown, the depth and width of the isolation region 40 can be controlled by controlling the depth and width of the deep trench 44 formed after etching. It is understood that after the ion implantation process, laser annealing can be performed to repair the crystal lattice of the semiconductor material; laser annealing can also be performed after the process of forming the first electrode 61 and the second electrode 62 to form a good ohmic contact, which will not be repeated here.

[0118] In order to facilitate the deposition of corresponding materials in the annular deep groove 44, such as Figure 11B As shown, after obtaining a substrate with an annular deep groove 44, a thin oxide layer can be grown on the side, bottom and substrate of the deep groove 44 by thermal oxidation or atomic layer deposition (ALD) to form a good interface state; then polysilicon 41, a high dielectric constant material film 43 or a dielectric material 42 is deposited on the oxide layer, and then the excess part is removed to obtain the required isolation area 40.

[0119] like Figure 12D As shown, for Figure 5 In the PN-type single-photon avalanche diode shown in FIG, an N-type buried layer 12 needs to be formed and added during the ion implantation step to isolate the N-type first doped region 20 from the P-type substrate 11 .

[0120] like Figure 13D As shown, the width of the first doping region 20 can be adjusted during the ion implantation step to meet relevant structural requirements.

[0121] like Figure 14E As shown, in order to obtain the desired first edge doping region 22 and / or second edge doping region 32 structure, in the ion implantation step, Figure 14D After forming the first doping region 20 and the second doping region 30 as shown in FIG, secondary doping is performed on the first edge doping region 22 and the second edge doping region 32 at the same time to obtain a corresponding structure.

[0122] like Figure 13C As shown, for a single-photon avalanche diode in which polysilicon 41 is deposited in an isolation region 40, polysilicon 41 is uniformly deposited on a substrate having an annular deep groove 44, and then excess polysilicon 41 is removed to obtain a corresponding structure in which polysilicon 41 is deposited in the isolation region 40; then, in the step of forming the first electrode 61 and the second electrode 62, a third electrode 63 can be formed simultaneously so that the third electrode 63 can contact outward, thereby facilitating the third electrode 63 to apply a voltage of the same polarity as the first electrode 61 to the isolation region 40.

[0123] like Figure 15CAs shown, for a single-photon avalanche diode with a dielectric 42 deposited in an isolation region 40 , it is only necessary to uniformly deposit the corresponding dielectric 42 material on a substrate having an annular deep groove 44 , and then remove the excess dielectric 42 to obtain a corresponding structure with the dielectric 42 deposited in the isolation region 40 .

[0124] like Figure 16C and Figure 16D As shown, for a single-photon avalanche diode in which the isolation region 40 includes a high-dielectric-constant material film 43 located on the side walls and bottom walls of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40, a layer of high-dielectric-constant material film 43 can be uniformly deposited in a substrate having an annular deep groove 44 by atomic layer deposition, and then the corresponding dielectric 42 material is uniformly deposited on top thereof, and then the excess dielectric 42 is removed, so as to obtain a corresponding structure in which the isolation region 40 includes a high-dielectric-constant material film 43 located on the side walls and bottom walls of the isolation region 40 and a dielectric 42 filling the remaining isolation region 40.

[0125] like Figure 11D As shown, for a lateral single-photon avalanche diode, it is only necessary to form the third doping region 70 during the ion implantation step, and then form the first electrode 61 electrically connected to the third doping region 70 on the third doping region 70 .

[0126] like 17D to 17I As shown, for a vertical single-photon avalanche diode, Figure 17E After the corresponding structure is formed, the structure outside the isolation region 40 needs to be removed. Then, after the wafer where the single photon avalanche diode is located is bonded to another logic circuit wafer, the substrate portion is thinned. Then, the fourth doped region 80 and the first electrode 61 are formed on the back of the substrate by ion implantation, thereby obtaining Figure 17I Single photon avalanche diode structure in .

[0127] The present application also provides a photoelectric detection device, which includes the aforementioned single-photon avalanche diode, and the photoelectric detection device is configured to obtain relevant information by sensing the electrical signal generated corresponding to the light signal received by the single-photon avalanche diode.

[0128] Specifically, the photoelectric detection device is used to emit sensing light pulses to an external object, receive sensing light pulses returned by the external object, and convert the sensing light pulses into corresponding electrical signals, which are used to obtain corresponding sensing information. For example, but not limited to, the electrical signal is used to obtain one or more of the proximity information, depth information, or distance information of the external object. Among them, depth information is used, for example, in 3D modeling, face recognition, autonomous driving, SLAM and other fields, which is not limited in this application. Proximity information is used, for example, to determine whether an object is approaching.

[0129] Specifically, the photoelectric detection device includes a transmitting module, a receiving module, and a processing circuit. The transmitting module is configured to transmit sensing light pulses into the space surrounding an external object. At least a portion of the transmitted sensing light pulses returns from the external object to form sensing light pulses, and at least a portion of the sensing light pulses is received by the receiving module. The returned sensing light pulses, for example, carry depth information of the external object.

[0130] The emission module may include a light-emitting component and an emission optical component. The light-emitting component is used to emit sensing light pulses. The emission optical component is used to modulate the sensing light pulses emitted by the light-emitting component to form the sensing light pulses required for sensing and project the sensing light pulses into the detection space.

[0131] The photosensor includes a pixel array composed of multiple pixel units. Each pixel unit may include one or more photoelectric conversion devices to sense the sensing light signal reflected by the external object and output a corresponding electrical signal to determine the flight time of the light pulse in space, thereby determining the distance information of the external object. The photoelectric conversion device is the aforementioned single-photon avalanche photodiode, which means that the photosensor is a SPAD array chip.

[0132] The receiving module may also include a readout circuit composed of one or more of a signal amplifier, a time-to-digital converter (TDC), an analog-to-digital converter (ADC), and other devices connected to the photosensor to pre-process the electrical signal output by the photoelectric conversion device. The receiving module may also include a receiving optical component for receiving sensing light pulses returned from an external object and transmitting the sensing light pulses to the corresponding pixel unit.

[0133] The processing circuit is used to determine the distance information of the external object based on the time difference between the emitted sensing light pulse and the received return sensing light pulse, thereby enabling the photoelectric detection device to realize the three-dimensional imaging function of the external object. In other embodiments, the processing circuit can also obtain relevant sensing information based on the sensing light pulse and other suitable detection principles, and is not limited to determining the relevant sensing information based on the time difference between the emitted sensing light pulse and the received return sensing light pulse. The processing circuit can be set on the photoelectric detection device, and can also be set on an electronic device that includes the photoelectric detection device, for example, on the main control circuit of the electronic device, and the embodiments of the present application are not limited thereto.

[0134] An embodiment of the present application further provides an electronic device, which includes the photoelectric detection device described above. The electronic device can perform corresponding functions based on relevant information obtained by sensing electrical signals by the photoelectric detection device.

[0135] Specifically, the electronic device may include an application module configured to execute preset operations or implement corresponding functions based on the detection results of the photoelectric detection device. For example, but not limited to: determining whether an external object appears within a preset detection range in front of the electronic device based on the proximity information of the external object; or controlling the movement of the electronic device to avoid obstacles based on the distance information of the external object; or implementing 3D modeling, facial recognition, machine vision, etc. based on the depth information of the external object's surface. The electronic device may also include a storage medium to support the storage needs of the photoelectric detection device during operation, and one or more processors to execute to control related components to implement corresponding functions.

[0136] It is understood that the corresponding functions include, but are not limited to, unlocking after identifying the user's identity, making payments, launching preset applications, avoiding obstacles, and using deep learning technology to determine the user's emotions and health status after recognizing the user's facial expressions. The electronic device may be, for example, but not limited to, suitable electronic products such as consumer electronics, home electronics, smart mobile tools, and financial terminal products. Among them, consumer electronics products include, but are not limited to, mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include, but are not limited to, smart door locks, televisions, refrigerators, and wearable devices. Smart mobile tools include, but are not limited to, cars, robots, and unmanned delivery vehicles. Financial terminal products include, but are not limited to, ATMs and self-service terminals.

[0137] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0138] Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this application is defined by the appended claims.

Claims

1. A single photon avalanche diode, characterized in that: include: basal layer (10); A first doping region (20) and a second doping region (30), wherein the first doping region (20) is located above the base layer (10), and the second doping region (30) is located above the first doping region (20), and the first doping region (20) and the second doping region (30) have opposite net doping types, so as to form a PN junction between the two, and form depletion regions on both sides of the PN junction interface; an isolation region (40), the isolation region (40) being attached to the outer sides of the first doping region (20) and the second doping region (30) in a horizontal direction, and being constructed to cover at least the region between the upper interface of the second doping region (30) and the lower interface of the first doping region (20) in a height direction; A first electrode (61) and a second electrode (62), wherein the first electrode (61) is electrically connected to the first doping region (20), and the second electrode (62) is electrically connected to the second doping region (30), a connection region between the first electrode (61) and the first doping region (20) and a connection region between the second electrode (62) and the second doping region (30) form a heavily doped region, and the first electrode (61) and the second electrode (62) are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region.

2. The single photon avalanche diode according to claim 1, characterized in that The isolation region (40) is constructed to be filled with polysilicon (41).

3. The single photon avalanche diode according to claim 2, characterized in that: The single-photon avalanche diode further includes a third electrode (63), wherein the third electrode (63) is electrically connected to the isolation region (40) to apply a voltage to the isolation region (40).

4. The single photon avalanche diode according to claim 1, characterized in that The isolation region (40) is configured to be filled with a dielectric (42).

5. The single photon avalanche diode according to claim 1, characterized in that The isolation region (40) includes a high dielectric constant material film (43) located on the sidewalls and bottom wall of the isolation region (40) and a dielectric (42) filling the remaining isolation region (40).

6. The single photon avalanche diode according to claim 1, characterized in that Also includes: An oxide layer (50) is constructed to be located at least between the isolation region (40) and the interface between the first doping region (20), the second doping region (30), and the base layer (10).

7. The single photon avalanche diode according to claim 1, characterized in that The first doping region (20) and the second doping region (30) are constructed to have equal dimensions extending in a horizontal direction.

8. The single photon avalanche diode according to claim 1, characterized in that The second doping region (30) is constructed so that its edges all extend beyond the horizontal edge of the first doping region (20) so as to respectively fit with the isolation region (40) on the outside in the horizontal direction.

9. The single photon avalanche diode according to claim 1, characterized in that: The first doping region (20) comprises a first central doping region (21) and a first edge doping region (22) located at an outer edge of the first central doping region (21) adjacent to the PN junction interface in a horizontal direction, wherein the net doping concentration of the first edge doping region (22) is configured to be less than the net doping concentration of the first central doping region (21); and / or, The second doping region (30) comprises a second central doping region (31) and a second edge doping region (32) located at an outer edge of the second central doping region (31) in a horizontal direction adjacent to the PN junction interface, wherein the net doping concentration of the second edge doping region (32) is configured to be less than the net doping concentration of the second central doping region (31).

10. The single photon avalanche diode according to any one of claims 1 to 9, characterized in that: It also includes a third doping region (70) arranged in a ring outside the isolation region (40) in a horizontal direction, the impurity concentration of the third doping region (70) being higher than the impurity concentration of the base layer (10), and the net doping type of the third doping region (70) being the same as the net doping type of the first doping region (20); The first electrode (61) is configured to be electrically connected to the third doping region (70).

11. The single photon avalanche diode according to any one of claims 1 to 9, characterized in that: It also includes a fourth doping region (80) located below the base layer (10), the impurity concentration of the fourth doping region (80) being higher than the impurity concentration of the base layer (10), and the net doping type of the fourth doping region (80) being the same as the net doping type of the first doping region (20); The first electrode (61) is configured to be electrically connected to the fourth doping region (80).

12. The single photon avalanche diode according to any one of claims 1 to 9, characterized in that: The net doping type of the first doping region (20) is P-type, the net doping type of the second doping region (30) is N-type, and the base layer (10) is a P-type substrate (11).

13. The single photon avalanche diode according to any one of claims 1 to 9, characterized in that: The net doping type of the first doping region (20) is N-type, the net doping type of the second doping region (30) is P-type, and the base layer (10) comprises an N-type buried layer (12) and a P-type substrate (11) located below the N-type buried layer (12).

14. A photoelectric detection device, characterized in that: Comprising the single-photon avalanche diode according to any one of claims 1 to 13, the photoelectric detection device is configured to obtain relevant information by sensing the electrical signal generated corresponding to the light signal received by the single-photon avalanche diode.

15. An electronic device, characterized in that: The electronic device comprises the photoelectric detection device as claimed in claim 14, and is configured to execute corresponding functions according to relevant information obtained by sensing electrical signals by the photoelectric detection device.

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