Decision feedback equalizer with number of comparators in PAM-4 decoder minimized and operating method thereof

Abstract

To provide a decision feedback equalizer whose number of comparators in a PAM-4 decoder is minimized and an operating method thereof.SOLUTION: A decision feedback equalizer includes: an adder that receives a PAM-4 signal based on a gray code and first and second bit signals, and outputs an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first and second bit signals; and a decoder that receives the input voltage and first to third reference voltages of the PAM-4 signal, and outputs the first and second bit signals. The decoder may include a first comparator that compares the magnitude of the input voltage with that of the first reference voltage to output the first bit signal, and a second comparator that compares the charge draining intensity of the input voltage with that of the second and third reference voltages to output the second bit signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a decision feedback equalizer that minimizes the number of comparators in a PAM-4 decoder and a method of operating the same. [Background technology]

[0002] Recently, as the transmission speed of wired transceivers increases, the hardware cost for transmitting high-speed clocks to the entire chip increases, and at the same time, power consumption increases. Therefore, transceivers require technology using a multi-phase architecture to process the huge amount of data signals transmitted at high speed.

[0003] For this purpose, the transceiver may include a continuous time linear equalizer, a decision feedback equalizer, etc. However, there is a problem that the power consumption in the data and clock paths increases due to the increased number of comparators in the decoder, and the bandwidth is limited at the same time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Republic of Korea Patent No. 10-1872310 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a decision feedback equalizer and an operating method thereof that minimizes the number of comparators in a PAM-4 decoder. [Means for solving the problem]

[0006] The present invention includes an adder that receives a PAM-4 signal based on a Gray code and first and second bit signals, and outputs an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first and second bit signals, and a decoder that receives the input voltage and first to third reference voltages of the PAM-4 signal and outputs the first and second bit signals, the decoder including a first comparator that compares the magnitude of the input voltage with the first reference voltage to output the first bit signal, and a second comparator that compares the charge draining strength of the input voltage with the second and third reference voltages to output the second bit signal.

[0007] In one embodiment of the present invention, the second comparator can output the second bit signal to 0 when the input voltage is greater than the second reference voltage and less than the third reference voltage, and can output the second bit signal to 1 when the input voltage is less than the second reference voltage and greater than the third reference voltage.

[0008] In an embodiment of the present invention, the adder may include a first tab for outputting an odd signal of the input voltage using odd bits of the first and second bit signals, and a second tab for outputting an even signal of the input voltage using even bits of the first and second bit signals.

[0009] In one embodiment of the present invention, the adder can add a first coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 1 and 0, respectively, add a second coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 1 and 1, respectively, add a third coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 0 and 1, respectively, and add a fourth coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 0 and 0, respectively.

[0010] In one embodiment of the present invention, the decision feedback equalizer may further include a continuous-time linear equalizer that receives a data signal and uniformly equalizes all frequency components of the data signal to output the PAM-4 signal, a variable gain amplifier that receives the PAM-4 signal and amplifies an interval between a voltage level of the PAM-4 signal and the first to third reference voltages, and a compensation circuit that maintains a common mode of the adder constant.

[0011] The present invention provides a method for operating a decision feedback equalizer, comprising the steps of: receiving a PAM-4 signal based on a Gray code and first and second bit signals, and outputting an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first and second bit signals; and receiving the input voltage and first to third reference voltages for the PAM-4 signal, and outputting the first and second bit signals, wherein the step of outputting the first and second bit signals includes the steps of comparing the magnitude of the input voltage with the first reference voltage to output the first bit signal, and comparing the charge drain strength of the input voltage with the second and third reference voltages to output the second bit signal.

[0012] In one embodiment of the present invention, the step of outputting the second bit signal may include outputting the second bit signal as 0 when the input voltage is greater than the second reference voltage and less than the third reference voltage, and outputting the second bit signal as 1 when the input voltage is less than the second reference voltage and greater than the third reference voltage.

[0013] In an embodiment of the present invention, the step of outputting the input voltage may include the steps of outputting an odd signal of the input voltage using odd bits of the first and second bit signals, and outputting an even signal of the input voltage using even bits of the first and second bit signals.

[0014] In one embodiment of the present invention, the step of outputting the input voltage may include adding a first coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 1 and 0, respectively, adding a second coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 1 and 1, respectively, adding a third coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 0 and 1, respectively, and adding a fourth coefficient to the voltage level of the PAM-4 signal when the first and second bit signals are 0 and 0, respectively.

[0015] In one embodiment of the present invention, the method of operating the decision feedback equalizer may further include the steps of receiving a data signal, uniformly equalizing all frequency components of the data signal, and outputting the PAM-4 signal, receiving the PAM-4 signal, amplifying intervals between a voltage level of the PAM-4 signal and the first, second, and third reference voltages, and maintaining a common mode of the steps of outputting the input voltage constant. Effect of the Invention

[0016] According to the present invention, a decision feedback equalizer that minimizes the number of comparators in a decoder can be realized by minimizing the number of comparators in a decoder and using an RZ signal. Therefore, the present invention can reduce the power consumption of the entire circuit and reduce the feedback loop delay. [Brief description of the drawings]

[0017] [Figure 1] 1 is a block diagram illustrating a decision feedback equalizer according to an embodiment of the present invention. [Diagram 2] 4 is a diagram illustrating first to third reference voltages of a PAM-4 signal according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a block diagram illustrating an example of a comparator according to an embodiment of the present invention. [Figure 4A] FIG. 2 is a circuit diagram illustrating an example of a comparator according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a circuit diagram illustrating an example of a comparator according to an embodiment of the present invention. [Diagram 5] FIG. 2 is a circuit diagram illustrating an example of an adder according to an embodiment of the present invention. [Figure 6] FIG. 13 is a block diagram showing another embodiment of a decision feedback equalizer. [Figure 7] 4 is a flow diagram of the operation of a decision feedback equalizer according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the embodiments of the present invention are described clearly and in detail to such an extent that those skilled in the art can easily practice the present invention. FIG. 1 is a block diagram illustrating a decision feedback equalizer according to an embodiment of the present invention.

[0019] A decision feedback equalizer (10) according to an embodiment of the present invention may be implemented in a receiving device that receives a PAM-4 (4-Level Plus Amplitude Modulation) signal in Gray Code. For example, the decision feedback equalizer 10 may be implemented in a receiving device of various devices such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable device, a video game console, a home appliance, a medical device, etc. More specifically, referring to FIG. 1, a decision feedback equalizer 10 according to an embodiment of the present invention includes a summer 100 and a decoder 200 .

[0020] The adder 100 receives a PAM-4 signal based on the Gray code and first and second bit signals, and can output an input voltage obtained by adding a preset coefficient to the voltage level of the PAM-4 signal in response to the first and second bit signals.

[0021] The decoder 200 receives an input voltage and first to third reference voltages of the PAM-4 signal and outputs first and second bit signals. To this end, the decoder 200 includes a first comparator 210 and a second comparator 220.

[0022] The first comparator 210 can compare the magnitude of the input voltage and the first reference voltage and output a first bit signal as 0 or 1. For example, the first comparator 210 can output the first bit signal as 1 if the input voltage is greater than the first reference voltage, and can output the first bit signal as 0 if the input voltage is less than the first reference voltage.

[0023] The second comparator 220 can compare the input voltage with the charge draining strength of the second and third reference voltages to output a second bit signal of 0 or 1. For example, if the input voltage is greater than the second reference voltage and less than the third reference voltage, the second comparator 220 can output the second bit signal of 0, and if the input voltage is less than the second reference voltage and greater than the third reference voltage, the second comparator 220 can output the second bit signal of 1. A more detailed description of the first and second comparators 210 and 220 will be described with reference to Figures 4A and 4B.

[0024] As described above, the decision feedback equalizer 10 according to the embodiment of the present invention can decode data through the first and second comparators 210 and 220 of the decoder 200, and the decoder 200 can feed back the first and second bit signals, which are return-to-zero (RZ) data, to the adder 100. Therefore, the decoder 200 can reduce the feedback loop delay of the decoder 200 by omitting an additional process of converting the data into non-return-to-zero (NRZ) data.

[0025] FIG. 2 is a diagram illustrating first to third reference voltages of a PAM-4 signal according to an embodiment of the present invention. Referring to FIG. 2, the lowest first level of the PAM-4 signal may be mapped to 2-bit data '00', and the highest fourth level of the PAM-4 signal may be mapped to 2-bit data '10'. The second level of the PAM-4 signal may be mapped to 2-bit data '01', and the third level of the PAM-4 signal may be mapped to 2-bit data '11'. Furthermore, the first reference voltage VREF of the PAM-4 signal may be a voltage level between the second and third levels, the second reference voltage VREFP of the PAM-4 signal may be a voltage level between the third and fourth levels, and the third reference voltage VREFN of the PAM-4 signal may be a voltage level between the first and second levels. The above-mentioned mapping of the first to fourth levels and data is based on the Gray code scheme, which is merely an example, and the mapping may be changed according to various purposes.

[0026] FIG. 3 is a block diagram illustrating an example of a comparator according to an embodiment of the present invention. 3, the decoder 200 can implement an even path and an odd path to decode a first bit signal (Most Significant Bit, MSB) and a second bit signal (Least Significant Bit, LSB). Meanwhile, the even path and the odd path of the decoder 200 are the same path except for the difference in bit signals. Therefore, the odd path will be representatively described below for convenience of explanation.

[0027] The first comparator 210 of the odd path may output first odd bit signals MSB_ODD and MSBB_ODD for the input voltages VINP and VINN in response to the odd clock signal CLK_ODD.

[0028] The second comparator 220 of the odd path may output second odd bit signals LSB_ODD and LSBB_ODD for the input voltages VINP and VINN in response to the odd clock signal CLK_ODD.

[0029] The decoder 200 may feed back the first odd bit signals MSB_ODD, MSBB_ODD and the second odd bit signals LSB_ODD, LSBB_ODD to the adder 100. In addition, the decoder 200 may convert the first odd bit signals MSB_ODD, MSBB_ODD and the second odd bit signals LSB_ODD, LSBB_ODD through the SR latch 230 to output odd decoded signals MSB_ODD_SR, LSB_ODD_SR.

[0030] As described above, the decoder 200 according to an embodiment of the present invention can distinguish between odd and even paths for bit signals to facilitate intuitive bit value representation and signal restoration of a PAM-4 signal.

[0031] 4A and 4B are circuit diagrams showing an example of a comparator according to an embodiment of the present invention. FIG. 4A is a circuit diagram showing an example of a first comparator 210, and FIG. 4B is a circuit diagram showing an example of a second comparator 220. Referring to FIG. 4A, the first comparator 210 may be implemented with a first input terminal 211, a second input terminal 212, and a first output terminal 213. For example, the first input terminal 211 may include a plurality of transistors to which a positive input voltage VINP and a first reference voltage VREF are applied to each gate, and the second input terminal 212 may include a plurality of transistors to which a negative input voltage VINN and a first reference voltage VREF are applied to each gate. More specifically, the first comparator 210 may perform a comparison operation by turning on a first transistor TR1 through a common signal. The first comparator 210 may receive a positive input voltage VINP and a first reference voltage VREF at the first input terminal 211. In addition, the first comparator 210 may receive a negative input voltage VINN and a first reference voltage VREF at a second input terminal 212. The first comparator 210 may compare received information at the first input terminal 211 and the second input terminal 212 and output a first bit signal MSB of 0 or 1 through a first output terminal 213. For example, the first comparator 210 may output the first bit signal MSB as 1 when the input voltages VINP, VINN are greater than the first reference voltage VREF, and may output the first bit signal MSB as 0 when the input voltages VINP, VINN are less than the first reference voltage VREF.

[0032] 4B, the second comparator 220 may be implemented with a third input terminal 221, a fourth input terminal 222, and a second output terminal 223. For example, the third input terminal 221 may include a plurality of transistors to which a positive input voltage VINP and a negative input voltage VINN are applied to each gate, and the fourth input terminal 222 may include a plurality of transistors to which a second reference voltage VREFP and a third reference voltage VREFN are applied to each gate. More specifically, the second comparator 220 may perform a comparison operation by turning on the second transistor TR2 through a common signal. The second comparator 220 may receive the positive input voltage VINP and the negative input voltage VINN at the third input terminal 221. Also, the second comparator 220 may receive the second reference voltage VREFP and the third reference voltage VREFN at the fourth input terminal 222. The second comparator 220 can compare the received information of the third input terminal 221 and the fourth input terminal 222 and output a second bit signal LSB of 0 or 1 through the second output terminal 223 .

[0033] More specifically, the second comparator 220 can compare different charge draining intensities of the third input terminal 221 and the fourth input terminal 222 to output the second bit signal as 0 or 1. For example, when the input voltages VINP, VINN are greater than the second reference voltage VREFP and less than the third reference voltage VREFN, the second comparator 220 can output the second bit signal LSB as 0. Also, when the input voltages VINP, VINN are less than the second reference voltage VREFP and greater than the third reference voltage VREFN, the second comparator 220 can output the second bit signal LSB as 1.

[0034] As described above, the decoder 200 according to an embodiment of the present invention can output a first bit signal MSB by comparing the magnitude of the input voltages VINP, VINN with the first reference voltage VREF, and can output a second bit signal LSB by comparing the charge drain strength of the input voltages VINP, VINN with the second and third reference voltages VREFP, VREFN. Therefore, the decoder 200 can minimize the number of comparators that output the first and second bit signals MSB, LSB, and can implement a 1-stage structure that can perform a decision feedback equalization operation.

[0035] FIG. 5 is a circuit diagram showing an example of an adder according to an embodiment of the present invention. 5, the adder 100 can output input voltages VINP and VINN obtained by adding the first through fourth coefficients to the voltage level of the PMA-4 signal in response to the first and second bit signals MSB and LSB. To this end, the adder 100 includes a first tab 110 and a second tab 120. Meanwhile, the first tab 110 and the second tab 120 of the adder 100 are identical circuits, with only differences in the bit signals. Therefore, in the following description, the first tab 110 will be representatively described for ease of explanation.

[0036] The first input terminal 110 may output even signals of input voltages VINP and VINN obtained by adding first to fourth coefficients to the voltage level of the PAM-4 signal using the first and second even bit signals MSB_EVEN and LSB_EVEN. For example, the first input terminal 110 may include a plurality of transistors to which the first and second even bit signals MSB_EVEN and LSB_EVEN and the operating voltages V1 and V2 are applied, respectively.

[0037] According to an embodiment of the present invention, the first tab 110 may add a first coefficient to the voltage level of the PAM-4 signal when the first and second even bit signals MSB_EVEN, LSB_EVEN are 1 and 0, respectively, and may add a second coefficient to the voltage level of the PAM-4 signal when the first and second even bit signals MSB_EVEN, LSB_EVEN are 1 and 1, respectively. Also, the first tab 110 may add a third coefficient to the voltage level of the PAM-4 signal when the first and second even bit signals MSB_EVEN, LSB_EVEN are 0 and 1, respectively, and may add a fourth coefficient to the voltage level of the PAM-4 signal when the first and second odd bit signals MSB_EVEN, LSB_EVEN are 0 and 0, respectively. Here, the first to fourth coefficients added to the voltage level of the PAM-4 signal may be, but are not limited to, +3, +1, -1, and -3, respectively.

[0038] FIG. 6 is a block diagram illustrating another embodiment of a decision feedback equalizer. Specifically, Fig. 6 illustrates an example further including a continuous-time linear equalizer 300, a variable gain amplifier 400, and a compensation circuit 500. The configuration of Fig. 6 other than the above-mentioned configuration is similar to that of Fig. 5. Therefore, the same or similar components are indicated by the same or similar reference numerals, and duplicated descriptions will be omitted below. Referring to FIG. 6, the decision feedback equalizer 10A may further include a continuous-time linear equalizer 300, a variable gain amplifier 400, and a compensation circuit 500.

[0039] The continuous-time linear equalizer 300 receives a data signal from a transmitter, amplifies the size of high-frequency components of the data signal, and generates a PAM-4 signal in which all frequency components of the data signal are uniformly equalized. For example, the continuous-time linear equalizer 300 receives a data signal capable of expressing four data values ​​00, 01, 10, and 11, and performs a sample / hold operation to equalize the data signal.

[0040] The variable gain amplifier 400 receives the PAM-4 signal from the continuous-time linear equalizer 300 and amplifies the interval between the voltage level of the PAM-4 signal and the first to third reference voltages. For example, the variable gain amplifier 400 can adjust the voltage gain using a variable gain control signal R_CONT that controls a variable resistor.

[0041] The compensation circuit 500 can maintain a constant common mode. For example, the decision feedback equalizer 10A reduces the common mode of the entire circuit due to the adder 100 where charge is drained. Therefore, the compensation circuit 500 can maintain a constant common mode of the entire circuit by pulling up the current applied to the adder 100 using a plurality of PMOS transistors. For example, the compensation circuit 500 can include a plurality of PMOS transistors connected to a plurality of transistors of the first tube 110.

[0042] As described above, the decision feedback equalizer 10A can facilitate the measurement of the voltage level of the PAM-4 signal and the first through third reference voltages without changing the operating range of the circuit.

[0043] FIG. 7 is a flow chart illustrating the operation of a decision feedback equalizer according to an embodiment of the present invention. Referring to FIG. 7, in step S110, the adder 100 may output input voltages VINP and VINN obtained by adding a preset coefficient to the voltage level of the PAM-4 signal in response to the first and second bit signals MSB and LSB.

[0044] In step S120, the first comparator 210 of the decoder 200 may compare the magnitudes of the input voltages VINP and VINN with the first reference voltage VREF to output a first bit signal MSB.

[0045] In step S130, the second comparator 220 of the decoder 200 may compare the charge draining strengths of the input voltages VINP and VINN with the second and third reference voltages VREFP and VREFN to output a second bit signal LSB.

[0046] In operation S140 , the decoder 200 may output the first and second bit signals MSB and LSB, which are RZ data, as even and odd signals, and input the output bit signals to the adder 100 .

[0047] The above is a specific embodiment for carrying out the present invention. In addition to the above-described embodiment, the present invention also includes embodiments that can be simply modified or easily modified. The present invention also includes techniques that can be easily modified using the embodiment. Therefore, the scope of the present invention should not be limited to the above-described embodiment, but should be defined by the following claims as well as equivalents to the claims of the present invention.

[0048] This study was supported by the National Research Foundation of Korea (NRF) GRANT (No. NRF-RS-2023-0281047), funded by the South Korean government. [Explanation of symbols]

[0049] 10 Decision Feedback Equalizer 100 Adder 110 First Tab 200 Decoder 120 Second Tab 300 Continuous-Time Linear Equalizer 210 First comparator 400 Variable Gain Amplifier 220 Second comparator 500 compensation circuit

Claims

1. an adder that receives a PAM-4 signal based on a Gray code and first and second bit signals, and outputs an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first and second bit signals; a decoder for receiving the input voltage and first to third reference voltages of the PAM-4 signal and outputting the first and second bit signals; The decoder comprises: a first comparator that compares the magnitude of the input voltage with the first reference voltage to output the first bit signal; a second comparator for comparing the input voltage with the charge draining intensities of the second and third reference voltages and outputting the second bit signal.

23. A decision feedback equalizer comprising:

2. The second comparator is If the input voltage is greater than the second reference voltage and less than the third reference voltage, outputting the second bit signal as 0; If the input voltage is smaller than the second reference voltage and larger than the third reference voltage, the second bit signal is output as 1.

2. The decision feedback equalizer of claim 1.

3. The adder is a first tab for outputting an odd signal of the input voltage using odd bits of the first and second bit signals; a second tab for outputting an even number signal of the input voltage using an even number bit of the first and second bit signals.

2. The decision feedback equalizer of claim 1.

4. The adder is adding a first coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 1 and 0, respectively; adding a second coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 1 and 1, respectively; adding a third coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 0 and 1, respectively; If the first and second bit signals are 0 and 0, respectively, a fourth coefficient is added to the voltage level of the PAM-4 signal.

2. The decision feedback equalizer of claim 1.

5. The decision feedback equalizer comprises: a continuous-time linear equalizer for receiving a data signal and uniformly equalizing all frequency components of the data signal to output the PAM-4 signal; a variable gain amplifier for receiving the PAM-4 signal and amplifying an interval between a voltage level of the PAM-4 signal and the first, second, and third reference voltages; a compensation circuit for maintaining the common mode of the adder constant.

2. The decision feedback equalizer of claim 1.

6. A method of operating a decision feedback equalizer, comprising: receiving a PAM-4 signal based on a Gray code and first and second bit signals, and outputting an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first and second bit signals; receiving the input voltage and first through third reference voltages of the PAM-4 signal, and outputting the first and second bit signals; The step of outputting the first and second bit signals comprises: comparing the magnitude of the input voltage with the first reference voltage to output the first bit signal; and comparing the input voltage with the charge draining strengths of the second and third reference voltages to output the second bit signal.

23. A method of operating a decision feedback equalizer comprising:

7. The step of outputting the second bit signal comprises: If the input voltage is greater than the second reference voltage and less than the third reference voltage, outputting the second bit signal as 0; If the input voltage is smaller than the second reference voltage and larger than the third reference voltage, the second bit signal is output as 1.

7. A method of operating a decision feedback equalizer as claimed in claim 6.

8. The step of outputting the input voltage comprises: outputting an odd signal of the input voltage using odd bits of the first and second bit signals; and outputting an even number signal of the input voltage using an even number bit of the first and second bit signals.

7. A method of operating a decision feedback equalizer as claimed in claim 6.

9. The step of outputting the input voltage comprises: adding a first coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 1 and 0, respectively; adding a second coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 1 and 1, respectively; adding a third coefficient to a voltage level of the PAM-4 signal when the first and second bit signals are 0 and 1, respectively; If the first and second bit signals are 0 and 0, respectively, a fourth coefficient is added to the voltage level of the PAM-4 signal.

7. A method of operating a decision feedback equalizer as claimed in claim 6.

10. The method of operating the decision feedback equalizer comprises: receiving a data signal and uniformly equalizing all frequency components of the data signal to output the PAM-4 signal; receiving the PAM-4 signal and amplifying an interval between a voltage level of the PAM-4 signal and the first through third reference voltages; and maintaining a common mode of the step of outputting the input voltage constant.

7. A method of operating a decision feedback equalizer as claimed in claim 6.

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