Image sensing device and distance sensing method

Abstract

To provide an image sensing device capable of sensing the distance to a target object.SOLUTION: An image sensing device 100 according to an embodiment of the present invention may include a first pixel PX1 including a first SPAD (single photon avalanche diode) having a first bias voltage applied to its cathode, a second pixel PX2 including a second SPAD having a second bias voltage applied to its anode, and a selection circuit for selecting one of the first pixel PX1 and the second pixel PX2.SELECTED DRAWING: Figure 4a

Description

[Technical field]

[0001] The present disclosure relates to an image sensing device and a distance sensing method capable of sensing the distance to a target object. [Background technology]

[0002] Image sensing devices are devices that capture optical images using the properties of light-sensitive semiconductor materials that react to light. With the development of industries such as automobiles, medicine, computers, and communications, there is an increasing demand for high-performance image sensing devices in various fields such as smartphones, digital cameras, game consoles, the Internet of Things, robots, security cameras, and medical micro cameras.

[0003] In recent years, image sensing devices have been actively used not only to obtain color images but also to sense the distance to a target object. In particular, the D-ToF (Direct time of flight) method, which directly or indirectly measures the time it takes for irradiated light to reflect off the target object and reach it, is widely used. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical idea of ​​the present invention provides an image sensing device and a distance sensing method that can operate in a mode suitable for the photographing conditions.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] An image sensing device according to one embodiment of the present invention disclosed in this document may include a first pixel including a first SPAD (single photon avalanche diode) having a first bias voltage applied to a cathode, a second pixel including a second SPAD having a second bias voltage applied to an anode, and a selection circuit for selecting one of the first pixel and the second pixel.

[0007] An image sensing device according to another embodiment of the present invention may include a first pixel including a first SPAD having a first sensitivity, a second pixel including a second SPAD having a second sensitivity higher than the first sensitivity, and a selection circuit for selecting one of the first pixel and the second pixel.

[0008] An image sensing device according to another embodiment of the present invention may include a first pixel including a first SPAD activated at a first illuminance, a second pixel including a second SPAD activated at a second illuminance lower than the first illuminance, and a selection circuit that activates one of the first pixel and the second pixel according to illuminance information.

[0009] An image sensing device according to yet another embodiment of the present invention may include SPADs, each of which receives a bias voltage for operating in Geiger mode, and a selection circuit for selecting one of the SPADs.

[0010] A distance sensing method according to yet another embodiment of the present invention may include a step of selecting one of a first pixel including a first SPAD having a first sensitivity and a second pixel including a second SPAD having a second sensitivity higher than the first sensitivity, and a step of calculating a distance to a target object based on a pulse signal output from the selected pixel. Effect of the Invention

[0011] According to the embodiments disclosed herein, SPAD pixels having different sensitivities can be arranged together and distance can be sensed using the SPAD pixel appropriate for the situation, thereby providing optimized performance of the imaging device. In addition, various other benefits may be provided by this document, either directly or indirectly. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device according to an embodiment of the present disclosure. [Figure 2a] 2 is a diagram showing a first SPAD included in a pixel included in the pixel array shown in FIG. 1. [Figure 2b] 2 is a diagram showing a second SPAD included in a pixel included in the pixel array shown in FIG. 1. [Diagram 3] 1 is a graph for explaining a comparison of characteristics of a first SPAD and a second SPAD. [Figure 4a] FIG. 2 is a diagram showing an example of an arrangement structure of the pixel array of FIG. [Figure 4b] 1. FIG. 4 is a diagram showing another example of the arrangement structure of the pixel array in FIG. [Diagram 5] FIG. 4b shows the sensor layer and logic layer for the array structure shown in FIG. 4a. [Figure 6] FIG. 4b shows the sensor layer and logic layer for the array structure shown in FIG. 4b. [Figure 7a] 2 is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 1. [Figure 7b] 2 is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 1. [Figure 7c] 2 is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 1. [Figure 8a] FIG. 2 is a schematic diagram illustrating an example of a sensor layer. [Figure 8b] FIG. 13 is a diagram illustrating another example of a sensor layer. [Figure 8c] FIG. 8c shows an example of an arrangement of the optical structures shown in FIGS. 8a and 8b. [Figure 9a] 1 is a diagram showing an example of a planar structure of a first SPAD or a second SPAD. [Figure 9b] 13A to 13C are diagrams showing other examples of the planar structure of the first SPAD or the second SPAD. [Figure 9c] 13 is a diagram showing still another example of the planar structure of the first SPAD or the second SPAD. FIG. [Figure 10a] 9A to 9C. FIG. 9B is a diagram showing an example of a cross-sectional structure taken along any one of the first to third lines in FIGS. 9A to 9C. [Figure 10b] FIG. 9C is a diagram showing another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 10c] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 10d] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 10e] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 10f] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11a] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11b] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11c] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11d]FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11e] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 11f] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 12a] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 12b] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 12c] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 13] FIG. 9C is a diagram showing still another example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. [Figure 14a] FIG. 10b is a diagram showing an example of a modified embodiment of the cross-sectional structure shown in FIG. 10a. [Figure 14b] FIG. 10b is a diagram showing another example of a modified embodiment of the cross-sectional structure shown in FIG. 10a. [Figure 15] FIG. 2 is a diagram showing an example of a planar structure for a plurality of pixels. [Figure 16] FIG. 13 is a diagram showing another example of a planar structure for a plurality of pixels. [Figure 17] FIG. 13 is a diagram showing yet another example of a planar structure for a plurality of pixels. [Figure 18] FIG. 13 is a diagram showing yet another example of a planar structure for a plurality of pixels. [Figure 19] FIG. 13 is a diagram showing yet another example of a planar structure for a plurality of pixels. [Figure 20] FIG. 13 is a diagram showing yet another example of a planar structure for a plurality of pixels. [Figure 21] FIG. 13 is a diagram showing yet another example of a planar structure for a plurality of pixels. [Figure 22a] 16 is a diagram showing an example of a cross-sectional structure taken along the fourth line in FIG. 15. FIG. [Figure 22b] 20 is a diagram showing an example of a cross-sectional structure taken along the fifth line in FIG. 19. [Figure 23a] FIG. 2 is a diagram showing an example of a planar structure for pixels included in a pixel array. [Figure 23b] FIG. 23b is a diagram showing an example of a cross section of the planar structure shown in FIG. 23a. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Various embodiments will be described below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to specific embodiments, and includes various modifications, equivalents, and / or alternatives of the embodiments. The embodiments of the present disclosure can provide various effects that are directly or indirectly recognizable by the present disclosure.

[0014] FIG. 1 is a block diagram illustrating an imaging device according to one embodiment of the present disclosure. Referring to FIG. 1, the imaging device (ID) may refer to a device such as a digital still camera for taking still images or a digital video camera for taking videos. For example, the imaging device (ID) may be realized by, but is not limited to, a digital single lens reflex (DSLR), a mirrorless camera, or a smartphone. The imaging device (ID) may be a concept including a device that includes an image sensor and can capture an object to generate an image. According to an embodiment, the imaging device (ID) may be a distance measuring device that measures a distance to a target object 1. For example, the imaging device (ID) may be a Lidar sensor.

[0015] The imaging device (ID) may include an image sensing device 100 and an image signal processor (ISP) 150 .

[0016] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) that converts incident light into an electrical signal. The image sensing device 100 may include a light source 10, a lens module 20, a light source driver 30, a pixel array 110, a sensor driver 120, a readout circuit 130, and a timing controller 140.

[0017] The light source 10 can irradiate the target object 1 with light in response to the control of the light source driver 30. The light source 10 may be a monochromatic illumination source in which a laser diode (LD), a light emitting diode (LED), a near infrared laser (NIR), a point light source, a white lamp, and a monochromator are combined, or a combination of other laser light sources, which emit light in a specific wavelength band (e.g., near infrared, infrared, or visible light). For example, the light in the specific wavelength band may be light in an infrared wavelength band having a wavelength of 800 nm to 1000 nm (hereinafter referred to as "infrared light"), and in the present disclosure, the description will be given on the assumption that the light source 10 irradiates infrared light. Meanwhile, the light irradiated from the light source 10 may be pulsed light having a predetermined period, amplitude, and pulse width. Although only one light source 10 is shown in FIG. 1 for convenience of explanation, a plurality of light sources may be arranged around the lens module 20.

[0018] The lens module 20 can collect light reflected from the target object 1 and focus it onto the pixels (PX) of the pixel array 110. For example, the lens module 20 can include a focusing lens or other cylindrical optical element with a glass or plastic surface. The lens module 20 can include multiple lenses aligned around an optical axis.

[0019] The light source driver 30 can drive the light source 10 under the control of the timing controller 140, and in particular can control the waveform (period, amplitude, pulse width, etc.) of the emitted light (EL) output from the light source 10.

[0020] The pixel array 110 may include a plurality of pixels (PX) continuously arranged in a two-dimensional matrix structure (e.g., continuously arranged in a column direction and / or a row direction). Each of the plurality of pixels (PX) may sense incident light incident through the lens module 20 and generate a pixel signal according to the control of the sensor driver 120.

[0021] Each pixel (PX) may be an infrared pixel that generates a pixel signal by sensing incident light including reached light (RL) that is incident on the target object 1 after reflection of illuminating light (EL) emitted from the light source 10. In the present disclosure, the reaching light (RL) is assumed to be light that is incident on the target object 1 after reflection of the illuminating light (EL), but the scope of the present invention is not limited thereto. For example, the light source 10 may be provided in a separate device instead of the image sensing device 100, and the reaching light (RL) may be light that is incident on the pixel array 110 after the illuminating light (EL) emitted from the light source 10. In the present disclosure, the infrared pixel may be a depth pixel for calculating the distance to the target object 1, and according to another embodiment, the infrared pixel may include a pixel for generating an infrared image by simply sensing infrared light incident from a scene, rather than the reaching light. According to another embodiment, the pixel (PX) may include a pixel for generating a color image by sensing visible light incident from a scene. Hereinafter, it will be described on the assumption that each pixel (PX) is a SPAD (single photon avalanche diode) pixel for detecting the distance to the target object 1 by a direct ToF method. A more detailed structure and operation of each unit pixel (PX) will be described later with reference to FIG. 2 and subsequent figures.

[0022] The sensor driver 120 may drive pixels (PX) of the pixel array 110 in response to a timing signal output from the timing controller 140. For example, the sensor driver 120 may generate a control signal capable of selecting and controlling pixels (PX) included in at least one row line among a plurality of row lines of the pixel array 110.

[0023] The readout circuit 130 can process pixel signals output from the pixel array 120 under the control of the timing controller 140, and generate and store depth data for detecting the distance to the target object 1. Specifically, the readout circuit 130 can calculate candidate times of flight corresponding to SPAD pulses generated by each pixel (PX) by sensing incident light including arriving light, and store the candidate times of flight corresponding to the SPAD pulses in units of subframes. The readout circuit 130 can transfer the candidate times of flight stored in units of subframes to the image signal processor 150 under the control of the timing controller 140. In the present disclosure, for convenience of explanation, the candidate times of flight can be mixed with the flight time.

[0024] The timing controller 140 may generate timing signals for controlling the operations of the light source driver 30, the sensor driver 120, and the readout circuit 130. According to an embodiment, the timing controller 140 may generate timing signals according to a prestored sequence, data transferred from the readout circuit 130, and / or a request from the image signal processor 150. According to an embodiment, the timing controller 140 may include a logic control circuit, a Phase Lock Loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0025] The image signal processor 150 may generate processed image data by performing image signal processing on the image data (IDATA) received from the image sensing device 100. The image signal processor 150 may perform image signal processing for improving image quality, such as reducing noise on the image data (IDATA) and performing image data interpolation and lens distortion correction on the image data (IDATA).

[0026] The image data (IDATA) may include candidate flight times stored in the above-mentioned subframe units. The image signal processor 150 may generate a histogram for one frame by accumulating data in subframe units, and may determine a target flight time for one frame based on the histogram. The target flight time may be determined for each pixel (PX), and the image signal processor 150 may calculate a target distance, which is a distance to a target object 1 sensed by each pixel (PX), based on the target flight time of each pixel (PX). A collection of target distances for pixels (PX) included in the pixel array 110 may be referred to as a depth image, and may be included in the processed image data.

[0027] The image signal processor 150 can transfer the processed image data to a host device (not shown), which may be a processor (e.g., an application processor) that processes the processed image data received from the image signal processor 150, a memory (e.g., non-volatile memory) that stores the image data, or a display device (e.g., a liquid crystal display (LCD)) that visually outputs the image data.

[0028] In addition, the image signal processor 150 can transmit a control signal to the image sensing device 100 for controlling the operation of the image sensing device 100 (whether or not to operate, operation timing, operation mode, etc.).

[0029] FIG. 2a illustrates a first SPAD included in a pixel included in the pixel array shown in FIG. 2a, at least one pixel (PX) included in the pixel array 110 of FIG. 1 may include a first SPAD (SPAD_C). The first SPAD (SPAD_C) may sense a single photon of the arriving light (RL) reflected by the target object 1, and generate a first voltage pulse (PLS1) corresponding to the sensed single photon. The first voltage pulse (PLS1) may have a pulse shape in which the voltage temporarily rises in response to the sensing of the single photon.

[0030] The first SPAD (SPAD_C) is a photodiode including a photosensitive PN junction, and in the Geiger mode where a reverse bias voltage higher than the breakdown voltage is applied between the cathode and anode, an avalanche breakdown is triggered by an incident single photon, and a first voltage pulse (PLS1) can be generated. This process in which a single photon triggers an avalanche breakdown to generate a voltage pulse is defined as the avalanche process.

[0031] The cathode of the first SPAD (SPAD_C) may receive a first bias voltage (VB1) for applying a reverse bias voltage to the first SPAD (SPAD_C) that can operate the first SPAD (SPAD_C) in Geiger mode. According to one embodiment, the first bias voltage (VB1) is set such that a value obtained by subtracting the voltage of the first node (N1) from the first bias voltage (VB1) is equal to the breakdown voltage (V B) The voltage of the first node (N1) may be initialized to a quenching voltage by the operation of an external circuit (e.g., a quenching circuit) connected to the first node (N1), and thus the first bias voltage (VB1) may be a voltage that causes a value obtained by subtracting the quenching voltage from the first bias voltage (VB1) to be higher than the breakdown voltage. For example, when the quenching voltage is a ground voltage (e.g., 0V), the first bias voltage (VB1) may be initialized to a quenching voltage by the operation of an external circuit (e.g., a quenching circuit) connected to the first node (N1), and thus the first bias voltage (VB1) may be a voltage that causes a value obtained by subtracting the quenching voltage from the first bias voltage (VB1) to be higher than the breakdown voltage. B ) and overvoltage (V EX ) where the excess voltage (V EX ) may be a predetermined voltage that allows the first SPAD (SPAD_C) to operate in Geiger mode.

[0032] In the first SPAD (SPAD_C), an avalanche breakdown is triggered by a single photon, causing the voltage of the first node (N1) to exceed the excess voltage (V EX ) to the first node (N1). An external circuit (e.g., a quenching circuit) connected to the first node (N1) can perform a quenching and recharge operation to return the first SPAD (SPAD_C) to the Geiger mode by initializing the voltage of the first node (N1) to a quenching voltage. As a result, an excess voltage (V EX ) may be generated.

[0033] FIG. 2b illustrates a second SPAD included in a pixel included in the pixel array shown in FIG. 2b, at least one pixel (PX) included in the pixel array 110 of FIG. 1 may include a second SPAD (SPAD_A). According to an embodiment, each pixel (PX) included in the pixel array 110 may include a first SPAD (SPAD_C) or a second SPAD (SPAD_A).

[0034] The second SPAD (SPAD_A) can sense a single photon of the reaching light (RL) reflected by the target object 1 and generate a second voltage pulse (PLS2) corresponding to the sensed single photon. The second voltage pulse (PLS2) can have a pulse shape in which the voltage temporarily drops in response to the sensing of the single photon.

[0035] The overall operation and characteristics of the second SPAD (SPAD_A) are similar to those of the first SPAD (SPAD_C), and therefore, for convenience of explanation, the following description will focus on the differences from the first SPAD (SPAD_C).

[0036] The anode of the second SPAD (SPAD_A) may receive a second bias voltage (VB2) for applying a reverse bias voltage to the second SPAD (SPAD_A) that can operate the second SPAD (SPAD_A) in Geiger mode. According to one embodiment, the second bias voltage (VB2) is set such that the breakdown voltage (VB2) of the second SPAD (SPAD_A) is a value obtained by subtracting the second bias voltage (VB2) from the voltage of the second node (N2). B ) The voltage of the second node (N2) may be initialized to a quenching voltage by the operation of an external circuit (e.g., a quenching circuit) connected to the second node (N2), and thus the second bias voltage (VB2) may be a voltage that causes a value obtained by subtracting the second bias voltage (VB2) from the quenching voltage to be higher than the breakdown voltage. For example, when the quenching voltage is a ground voltage (e.g., 0V), the second bias voltage (VB2) may be set to a value higher than the breakdown voltage (V B ) and overvoltage (V EX ) (i.e., -(V B +V EX Here, the overvoltage (V EX ) may be a predetermined voltage to enable the second SPAD (SPAD_A) to operate in Geiger mode.

[0037] The second SPAD (SPAD_A) is triggered by a single photon into avalanche breakdown, causing the voltage at the second node (N2) to rise to an excess voltage (V EX ) to the second node (N2). An external circuit (e.g., a quenching circuit) connected to the second node (N2) can perform a quenching and recharge operation to return the second SPAD (SPAD_A) to the Geiger mode by initializing the voltage of the second node (N2) to a quenching voltage. As a result, an excess voltage (V EX A second voltage pulse (PLS2) having an amplitude of .times. ...

[0038] FIG. 3 is a graph for explaining the characteristics of the first SPAD and the second SPAD in comparison. 3, a graph of the sensitivity of the first SPAD (SPAD_C) and the second SPAD (SPAD_A) versus illumination is shown. Sensitivity can also be defined as photon detection efficiency (PDE).

[0039] 2, the first SPAD (SPAD_C) may generate a first voltage pulse (PLS1) in which the voltage of the first node (N1) temporarily increases when an avalanche process occurs while the first SPAD (SPAD_C) is operating in Geiger mode with the first bias voltage (VB1) applied to the cathode. That is, in the first SPAD (SPAD_C), since the carriers flowing into the first node (N1) to generate the first voltage pulse (PLS1) are positive charge holes, the mobility of the holes is relatively low, and therefore the sensitivity of the first SPAD (SPAD_C) may be relatively low.

[0040] In contrast, the second SPAD (SPAD_A) can generate a second voltage pulse (PLS2) in which the voltage of the second node (N2) is temporarily lowered when an avalanche process occurs while the second SPAD (SPAD_A) is operating in Geiger mode with the second bias voltage (VB2) applied to the anode. That is, in the second SPAD (SPAD_A), the carriers flowing into the second node (N2) to generate the second voltage pulse (PLS2) are negatively charged electrons, and the mobility of the electrons is relatively high, so that the sensitivity of the second SPAD (SPAD_A) can be relatively high. That is, the first sensitivity of the first SPAD (SPAD_C) can be lower than the second sensitivity of the second SPAD (SPAD_A).

[0041] Within the range of illuminance at which the first SPAD (SPAD_C) and the second SPAD (SPAD_A) can detect light, the intensity of the incident light is relatively weak below a specific illuminance (SL) that is arbitrarily determined (for example, an intermediate value), so the second SPAD (SPAD_A) with high sensitivity is more suitable to increase the signal-to-noise ratio (SNR). Conversely, above the specific illuminance (SL), the intensity of the incident light is relatively strong, so the first SPAD (SPAD_C) with low sensitivity is more suitable to reduce false detection of signals (or pulses) due to ambient light. The degree of false detection of signals due to ambient light can be defined as the dark count rate (DCR).

[0042] Thus, since either the first SPAD (SPAD_C) or the second SPAD (SPAD_A) is more suitable depending on the illumination conditions, in the present disclosure, the pixel array 110 includes both the first SPAD (SPAD_C) and the second SPAD (SPAD_A), but at least one of the first SPAD (SPAD_C) and the second SPAD (SPAD_A) can be selectively activated.

[0043] FIG. 4a is a diagram showing an example of an arrangement structure of the pixel array of FIG. Referring to FIG. 4a, an arrangement structure 400a of the pixel array 110 shows a part of the pixel array 110, and the pixel array 110 may have a structure in which the arrangement structure 400a is repeatedly arranged in both the row direction and the column direction. Each pixel shown in FIG. 4a may be distinguished according to the type of SPAD included in each pixel, and for convenience of explanation, the indication of the SPAD type (SPAD_C, SPAD_A) may be mixed with the indication of the pixel (SPAD_C, SPAD_A). That is, the area indicated by SPAD_C in FIG. 4a may refer to the first pixel (SPAD_C) which is a pixel including the first SPAD (SPAD_C), and the area indicated by SPAD_A may refer to the second pixel (SPAD_A) which is a pixel including the second SPAD (SPAD_A).

[0044] The array structure 400a may include a first pixel (SPAD_C) arranged in a 4×2 matrix having four rows and two columns, and a second pixel (SPAD_A) arranged in a 4×2 matrix having four rows and two columns. The first pixel (SPAD_C) arranged in the 4×2 matrix may constitute one block, and the second pixel (SPAD_A) arranged in the 4×2 matrix may constitute another block.

[0045] That is, in the array structure 400a, a plurality of first pixels (SPAD_C) or a plurality of second pixels (SPAD_A) may be arranged in blocks. Although FIG. 4a illustrates one block including pixels arranged in a 4×2 matrix, the scope of the present invention is not limited thereto, and one block may include pixels arranged in an M×N matrix (M and N are natural numbers, and at least one of M and N is a natural number equal to or greater than 2).

[0046] According to the array structure 400a, pixels of the same type can be arranged adjacent to each other, making it easier to arrange circuits for signal processing of pixels of the same type and minimizing the area where pixels of different types contact each other.

[0047] FIG. 4b is a diagram showing another example of the arrangement structure of the pixel array of FIG. Referring to FIG. 4b, an arrangement structure 400b of the pixel array 110 shows a part of the pixel array 110, and the pixel array 110 may have a structure in which the arrangement structure 400b is repeatedly arranged in both the row direction and the column direction. Each pixel shown in FIG. 4b may be distinguished according to the type of SPAD included in each pixel, and for convenience of explanation, the indication of the SPAD type (SPAD_C, SPAD_A) may be mixed with the indication of the pixel (SPAD_C, SPAD_A). That is, the area indicated by SPAD_C in FIG. 4b may refer to the first pixel (SPAD_C) which is a pixel including the first SPAD (SPAD_C), and the area indicated by SPAD_A may refer to the second pixel (SPAD_A) which is a pixel including the second SPAD (SPAD_A).

[0048] The array structure 400b may include first pixels (SPAD_C) and second pixels (SPAD_A) alternately arranged along the row and column directions. That is, in the array structure 400a, the first pixels (SPAD_C) may be arranged adjacent to each other in the diagonal direction and spaced apart by a distance of one pixel in the row or column direction. Also, the second pixels (SPAD_A) may be arranged adjacent to each other in the diagonal direction and spaced apart by a distance of one pixel in the row or column direction. Here, the pixel distance may refer to the width of the first pixel (SPAD_C) or the second pixel (SPAD_A).

[0049] According to the array structure 400b, different types of pixels can be evenly arranged per unit area (e.g., a 2×2 matrix), making image processing (e.g., interpolation, etc.) easier and reducing the phenomenon of the lens module 20 being out of focus on a particular block.

[0050] FIG. 5 shows the sensor and logic layers for the array structure shown in FIG. 4a. 4a and 5, the array structure 400a may have a stacked structure including a sensor layer and a logic layer. That is, the sensor layer may be disposed closer to the lens module 20 on top of the logic layer, and the logic layer may be disposed farther from the lens module 20 on the bottom of the sensor layer. The sensor layer and the logic layer may correspond to different semiconductor substrates, and electrical connection between the sensor layer and the logic layer may be achieved by a Through Silicon Via (TSV) method, a bonding method (e.g., hybrid bonding, Thermo-Compression (TC) bonding, etc.), etc. The sensor layer may include a first SPAD (SPAD_C) and a second SPAD (SPAD_A) arranged in a configuration corresponding to the array structure 400a.

[0051] The logic layer may include a circuit (hereinafter referred to as the "first SPAD circuit (SPAD_C)") for driving the first SPAD (SPAD_C) or processing a signal output from the first SPAD (SPAD_C), and a circuit (hereinafter referred to as the "second SPAD circuit (SPAD_A)") for driving the second SPAD (SPAD_A) or processing a signal output from the second SPAD (SPAD_A). The SPADs included in the sensor layer and the SPAD circuits included in the logic layer can correspond to each other according to a predetermined rule.

[0052] According to one embodiment, the SPADs arranged in a 2×2 matrix on the sensor layer and the SPAD circuits on the logic layer can have substantially the same area as each other and be arranged in the same position.

[0053] 5, the first SPADs (SPAD_C) arranged in a 2×2 matrix included in the first pixel group (PG1) and the first SPAD circuit (SPAD_C Circuit) for the first SPADs (SPAD_C) of the first pixel group (PG1) may have substantially the same area and may be arranged to overlap each other. Although the first pixel group (PG1) has been described as an example, the other pixels may also be arranged in a 2×2 matrix unit in a substantially similar form to the first pixel group (PG1).

[0054] According to the layout form shown in FIG. 5, when the first SPAD (SPAD_C) of the first pixel group (PG1) shares at least a portion of the first SPAD circuit (SPAD_C Circuit), the design margin for the first SPAD circuit (SPAD_C Circuit) can be further secured.

[0055] FIG. 6 shows the sensor and logic layers for the array structure shown in FIG. 4b. 4b and 6, the array structure 400b may have a stacked structure including a sensor layer and a logic layer. That is, the sensor layer may be disposed closer to the lens module 20 on top of the logic layer, and the logic layer may be disposed farther from the lens module 20 on bottom of the sensor layer. The sensor layer and the logic layer may correspond to different semiconductor substrates, and electrical connection between the sensor layer and the logic layer may be achieved by a TSV method, a bonding method (e.g., hybrid bonding, TC bonding, etc.), etc. The sensor layer may include a first SPAD (SPAD_C) and a second SPAD (SPAD_A) arranged in a configuration corresponding to the array structure 400b.

[0056] The logic layer may include a first SPAD circuit (SPAD_C circuit) for driving the first SPAD (SPAD_C) or processing a signal output from the first SPAD (SPAD_C), and a second SPAD circuit (SPAD_A circuit) for driving the second SPAD (SPAD_A) or processing a signal output from the second SPAD (SPAD_A). The SPADs included in the sensor layer and the SPAD circuits included in the logic layer can correspond to each other according to a predetermined rule.

[0057] According to one embodiment, the SPADs arranged in the diagonal direction on the sensor layer and the SPAD circuits on the logic layer can be arranged to have substantially the same area as each other and to overlap with each other.

[0058] In the example of FIG. 6, the first SPAD (SPAD_C) arranged in the diagonal direction included in the second pixel group (PG2) and the first SPAD circuit (SPAD_C Circuit) for the first SPAD (SPAD_C) of the second pixel group (PG2) may have substantially the same area and be arranged to overlap with each other. Also, the second SPAD (SPAD_A) arranged in the diagonal direction included in the second pixel group (PG2) and the second SPAD circuit (SPAD_A Circuit) for the second SPAD (SPAD_A) of the second pixel group (PG2) may have substantially the same area and be arranged to overlap with each other. Although the second pixel group (PG2) has been described as an example, other pixels may also be arranged in a substantially similar form to the second pixel group (PG2) in units of a 2×2 matrix.

[0059] 6, when the first SPAD (SPAD_C) of the second pixel group (PG2) shares at least a portion of the first SPAD circuit (SPAD_C Circuit), a design margin for the first SPAD circuit (SPAD_C Circuit) can be ensured. Also, when the second SPAD (SPAD_A) of the second pixel group (PG2) shares at least a portion of the second SPAD circuit (SPAD_A Circuit), a design margin for the second SPAD circuit (SPAD_A Circuit) can be ensured.

[0060] FIG. 7a is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 7a, a first pixel signal processing path 700-1 is shown for processing signals generated by a first SPAD (SPAD_C) and a second SPAD (SPAD_A). Although the first pixel signal processing path 700-1 is shown as including one first SPAD (SPAD_C) and one second SPAD (SPAD_A), the scope of the invention is not limited in this respect and the first pixel signal processing path 700-1 may include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A).

[0061] The first pixel signal processing path 700-1 may include a first SPAD (SPAD_C), a second SPAD (SPAD_A), a first quenching transistor (QX_C), a second quenching transistor (QX_A), a first control transistor (CX_C), a second control transistor (CX_A), a mode selector 710, a first buffer (BF1), a first inverter (IV1), a time-to-digital converter (TDC) 720, and a TDC memory 730. Here, the first SPAD (SPAD_C), the first quenching transistor (QX_C), the first control transistor (CX_C), and the first buffer (BF1) can be included in the first SPAD pixel 701, and the second SPAD (SPAD_A), the second quenching transistor (QX_A), the second control transistor (CX_A), and the first inverter (IV1) can be included in the second SPAD pixel 702.

[0062] The first SPAD (SPAD_C) and the second SPAD (SPAD_A) may correspond to the first SPAD (SPAD_C) and the second SPAD (SPAD_A) described in FIG. 2a and FIG. 2b, respectively.

[0063] The first quenching transistor (QX_C) may be an N-channel MOSFET (NMOS) including a gate receiving a quenching control signal (Rq), a drain coupled to a first node (N1), and a source receiving a quenching voltage (Vq). The quenching control signal (Rq) may have a first voltage higher than the quenching voltage (Vq) by (or more than) the threshold voltage of the first quenching transistor (QX_C), a second voltage equal to the quenching voltage (Vq), or a third voltage lower than the quenching voltage (Vq) by (or less than) the threshold voltage of the second quenching transistor (QX_A).

[0064] When the quenching control signal (Rq) has a first voltage, the first quenching transistor (QX_C) may be turned on to supply the quenching voltage (Vq) to the first node (N1), or when the quenching control signal (Rq) has a second voltage or a third voltage, the first quenching transistor (QX_C) may be turned off to not supply the quenching voltage (Vq) to the first node (N1).

[0065] The second quenching transistor (QX_A) may be a P-channel MOSFET (PMOS) including a gate receiving the quenching control signal (Rq), a drain coupled to the second node (N2), and a source receiving the quenching voltage (Vq).

[0066] When the quenching control signal (Rq) has a third voltage, the second quenching transistor (QX_A) may be turned on to supply the quenching voltage (Vq) to the second node (N2), or when the quenching control signal (Rq) has the first voltage or the second voltage, the second quenching transistor (QX_A) may be turned off to not supply the quenching voltage (Vq) to the second node (N2).

[0067] The first control transistor (CX_C) may be a PMOS having a gate for receiving the selection signal (RS), a drain coupled to the cathode of the first SPAD (SPAD_C), and a source for receiving a mode selection voltage (V_MS). The mode selection voltage (V_MS) may have a first bias voltage (VB1) higher than the selection signal (RS) by a threshold voltage of the first control transistor (CX_C), a deactivation voltage equal to the selection signal (RS), or a second bias voltage (VB2) lower than the selection signal (RS) by a threshold voltage of the second control transistor (CX_A).

[0068] When the mode selection voltage (V_MS) has a first bias voltage (VB1), the first control transistor (CX_C) can be turned on to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C), or when the mode selection voltage (V_MS) has a second bias voltage (VB2) or a deactivation voltage, the first control transistor (CX_C) can be turned off to not supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C).

[0069] The second control transistor (CX_A) may be an NMOS having a gate that receives the selection signal (RS), a drain that is coupled to the anode of the second SPAD (SPAD_A), and a source that receives the mode selection voltage (V_MS).

[0070] When the mode selection voltage (V_MS) has the second bias voltage (VB2), the second control transistor (CX_A) can be turned on to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A), or when the mode selection voltage (V_MS) has the first bias voltage (VB1) or the deactivation voltage, the second control transistor (CX_A) can be turned off to not supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A).

[0071] In this disclosure, for convenience of explanation, it is assumed that the quenching voltage (Vq) and the selection signal (RS) are ground voltages (e.g., 0 V), but the scope of the present invention is not limited to this. That is, the quenching voltage (Vq) and the selection signal (RS) can be varied within the range in which the SPADs (SPAD_C, SPAD_A) and the transistors (CX_C, CX_A, QX_C, QX_A) can operate.

[0072] In addition, the first control transistor (CX_C) and the second control transistor (CX_A) can be called a control circuit that selectively activates the first SPAD (SPAD_C) and the second SPAD (SPAD_A), and the first control transistor (CX_C) and the second control transistor (CX_A) are merely one example of a control circuit, and the configuration for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A) is not limited to this.

[0073] The mode selector 710 may be included as part of the sensor driver 120 of Figure 1, although the scope of the present invention is not limited in this respect. The quenching voltage (Vq), the quenching control signal (Rq), and the selection signal (RS) supplied to the first SPAD pixel 701 and the second SPAD pixel 702 may be provided from the sensor driver 120.

[0074] The mode selector 710 may generate a mode selection voltage (V_MS) in response to a mode selection signal (MS). The mode selection signal (MS) may be generated by the image sensing device 100, the image signal processor 150, or an external device (e.g., an application processor) using illumination information.

[0075] The illuminance information may include an illuminance value output by an illuminance sensor (not shown) included in the imaging device (ID) and / or an illuminance value estimated from the occurrence frequency of image data (IDATA) per subframe. Here, the illuminance sensor (not shown) may detect light of a specific wavelength band (e.g., light of the same wavelength band as the wavelength band of light irradiated by the light source 10) and output an illuminance value. To this end, the illuminance sensor (not shown) may include an optical filter for selectively receiving light of a specific wavelength band.

[0076] The illuminance information is one example of information on which the mode selection signal (MS) is based, and in other embodiments, other information (e.g., power information indicating a power consumption state of the imaging device (ID), user selection information indicating a mode selected by a user, temperature information indicating a temperature state of the imaging device (ID)) may be the basis for the mode selection signal (MS). In other embodiments, the mode selection signal (MS) may be determined based on at least one of the illuminance information, the power information, the user selection information, or the temperature information.

[0077] If the illuminance value is equal to or greater than the predetermined threshold (or if the current illuminance is a first illuminance equal to or greater than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic high level. Here, the threshold may be a value that is experimentally determined such that the suitability of the first SPAD (SPAD_C) and the suitability of the second SPAD (SPAD_A) for sensing the arriving light (RL) are equal to each other. Upon receiving the mode selection signal (MS) at a logic high level, the mode selector 710 may output a first bias voltage (VB1).

[0078] When a first bias voltage (VB1) is applied to the first control transistor (CX_C) and the second control transistor (CX_A), the first control transistor (CX_C) can be turned on and the second control transistor (CX_A) can be turned off. This allows the first SPAD (SPAD_C) to enter the Geiger mode and the second SPAD (SPAD_A) to not enter the Geiger mode. When a photon is incident on the first SPAD (SPAD_C), an avalanche process occurs and the voltage of the first node (N1) becomes an overvoltage (V EX) at a predetermined timing (e.g., timing when the avalanche process is completed), the quenching control signal (Rq) may transition from the second voltage to the first voltage, whereby a quenching operation and a recharge operation for the first SPAD (SPAD_C) are performed, the voltage of the first node (N1) returns to the quenching voltage (Vq), and the first voltage pulse (PLS1) may be output from the first node (N1). Also, when the quenching operation and the recharge operation for the first SPAD (SPAD_C) are completed, the quenching control voltage (Vq) may transition from the first voltage to the second voltage.

[0079] When the illuminance value is less than the predetermined threshold (or when the current illuminance is a second illuminance less than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic low level. Upon receiving the mode selection signal (MS) at a logic low level, the mode selector 710 may output the second bias voltage (VB2).

[0080] When the second bias voltage (VB2) is applied to the first control transistor (CX_C) and the second control transistor (CX_A), respectively, the first control transistor (CX_C) can be turned off and the second control transistor (CX_A) can be turned on. As a result, the first SPAD (SPAD_C) can not enter the Geiger mode and the second SPAD (SPAD_A) can enter the Geiger mode. When a photon is incident on the second SPAD (SPAD_A), an avalanche process occurs and the voltage of the second node (N2) becomes the overvoltage (V EX) at a predetermined timing (e.g., timing when the avalanche process is completed), the quenching control signal (Rq) may transition from the second voltage to the third voltage, whereby a quenching operation and a recharge operation for the second SPAD (SPAD_A) are performed, the voltage of the second node (N2) returns to the quenching voltage (Vq), and the second voltage pulse (PLS2) may be output from the second node (N2). Also, when the quenching operation and the recharge operation for the second SPAD (SPAD_A) are completed, the quenching control voltage (Vq) may transition from the third voltage to the second voltage.

[0081] That is, the mode selector 710 can activate the first SPAD (SPAD_C) or the second SPAD (SPAD_A) by generating a mode selection voltage (V_MS) based on the mode selection signal (MS) that varies depending on the illuminance, and the activated first SPAD (SPAD_C) or second SPAD (SPAD_A) can detect incident photons and output a first voltage pulse (PLS1) or a second voltage pulse (PLS2).

[0082] The first buffer (BF1) samples the first voltage pulse (PLS1) in an analog form generated at the first node (N1), converts it into a digital pulse signal having an inverse waveform of the first voltage pulse (PLS1), and inverts and outputs the digital pulse signal having an inverse waveform of the first voltage pulse (PLS1). For this operation, the first buffer (BF1) may include two inverters connected in cascade. Here, the sampling method may be a method of converting the level of the voltage pulse into a pulse signal having a logic level of 0 or 1 depending on whether the level of the voltage pulse is equal to or higher than a threshold level, but the scope of the present invention is not limited thereto. The first voltage pulse (PLS1) generated at the first node (N1) may have a waveform that instantaneously rises from the quenching voltage (Vq) due to an avalanche process and then returns to the quenching voltage (Vq) again due to a quenching operation and a recharge operation. As a result, the first inverter of the first buffer (BF1) converts the first voltage pulse (PLS1) into a digital pulse signal having an inverse waveform, so that the output of the first inverter may have a waveform that maintains a logic level of 1, then transitions instantaneously to a logic level of 0 when the first voltage pulse (PLS1) occurs, and then returns to a logic level of 1. The second inverter of the first buffer (BF1) may invert and output a digital pulse signal having an inverse waveform of the first voltage pulse (PLS1) transmitted through the first inverter. That is, the output of the second inverter may have a waveform that maintains a logic level of 0, then transitions instantaneously to a logic level of 1 in response to the occurrence of the first voltage pulse (PLS1), and then returns to a logic level of 0. The output of the first buffer (BF1) can be referred to as the first SPAD pulse, where the first voltage pulse (PLS1) is a digitized pulse.

[0083] The first inverter (IV1) samples the second voltage pulse (PLS2) in an analog form generated at the second node (N2) and converts it into a digital pulse signal having an inverse waveform of the second voltage pulse (PLS2). The second voltage pulse (PLS2) generated at the second node (N2) may have a waveform that momentarily drops from the quenching voltage (Vq) due to an avalanche process, and then returns to the quenching voltage (Vq) again due to a quenching operation and a recharge operation. As a result, since the first inverter (IV1) converts the second voltage pulse (PLS2) into a digital pulse signal having an inverse waveform of the second voltage pulse (PLS2), the output of the second inverter (IV2) may have a waveform that maintains a logic level of 0, then momentarily transitions to a logic level of 1 when the second voltage pulse (PLS2) occurs, and then returns to a logic level of 0. The output of the first inverter (IV1) can be referred to as the second SPAD pulse, which is an inverted and digitized version of the second voltage pulse (PLS2).

[0084] The first SPAD pulse output from the first SPAD pixel 701 and the second SPAD pulse output from the second SPAD pixel 702 can be transmitted to the TDC 720 as a pixel signal (PX_OUT).

[0085] The TDC 720 can calculate a time delay between a pulse of the pixel signal (PX_OUT) and a reference pulse of the illumination light (EL) and generate TDC data indicating the time delay. The TDC 720 can obtain the occurrence time of the reference pulse of the illumination light (EL) from the timing controller 140 that controls the light source driver 30, or can consider a predetermined time (e.g., a time before a certain time from the start of a subframe) as the occurrence time of the reference pulse. The TDC data output by the TDC 720 can indicate the above-mentioned candidate times of flight.

[0086] The TDC 720 can be activated or deactivated in response to a TDC enable signal provided by the timing controller 140. The TDC enable signal can have an activated level (e.g., a logic level of 1) when generation of TDC data for a pixel (701 or 702) is required (e.g., between each subframe) and can have a deactivated level (e.g., a logic level of 0) when generation of TDC data for a pixel (701 or 702) is not required.

[0087] The TDC memory 730 can store the TDC data and then output the stored TDC data as image data to the image signal processor 150 in fixed units (eg, subframes).

[0088] TDC 720 and TDC memory 730 may be included in readout circuit 130 of FIG. 1 and may be provided corresponding to one column of pixel array 110, although the scope of the present invention is not limited in this respect.

[0089] According to the present disclosure, by selectively activating a SPAD appropriate for the current illuminance from among the first SPAD (SPAD_C) and the second SPAD (SPAD_A), which have different sensitivities, and sensing the distance to the target object 1 using the activated SPAD, unnecessary power consumption can be reduced and a more accurate distance can be obtained.

[0090] FIG. 7b is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 7b, a second pixel signal processing path 700-2 is shown for processing signals generated by a first SPAD (SPAD_C) and a second SPAD (SPAD_A). Although the second pixel signal processing path 700-2 is shown as including one first SPAD (SPAD_C) and one second SPAD (SPAD_A), the scope of the invention is not limited in this respect and the second pixel signal processing path 700-2 may include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A).

[0091] The second pixel signal processing path 700-2 is substantially similar to the first pixel signal processing path 700-1 except for some differences, so the following description will focus on the differences from the first pixel signal processing path 700-1.

[0092] The first control transistor (CX_C) may be a PMOS having a gate receiving a mode selection voltage (V_MS'), a drain coupled to the cathode of the first SPAD (SPAD_C), and a source receiving a first bias voltage (VB1). The mode selection voltage (V_MS') may have a first activation voltage lower than the first bias voltage (VB1) by a threshold voltage of the first control transistor (CX_C) or a second activation voltage higher than the second bias voltage (VB2) by a threshold voltage of the second control transistor (CX_A).

[0093] When the mode selection voltage (V_MS') has a first activation voltage, the first control transistor (CX_C) may be turned on to supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C), or when the mode selection voltage (V_MS') has a second activation voltage, the first control transistor (CX_C) may be turned off to not supply the first bias voltage (VB1) to the cathode of the first SPAD (SPAD_C).

[0094] The second control transistor (CX_A) may be an NMOS having a gate receiving the mode selection voltage (V_MS'), a drain coupled to the anode of the second SPAD (SPAD_A), and a source receiving the second bias voltage (VB2).

[0095] When the mode selection voltage (V_MS') has a second activation voltage, the second control transistor (CX_A) may be turned on to supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A), or when the mode selection voltage (V_MS') has a first activation voltage, the second control transistor (CX_A) may be turned off to not supply the second bias voltage (VB2) to the anode of the second SPAD (SPAD_A).

[0096] The first control transistor (CX_C) and the second control transistor (CX_A) can be referred to as a control circuit that selectively activates the first SPAD (SPAD_C) and the second SPAD (SPAD_A). The first control transistor (CX_C) and the second control transistor (CX_A) are merely one example of a control circuit, and the configuration for selectively activating the first SPAD (SPAD_C) and the second SPAD (SPAD_A) is not limited to this. The mode selector 710 can generate a mode selection voltage (V_MS') in response to a mode selection signal (MS).

[0097] When the illuminance value is equal to or greater than the predetermined threshold (or when the current illuminance is a first illuminance equal to or greater than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic high level. Upon receiving the mode selection signal (MS) at a logic high level, the mode selector 710 may output a first activation voltage.

[0098] When a first activation voltage is applied to the first control transistor (CX_C) and the second control transistor (CX_A), respectively, the first control transistor (CX_C) can be turned on and the second control transistor (CX_A) can be turned off. As a result, the first SPAD (SPAD_C) can enter the Geiger mode and the second SPAD (SPAD_A) can not enter the Geiger mode. When a photon is incident on the first SPAD (SPAD_C), an avalanche process proceeds and the voltage of the first node (N1) becomes the overvoltage (V EX) at a predetermined timing (e.g., the timing when the avalanche process is completed), the quenching control signal (Rq) may transition from the second voltage to the first voltage, whereby a quenching operation and a recharge operation for the first SPAD (SPAD_C) are performed, the voltage of the first node (N1) returns to the quenching voltage (Vq), and the first voltage pulse (PLS1) may be output from the first node (N1). Also, when the quenching operation and the recharge operation for the first SPAD (SPAD_C) are completed, the quenching control voltage (Vq) may transition from the first voltage to the second voltage.

[0099] When the illuminance value is less than the predetermined threshold (or when the current illuminance is a second illuminance less than the predetermined threshold illuminance), the mode selection signal (MS) may be at a logic low level. Upon receiving the mode selection signal (MS) at a logic low level, the mode selector 710 may output a second activation voltage.

[0100] When the second activation voltage is applied to the first control transistor (CX_C) and the second control transistor (CX_A), respectively, the first control transistor (CX_C) can be turned off and the second control transistor (CX_A) can be turned on. As a result, the first SPAD (SPAD_C) can not enter the Geiger mode and the second SPAD (SPAD_A) can enter the Geiger mode. When a photon is incident on the second SPAD (SPAD_A), an avalanche process proceeds and the voltage of the second node (N2) becomes the overvoltage (V EX) at a predetermined timing (e.g., timing when the avalanche process is completed), the quenching control signal (Rq) may transition from the second voltage to the third voltage, whereby a quenching operation and a recharge operation for the second SPAD (SPAD_A) are performed, the voltage of the second node (N2) returns to the quenching voltage (Vq), and the second voltage pulse (PLS2) may be output from the second node (N2). Also, when the quenching operation and the recharge operation for the second SPAD (SPAD_A) are completed, the quenching control voltage (Vq) may transition from the third voltage to the second voltage.

[0101] That is, the mode selector 710 can activate the first SPAD (SPAD_C) or the second SPAD (SPAD_A) by generating a mode selection voltage (V_MS') based on the mode selection signal (MS) that varies according to the illuminance, and the activated first SPAD (SPAD_C) or second SPAD (SPAD_A) can detect incident photons and output a first voltage pulse (PLS1) or a second voltage pulse (PLS2).

[0102] FIG. 7c is a diagram for explaining the operation of a pixel included in the pixel array of FIG. 7c, a third pixel signal processing path 700-3 is shown for processing signals generated by a first SPAD (SPAD_C) and a second SPAD (SPAD_A). Although the third pixel signal processing path 700-3 is shown as including one first SPAD (SPAD_C) and one second SPAD (SPAD_A), the scope of the invention is not limited in this respect and the third pixel signal processing path 700-3 may include multiple first SPADs (SPAD_C) and / or multiple second SPADs (SPAD_A).

[0103] The third pixel signal processing path 700-3 may include a first SPAD (SPAD_C), a second SPAD (SPAD_A), a first quenching transistor (QX_C), a second quenching transistor (QX_A), a second buffer (BF2), a second inverter (IV2), an output selector 750, a TDC 760, and a TDC memory 770. Here, the first SPAD (SPAD_C), the first quenching transistor (QX_C), and the second buffer (BF2) may be included in a first SPAD pixel 703, and the second SPAD (SPAD_A), the second quenching transistor (QX_A), and the second inverter (IV2) may be included in a second SPAD pixel 704.

[0104] The third pixel signal processing path 700-3 is generally similar to the first pixel signal processing path 700-1 described above, and therefore, to avoid duplication, the following description will focus on the differences.

[0105] The third pixel signal processing path 700-3 may not include the mode selector 710 and the control transistors (CX_C, CX_A). That is, the first SPAD (SPAD_C) and the second SPAD (SPAD_A) may receive the first bias voltage (VB1) and the second bias voltage (VB2), respectively. This allows the first SPAD (SPAD_C) and the second SPAD (SPAD_A) to enter the Geiger mode regardless of the mode, and the first SPAD pixel 703 and the second SPAD pixel 704 to independently output the first SPAD pulse and the second SPAD pulse in response to photon detection. The operation of the second buffer (BF2) and the second inverter (IV2) may be substantially similar to the operation of the first buffer (BF1) and the first inverter (IV1), respectively.

[0106] The output selector 750 can select and output at least one of the first SPAD pulse and the second SPAD pulse as a pixel signal (PX_OUT) in response to a mode selection signal (MS).

[0107] When the illuminance value is equal to or greater than the predetermined threshold, the mode selection signal (MS) may be at a logic high level. Upon receiving the mode selection signal (MS) at a logic high level, the output selector 750 may output the first SPAD pulse as the pixel signal (PX_OUT).

[0108] When the illumination value is less than the predetermined threshold, the mode selection signal (MS) may be at a logic low level. Upon receiving the mode selection signal (MS) at a logic low level, the output selector 750 can output the second SPAD pulse as the pixel signal (PX_OUT).

[0109] According to another embodiment, when the illuminance value is within a certain range from a predetermined threshold or when there is a request from an external device, the mode selection signal (MS) may be at a third logic level. The output selector 750 that receives the mode selection signal (MS) at the third logic level may output the first SPAD pulse and the second SPAD pulse as the pixel signal (PX_OUT), respectively. In this case, the first SPAD pulse and the second SPAD pulse may be output via independent signal lines or may be output sequentially via one signal line. The operation of TDC 760 and TDC memory 770 may be substantially similar to the operation of TDC 720 and TDC memory 730, respectively, of FIG. 7a.

[0110] According to the present disclosure, the distance to the target object 1 is sensed using one of the first SPAD (SPAD_C) and the second SPAD (SPAD_A), which have different sensitivities and are appropriate for the current illuminance, but a more accurate distance can be obtained by sensing the distance to the target object 1 using both the first SPAD (SPAD_C) and the second SPAD (SPAD_A) as necessary.

[0111] In the present disclosure, an embodiment is described in which one of a first SPAD pixel including a first SPAD (SPAD_C) or a second SPAD pixel including a second SPAD (SPAD_A) is selected depending on illumination information, and Figures 7a and 7b relate to an embodiment in which one of the first SPAD pixel 701 and the second SPAD pixel 702 is selected in an activating manner, and Figure 7c relates to an embodiment in which at least one of the first SPAD pixel 703 and the second SPAD pixel 704 is selected in an output selecting manner.

[0112] The mode selector 710 of FIG. 7a or FIG. 7b and the output selector 750 of FIG. 7c, respectively, may be referred to as or included in a selection circuit in that they may select either the first SPAD pixel or the second SPAD pixel.

[0113] FIG. 8a is a schematic diagram of an example of a sensor layer. Referring to FIG. 8a, a cross-sectional structure 800-1 is shown that illustrates a schematic of a region in the sensor layer that corresponds to a second SPAD (SPAD_A).

[0114] The cross-sectional structure 800-1 may include a semiconductor substrate 802, a microlens 804, and a first optical structure 810. The semiconductor substrate 802 may include opposing upper and lower surfaces. For example, the semiconductor substrate 802 may be a P-type or N-type bulk substrate, a substrate in which a P-type or N-type epitaxial layer is grown on a P-type bulk substrate, or a substrate in which a P-type or N-type epitaxial layer is grown on an N-type bulk substrate. A second SPAD (SPAD_A) may be formed inside the semiconductor substrate 802, and a specific structure of the second SPAD (SPAD_A) will be described later with reference to FIG. 9a and subsequent drawings. The semiconductor substrate 802 may include at least one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0115] The microlens 804 may be formed in a hemispherical shape on the lower part of the semiconductor substrate 802, and may increase light gathering power for incident light and improve light receiving efficiency (or amount of light received per area). An overcoating layer (not shown) may be further formed on the upper or lower part of the microlens 804 to prevent diffuse reflection of light incident from the lens module 20 and suppress flare characteristics.

[0116] The first optical structure 810 may be disposed on the lower surface of the semiconductor substrate 802 where light is incident, and may scatter the incident light to improve the light receiving efficiency of the second SPAD (SPAD_A). The first optical structure 810 may include uneven structures 815 periodically disposed on the lower surface of the semiconductor substrate 802. According to an embodiment, the uneven structures 815 may be pyramidal or cylindrical. The width, depth, period, and number of the uneven structures 815 may be experimentally determined according to the size and internal structure of the second SPAD pixel, and the thickness of the semiconductor substrate 802.

[0117] For example, the relief structure 815 can be formed by selectively wet etching the bottom surface of the semiconductor substrate 802 and gap-filling with a material having a refractive index different from that of the semiconductor substrate 802 .

[0118] The first optical structure 810 is disposed in the region corresponding to the second SPAD (SPAD_A), so that the sensitivity of the second SPAD (SPAD_A) which has a higher sensitivity than the first SPAD (SPAD_C) can be increased. According to another embodiment, in order to facilitate the process, the uneven structure 815 can be included not only in the region corresponding to the second SPAD (SPAD_A) but also in the region corresponding to the first SPAD (SPAD_C).

[0119] FIG. 8b is a schematic diagram of another example of a sensor layer. Referring to FIG. 8b, a cross-sectional structure 800-2 is shown that is a schematic representation of a region corresponding to a first SPAD (SPAD_C) in the sensor layer.

[0120] The cross-sectional structure 800-2 may include a semiconductor substrate 802, a microlens 804, and a second optical structure 850. The cross-sectional structure 800-2 is substantially similar to the cross-sectional structure 800-1 described above, except for some differences, and therefore the differences will be mainly described.

[0121] A first SPAD (SPAD_C) may be formed inside the semiconductor substrate 802, and a specific structure of the first SPAD (SPAD_C) will be described later with reference to FIG. 9a and subsequent figures.

[0122] The second optical structure 850 may be disposed on the lower surface of the semiconductor substrate 802 on which light is incident, and may block (reflect or absorb) a portion of the incident light, thereby reducing the light receiving efficiency of the first SPAD (SPAD_C). The second optical structure 850 may include a light blocking structure 855 disposed on the lower surface of the semiconductor substrate 802 in at least a portion of the microlens 804 (or a pixel including the microlens 804). According to an embodiment, the light blocking structure 855 may be disposed on the edge of the microlens 804, and may form an opening that allows the incident light to pass near the center of the microlens 804. The light blocking structure 855 may be disposed on the edge of the microlens 804 to prevent crosstalk with surrounding pixels. The width, position, and number of the light blocking structure 855 may be determined experimentally according to the size and internal structure of the first SPAD pixel, and the thickness of the semiconductor substrate 802.

[0123] For example, the light blocking structure 855 can be formed by selectively wet etching the underside of the semiconductor substrate 802 and gap filling with a material that is highly optically reflective or highly optically absorbing (e.g., tungsten, aluminum, copper, or alloys thereof).

[0124] The second optical structure 850 is disposed in the region corresponding to the first SPAD (SPAD_C), so that the sensitivity of the first SPAD (SPAD_C), which has a lower sensitivity than the second SPAD (SPAD_A), can be lowered. According to another embodiment, in order to facilitate the process, the uneven structure 815 can be included not only in the region corresponding to the first SPAD (SPAD_C) but also in the region corresponding to the second SPAD (SPAD_A).

[0125] FIG. 8c shows an example of how the optical structures shown in FIGS. 8a and 8b may be arranged. Referring to FIG. 8c, there is shown an example 800a in which a first optical structure 810 and a second optical structure 850 are arranged in the arrangement structure 400a of the pixel array 110 shown in FIG.

[0126] A light blocking structure 855 is disposed in each pixel including a first SPAD (SPAD_C) and can block (reflect or absorb) a portion of the incident light and reduce the light receiving efficiency of the first SPAD (SPAD_C).

[0127] A concave-convex structure 815 is disposed in each pixel including a second SPAD (SPAD_A) to scatter incident light and improve the light receiving efficiency of the second SPAD (SPAD_A).

[0128] 8c, the light shielding structure 855 is disposed on all pixels including the first SPAD (SPAD_C) and the uneven structure 815 is disposed on all pixels including the second SPAD (SPAD_A), but the scope of the present invention is not limited thereto. For example, the light shielding structure 855 may be disposed only on a portion of the pixels including the first SPAD (SPAD_C), or the uneven structure 815 may be disposed only on a portion of the pixels including the second SPAD (SPAD_A).

[0129] In addition, at least one of the width, position, and number of the light blocking structure 855 arranged in each pixel including the first SPAD (SPAD_C) may be different for each pixel. At least one of the width, depth, period, and number of the uneven structure 815 arranged in each pixel including the second SPAD (SPAD_A) may be different for each pixel.

[0130] By selectively placing the second optical structure 850 in a pixel including the first SPAD (SPAD_C) and / or the first optical structure 810 in a pixel including the second SPAD (SPAD_A), the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A) can be further increased, thereby further increasing the suitability of the first SPAD (SPAD_C) for high illumination and the suitability of the second SPAD (SPAD_A) for low illumination.

[0131] Furthermore, the structures for improving or reducing the sensitivity of the first SPAD (SPAD_C) or the second SPAD (SPAD_A) described in Figures 9a and following may be combined with each other or with the first optical structure 810 and the second optical structure 850 to adjust the sensitivity of the first SPAD (SPAD_C) or the second SPAD (SPAD_A).

[0132] In addition, to facilitate processing, the structures that improve or reduce the sensitivity of the first SPAD (SPAD_C) or the second SPAD (SPAD_A) may be arranged substantially similarly to each other in the area corresponding to the first SPAD (SPAD_C) and the area corresponding to the second SPAD (SPAD_A).

[0133] FIG. 9a is a diagram showing an example of the planar structure of the first SPAD or the second SPAD. Referring to FIG. 9a, a planar structure 900-1 of a first SPAD (SPAD_C) or a second SPAD (SPAD_A) is shown diagrammatically.

[0134] The first SPAD (SPAD_C) may include a cathode that receives a first bias voltage (VB1) and an anode that outputs a first voltage pulse (PLS1), and the second SPAD (SPAD_A) may include an anode that receives a second bias voltage (VB2) and a cathode that outputs a second voltage pulse (PLS2).

[0135] The cathode of the first SPAD (SPAD_C) and the anode of the second SPAD (SPAD_A) can each be defined as a bias node (BN) to which a bias voltage is applied, and further, the anode of the first SPAD (SPAD_C) and the cathode of the second SPAD (SPAD_A) can each be defined as an output node (ON) that outputs a voltage pulse.

[0136] The planar structure 900-1 may include an output node (ON) and a bias node (BN), and may correspond to a first SPAD (SPAD_C) or a second SPAD (SPAD_A). That is, when the planar structure 900-1 corresponds to a first SPAD (SPAD_C), the output node (ON) may correspond to an anode of the first SPAD (SPAD_C), and the bias node (BN) may correspond to a cathode of the first SPAD (SPAD_C). Conversely, when the planar structure 900-1 corresponds to a second SPAD (SPAD_A), the output node (ON) may correspond to a cathode of the second SPAD (SPAD_A), and the bias node (BN) may correspond to an anode of the second SPAD (SPAD_A).

[0137] The output node (ON) may have a circular shape located in the center of the SPAD. The bias node (BN) may be spaced a predetermined distance from the output node (ON) and may have a circular ring (or donut) shape surrounding the output node (ON).

[0138] If the distance between the bias node (BN) and the output node (ON) becomes too close, an edge breakdown phenomenon (or tunneling phenomenon) may occur in which charges are directly transferred from the bias node (BN) to the output node (ON) without flowing into the output node (ON) due to an avalanche process, so the distance between the bias node (BN) and the output node (ON) can be experimentally determined so as to prevent the edge breakdown phenomenon. Also, the distance between the bias node (BN) and the output node (ON) can be arranged to be maintained substantially constant.

[0139] FIG. 9b shows another example of the planar structure of the first SPAD or the second SPAD. Referring to FIG. 9b, a planar structure 900-2 of the first SPAD (SPAD_C) or the second SPAD (SPAD_A) is shown diagrammatically.

[0140] The planar structure 900-2 is substantially similar to the planar structure 900-1 described above, except for some differences, and therefore the differences will be mainly described. The output node (ON) may have a rectangular shape with rounded corners that is disposed in the center of the SPAD. By having the output node (ON) have a rectangular shape with rounded corners, the output node (ON) may be disposed so that the distance between the bias node (BN) and the output node (ON) is not too close, thereby minimizing the edge breakdown phenomenon. The bias node (BN) is spaced a predetermined distance from the output node (ON) and can have a rectangular ring shape surrounding the output node (ON).

[0141] FIG. 9c shows still another example of the planar structure of the first SPAD or the second SPAD. Referring to FIG. 9c, a planar structure 900-3 of the first SPAD (SPAD_C) or the second SPAD (SPAD_A) is shown diagrammatically.

[0142] The planar structure 900-3 is substantially similar to the planar structure 900-1 described above except for some differences, and therefore the differences will be mainly described. The output node (ON) may have a square shape with an angled corner located in the center of the SPAD. The bias node (BN) is spaced a predetermined distance from the output node (ON) and can have a rectangular ring shape surrounding the output node (ON).

[0143] The area of ​​the output node (ON) may correspond to the area of ​​the active region capable of detecting photons, and a larger area of ​​the output node (ON) may result in higher sensitivity, but may also result in a higher probability of noise due to background noise, and a larger area of ​​the output node (ON) may also result in a higher probability of edge breakdown.

[0144] Assuming that the output nodes (ON) included in the planar structures (900-1 to 900-3) have the same width (e.g., width in the horizontal direction), the planar structure 900-3 having the largest area of ​​the output node (ON) may have the highest sensitivity, the planar structure 900-2 having the second largest area of ​​the output node (ON) may have the second highest sensitivity, and the planar structure 900-1 having the smallest area of ​​the output node (ON) may have the lowest sensitivity.

[0145] According to one embodiment, in order to further increase the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A), the first SPAD (SPAD_C) can be formed in a planar structure 900-1, and the second SPAD (SPAD_A) can be formed in a planar structure 900-3.

[0146] FIG. 10a is a diagram showing an example of a cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10a, a cross-sectional structure 1000-1 cut along any one of the first line (A-A') to the third line (C-C') in FIG. 9a to FIG. 9c is shown. The cross-sectional structures (1000-1 to 1000-6) shown in FIG. 10a to FIG. 10f may be cross-sectional structures related to the case where the planar structure (900-1 to 900-3) in FIG. 9a to FIG. 9c corresponds to the first SPAD (SPAD_C). In addition, the cross-sectional structures (1000-1 to 1000-6) are described on the premise that they are structures formed on an N-substrate doped with N-type impurities (e.g., Group 5 elements), but the scope of the present invention is not limited thereto, and may be structures formed on a well region doped with N-type impurities inside a P-substrate doped with P-type impurities (e.g., Group 3 elements).

[0147] Cross-sectional structure 1000 - 1 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0148] The first P-type region 1010 may correspond to the output node (ON) of the planar structure (900-1 to 900-3) and may be a region doped with P-type impurities.

[0149] The second P-type region 1020 may surround the first P-type region 1010 and have a width greater than the first P-type region 1010 and a depth greater than the first P-type region 1010. In the following description, the width may mean the left-right width, and the depth may mean the depth from the top surface of the substrate. The second P-type region 1020 may be a region doped with P-type impurities at a doping concentration lower than the doping concentration of the first P-type region 1010.

[0150] First N-type region 1110 may be a region disposed on a top surface of an N-type substrate and doped with N-type impurities. The second N-type region 1120 may be in contact with the lower surface of the first N-type region 1110, and may have the same width as the first N-type region 1110, and may have a greater depth than the first N-type region 1110. The second N-type region 1120 may be a region doped with N-type impurities at a doping concentration lower than the doping concentration of the first N-type region 1110.

[0151] The third N-type region 1130 may be in contact with the lower surface of the second N-type region 1120, have the same width as the second N-type region 1120, and may have a greater depth than the second N-type region 1120. The third N-type region 1130 may be a region doped with an N-type impurity at a doping concentration lower than the doping concentration of the second N-type region 1120. On the other hand, the third N-type region 1130 may be a region doped with an N-type impurity at a doping concentration higher than the doping concentration of the N-type substrate.

[0152] The first N-type region 1110, the second N-type region 1120, and the third N-type region 1130 may correspond to the bias nodes (BN) of the planar structures (900-1 to 900-3).

[0153] The N-type region including the first N-type region 1110, the second N-type region 1120, the third N-type region 1130, and the N-type substrate, and the P-type region including the first P-type region 1010 and the second P-type region 1020 can form a first SPAD (SPAD_C).

[0154] Photons of the incoming light (RL) transmitted through the bottom surface of the N-type substrate cause photoelectric conversion to generate electrons and holes 1001. Although FIG. 10a shows three holes 1001 being generated at a specific position by the incoming light (RL), the scope of the present invention is not limited thereto, and at least one hole 1001 may be generated at any position within the cross-sectional structure 1000-1, and an avalanche process may proceed. When the avalanche process by photons proceeds, the doping concentration increases in the second P-type region 1020 and the first P-type region 1010 in that order, and thus, an amplification of carriers (i.e., holes 1001) may occur in the direction of the first P-type region 1010. The second P-type region 1020 may be defined as a multiplier region in that it causes such an amplification of carriers and increases the detection speed of the carriers, thereby improving sensitivity.

[0155] The doping concentrations decrease in the order of first N-type region 1110, second N-type region 1120, third N-type region 1130, and N-type substrate, so that the electric field (or reverse bias) caused by the first bias voltage (VB1) applied to first N-type region 1110 can affect a deeper position in the N-type substrate. This allows the avalanche process to proceed even with photons that reach a deep position in the N-type substrate, improving the sensitivity of the first SPAD (SPAD_C).

[0156] Furthermore, the third N-type region 1130 is formed deep near the bottom surface of the N-type substrate, which can also contribute to pixel isolation between adjacent pixels.

[0157] On the other hand, since the second P-type region 1020 forms a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010, the edge breakdown phenomenon between the first N-type region 1110 and the first P-type region 1010 can be prevented.

[0158] FIG. 10b is a diagram showing another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10b, there is shown a cross-sectional structure 1000-2 cut along any one of the first line (A-A') to the third line (C-C') in FIGS. 9a to 9c.

[0159] The cross-sectional structure 1000-2 is substantially similar to the cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. Cross-sectional structure 1000 - 2 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0160] The second P-type region 1020 is disposed adjacent to both the left and right sides of the first P-type region 1010 and may have a greater depth than the first P-type region 1010. The second P-type region 1020 may be a region doped with P-type impurities at a doping concentration lower than the doping concentration of the first P-type region 1010.

[0161] The second P-type region 1020 is not positioned below the first P-type region 1010, leaving the first P-type region 1010 open, thereby reducing the amplification region and decreasing the sensitivity of the first SPAD (SPAD_C).

[0162] On the other hand, the second P-type region 1020 can prevent the edge breakdown phenomenon between the first N-type region 1110 and the first P-type region 1010 by forming a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010.

[0163] FIG. 10c is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10c, there is shown a cross-sectional structure 1000-3 cut along any one of the first line (A-A') to the third line (C-C') in FIGS. 9a to 9c.

[0164] The cross-sectional structure 1000-3 is substantially similar to the cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. Cross-sectional structure 1000-3 may include a first P-type region 1010, a second P-type region 1020, a third P-type region 1030, a first N-type region 1110, a second N-type region 1120, and a third N-type region 1130.

[0165] The second P-type region 1020 is disposed adjacent to a third P-type region 1030 on both the left and right sides of the first P-type region 1010 and may have a greater depth than the first P-type region 1010 and the third P-type region 1030. The second P-type region 1020 may be a region doped with P-type impurities at a doping concentration lower than the doping concentration of the first P-type region 1010.

[0166] The second P-type region 1020 is not disposed below the first P-type region 1010, thereby making it possible to reduce the amplification region and decrease the sensitivity of the first SPAD (SPAD_C).

[0167] On the other hand, the second P-type region 1020 can prevent the edge breakdown phenomenon between the first N-type region 1110 and the first P-type region 1010 by forming a PN junction with the N-type substrate between the first N-type region 1110 and the first P-type region 1010.

[0168] The third P-type region 1030 is disposed inside the second P-type region 1020 and in contact with the second P-type region 1020, and surrounding the first P-type region 1010, and may have a depth deeper than the first P-type region 1010 and shallower than the second P-type region 1020. The third P-type region 1030 may be a region doped with P-type impurities at a doping concentration lower than that of the first P-type region 1010 and higher than that of the second P-type region 1020.

[0169] The third P-type region 1030 is disposed below the first P-type region 1010 and expands the amplification region to improve the sensitivity of the first SPAD (SPAD_C) and also functions as a double guard ring together with the second P-type region 1020 to prevent edge breakdown.

[0170] FIG. 10d is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10d, there is shown a cross-sectional structure 1000-4 cut along any one of the first line (A-A') to the third line (C-C') in FIGS. 9a to 9c.

[0171] The cross-sectional structure 1000-4 is substantially similar to the cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. Cross-sectional structure 1000-4 may include a first P-type region 1010, a second P-type region 1020, a third P-type region 1030, a first N-type region 1110, a second N-type region 1120, and a third N-type region 1130.

[0172] The third P-type region 1030 is disposed in contact with the lower surface of the second P-type region 1020 and may have the same width as the second P-type region 1020 and a greater depth than the second P-type region 1020. The third P-type region 1030 may be a region doped with P-type impurities at a lower doping concentration than the second P-type region 1020.

[0173] The third P-type region 1030 is disposed below the second P-type region 1020, and can improve the sensitivity of the first SPAD (SPAD_C) by expanding the amplification region.

[0174] FIG. 10e is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10e, there is shown a cross-sectional structure 1000-5 cut along any one of the first line (A-A') to the third line (C-C') in FIGS. 9a to 9c.

[0175] Cross-sectional structure 1000-5 is substantially similar to cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. Cross-sectional structure 1000-5 may include a first P-type region 1010, a second P-type region 1020, a third P-type region 1030, a first N-type region 1110, and a second N-type region 1120.

[0176] The third P-type region 1030 contacts the lower surface of the second P-type region 1020 and the lower surface of the second N-type region 1120, and is disposed over the entire area of ​​the first SPAD (SPAD_C), and may have a depth greater than the second P-type region 1020 and the second N-type region 1120. The third P-type region 1030 may be a region doped with P-type impurities at a lower doping concentration than the second P-type region 1020. The third P-type region 1030 allows the third N-type region 1130 to be omitted.

[0177] The third P-type region 1030 is disposed over the entire area of ​​the first SPAD (SPAD_C) and can increase the amplification region, thereby improving the sensitivity of the first SPAD (SPAD_C). According to an embodiment, the third P-type region 1030 may be integrally formed and connected to the third P-type region of an adjacent pixel.

[0178] FIG. 10f is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 10f, there is shown a cross-sectional structure 1000-6 cut along any one of the first line (A-A') to the third line (C-C') in FIGS. 9a to 9c.

[0179] Cross-sectional structure 1000-6 is substantially similar to cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. Cross-sectional structure 1000 - 6 may include a first P-type region 1010 , a second P-type region 1020 , a first N-type region 1110 , a second N-type region 1120 , and a third N-type region 1130 .

[0180] The third N-type region 1130 contacts the lower surface of the second P-type region 1020 and the lower surface of the second N-type region 1120, and is disposed over the entire area of ​​the first SPAD (SPAD_C), and can have a depth greater than the second P-type region 1020 and the second N-type region 1120. The third N-type region 1130 may be a region doped with N-type impurities at a lower doping concentration than the second N-type region 1120.

[0181] The third N-type region 1130 allows the electric field (or reverse bias) caused by the first bias voltage (VB1) applied to the first N-type region 1110 to affect a wider region, even to a deeper position in the N-type substrate. Also, since the electric field caused by the first bias voltage (VB1) can be made to affect the entire first SPAD (SPAD_C), the first SPAD (SPAD_C) can be driven with a first bias voltage (VB1) lower than the first bias voltage (VB1) that must be applied to the cross-sectional structure 1000-1, thereby reducing power consumption.

[0182] However, by extending the third N-type region 1130 to the bottom of the second P-type region 1020, the sensitivity of the first SPAD (SPAD_C) may be reduced because the avalanche process may be inhibited due to the PN junction between the third N-type region 1130 and the second P-type region 1020 and the reduction in the area of ​​the N-type substrate where photons are detected. According to an embodiment, the third N-type region 1130 may be integrally formed and connected to the third N-type region of an adjacent pixel.

[0183] FIG. 11a is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to FIG. 11a, a cross-sectional structure 1100-1 cut along any one of the first line (A-A') to the third line (C-C') in FIG. 9a to FIG. 9c is shown. The cross-sectional structures (1100-1 to 1100-6) shown in FIG. 11a to FIG. 11f may be cross-sectional structures related to the case where the planar structure (900-1 to 900-3) in FIG. 9a to FIG. 9c corresponds to the second SPAD (SPAD_A). In addition, the cross-sectional structures (1100-1 to 1100-6) are described on the premise that they are structures formed on a P-type substrate (P-substrate) doped with P-type impurities, but the scope of the present invention is not limited thereto, and they may be structures formed on a well region doped with P-type impurities inside an N-type substrate doped with N-type impurities.

[0184] The cross-sectional structure 1100-1 may include a first N-type region 2110, a second N-type region 2120, a first P-type region 2010, a second P-type region 2020, and a third P-type region 2030. The materials, structures, and functions of the first to third P-type regions (2010 to 2030) and the first to third N-type regions (2110 to 2130) described in Figures 11a to 11f are substantially similar to the materials, structures, and functions of the first to third P-type regions (1010 to 1030) and the first to third N-type regions (1110 to 1130) described in the corresponding Figures 10a to 10f, and some differences will be mentioned separately.

[0185] The first N-type region 2110 may correspond to the output node (ON) of the planar structure (900-1 to 900-3) and may be a region doped with N-type impurities.

[0186] The second N-type region 2120 surrounds the first N-type region 2110 and may have a width greater than the first N-type region 2110 and a depth greater than the first N-type region 2110. The second N-type region 2120 may be a region doped with N-type impurities at a doping concentration lower than the doping concentration of the first N-type region 2110.

[0187] The first P-type region 2010 may correspond to a bias node (BN) of the planar structure (900-1 to 900-3) and may be a region doped with P-type impurities.

[0188] The second P-type region 2020 contacts the lower surface of the first P-type region 2010, and may have the same width as the first P-type region 2010 and a greater depth than the first P-type region 2010. The second P-type region 2020 may be a region doped with P-type impurities at a doping concentration lower than the doping concentration of the first P-type region 2010.

[0189] The third P-type region 2030 may be in contact with the lower surface of the second P-type region 2020, and may have the same width as the second P-type region 2020, and may have a greater depth than the second P-type region 2020. The third P-type region 2030 may be a region doped with P-type impurities at a doping concentration lower than the doping concentration of the second P-type region 2020. On the other hand, the third P-type region 2030 may be a region doped with P-type impurities at a doping concentration higher than the doping concentration of the P-type substrate.

[0190] The P-type region including the first P-type region 2010, the second P-type region 2020, the third P-type region 2030, and the P-type substrate, and the N-type region including the first N-type region 2110 and the second N-type region 2120 can form a second SPAD (SPAD_A).

[0191] Photons of the incoming light (RL) transmitted through the lower surface of the P-type substrate cause photoelectric conversion to generate electrons 1101 and holes. Although FIG. 11a shows three electrons 1101 being generated at a specific position by the incoming light (RL), the scope of the present invention is not limited thereto, and at least one electron 1101 may be generated at any position within the cross-sectional structure 1100-1, and an avalanche process may proceed. When the avalanche process by photons proceeds, the doping concentration increases in the second N-type region 2120 and the first N-type region 2110 in that order, and thus an amplification of carriers (i.e., electrons 1101) may occur in the direction of the first N-type region 2110. The second N-type region 2120 may be defined as an amplification region in that it causes such an amplification of carriers and increases the detection speed of the carriers, thereby improving sensitivity.

[0192] The doping concentration decreases in the order of the first P-type region 2010, the second P-type region 2020, the third P-type region 2030, and the P-type substrate, so that the electric field (or reverse bias) caused by the second bias voltage (VB2) applied to the first P-type region 2010 can affect a deeper position in the P-type substrate. This allows the avalanche process to proceed even with photons that reach a deep position in the P-type substrate, improving the sensitivity of the second SPAD (SPAD_A). Furthermore, by forming the third P-type region 2030 to a deep position close to the lower surface of the P-type substrate, it can also contribute to pixel isolation between adjacent pixels.

[0193] On the other hand, since the second N-type region 2120 forms a PN junction with the P-type substrate between the first P-type region 2010 and the first N-type region 2110, the edge breakdown phenomenon between the first P-type region 2010 and the first N-type region 2110 can be prevented.

[0194] Each of FIGS. 11b to 11f is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. Referring to Figures 10b to 10f and 11b to 11f, cross-sectional structures (1100-2 to 1100-6) cut along any one of the first line (A-A') to third line (C-C') in Figures 9a to 9c are shown.

[0195] Each of the cross-sectional structures (1100-2 to 1100-6) has substantially the same structure and operation as each of the cross-sectional structures (1000-2 to 1000-6) described above, except that the conductivity types of the respective components are opposite to each other, so a duplicated description will be omitted.

[0196] FIG. 12a is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. 10a and 12a, a cross-sectional structure 1200-1 cut along any one of the first line (A-A') to the third line (C-C') in Fig. 9a to Fig. 9c is shown. The cross-sectional structure 1200-1 may correspond to a modified embodiment of the cross-sectional structure 1000-1 described in Fig. 10a.

[0197] Cross-sectional structure 1200-1 is substantially similar to cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. The third N-type region 1130 may be in contact with the lower surface of the second N-type region 1120 and may have a depth greater than that of the second N-type region 1120. The third N-type region 1130 may extend horizontally toward the center of the cross-sectional structure 1200-1 so as to have a width greater than that of the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-1 may not extend to contact each other, but may form an opening region near the center of the cross-sectional structure 1200-1. The size of the opening region may be determined experimentally in consideration of the sensitivity of the first SPAD (SPAD_C) and the magnitude of noise due to background light.

[0198] The light incident on the first SPAD (SPAD_C) may include arriving light (RL) reflected from the target object 1 and ambient light (AL) which causes background noise. Due to the effect of the lens module 20 and the microlenses 804 which focus the arriving light (RL) on the pixel array 110, the arriving light (RL) may be more concentrated at the center of the first SPAD (SPAD_C) compared to the ambient light (AL) which is uniformly incident throughout the first SPAD (SPAD_C).

[0199] Since the third N-type region 1130 may hinder the transmission of light, by arranging the third N-type region 1130 in an area excluding the opening area near the center of the first SPAD (SPAD_C), the occurrence of an avalanche process caused by background light (AL) can be minimized and the avalanche process caused by the arriving light (RL) concentrated at the center of the first SPAD (SPAD_C) can be induced, thereby reducing the effects of noise caused by background light.

[0200] FIG. 12b is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. 10b and 12b, a cross-sectional structure 1200-2 cut along any one of the first line (A-A') to the third line (C-C') in Fig. 9a to Fig. 9c is shown. The cross-sectional structure 1200-2 may correspond to a modified embodiment of the cross-sectional structure 1000-2 described in Fig. 10b.

[0201] Cross-sectional structure 1200-2 is substantially similar to cross-sectional structure 1000-2 described above except for some differences, and therefore the differences will be mainly described. The third N-type region 1130 may be in contact with a lower surface of the second N-type region 1120 and may have a depth greater than that of the second N-type region 1120. The third N-type region 1130 may extend horizontally toward the center of the cross-sectional structure 1200-2 so as to have a width greater than that of the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-2 may not extend in contact with each other, and an opening region may be formed near the center of the cross-sectional structure 1200-2.

[0202] The function and effect of the third N-type region 1130 are substantially similar to the function and effect of the third N-type region 1130 in the cross-sectional structure 1200-1, and therefore a duplicated description will be omitted.

[0203] FIG. 12c is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. 10c and 12c, a cross-sectional structure 1200-3 cut along any one of the first line (A-A') to the third line (C-C') in Fig. 9a to Fig. 9c is shown. The cross-sectional structure 1200-3 may correspond to a modified embodiment of the cross-sectional structure 1000-3 described in Fig. 10c.

[0204] Cross-sectional structure 1200-3 is substantially similar to cross-sectional structure 1000-3 described above except for some differences, and therefore the differences will be mainly described. The third N-type region 1130 may be in contact with a lower surface of the second N-type region 1120 and may have a depth greater than that of the second N-type region 1120. The third N-type region 1130 may extend horizontally toward the center of the cross-sectional structure 1200-3 so as to have a width greater than that of the second N-type region 1120. However, the third N-type regions 1130 disposed on both sides of the cross-sectional structure 1200-3 may not extend to be in contact with each other, and an opening region may be formed near the center of the cross-sectional structure 1200-3.

[0205] The function and effect of the third N-type region 1130 are substantially similar to the function and effect of the third N-type region 1130 in the cross-sectional structure 1200-1, and therefore a duplicated description will be omitted.

[0206] 12a to 12c have described the modified embodiment of Figures 10a to 10c, but the scope of the present invention is not limited thereto, and substantially the same technical idea can be realized in the modified embodiment of Figures 11a to 11c. That is, the third P-type region 1030 of the cross-sectional structures (1100-1 to 1100-3) can extend to the center while forming an opening region near the center of the cross-sectional structures (1100-1 to 1100-3).

[0207] FIG. 13 is a diagram showing still another example of the cross-sectional structure cut along any one of the first to third lines in FIGS. 9a to 9c. 10d and 13, a cross-sectional structure 1300 cut along any one of the first line (A-A') to the third line (C-C') in Fig. 9a to Fig. 9c is shown. The cross-sectional structure 1300 may correspond to a modified embodiment of the cross-sectional structure 1000-4 described in Fig. 10d.

[0208] Cross-sectional structure 1300 is substantially similar to cross-sectional structure 1000-4 described above except for some differences, and therefore the following description will focus on the differences. The cross-sectional structure 1300 may include, instead of the third P-type region 1030, third P-type regions 1030-1, 1030-2 disposed above and below.

[0209] The width of the third P-type region 1030-1 may be greater than the width of the third P-type region 1030-2 and less than the width of the second P-type region 1020. That is, the widths of the P-type regions 1020, 1030-1, and 1030-2 may decrease downward.

[0210] Since the incident light (RL) is infrared light, it may have a relatively large penetration depth into the semiconductor substrate compared to the background light (AL) which has a high proportion of visible light. Since the amplification region corresponding to the P-type regions 1020, 1030-1, and 1030-2 is an area where an avalanche process is likely to occur due to the incident light, the width of the P-type regions 1020, 1030-1, and 1030-2 becomes smaller toward the bottom, thereby minimizing the occurrence of the avalanche process due to the background light (AL) which has a relatively small penetration depth.

[0211] In addition, the doping concentration of the third P-type region 1030-1 may be higher than the doping concentration of the third P-type region 1030-2 and lower than the doping concentration of the second P-type region 1020. That is, the doping concentrations of the P-type regions 1020, 1030-1, and 1030-2 may decrease downward.

[0212] This strengthens the electric field from the P-type regions 1020, 1030-1, and 1030-2 toward the first P-type region 1010, thereby allowing an avalanche process to occur due to the arriving light (RL) that is incident near the center of the first SPAD (SPAD_C) but has a weaker light intensity and a smaller penetration depth into the semiconductor substrate, thereby improving the sensitivity of the first SPAD (SPAD_C).

[0213] Also, although an embodiment in which the number of third P-type regions 1030-1, 1030-2 is two has been described, the scope of the present invention is not limited to this, and may correspond to three or more.

[0214] Although the modified embodiment of Fig. 10d has been described in Fig. 13, the scope of the present invention is not limited thereto, and substantially the same technical idea may be realized in the modified embodiment of Fig. 11d. That is, the third N-type region 1130 of the cross-sectional structure 1100-4 may be replaced with two or more third N-type regions having a narrower width and a lower doping concentration toward the bottom.

[0215] FIG. 14a is a diagram showing an example of a modified embodiment of the cross-sectional structure shown in FIG. 10a. 10a and 14a, there is shown a cross-sectional structure 1400-1 which is an alternative embodiment of the cross-sectional structure 1000-1 described in FIG. 10a.

[0216] Cross-sectional structure 1400-1 is substantially similar to cross-sectional structure 1000-1 described above except for some differences, and therefore the differences will be mainly described. The cross-sectional structure 1400-1 may include a plurality of first P-type regions (1010-1 to 1010-3) instead of one first P-type region 1010. The plurality of first P-type regions (1010-1 to 1010-3) may have substantially similar characteristics (e.g., the same material, the same function) as the first P-type region 1010.

[0217] The first P-type regions (1010-1 to 1010-3) may be arranged at a predetermined interval in the second P-type region 1020. Although the number of the first P-type regions (1010-1 to 1010-3) is shown as three in FIG. 14a, two or four or more first P-type regions may be included in the cross-sectional structure as necessary. The first P-type regions (1010-1 to 1010-3) may be physically separated from each other, but may be electrically connected to each other and operate as one output node (ON). The electrical connection between the first P-type regions (1010-1 to 1010-3) may be performed via metal lines of a wiring layer disposed on the upper portion of a semiconductor substrate, but the scope of the present invention is not limited thereto.

[0218] By arranging multiple first P-type regions (1010-1 to 1010-3), the detection efficiency of carriers transmitted by the avalanche process can be further improved compared to when a single first P-type region having the same area as each of the first P-type regions (1010-1 to 1010-3) is arranged.

[0219] Furthermore, compared to when multiple first P-type regions (1010-1 to 1010-3) are connected and arranged to form a single first P-type region, by arranging the multiple first P-type regions (1010-1 to 1010-3) separately, the detection efficiency of carriers transmitted by the avalanche process due to background light is further lowered, thereby reducing the effects of noise.

[0220] FIG. 14b is a diagram showing another example of a modified embodiment of the cross-sectional structure shown in FIG. 10a. 10a and 14b, there is shown a cross-sectional structure 1400-2 which is an alternative embodiment of the cross-sectional structure 1000-1 described in FIG. 10a.

[0221] Cross-sectional structure 1400-2 is substantially similar to cross-sectional structure 1000-1 described above except for some differences, and therefore the following description will focus on the differences. The cross-sectional structure 1400-2 may include a plurality of first P-type regions (1010-1 to 1010-3) and a plurality of second P-type regions (1020-1 to 1020-3) instead of one first P-type region 1010 and one second P-type region 1020. The plurality of first P-type regions (1010-1 to 1010-3) may have substantially similar characteristics (e.g., the same material, the same function) as the first P-type region 1010. Also, the plurality of second P-type regions (1020-1 to 1020-3) may have substantially similar characteristics (e.g., the same material, the same function) as the second P-type region 1020.

[0222] The first detection region consisting of the first P-type region 1010-1 and the second P-type region 1020-1 surrounding the first P-type region 1010-1, the second detection region consisting of the first P-type region 1010-2 and the second P-type region 1020-2 surrounding the first P-type region 1010-2, and the third detection region consisting of the first P-type region 1010-3 and the second P-type region 1020-3 surrounding the first P-type region 1010-3 may be spaced apart from each other at a predetermined interval. Also, although FIG. 14b shows the number of detection regions as three, two or four or more detection regions may be included in the cross-sectional structure as necessary. The first P-type regions (1010-1 to 1010-3) may be physically separated from each other, but may be electrically connected to each other and operate as one output node (ON). The electrical connection between the plurality of first P-type regions (1010-1 to 1010-3) may be performed via metal lines of a wiring layer disposed on the upper portion of the semiconductor substrate, but the scope of the present invention is not limited thereto.

[0223] By arranging multiple detection regions, the detection efficiency of carriers transmitted by the avalanche process can be further improved compared to when a single detection region having the same area as each detection region is arranged.

[0224] Furthermore, compared to a case in which multiple first P-type regions (1010-1 to 1010-3) are connected and arranged to form a single first P-type region, by arranging not only multiple first P-type regions (1010-1 to 1010-3) but also separate them on a detection region basis, the detection efficiency of carriers transmitted by the avalanche process due to background light can be further reduced, thereby reducing the effects of noise.

[0225] FIG. 15 is a diagram showing an example of a planar structure for a plurality of pixels. 15, a planar structure 1500 of a sensor layer of the first to fourth pixels (PX1 to PX4) is shown. Each of the first to fourth pixels (PX1 to PX4) may correspond to a pixel (PX) included in the pixel array 110 of FIG. 1, and although the first to fourth pixels (PX1 to PX4) will be described as an example, substantially the same technical idea can be applied to the other pixels (PX).

[0226] The first to fourth pixels (PX1 to PX4) may be the same type of SPAD pixels. That is, the SPAD included in each of the first to fourth pixels (PX1 to PX4) may be the same SPAD as the first SPAD (SPAD_C) or the second SPAD (SPAD_A). When the SPAD included in each of the first to fourth pixels (PX1 to PX4) is the first SPAD (SPAD_C), the output nodes (ON1 to ON4) may correspond to the anode of the first SPAD (SPAD_C), and the bias nodes (BN1a to BN4d) may correspond to the cathode of the first SPAD (SPAD_C). If the SPAD included in each of the first to fourth pixels (PX1 to PX4) is the second SPAD (SPAD_A), the output nodes (ON1 to ON4) can correspond to the cathode of the second SPAD (SPAD_A), and the bias nodes (BN1a to BN4d) can correspond to the anode of the second SPAD (SPAD_A).

[0227] The first pixel (PX1) can include a first output node (ON1) having a cross shape (cross) that is disposed at the center of the first pixel (PX1), and a plurality of first bias nodes (BN1a to BN1d) that are disposed a predetermined distance away from the first output node (ON1) and at each vertex of the first pixel (PX).

[0228] By arranging each of the first bias nodes (BN1a to BN1d) at each vertex of the first pixel (PX1), the first output node (ON) can have a cross shape to prevent the distance between each of the first bias nodes (BN1a to BN1d) and the first output node (ON1) from becoming too close and causing an edge breakdown phenomenon. The second to fourth pixels (PX2 to PX4) have a structure corresponding to that of the first pixel (PX1), and therefore a duplicated description will be omitted.

[0229] By arranging each bias node (BN1a to BN4d) at each vertex of the first to fourth pixels (PX1 to PX4), the bias nodes of adjacent pixels (for example, BN1b and BN2a, or BN1d, BN2c, BN3b and BN4a) can be formed integrally.

[0230] By integrally forming adjacent bias nodes, the degree of difficulty of the process for forming the bias nodes can be improved, and a design margin for wiring for supplying a bias voltage can be secured. In addition, by reducing the number of bias nodes to which a bias voltage must be supplied, the power consumption for supplying the bias voltage can be reduced.

[0231] FIG. 16 is a diagram showing another example of a planar structure for a plurality of pixels. 16, a planar structure 1600 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown. The planar structure 1600 is substantially similar to the planar structure 1500 described above, except for some differences, and therefore the differences will be mainly described.

[0232] The first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may each have a circular shape. Typically, by having the first output node (ON1) have a circular shape, the edge breakdown phenomenon can be minimized by arranging the first bias nodes (BN1a to BN1d) so that the distance between the first output node (ON1) and each of the first bias nodes (BN1a to BN1d) is not closer than necessary.

[0233] FIG. 17 is a diagram showing still another example of a planar structure for a plurality of pixels. 17, a planar structure 1700 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown. The planar structure 1700 is substantially similar to the planar structure 1500 described above, except for some differences, and therefore the differences will be mainly described.

[0234] The first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may each have a circular shape. The first to fourth bias nodes (BN1 to BN4) of the first to fourth pixels (PX1 to PX4), respectively, are spaced apart from and surround the corresponding output nodes (ON1 to ON4), but may be disposed along the edges of the corresponding pixels (PX1 to PX4).

[0235] By arranging each bias node (BN1 to BN4) along the edges of the first to fourth pixels (PX1 to PX4), the bias nodes (for example, BN1 to BN4) of adjacent pixels can be integrally formed.

[0236] FIG. 18 is a diagram showing yet another example of a planar structure for a plurality of pixels. 18, a planar structure 1800 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown. The planar structure 1800 is substantially similar to the planar structure 1500 described above, except for some differences, and therefore the differences will be mainly described.

[0237] The first to fourth output nodes (ON1 to ON4) of the first to fourth pixels (PX1 to PX4) may each have a circular shape. The first to fourth bias nodes (BN1a to BN4d) of the first to fourth pixels (PX1 to PX4) are spaced apart from and surround the output nodes (ON1 to ON4), but can be disposed at the vertices of the pixels (PX1 to PX4). Also, the first to fourth bias nodes (BN1a to BN4d) can be formed into a circular inner shape so that the distance between the output nodes (ON1 to ON4) is constant. This makes it possible to prevent an edge breakdown phenomenon that occurs when the distance between the first to fourth bias nodes (BN1a to BN4d) and the output nodes (ON1 to ON4) becomes closer than necessary at a specific position.

[0238] By arranging each bias node (BN1a to BN4d) at each vertex of the first to fourth pixels (PX1 to PX4), the bias nodes of adjacent pixels (for example, BN1b and BN2a, or BN1d, BN2c, BN3b and BN4a) can be formed integrally.

[0239] FIG. 19 is a diagram showing yet another example of a planar structure for a plurality of pixels. 19, a planar structure 1900 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown in schematic form. The planar structure 1900 is substantially similar to the planar structure 1500 described above, except for some differences, and therefore the differences will be mainly described.

[0240] In the planar structure 1900, the first to fourth pixels (PX1 to PX4) may further include first to fourth guard rings (GR1 to GR4), respectively. The first to fourth guard rings (GR1 to GR4) may surround the first to fourth output nodes (ON1 to ON4), respectively, and may be spaced a predetermined distance from the first to fourth output nodes (ON1 to ON4), respectively.

[0241] The first to fourth guard rings (GR1 to GR4) can prevent an edge breakdown phenomenon by electrically isolating the first to fourth output nodes (ON1 to ON4) from the adjacent first to fourth bias nodes (BN1a to BN4d), respectively.

[0242] The first to fourth guard rings (GR1 to GR4) may have the same conductivity type as the first to fourth output nodes (ON1 to ON4) or the same conductivity type as the first to fourth bias nodes (BN1a to BN4d).

[0243] FIG. 20 is a diagram showing yet another example of a planar structure for a plurality of pixels. 20, a planar structure 2000 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown. The planar structure 2000 is substantially similar to the planar structure 1500 described above except for some differences, and therefore the differences will be mainly described.

[0244] In the planar structure 2000, the first to fourth pixels (PX1 to PX4) may further include first to fourth guard rings (GR1a to GR4d), respectively.

[0245] Each of the first guard rings (GR1a to GR1d) has an angle bracket shape surrounding each of the first bias nodes (BN1a to BN1d), and can be spaced a predetermined distance from each of the first bias nodes (BN1a to BN1d).

[0246] Each of the first guard rings (GR1a to GR1d) can electrically isolate each of the first bias nodes (BN1a to BN1d) from the adjacent first output node (ON1) to prevent an edge breakdown phenomenon.

[0247] The conductivity type of the first guard rings (GR1a to GR1d) may be the same as that of the first output node (ON1) or the same as that of the first bias nodes (BN1a to BN1d).

[0248] The second to fourth guard rings (GR2a to GR4d) can each have a structure and conductivity type corresponding to the first guard ring (GR1a to GR1d).

[0249] FIG. 21 is a diagram showing yet another example of a planar structure for a plurality of pixels. 21, a planar structure 2100 of the sensor layers of the first to fourth pixels (PX1 to PX4) is shown. The planar structure 2100 is substantially similar to the planar structure 1500 described above except for some differences, and therefore the differences will be mainly described.

[0250] In the planar structure 2100, the first to fourth pixels (PX1 to PX4) may further include first to fourth guard rings (GR1 to GR4). The first to fourth guard rings (GR1 to GR4) may be disposed so as to surround and be in contact with the first to fourth output nodes (ON1 to ON4), respectively. Also, the first to fourth guard rings (GR1 to GR4) may extend in the up, down, left and right directions with the first to fourth output nodes (ON1 to ON4) at the center, respectively, and may have a shape similar to a cross shape as a whole. This allows the first to fourth guard rings (GR1 to GR4) to be formed integrally.

[0251] The first to fourth guard rings (GR1 to GR4) can prevent an edge breakdown phenomenon by electrically isolating the first to fourth output nodes (ON1 to ON4) from the adjacent first to fourth bias nodes (BN1a to BN4d), respectively.

[0252] The first to fourth guard rings (GR1 to GR4) may have the same conductivity type as the first to fourth output nodes (ON1 to ON4), thereby expanding the amplification region and improving the sensitivity of the SPAD.

[0253] The guard ring described in Figures 19 to 21 has been described using the guard ring applied to the planar structure 1500 of Figure 15 as an example, but the guard ring described in Figures 19 to 21 can also be similarly applied to the planar structures (1600 to 1800) of Figures 16 to 18.

[0254] FIG. 22a is a diagram showing an example of a cross-sectional structure taken along the fourth line in FIG. 15 and 22a, there is shown a cross-sectional structure 2200-1 obtained by cutting the first pixel (PX1) and the fourth pixel (PX4) along the fourth line (D-D') in Fig. 15. Fig. 22a illustrates a cross section obtained by cutting the first pixel (PX1) and the fourth pixel (PX4) as an example, but the cross sections obtained by cutting the second pixel (PX2) and the third pixel (PX3) and the cross sections of the planar structures in Figs. 16 to 18 may also have substantially similar structures except for some differences (e.g., the width of the structure, etc.).

[0255] The cross-sectional structure 2200-1 may include, inside a semiconductor substrate, a first output node (ON1) and a fourth output node (ON4) arranged apart from each other, a first bias node (BN1a) arranged to the left of the first output node (ON1), first and fourth bias nodes (BN1d, BN4a) arranged between the first output node (ON1) and the fourth output node (ON4), and a fourth bias node (BN4d) arranged to the right of the fourth output node (ON4).

[0256] The depth of the first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d) can be greater than the depth of the first and fourth output nodes (ON1, ON4). The first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d) are formed deep to a position close to the bottom surface of the semiconductor substrate, thereby hindering the movement of carriers (C) generated inside a particular pixel, thereby contributing to pixel isolation from adjacent pixels.

[0257] Carriers (C) generated by an avalanche process caused by photons incident inside a particular pixel can be transmitted to the corresponding output node (ON1, ON4) by the electric field generated by the first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d) formed deep near the bottom surface of the semiconductor substrate, and can be detected.

[0258] FIG. 22b is a diagram showing an example of a cross-sectional structure taken along the fifth line in FIG. 19 and 22b, a cross-sectional structure 2200-2 is shown in which the first pixel (PX1) and the fourth pixel (PX4) are cut along the fifth line (E-E') in Fig. 19. Fig. 22b illustrates a cross section of the first pixel (PX1) and the fourth pixel (PX4) as an example, but the cross sections of the second pixel (PX2) and the third pixel (PX3) and the cross sections of the planar structures of Figs. 20 and 21 may have substantially similar structures except for some differences (e.g., widths and positions of the components).

[0259] The cross-sectional structure 2200-2 may include, inside a semiconductor substrate, a first output node (ON1) and a fourth output node (ON4) arranged apart from each other, a first bias node (BN1a) arranged on the left side of the first output node (ON1), first and fourth bias nodes (BN1d, BN4a) arranged between the first output node (ON1) and the fourth output node (ON4), a fourth bias node (BN4d) arranged on the right side of the fourth output node (ON4), a first guard ring (GR1) arranged on both the left and right sides of the first output node (ON1), and a fourth guard ring (GR4) arranged on both the left and right sides of the fourth output node (ON4).

[0260] The first and fourth output nodes (ON1, ON4) and the first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d) are substantially similar to those described in FIG. 22a, and therefore a duplicated description will be omitted.

[0261] The depth of the first and fourth guard rings (GR1, GR4) can be less than the depth of the first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d) and greater than the depth of the first and fourth output nodes (ON1, ON4).

[0262] The first and fourth guard rings (GR1, GR4) can electrically isolate the first and fourth output nodes (ON1, ON4) from the adjacent first and fourth bias nodes (BN1a, BN1d, BN4a, BN4d), respectively, to prevent an edge breakdown phenomenon.

[0263] FIG. 23a is a diagram showing an example of a planar structure for pixels included in a pixel array. 16 and 23a, there is shown a planar structure 2300-1 for a sensor layer of a pixel (PX) included in the pixel array 110. The planar structure 2300-1 will be described taking as an example an embodiment modified based on the first pixel (PX1) of FIG. 16 as a representative example, but the technical idea of ​​the present invention can be substantially similarly applied to the other pixels shown in FIGS. 15 to 21.

[0264] The planar structure 2300-1 may include a plurality of first bias nodes (BN1a to BN1d) arranged at each vertex of the planar structure 2300-1, a circular first bias node (BN1e) arranged at the center of the planar structure 2300-1, and a first output node (ON1) surrounding the first bias node (BN1e).

[0265] That is, in the pixel shown by the planar structure 2300-1, unlike the first pixel (PX1) in Fig. 16, a first bias node (BN1e) may be added and placed in the center of the pixel. The first bias node (BN1e) may be defined as a central bias node.

[0266] The first output node (ON1) may have a circular ring shape surrounding the first bias node (BN1e) at a predetermined distance from the first bias node (BN1e). In the example of FIG. 23a, the first bias node (BN1e) may have a circular ring shape so that the distance between the first output node (ON1) and the first bias node (BN1e) is maintained constant due to the first bias node (BN1e) having a circular shape. The scope of the present invention is not limited thereto, and the first output node (ON1) may have a ring shape corresponding to the shape of the first bias node (BN1e) so that the distance between the first output node (ON1) and the first bias node (BN1e) is maintained constant.

[0267] FIG. 23b is a diagram showing an example of a cross section of the planar structure shown in FIG. 23a. 23a and 23b, a cross-sectional structure 2300-2 is shown in which the planar structure 2300-1 of FIG. 23a is cut along the sixth line (F-F'). In this disclosure, the cross-sectional structure 2300-2 in the back-slash direction is described, but since substantially the same description can be applied to the cross-sectional structure in the slash direction, a duplicated description will be omitted.

[0268] The cross-sectional structure 2300-2 may include, in the semiconductor substrate, a first output node (ON1) spaced apart from each other, a first bias node (BN1e) between the first output nodes (ON1), a first bias node (BN1a) on the left side of the left first output node (ON1), and a first bias node (BN1d) on the right side of the right first output node (ON1). The depth of the first output node (ON1) may be deeper than the depth of the first bias nodes (BN1a, BN1d, BN1e), but the scope of the present invention is not limited thereto.

[0269] The first bias node (BN1e) can receive a bias voltage (VB) for causing the SPAD corresponding to the cross-sectional structure 2300-2 to enter the Geiger mode. Here, the bias voltage (VB) may be the first bias voltage (VB1) or the second bias voltage (VB2), but in the following description, it is assumed that the bias voltage (VB) is the first bias voltage (VB1). In addition, the first bias nodes BN1a and BN1d may be connected to the ground and may receive a ground voltage (eg, 0V).

[0270] A voltage difference between the first bias nodes (BN1a, BN1e) allows a first current (I1) to flow between the first bias nodes (BN1a, BN1e) through the semiconductor substrate. Also, a voltage difference between the first bias nodes (BN1d, BN1e) allows a second current (I2) to flow between the first bias nodes (BN1d, BN1e) through the semiconductor substrate. The paths of the first current (I1) and the second current (I2) shown in FIG. 23b are exemplary and are not limited to the paths shown, and the currents can flow through various paths.

[0271] Furthermore, when the bias voltage (VB) is the second bias voltage (VB2), the first current (I1) and the second current (I2) can flow in opposite directions. Carriers (C) generated by photons incident in the semiconductor substrate can move along the flow of the first current (I1) or the second current (I2), and an avalanche breakdown can be triggered by the electric field toward the first output node (ON1).

[0272] That is, even if the carriers (C) generated by the photons incident on the semiconductor substrate are unlikely to cause an avalanche process, the carriers (C) can be moved via the current flowing between the bias nodes to induce the avalanche process, thereby improving the sensitivity of the SPAD.

[0273] 8a to 23b, various structures for increasing or decreasing the sensitivity (PDE or DCR) of the SPAD have been described. In the pixel array 110 according to the present disclosure, a first SPAD (SPAD_C) and a second SPAD (SPAD_A) having different characteristics may be disposed, and the structure of the first SPAD (SPAD_C) and the structure of the second SPAD (SPAD_A) optimized according to the design purpose of the imaging device (ID) may be selected. For example, when aiming to maximize the sensitivity difference between the first SPAD (SPAD_C) and the second SPAD (SPAD_A) and expand the dynamic range, a structure for minimizing the sensitivity may be selected and applied to the first SPAD (SPAD_C), and a structure for maximizing the sensitivity may be selected and applied to the second SPAD (SPAD_A).

[0274] In addition, if necessary, the first SPADs (SPAD_C) included in one pixel array 110 may have different structures, or the second SPADs (SPAD_A) included in one pixel array 110 may have different structures. For example, a structure capable of relatively increasing sensitivity may be applied to the first SPAD (SPAD_C) in a region disposed near the edge of the pixel array 110 and where light receiving efficiency (or amount of light received per area) is reduced, and a structure capable of relatively decreasing sensitivity may be applied to the first SPAD (SPAD_C) in a region disposed near the optical axis of the pixel array 110 and where light receiving efficiency is high.

[0275] The structures, operations, positions of impurity regions, doping concentrations, and the like of the SPAD and pixels described in this disclosure are merely exemplary and may be modified as desired within the scope of the technical concept of the present invention.

Claims

1. A first pixel including a first single photon avalanche diode (SPAD) having a cathode to which a first bias voltage is applied; a second pixel including a second SPAD having an anode to which a second bias voltage is applied; a selection circuit for selecting one of the first pixel and the second pixel; 13. An image sensing device comprising:

2. 2. The image sensing device of claim 1, wherein the selection circuit includes a mode selector that activates one of the first pixel and the second pixel in response to a mode selection signal based on at least one of illuminance information, power information, user selection information, or temperature information.

3. the first pixel includes a first control transistor connected between the cathode of the first SPAD and the mode selector and receiving a mode selection voltage responsive to the mode selection signal; The image sensing device of claim 2 , wherein the second pixel comprises a second control transistor connected between the anode of the second SPAD and the mode selector, the second control transistor receiving the mode selection voltage.

4. 4. The image sensing device of claim 3, wherein when the mode selection voltage is the first bias voltage, the first control transistor is turned on and the first bias voltage is transmitted to the cathode of the first SPAD.

5. 4. The image sensing device of claim 3, wherein when the mode selection voltage is the second bias voltage, the second control transistor is turned on and the second bias voltage is transmitted to the anode of the second SPAD.

6. the first control transistor is a PMOS; 4. The image sensing device of claim 3, wherein the second control transistor is an NMOS.

7. the first pixel includes a first control transistor connected between the cathode of the first SPAD and a node to which the first bias voltage is applied, the first control transistor receiving a mode selection voltage in response to the mode selection signal; 3. The image sensing device of claim 2, wherein the second pixel comprises a second control transistor connected between the anode of the second SPAD and a node to which the second bias voltage is applied, the second control transistor receiving the mode selection voltage.

8. 8. The image sensing device of claim 7, wherein when the mode selection voltage is a first activation voltage lower than the first bias voltage, the first control transistor is turned on and the first bias voltage is transmitted to the cathode of the first SPAD.

9. 8. The image sensing device of claim 7, wherein when the mode selection voltage is a second activation voltage higher than the second bias voltage, the second control transistor is turned on and the second bias voltage is transmitted to the anode of the second SPAD.

10. the first control transistor is a PMOS; 8. The image sensing device of claim 7, wherein the second control transistor is an NMOS.

11. The image sensing device of claim 2 , wherein the mode selector activates the first pixel when the illuminance information indicates that an illuminance value is equal to or greater than a predetermined threshold.

12. The image sensing device of claim 2 , wherein the mode selector activates the second pixel when the illuminance information indicates that the illuminance value is less than a predetermined threshold.

13. The image sensing device of claim 1 , wherein the selection circuit includes an output selector that selects one of the output of the first pixel and the output of the second pixel in response to a mode selection signal based on illuminance information.

14. The image sensing device of claim 13 , wherein the output selector selects the output of the first pixel if the illuminance information indicates that the illuminance value is greater than or equal to a predetermined threshold.

15. The image sensing device of claim 2 , wherein the output selector selects the output of the second pixel if the illuminance information indicates that the illuminance value is less than a predetermined threshold.

16. The image sensing device of claim 1 , wherein the first pixels and the second pixels are alternately arranged along a first direction.

17. The first pixels and the second pixels are arranged in units of an M×N matrix such that identical pixels are adjacent to each other, The image sensing device according to claim 1 , wherein at least one of the M and the N is a natural number equal to or greater than two.

18. 2. The image sensing device of claim 1, wherein each of the first pixel and the second pixel includes a sensor layer including the first SPAD or the second SPAD, and a logic layer including circuitry for driving the first SPAD or the second SPAD.

19. The image sensing device of claim 1 , wherein the second pixel further comprises a first optical structure for increasing a sensitivity of the second SPAD.

20. The image sensing device of claim 19 , wherein the first optical structure comprises a plurality of relief structures that scatter light.

21. The image sensing device of claim 1 , wherein the first pixel further comprises a second optical structure for reducing a sensitivity of the first SPAD.

22. The image sensing device of claim 21 , wherein the second optical structure includes a light blocking structure disposed in at least a portion of the first pixel.

23. The first pixel is a first output node disposed at the center of the first pixel and corresponding to the anode of the first SPAD; 2. The image sensing device of claim 1, further comprising: a first bias node disposed to surround the first output node and corresponding to the cathode of the first SPAD.

24. the first output node is circular; 24. The image sensing device of claim 23, wherein the second output node has a circular ring shape.

25. the first output node is rectangular with rounded corners; 24. The image sensing device of claim 23, wherein the second output node has a square ring shape.

26. the first output node is rectangular with sharp corners; 24. The image sensing device of claim 23, wherein the second output node has a square ring shape.

27. The first pixel is a first P-type region disposed on an upper surface of a semiconductor substrate and corresponding to an anode of the first SPAD; 2. The image sensing device of claim 1, further comprising: a first N-type region spaced apart from the first P-type region and corresponding to the cathode of the first SPAD.

28. 28. The image sensing device of claim 27, wherein the first pixel further includes a second P-type region disposed to surround the first P-type region and including a P-type impurity doped at a doping concentration lower than a doping concentration of the first P-type region.

29. 30. The image sensing device of claim 28, wherein the first P-type region comprises a plurality of P-type regions spaced apart from one another within the second P-type region.

30. the first P-type region includes a plurality of P-type regions spaced apart from one another; The image sensing device of claim 28 , wherein each of the plurality of P-type regions is arranged to be surrounded by a corresponding second P-type region.

31. 28. The image sensing device of claim 27, wherein the first pixel further includes second P-type regions disposed on both sides of the first P-type region, having a depth greater than a depth of the first P-type region, and including P-type impurities doped at a doping concentration lower than a doping concentration of the first P-type region.

32. The first pixel is a second P-type region disposed on both sides of the first P-type region, the second P-type region having a depth greater than a depth of the first P-type region, and including a P-type impurity doped at a doping concentration lower than a doping concentration of the first P-type region; 28. The image sensing device of claim 27, further comprising: a third P-type region disposed between the first P-type region and the second P-type region so as to surround the first P-type region, having a depth deeper than a depth of the first P-type region, and containing P-type impurities doped at a doping concentration lower than a doping concentration of the second P-type region.

33. The image sensing device of claim 32 , wherein the third P-type region includes a plurality of P-type regions each having a narrower width and a lower doping concentration of P-type impurities closer to the bottom surface of the semiconductor substrate.

34. The first pixel is a second P-type region disposed adjacent to both sides of the first P-type region, having a depth greater than a depth of the first P-type region, and containing a P-type impurity doped at a doping concentration lower than a doping concentration of the first P-type region; 28. The image sensing device of claim 27, further comprising: a third P-type region disposed in contact with a lower surface of the second P-type region, having a depth greater than a depth of the second P-type region, and containing P-type impurities doped at a doping concentration lower than a doping concentration of the second P-type region.

35. 35. The image sensing device of claim 34, wherein the third P-type region has the same width as a width of the second P-type region.

36. 35. The image sensing device of claim 34, wherein the third P-type region has a width greater than a width of the second P-type region and extends underneath the first N-type region.

37. The first pixel is a second N-type region disposed in contact with a lower surface of the first N-type region, having a depth greater than a depth of the first N-type region, and including an N-type impurity doped at a doping concentration lower than a doping concentration of the first N-type region; 28. The image sensing device of claim 27, further comprising: a third N-type region disposed in contact with a lower surface of the second N-type region, having a depth greater than a depth of the second N-type region, and containing an N-type impurity doped at a doping concentration lower than a doping concentration of the second N-type region.

38. 38. The image sensing device of claim 37, wherein the third N-type region has a width the same as a width of the second N-type region.

39. 38. The image sensing device of claim 37, wherein the third N-type region has a width greater than a width of the second N-type region and extends underneath the first P-type region.

40. 38. The image sensing device of claim 37, wherein the third N-type region has a width greater than a width of the second N-type region and forms an aperture region in a center of the first pixel.

41. The first pixel is a first output node disposed at the center of the first pixel and corresponding to the anode of the first SPAD; 2. The image sensing device of claim 1, further comprising: a first bias node disposed at each vertex of the first pixel and corresponding to the cathode of the first SPAD.

42. 42. The image sensing device of claim 41, wherein the first bias node abuts a bias node of a pixel adjacent to the first pixel.

43. 42. The image sensing device of claim 41, wherein the first output node has a cross shape.

44. 42. The image sensing device of claim 41, wherein the first output node has a circular shape.

45. The image sensing device of claim 44 , wherein the first bias node has a circular ring shape with a constant distance from the first output node.

46. 42. The image sensing device of claim 41, wherein the first bias node is disposed to surround the first output node along an edge of the first pixel.

47. 42. The image sensing device of claim 41, wherein the first pixel further comprises a first guard ring disposed to surround the first output node and separating the first output node from the first bias node.

48. 42. The image sensing device of claim 41, wherein the first pixel further includes a first guard ring that is in contact with the first output node and is arranged to extend in an up-down and left-right direction centered on the first output node, and separates the first output node from the first bias node.

49. 49. The image sensing device of claim 48, wherein the first guard ring abuts a guard ring of a pixel adjacent to the first pixel.

50. The first pixel is a central bias node disposed at the center of the first pixel and corresponding to the cathode of the first SPAD; a first output node disposed around the central bias node and corresponding to the anode of the first SPAD; 2. The image sensing device of claim 1, further comprising: a first bias node disposed at each vertex of the first pixel.

51. the central bias node is supplied with the first bias voltage; 51. The image sensing device of claim 50, wherein the first bias node is supplied with a ground voltage.

52. a first pixel including a first SPAD having a first sensitivity; a second pixel including a second SPAD having a second sensitivity higher than the first sensitivity; a selection circuit for selecting one of the first pixel and the second pixel; 13. An image sensing device comprising:

53. a first pixel including a first SPAD activated with a first illumination intensity; a second pixel including a second SPAD that is activated by a second illumination intensity lower than the first illumination intensity; a selection circuit for activating one of the first pixel and the second pixel in response to illuminance information; 13. An image sensing device comprising:

54. a SPAD, each of which receives a bias voltage for operation in Geiger mode; A selection circuit for selecting one of the SPADs; 13. An image sensing device comprising:

55. selecting one of a first pixel including a first SPAD having a first sensitivity and a second pixel including a second SPAD having a second sensitivity higher than the first sensitivity; calculating a distance to a target object based on the pulse signals output from the selected pixels; A distance sensing method comprising:

Images