Delta-sigma modulation device

Abstract

To allow a signal feedback signal represented by a complex number to be converted to a real value.SOLUTION: A delta-sigma modulation device includes a delta-sigma modulation section that applies delta-sigma modulation to an input signal to generate an output signal, a feedback signal generation section that receives the output signal as a feedback signal, where the output signal includes waveform distortion and the amount of waveform distortion is represented by a complex number, and a feedback signal conversion section that converts the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputs the converted feedback signal to the delta-sigma modulation section.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a delta-sigma modulation device, and more particularly to a delta-sigma modulation device capable of reducing waveform distortion received from a communication path. [Background technology]

[0002] In the field of wireless communication, technological developments are underway to achieve high-speed communication in order to cope with increasing traffic.

[0003] Usually, to realize high-speed communication, a wireless communication device needs to have a high-speed and high-precision digital-to-analog converter (DAC). However, since the price and power consumption of such a DAC are generally high, there is a problem that the manufacturing cost and power consumption of a wireless communication device equipped with a DAC are generally high.

[0004] As one method for solving the above-mentioned problems, delta-sigma modulation can be used. Delta-sigma modulation makes it possible to output a signal obtained by converting a multi-bit digital signal, which is an input signal, into a 1-bit bit string. Delta-sigma modulation has a feature that it is possible to obtain an analog signal that is almost equivalent to the input signal by passing an output signal through a band-pass filter having the same pass band as the signal band of the input signal and removing the quantization noise added by the quantization process of delta-sigma modulation.

[0005] The use of delta-sigma modulation eliminates the need for a DAC, thereby reducing the manufacturing costs and power consumption of wireless communication devices. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2023-029230 A Summary of the Invention [Problem to be solved by the invention]

[0007] Typically, a bandpass filter has characteristics such as gain ripple, group delay ripple, and asymmetry with respect to the center frequency axis, which causes waveform distortion in the output signal of the delta-sigma modulation circuit, resulting in a problem of deterioration in signal quality.

[0008] In addition, various components such as cables and amplifiers arranged on a communication path through which an output signal is transmitted may also cause waveform distortion in the output signal, similar to the bandpass filter.For this reason, Patent Document 1 discloses a method for reducing the waveform distortion of the output signal and improving signal quality by estimating the waveform distortion received from the communication path, adding the estimated waveform distortion to the output signal, and feeding back the output signal with the waveform distortion added.

[0009] In the technology disclosed in Patent Document 1, the output signal used as the feedback signal includes a signal represented by a complex number. The signal represented by a complex number includes a signal including a real component and a signal including an imaginary component. In the technology disclosed in Patent Document 1, when the value of the output signal is limited to real values, the signal represented by a complex number is converted into a signal represented by a real number by performing frequency conversion and inverse frequency conversion.

[0010] According to the technique disclosed in Patent Document 1, the arithmetic processing of the above-mentioned frequency conversion and frequency inverse conversion is complicated, and there is a problem in that the circuit scale becomes large.

[0011] The present invention has been made in consideration of the problems associated with the related art described above, and has an object to provide a simple method for converting a feedback signal represented by a complex number to which waveform distortion has been added, into a real value. [Means for solving the problem]

[0012] A delta-sigma modulation device according to one aspect of the present invention includes a delta-sigma modulation section that applies delta-sigma modulation to an input signal to generate an output signal, a feedback signal generation section that receives the output signal as a feedback signal, wherein the output signal includes waveform distortion and an amount of waveform distortion of the waveform distortion is represented by a complex number, and the feedback signal conversion section that converts the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputs the converted feedback signal to the delta-sigma modulation section.

[0013] A method performed by a computing device according to one aspect of the present invention includes applying delta-sigma modulation to an input signal to generate an output signal, receiving the output signal as a feedback signal, the output signal including waveform distortion, an amount of the waveform distortion being represented by a complex number, converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal.

[0014] A program according to one aspect of the present invention, when executed, causes a processor in a computer device to apply delta-sigma modulation to an input signal to generate an output signal; receive the output signal as a feedback signal, the output signal including waveform distortion, an amount of waveform distortion of the waveform distortion being represented by a complex number; convert the feedback signal from a signal represented by a complex number to a signal represented by a real number, and output the converted feedback signal. Effect of the Invention

[0015] According to the present invention, a feedback signal to which waveform distortion has been added can be converted from a signal represented by a complex number to a real value by a simple method. [Brief description of the drawings]

[0016] [Figure 1]1 is a block diagram showing an example of a schematic configuration of a wireless communication system to which a delta-sigma modulation device according to a first embodiment is applied. [Diagram 2] 1 is a block diagram showing an example of a schematic physical configuration of a delta-sigma modulation device according to a first embodiment. [Diagram 3] 1 is a block diagram showing an example of a schematic logical configuration of a delta-sigma modulation device according to a first embodiment. [Figure 4] 2 is a block diagram showing an example of a schematic logical configuration of a delta-sigma modulation section according to the first embodiment. FIG. [Diagram 5] 2 is a block diagram showing an example of a schematic logical configuration of a delta-sigma modulation section according to the first embodiment. FIG. [Figure 6] 2 is a block diagram showing an example of a schematic logical configuration of an up-conversion section and a complex waveform distortion estimation section according to the first embodiment. FIG. [Figure 7] FIG. 2 is a block diagram showing an example of a schematic logical configuration of a down-conversion section according to the first embodiment. [Figure 8] 5 is a flowchart showing an example of an output signal generation and transmission process according to the first embodiment. [Figure 9] 5 is a flowchart showing an example of a feedback signal generation process according to the first embodiment. [Figure 10] FIG. 11 is a block diagram showing an example of a schematic logical configuration of a delta-sigma modulation device according to a second embodiment. [Figure 11] FIG. 11 is a block diagram showing an example of a schematic logical configuration of a down-conversion section according to a second embodiment. [Figure 12] 10 is a flowchart showing an example of a feedback signal generation process according to the second embodiment. [Figure 13] FIG. 11 is a block diagram showing an example of a schematic logical configuration of a delta-sigma modulation device according to a third embodiment. [Figure 14] FIG. 1 is a block diagram showing an example of a schematic configuration of a delta-sigma modulation device according to a related art. [Figure 15] FIG. 1 is a block diagram showing an example of a schematic configuration of a down-conversion unit according to a related technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] One or more embodiments will be described below with reference to the accompanying drawings. In this specification and drawings, elements that can be similarly described are designated by the same reference numerals to avoid redundant description.

[0018] The explanation will be given in the following order: 1.Technical challenges 1-1. Outline of the configuration of a delta-sigma modulation device according to the related art 1-2. Outline of the configuration of an up-conversion unit according to related technology 2. First embodiment 2-1.Overview of wireless communication system 2-2. Physical configuration of delta-sigma modulator 2-3.Outline of logical configuration of delta-sigma modulator 2-4. Schematic configuration of delta-sigma modulation section 2-5. Schematic configuration of delta-sigma modulation section 2-6.Outline of the up-conversion section 2-7.Outline of down-conversion section 2-8. Output signal generation and transmission processing 2-9. Feedback signal generation processing 3. Second embodiment 3-1.Outline of logical configuration of delta-sigma modulator 3-2.Outline of the down-conversion section 3-3. Feedback signal generation processing 4. Third embodiment 5. Other embodiments

[0019] <<1.Technical issues>> One or more embodiments will be outlined below.

[0020] 1-1. Outline of the configuration of a delta-sigma modulation device according to the related art First, a delta-sigma modulation device according to the related technology will be described. FIG. 14 shows an example of a schematic configuration of a delta-sigma modulation device DA according to the related technology. The delta-sigma modulation device DA is implemented according to the technology disclosed in Patent Document 1. The delta-sigma modulation according to the related technology is used, for example, in communication between a base station and an access point in a wireless network. In such an implementation form, the delta-sigma modulation device DA is implemented in the base station.

[0021] The delta-sigma modulation device DA applies delta-sigma modulation to an input signal, converts the input signal into a 1-bit bit string to generate an output signal, and transmits the output signal to an access point (not shown) via a communication path (not shown). The input signal to the delta-sigma modulation device DA is an OFDM signal represented by a complex number, and includes a signal including a real component (real part) and a signal including an imaginary component (imaginary part). The real part and imaginary part of the input signal are represented by multi-bit digital data. The real part represents the in-phase component in the IQ plane, and the imaginary part represents the quadrature component in the IQ plane.

[0022] The delta-sigma modulation device DA includes a delta-sigma modulation section DM1, a delta-sigma modulation section DM2, a down-conversion section DC, an up-conversion section UC, and a complex waveform distortion estimation section CD.

[0023] The real part data of the input signal is input to the delta-sigma modulation unit DM1. The imaginary part data of the input signal is input to the delta-sigma modulation unit DM2. The delta-sigma modulation unit DM1 applies delta-sigma modulation to the input signal, converts the input signal (real part) into a 1-bit bit string, and outputs it to the up-conversion unit UC. Similarly, the delta-sigma modulation unit DM2 applies delta-sigma modulation to the input signal, converts the input signal (imaginary part) into a 1-bit bit string, and outputs it to the up-conversion unit UC.

[0024] The up-conversion unit UC rearranges (serializes) two bit strings, one bit string of the input signal (real part) input from the delta-sigma modulation unit DM1 and one bit string of the input signal (imaginary part) input from the delta-sigma modulation unit DM2, into one bit string.The up-conversion unit UC then outputs the rearranged bit string as an output signal to a communication channel (not shown) and also outputs it to the complex waveform distortion estimation unit CD.

[0025] The complex waveform distortion estimation unit CD estimates waveform distortion that the output signal from the up-conversion unit UC experiences in the communication path from the delta-sigma modulation device DA to the access point. The complex waveform distortion estimation unit CD then adds the estimated amount of waveform distortion to the output signal to generate a feedback signal (FD signal). The feedback signal is output to the delta-sigma modulation unit DM1 and the delta-sigma modulation unit DM2 via the down-conversion unit DC.

[0026] The feedback signal representing the waveform distortion estimated by the complex waveform distortion estimation unit CD is a signal represented by a complex number. By expressing the waveform distortion estimate value as a complex number, the compensation accuracy is improved. However, when the value of the feedback signal is limited to a real number, the feedback signal needs to be converted from a signal represented by a complex number to a signal represented by a real number.

[0027] As described above, the feedback signal is generated by adding the estimated waveform distortion amount to the input signal (real part) input from the delta-sigma modulation unit DM1 and the input signal (imaginary part) input from the delta-sigma modulation unit DM2. Therefore, the feedback signal is a signal represented by a complex number. When the value of the feedback signal is limited to real values, the down-conversion unit DC converts the feedback signal from a signal represented by a complex number to a signal represented by a real number.

[0028] 1-2. Schematic configuration of a down-conversion unit according to related technology Next, a down-conversion unit according to the related technology will be described. Fig. 15 shows an example of a schematic configuration of a down-conversion unit DC according to the related technology. The down-conversion unit DC corresponds to the down-conversion unit DC described with reference to Fig. 14. The down-conversion unit DC converts a feedback signal from a complex waveform distortion estimation unit CD from a signal represented by a complex number to a signal represented by a real number, and outputs the signal to the delta-sigma modulation unit DM1 and the delta-sigma modulation unit DM2.

[0029] The downconversion unit DC includes a downconversion unit dc and an upconversion unit uc, which shift the frequency of the input feedback signal from a desired frequency band and convert the shifted frequency back to the original frequency band by frequency conversion and inverse frequency conversion, thereby outputting a signal represented by a real number.

[0030] The downconverter dc downconverts a signal represented by a complex number among the feedback signals to output a signal represented by a real number, and outputs the downconverted signal to the upconverter uc. The upconverter uc upconverts the downconverted signal, and outputs the upconverted signal to the delta-sigma modulation units DM1 and DM2 as a signal represented by a real number (feedback signal).

[0031] 1-3.Technical issues A delta-sigma modulation device DA according to the related technology converts a feedback signal from a signal represented by a complex number to a signal represented by a real number by performing frequency conversion and inverse frequency conversion. The delta-sigma modulation device DA according to the related technology can reduce waveform distortion suffered by an output signal and improve signal quality. However, the above-mentioned related technology has a problem that the calculation processing of frequency conversion and frequency inverse conversion by the down-conversion unit DC is complicated and the circuit scale is large. In view of the above circumstances, a simple configuration is required for converting a feedback signal to which waveform distortion has been imparted from a signal represented by a complex number to a signal represented by a real number.

[0032] <<2. First embodiment>> 2-1.Overview of wireless communication system Next, a delta-sigma modulation device according to a first embodiment will be described. The delta-sigma modulation device according to this embodiment is applied to, for example, a wireless communication system 1 that complies with technical specifications of 3GPP (Third Generation Partnership Project). Fig. 1 shows an example of a schematic configuration of the wireless communication system 1 to which a delta-sigma modulation device 100 is applied. In the wireless communication system 1, delta-sigma modulation and ROF (Radio over Fiber) technology are used.

[0033] The wireless communication system 1 includes a first device 100 and a second device 200. The first device 100 and the second device 200 are connected via a communication path 300. The first device 100 may be, for example, a base station (such as a gNB or an eNB) that complies with technical specifications of the Third Generation Partnership Project (3GPP). The first device 100 communicates with an accommodation station (not shown) and a second device 200 (such as an access point).

[0034] The second device 200 may be, for example, an access point conforming to technical specifications of the Third Generation Partnership Project (3GPP). The second device 200 communicates with the first device 100 (base station device) and a user device (not shown), etc.

[0035] The communication path 300 includes one or both of an electrical transmission line (e.g., a metal line) that transmits an electrical signal and an optical transmission line (e.g., an optical fiber) that transmits an optical signal. The communication path 300 may include one or a combination of an E / O conversion unit that converts an electrical signal into an optical signal, an O / E conversion unit that converts an optical signal into an electrical signal, a bandpass filter, and a frequency conversion unit.

[0036] In this embodiment, the delta-sigma modulation device is implemented in a first device 100. Hereinafter, the terms first device 100 and delta-sigma modulation device 100 are used interchangeably. Note that the above-described configuration of wireless communication system 1 is not limited to the example in this embodiment.

[0037] 2-2. Physical configuration of delta-sigma modulator Next, the physical configuration of the delta-sigma modulation device according to the first embodiment will be described. Fig. 2 shows an example of a schematic physical configuration of delta-sigma modulation device 100 (first device 100). Delta-sigma modulation device 100 is a computer device including a processor 101, a memory 102, and a transceiver 103 as physical components. The above components provided in delta-sigma modulation device 100 are connected to each other by an internal bus. Note that delta-sigma modulation device 100 may have physical components other than those shown in Fig. 2.

[0038] Processor 101 is a computing element that implements various functions of delta-sigma modulation device 100. Processor 101 may be a central processing unit (CPU), a graphics processing unit (GPU), a micro processing unit (MPU), a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like.

[0039] Memory 102 includes storage media such as a RAM (Random Access Memory) and an eMMC (embedded Multi Media Card). Memory 102 is an element that temporarily or permanently stores programs and data used to execute various processes in delta-sigma modulation device 100. The programs include one or more instructions for the operation of delta-sigma modulation device 100. Processor 101 implements the functions of delta-sigma modulation device 100 by expanding the programs stored in memory 102 into memory 102 and / or a system memory (not shown) and executing them.

[0040] The transceiver 103 includes a transmitter and a receiver (not shown), and is a circuit that performs various signal processing for implementing wired communication and wireless communication, including a baseband processor and an RF circuit. The transceiver 103 exchanges signals with other devices such as the second device 200.

[0041] 2-3.Outline of logical configuration of delta-sigma modulator Next, a logical configuration of the delta-sigma modulation device according to the first embodiment will be described. Fig. 3 shows an example of a schematic logical configuration of the delta-sigma modulation device (first device) 100. The delta-sigma modulation device 100 is connected to a second device 200 via a communication path 300. The delta-sigma modulation device 100 receives an OFDM signal represented by a complex number from an access station or the like, and outputs an output signal (quantized signal) to the second device 200 via the communication path 300.

[0042] The delta-sigma modulation device 100 includes a delta-sigma modulation section 110, a delta-sigma modulation section 120, an up-conversion section 130, a complex waveform distortion estimating section 140, and a down-conversion section 150. These logical components are implemented by the processor 101 executing a program stored in the memory 102.

[0043] The real part data of the input signal (OFDM signal) is input to the delta-sigma modulation unit 110. The imaginary part data of the input signal is input to the delta-sigma modulation unit 120. Hereinafter, the real part data of the input signal is referred to as the "I signal." Also, the imaginary part data of the input signal is referred to as the "Q signal." The delta-sigma modulation unit 110 applies delta-sigma modulation to the I signal, converts the I signal into a 1-bit bit string, and outputs it to the up-conversion unit 130. Similarly, the delta-sigma modulation unit 120 applies delta-sigma modulation to the Q signal, converts the Q signal into a 1-bit bit string, and outputs it to the up-conversion unit 130.

[0044] The I signal output to the up-conversion unit 130 is referred to as a first output signal, and the Q signal output to the up-conversion unit 130 is referred to as a second output signal.

[0045] The up-conversion unit 130 rearranges (serializes) two bit strings, namely, a 1-bit bit string of the first output signal (I signal) input from the delta-sigma modulation unit 110 and a 1-bit bit string of the second output signal (Q signal) input from the delta-sigma modulation unit 120, into one bit string. Then, the up-conversion unit 130 outputs the rearranged bit string as an output signal to the communication path 300 and also outputs it to the complex waveform distortion estimation unit 140. The signal output from the up-conversion unit 130 to the communication path 300 and the complex waveform distortion estimation unit 140 is the final output signal from the delta-sigma modulation device 100, and is therefore hereinafter referred to as the "final output signal."

[0046] The complex waveform distortion estimation unit 140 estimates the waveform distortion that the final output signal receives in the communication path 300. Then, the complex waveform distortion estimation unit 140 adds the estimated amount of waveform distortion to the final output signal to generate a feedback signal (FD signal). The feedback signal is output to the down-conversion unit 150. The estimated amount of waveform distortion is represented by a complex number.

[0047] The down-conversion section 150 converts the feedback signal from a signal represented by a complex number to a signal represented by a real number, and separates it into an I signal and a Q signal. The I signal is output to the delta-sigma modulation section 110. The Q signal is output to the delta-sigma modulation section 120.

[0048] As described above, the feedback signal is generated by serializing the I signal input from the delta-sigma modulation unit 110 and the Q signal input from the delta-sigma modulation unit 120, and adding the estimated waveform distortion amount to the serialized signal. Therefore, the feedback signal is a signal represented by a complex number. When the feedback value of the feedback signal is limited to a real value, the down-conversion unit 150 converts the feedback signal from a signal represented by a complex number to a signal represented by a real number.

[0049] The up-conversion unit 130 and the complex waveform distortion estimation unit 140 in combination function as a feedback signal generation unit. Alternatively, the complex waveform distortion estimation unit 140 functions alone as a feedback signal generation unit. Also, the down-conversion unit 150 functions as a feedback signal conversion unit. The up-conversion unit 130, the complex waveform distortion estimation unit 140, and the down-conversion unit 150 will be described in detail below.

[0050] The second device 200 includes a BPF 210, an amplifier 220, and an antenna 230. The BPF 210 performs bandpass processing on the quantized signal from the delta-sigma modulation device 100 to pass only a desired frequency band. The quantized signal is converted to an analog signal through the BPF 210. That is, the quantized signal is restored to the original analog signal before the delta-sigma modulation by the delta-sigma modulation device 100 is performed. The amplifier 220 amplifies the analog signal. The antenna 230 outputs the amplified analog signal.

[0051] 2-4. Schematic configuration of delta-sigma modulation section Next, a logical configuration of the delta-sigma modulation section according to the first embodiment will be described. Fig. 4 shows an example of a schematic logical configuration of the delta-sigma modulation section 110. The delta-sigma modulation section 110 corresponds to the delta-sigma modulation section 110 described with reference to Fig. 3. The delta-sigma modulation section 110 serves as a first delta-sigma modulation section.

[0052] The delta sigma modulation unit 110 may use, for example, a second-order error feedback delta sigma modulation circuit, but the number of orders corresponding to the number of integrators implemented by the delta sigma modulation unit 110 is not limited. For example, the delta sigma modulation unit 110 may use a first-order error feedback delta sigma modulation circuit, or an n-th order (n is an integer of 3 or more) error feedback delta sigma modulation circuit. As is clear from FIG. 4, the delta sigma modulation unit 110 is a type of infinite impulse response (IIR) filter. The delta sigma modulation unit 110 outputs an output signal to the up-conversion unit 130 and receives a feedback signal from the down-conversion unit 150.

[0053] The delta-sigma modulation section 110 includes an adder / subtractor 110-1, an integrator 110-2, and a quantizer 110-3.

[0054] An I signal, which is an input signal, is input to the delta-sigma modulation unit 110. Hereinafter, the I signal, which is an input signal, is referred to as a "first I signal." The first I signal is input to an adder-subtractor 110-1. In addition, a feedback signal is input to the delta-sigma modulation unit 110 from the down-conversion unit 150. The feedback signal corresponds to the real part data of the feedback signal. Hereinafter, the real part data of the feedback signal is referred to as a "second I signal."

[0055] The second I signal is a signal represented by a complex number, but is converted into a signal represented by a real number by the down-conversion section 150. The process of converting into a signal represented by a real number will be described in detail later.

[0056] The adder-subtracter 110-1 subtracts the second I signal from the first I signal and outputs the subtracted signal to the integrator 110-2. The signal output from the adder-subtracter 110-1 is the difference between the first I signal and the second I signal. As will be described later, the second I signal is input from the complex waveform distortion estimation unit 140 to the delta-sigma modulation unit 110 via the down-conversion unit 150, and therefore the second I signal includes a portion of the transmission distortion component occurring in the transmission process of the final output signal. Therefore, the signal output from the adder-subtracter 110-1 also includes a portion of the transmission distortion component occurring in the transmission process of the final output signal.

[0057] Integrator 110-2 adds the signal input from adder-subtractor 110-1 and the signal output from integrator 110-2 immediately before, and outputs the added signal to quantizer 110-3.

[0058] Quantizer 110-3 is a 1-bit quantizer. Quantizer 110-3 quantizes the signal input from integrator 110-2 with 1 bit, and outputs the quantized signal to up-conversion section .

[0059] 2-5. Schematic configuration of delta-sigma modulation section Fig. 5 shows an example of a schematic logical configuration of the delta-sigma modulation section 120. The delta-sigma modulation section 120 corresponds to the delta-sigma modulation section 120 described with reference to Fig. 3. The delta-sigma modulation section 120 serves as a second delta-sigma modulation section.

[0060] The delta sigma modulation unit 120 may use, for example, a second-order error feedback type delta sigma modulation circuit, but the number of orders corresponding to the integrator implemented by the delta sigma modulation unit 120 is not limited. For example, the delta sigma modulation unit 120 may use a first-order error feedback type delta sigma modulation circuit, or may use an n-th order (n is an integer of 3 or more) error feedback type delta sigma modulation circuit. As is clear from FIG. 5, the delta sigma modulation unit 120 is a type of infinite impulse response filter. The delta sigma modulation unit 120 outputs an output signal to the up-conversion unit 130 and receives a feedback signal from the down-conversion unit 150.

[0061] The delta-sigma modulation section 120 includes an adder / subtractor 120-1, an integrator 120-2, and a quantizer 120-3.

[0062] A Q signal, which is an input signal, is input to the delta-sigma modulation unit 120. Hereinafter, the Q signal, which is an input signal, is referred to as a "first Q signal." The first Q signal is input to an adder-subtractor 120-1. In addition, a feedback signal is input from the down-conversion unit to the delta-sigma modulation unit 120. The feedback signal corresponds to the imaginary part data of the feedback signal. Hereinafter, the imaginary part data of the feedback signal is referred to as a "second Q signal."

[0063] The second Q signal is a signal represented by a complex number, but is converted into a signal represented by a real number by the down-conversion section 150. The process of converting into a signal represented by a real number will be described in detail later.

[0064] The adder-subtracter 120-1 subtracts the second Q signal from the first Q signal and outputs the subtracted signal to the integrator 120-2. The signal output from the adder-subtracter 120-1 is the difference between the first Q signal and the second Q signal. As will be described later, the second Q signal is input from the complex waveform distortion estimation unit 140 through the down-conversion unit 150 to the delta-sigma modulation unit 120, and therefore includes a portion of the transmission distortion component occurring in the transmission process of the final output signal. Therefore, the signal output from the adder-subtracter 120-1 also includes a portion of the transmission distortion component occurring in the transmission process of the final output signal.

[0065] Integrator 120-2 adds the signal input from adder / subtractor 120-1 and the signal output from integrator 120-2 immediately before, and outputs the added signal to quantizer 120-3.

[0066] The quantizer 120-3 is a 1-bit quantizer. The quantizer 120-3 quantizes the signal output from the integrator 120-2 with 1 bit, and outputs the quantized signal to the up-conversion unit .

[0067] 2-6. Outline of the up-conversion section and complex waveform distortion estimation section Next, the logical configuration of the up-conversion section and the complex waveform distortion estimation section according to the first embodiment will be described. Fig. 6 shows an example of a schematic logical configuration of the up-conversion section 130 and the complex waveform distortion estimation section 140. The up-conversion section 130 corresponds to the up-conversion section 130 described with reference to Fig. 3. The complex waveform distortion estimation section 140 corresponds to the complex waveform distortion estimation section 140 described with reference to Fig. 3.

[0068] The up-conversion section 130 includes an up-sampling section 130-1, an up-sampling section 130-2, a multiplier 130-3, a multiplier 130-4, and an adder 130-5.

[0069] The up-conversion unit 130 receives as input the signal output from the delta-sigma modulation unit 110. This signal is generated from the first I signal and includes a real component (real part) of the input signal. The up-conversion unit 130 also receives as input the signal output from the delta-sigma modulation unit 120. This signal is generated from the first Q signal and includes an imaginary component (imaginary part) of the input signal.

[0070] Upsampling unit 130-1 upsamples the signal input from delta-sigma modulation unit 110 at twice the sampling rate and outputs the upsampled signal to multiplier 130-3. Upsampling unit 130-2 upsamples the signal input from delta-sigma modulation unit 120 at twice the sampling frequency and outputs the upsampled signal to multiplier 130-4.

[0071] One type of upsampling process is the sample-and-hold process, which doubles the sampling rate and repeats the bits of the input signal twice. For example, if the input bit sequence is x(0), x(1), x(2), x(3), ..., the sample-and-hold process results in the bit sequence x(0), x(0), x(1), x(1), x(2), x(2), x(3), x(3), ....

[0072] The multiplier 130-3 multiplies the signal input from the upsampling unit 130-1 by cos(2πΔf c t) and outputs the multiplied signal to the adder 130-5. cos() is a cosine function. Furthermore, the multiplier 130-4 multiplies the signal output from the upsampling unit 130-2 by -sin(2πΔf c t) and outputs the multiplied signal to the adder 130-5. sin() is a sine function. Here, t=nT s where n is an integer value equal to or greater than zero, and Ts is the reciprocal of the sampling rate of the bitstream that has been upsampled by twice the sampling rate.

[0073] The adder 130-5 adds the signal input from the multiplier 130-3 and the signal input from the multiplier 130-4, and outputs the added signal as a final output signal to the communication path 300 and the complex waveform distortion estimation unit 140. In the addition process by the adder 130-5, the two bit strings of the signal input from the multiplier 130-3 and the signal input from the multiplier 130-4 are rearranged (serialized) into one string.

[0074] The final output signal from the up-conversion unit 130 is a signal including a real component output from the delta-sigma modulation unit 110 and a signal including an imaginary component output from the delta-sigma modulation unit 120, which is multiplied by Δf c The signal is frequency shifted by

[0075] Here, 2πΔf c t=2π(1 / (4T s ))(nT s )=n(π / 2) so that Δf c In this case, when the bit strings input to multiplier 130-3 are I(0), I(1), I(2), I(3), I(4), I(5), I(6), ..., the bit strings output from multiplier 130-3 are I(0), 0, -I(2), 0, I(4), 0, -I(6), 0, ....

[0076] Similarly, when the bit string input to multiplier 130-4 is Q(0), Q(1), Q(2), Q(3), Q(4), Q(5), Q(6), ..., the bit string output from multiplier 130-4 will be 0, -Q(1), 0, Q(3), 0, -Q(5), 0, ....

[0077] Therefore, the bit string output from adder 130-5 is I(0), -Q(1), -I(2), Q(3), I(4), -Q(5), -I(6), ..., so the two bit strings input to the upconversion unit 130 can be rearranged (serialized) into a single string.

[0078] The final output signal output to the communication path 300 is transmitted to the second device 200. The final output signal output to the complex waveform distortion estimating section 140 is fed back to the delta-sigma modulating section 110 and the delta-sigma modulating section 120 via the down-conversion section 150 as a feedback signal.

[0079] The communication path 300 may be an electrical transmission line (electrical cable) that transmits an electrical signal or an optical transmission line (e.g., optical fiber) that transmits an optical signal. For example, when the communication path 300 is an optical transmission line, the final output signal may be converted into an optical signal, transmitted through the optical transmission line, and converted back into an electrical signal.

[0080] The final output signal sent to the second device 200 is input to the BPF 210. The BPF 210 has a passband with a center frequency of Δf c The filter 210 extracts only the radio signal component of the final output signal, and outputs the signal from which only the radio signal component has been extracted to the amplifier 220. The amplifier 220 amplifies the signal output from the BPF 210, and transmits the amplified signal from the antenna 303 into space.

[0081] The complex waveform distortion estimation unit 140 estimates the waveform distortion suffered by the final output signal from the first device 100, and generates a feedback signal by adding the estimated amount of waveform distortion to the final output signal from the up-conversion unit 130. Then, the complex waveform distortion estimation unit 140 outputs the generated feedback signal to the down-conversion unit 150.

[0082] Assume that the input signal (I signal) to the delta-sigma modulation unit 110 is Re{X(z)}, the input signal (Q signal) to the delta-sigma modulation unit 120 is Im{X(z)}, and the output signal from the antenna 230 is Y(z). In this case, it can be expressed as Y(z)=STF(z)X(z)+NTF(z)(E(z)+R(z)). Here, E(z) is the quantization noise added by the delta-sigma modulation. R(z) is the waveform distortion that the final output signal from the up-conversion unit 130 receives in the transmission path from the communication path 300 to the antenna 230, and is calculated by the complex waveform distortion estimation unit 140. Moreover, STF(z) is the signal transfer function, and NTF(z) is the noise transfer function.

[0083] The noise transfer function NTF(z) is designed so that its gain is sufficiently small in the signal band of the input signal X(z). Also, the noise transfer function NTF(z) is designed so that its gain is high in a frequency region sufficiently far from the signal band of the input signal X(z). Therefore, in the BPF 210, it is possible to reduce the waveform distortion suffered by the final output signal from the up-conversion unit 130 together with the quantization noise, and the quality of the signal transmitted from the antenna 230 to space can be improved.

[0084] The complex waveform distortion estimation unit 140 models the waveform distortion that the final output signal from the up-conversion unit 130 experiences in the transmission path from the up-conversion unit 130 to the antenna 230. The modeled waveform distortion value can be realized as a filter having real or complex coefficients.

[0085] When a filter having complex coefficients is used, modeling can be performed with higher accuracy than with real numbers, and the improvement in signal quality is large, so here, the complex waveform distortion estimating unit 140 uses a filter having complex coefficients. The signal output from the complex waveform distortion estimating unit 140 is represented by a complex number with a multi-bit width. In an actual circuit, a complex number can be realized by a combination of two parts: a real part and an imaginary part.

[0086] 2-7.Outline of down-conversion section Next, a description will be given of the logical configuration of the down-conversion section according to the first embodiment. Fig. 7 shows an example of a schematic logical configuration of the down-conversion section 150. The down-conversion section 150 corresponds to the down-conversion section 150 described with reference to Fig. 3.

[0087] The down-conversion unit 150 includes a branching unit 150-1, a multiplier 150-2, a multiplier 150-3, an interpolation unit 150-4, an interpolation unit 150-5, a mixer 150-6, a downsampling unit 150-7, and an IQ separator 150-8. The mixer 150-6 includes an adder 150-6a and a multiplier 150-6b.

[0088] The down-conversion unit 150 receives the feedback signal output from the complex waveform distortion estimation unit 140. This feedback signal includes a real component (real part) and an imaginary component (imaginary part) of the signal. In other words, the feedback signal is a signal represented by a complex number. The down-conversion unit 150 converts the feedback signal from a signal represented by a complex number to a signal represented by a real number.

[0089] Branching section 150-1 replicates the feedback signal and outputs it to multiplier 150-2 and multiplier 150-3, respectively. The signal output to multiplier 150-2 is referred to as a first feedback signal, and the signal output to multiplier 150-3 is referred to as a second feedback signal.

[0090] The multiplier 150-2 multiplies the signal input from the branching unit 150-1 by cos(2πΔf c t) and outputs the multiplied signal to the interpolation section 150-4. The multiplier 150-3 also multiplies the signal input from the branching section 150-1 by -sin(2πΔf c t) and outputs the multiplied signal to interpolation section 150-5.

[0091] As mentioned above, 2πΔf c t=2π(1 / (4T s ))(nTs )=n(π / 2). It is assumed that the feedback signals for the bit strings I(0), -Q(1), -I(2), Q(3), I(4), -Q(5), -I(6), ... output from the up-conversion unit 130 are e(0), e(1), e(2), e(3), e(4), e(5), ..., e(n), ... (n is an integer). In this case, the signals output from the multiplier 150-2 are e(0), 0, -e(2), 0, e(4), 0, -e(6), 0, ..., +e(4m), 0, -e(4m+2), ... (m is an integer). The signals output from the multiplier 150-3 are 0, -e(1), 0, e(3), 0, -e(5), 0, ..., -e(4m+1), 0, +e(4m+3), ....

[0092] The interpolation unit 150-4 interpolates zero values ​​in the signal output from the multiplier 150-2, and outputs the interpolated signal to the mixer 150-6. The signal interpolated by the interpolation unit 150-4 is called a "first interpolation signal", and the first interpolation signal includes an interpolated data string. The interpolation unit 150-5 interpolates zero values ​​in the signal output from the multiplier 150-3, and outputs the interpolated signal to the mixer 150-6. The signal interpolated by the interpolation unit 150-5 is called a "second interpolation signal", and the first interpolation signal includes an interpolated data string. Linear interpolation or sample-and-hold may be used as the interpolation process. Hereinafter, an example in which sample-and-hold, which is the simplest process, is used as the interpolation process, will be described.

[0093] The first interpolated signal is e(0), e(0), -e(2), -e(2), e(4), e(4), -e(6), -e(6), .... These data strings are output to the mixer 150-6. The second interpolated signal is -e(1), -e(1), e(3), e(3), -e(5), -e(5), .... These data strings are output to the mixer 150-6.

[0094] In the mixer 150-6, the first interpolation signal is input to an adder 150-6a, and the second interpolation signal is input to a multiplier 150-6b.

[0095] The multiplier 150-6b multiplies the second interpolation signal by the imaginary unit i and outputs the multiplied signal to the adder 150-6a. The adder 150-6a adds the first interpolation signal and the signal input from the multiplier 150-6b and outputs the added signal to the downsampling unit 150-7.

[0096] As a result of the above-mentioned processing, the signals output from the mixer 150-6 are e(0)-ie(1), e(0)-ie(1), -e(2)+ie(3), -e(2)+ie(3), e(4)-ie(5), e(4)-ie(5), .... These data strings are output to the downsampling unit 150-7.

[0097] The downsampling unit 150-7 downsamples the signal output from the mixer 150-6 at half the sampling rate, and outputs the downsampled signal to the IQ separator 150-8. If the operation timing of the delta-sigma modulators 110 and 120 is assumed to be n=2m (m is an integer), the signals output from the downsampling unit 150-7 are e(0)-ie(1), -e(2)+ie(3), e(4)-ie(5), ...

[0098] The IQ separator 150-8 extracts a real part from the signal input from the downsampling unit 150-7, and outputs the extracted signal as a feedback signal to the delta-sigma modulator 110. This feedback signal corresponds to the second I signal described in FIG. 4. The IQ separator 150-8 also extracts an imaginary part from the signal input from the downsampling unit 150-7, and outputs the extracted signal as a feedback signal to the delta-sigma modulator 120. This feedback signal corresponds to the second Q signal described in FIG. 5.

[0099] Here, it is assumed that e(2m)=a(m)+ib(m), e(2m+1)=c(m)+id(m) (m is an integer). In this case, the signal output from the downsampling unit 150-7 is (a(0)+d(0))+i(b(0)-c(0)),-(a(1)+d(1))-i(b(1)-c(1)),(a(2)+d(2))+i(b(2)-c(2)),...,(a(m)+d(m))(-1) m +i(b(m)-c(m))(-1) m It becomes.

[0100] Therefore, delta-sigma modulation section 110 receives (a(m)+d(m))(-1) m The delta sigma modulation section 120 outputs (b(m)-c(m))(-1). m In this manner, the down-conversion unit 150 converts the feedback signal from a signal represented by a complex number to a signal represented by a real number.

[0101] 2-8. Output signal generation and transmission processing Next, an output signal generation and transmission process according to the first embodiment will be described. Fig. 8 shows an example of the output signal generation and transmission process executed by delta-sigma modulation device 100. In the process shown in Fig. 8, delta-sigma modulation device (first device) 100 generates a final output signal and transmits the final output signal to second device 200. The process shown in Fig. 8 is executed by logical components included in delta-sigma modulation device 100 as a result of processor 101 executing a program stored in memory 102.

[0102] 8, delta-sigma modulation apparatus 100 receives an OFDM signal represented by a complex number from an access point or the like. Real part data of the OFDM signal is input to delta-sigma modulation section 110 as a first I signal. Imaginary part data of the OFDM signal is input to delta-sigma modulation section 120 as a first Q signal.

[0103] The delta-sigma modulation section 110 receives data of the real part of the feedback signal from the down-conversion section 150 as a second I signal. The delta-sigma modulation section 120 receives data of the imaginary part of the feedback signal from the down-conversion section 150 as a second Q signal.

[0104] In step S801, the delta-sigma modulation unit 110 applies delta-sigma modulation to the first I signal to convert the first I signal into a 1-bit bit string, and outputs the 1-bit bit string to the up-conversion unit 130. Specifically, the delta-sigma modulation unit 110 subtracts the second I signal from the first I signal, adds the subtracted signal to the signal integrated one time previously, and quantizes the added signal at 1 bit. The quantized signal is output to the up-conversion unit 130.

[0105] In step S802, the delta-sigma modulation unit 120 applies delta-sigma modulation to the first Q signal to convert the first Q signal into a 1-bit bit string, and outputs the 1-bit bit string to the up-conversion unit 130. Specifically, the delta-sigma modulation unit 120 subtracts the second Q signal from the first Q signal, adds the subtracted signal to the signal integrated one time previously, and quantizes the added signal at 1 bit. The quantized signal is output to the up-conversion unit 130.

[0106] In step S803, the up-conversion unit 130 rearranges (serializes) two bit strings, the one-bit bit string of the I signal input from the delta-sigma modulation unit 110 and the one-bit bit string of the Q signal input from the delta-sigma modulation unit 120, into one bit string. Specifically, the up-conversion unit 130 up-samples the signal input from the delta-sigma modulation unit 110 at twice the sampling rate, and applies cos(2πΔf c Furthermore, the up-conversion unit 130 up-samples the signal input from the delta-sigma modulation unit 120 at twice the sampling rate, and multiplies the up-sampled signal by -sin(2πΔf cFurthermore, the up-conversion unit 130 multiplies the signal by cos(2πΔf c t) and -sin(2πΔf c t) and add it to the signal multiplied by t.

[0107] In step S804, the up-conversion unit 130 outputs the added signal as a final output signal to the communication path 300. The final output signal is transmitted to the second device 200 through the communication path 300. In the second device 200, only the radio signal component of the final output signal is extracted by the BPF 210, the signal is amplified by the amplifier 220, and the signal is transmitted to space by the antenna 303.

[0108] In this manner, the delta-sigma modulation device 100 can suppress the transmission distortion components contained in the feedback signal and generate the final output signal.

[0109] 2-9. Feedback signal generation processing Next, a feedback signal generation process according to the first embodiment will be described. Fig. 9 shows an example of the feedback signal generation process executed by the delta-sigma modulation device 100. In the process shown in Fig. 9, the final output signal generated by the up-conversion section 130 is output as a feedback signal to the delta-sigma modulation section 110 and the delta-sigma modulation section 120. The feedback signal output to the delta-sigma modulation section 120 is expressed by a complex number, but is converted to a real value by the down-conversion section 150. The process shown in Fig. 9 is executed by logical components included in the delta-sigma modulation device 100 as the processor 101 executes a program stored in the memory 102.

[0110] In step S901, the up-conversion unit 130 outputs the final output signal to the complex waveform distortion estimation unit 140. In step S902, the complex waveform distortion estimation unit 140 estimates waveform distortion that the final output signal receives in the communication path 300, and applies the estimated waveform distortion amount to the final output signal to generate a feedback signal. The feedback signal is output to the down-conversion unit 150.

[0111] In step S903, the down-conversion unit 150 splits the feedback signal and applies cos(2πΔf c t) and interpolating zero values ​​in the multiplied signal, where this interpolated signal corresponds to the first interpolated signal.

[0112] In step S904, the down-conversion unit 150 applies −sin(2πΔf c t) and interpolating zero values ​​in the multiplied signal. This interpolated signal corresponds to the second interpolated signal.

[0113] In step S905, the down-conversion unit 150 multiplies the data string of the second interpolation signal by the imaginary unit i, and adds the data string multiplied by the imaginary unit i to the data string of the first interpolation signal. In step S906, the down-conversion unit 150 down-samples the added signal at half the sampling rate, and performs IQ separation on the down-sampled signal. Of the separated signals, a signal including an I component is input to the delta-sigma modulation unit 110. This signal corresponds to the second I signal. Of the separated signals, a signal including a Q component is input to the delta-sigma modulation unit 120. This signal corresponds to the second Q signal.

[0114] In this manner, delta-sigma modulator 100 can convert the feedback signal from a complex-valued signal to a real-valued signal.

[0115] As described above, an example of the delta-sigma modulation device according to the first embodiment has been described. According to the first embodiment, it is possible to convert a complex feedback signal to which waveform distortion has been added into a real value by a simple method and feed the real value back to the delta-sigma modulation section.

[0116] For example, in the delta-sigma modulation device according to the related art described in Fig. 14 and Fig. 15, the arithmetic processing of frequency conversion and frequency inverse conversion is complicated, and there is a problem that the circuit scale becomes large. The down-conversion section 150 of the delta-sigma modulation device 100 according to the first embodiment employs a multiplier 150-2, a multiplier 150-3, an adder 150-7a, and a multiplier 150-6b as arithmetic units. The multiplier 150-2 and the multiplier 150-3 simply multiply by 0 or ±1, respectively. Also, the multiplier 150-6b simply multiplies by ±1.

[0117] The delta-sigma modulation device according to the first embodiment does not require the arithmetic processing of frequency conversion and frequency inverse conversion executed in the delta-sigma modulation device according to the related technology. Therefore, the delta-sigma modulation device according to the first embodiment can convert a feedback signal of a complex number to which waveform distortion has been added into a real value by a simple method and with a small circuit scale compared to the related technology.

[0118] <<3. Second embodiment>> Next, a description will be given of a delta-sigma modulation device according to a second embodiment. The delta-sigma modulation device according to the second embodiment is different from the delta-sigma modulation device according to the first embodiment in the configuration of the down-conversion section.

[0119] 3-1.Outline of logical configuration of delta-sigma modulator Next, the logical configuration of the delta-sigma modulation device according to the second embodiment will be described. Fig. 10 shows an example of a schematic logical configuration of a delta-sigma modulation device 400. The delta-sigma modulation device 400 includes a delta-sigma modulation section 410, a delta-sigma modulation section 420, an up-conversion section 430, a complex waveform distortion estimation section 440, and a down-conversion section 450. The delta-sigma modulation section 410, the delta-sigma modulation section 420, the up-conversion section 430, and the complex waveform distortion estimation section 440 are the same as the elements described in the first embodiment, so description thereof will be omitted.

[0120] The up-conversion unit 430 and the complex waveform distortion estimation unit 440 in combination serve as a feedback signal generation unit. Alternatively, the complex waveform distortion estimation unit 440 serves as a feedback signal generation unit by itself. Also, the down-conversion unit 450 serves as a feedback signal conversion unit. The down-conversion unit 450 will be described in detail later.

[0121] The down-conversion unit 450 converts the feedback signal input from the complex waveform distortion estimation unit 440 from a signal represented by a complex number to a signal represented by a real number, and separates it into an I signal and a Q signal. The I signal is output to the delta-sigma modulation unit 410. The Q signal is output to the delta-sigma modulation unit 420.

[0122] 3-2.Outline of the down-conversion section Next, a logical configuration of the down-conversion section according to the second embodiment will be described. Fig. 11 shows an example of a schematic logical configuration of the down-conversion section 450 according to the second embodiment. The down-conversion section 450 corresponds to the down-conversion section 450 described with reference to Fig. 10.

[0123] The down-conversion section 450 includes a selection section 450-1, an IQ separation section 450-2, an IQ separation section 450-3, an adder 450-4, an adder 450-5, a multiplier 450-6, and a multiplier 450-7.

[0124] The selection unit 450-1 receives a feedback signal from the complex waveform distortion estimation unit 440. The selection unit 450-1 selects a predetermined bit sequence from the feedback signal and outputs the selected bit sequence to the IQ separation unit 450-2. The selection unit 450-1 also selects a predetermined bit sequence from the feedback signal and outputs the selected bit sequence to the IQ separation unit 450-3.

[0125] The bit strings output to the IQ separator 450-2 and the IQ separator 450-3 are selected so that the bits of the bit strings in the feedback signal alternate. For example, a bit string including the 0th, 2nd, 4th, and 6th bits of the bit string in the feedback signal is output to the IQ separator 450-2. Also, a bit string including the 1st, 3rd, 5th, and 7th bits of the bit string in the feedback signal is output to the IQ separator 450-3.

[0126] The feedback signal output to IQ separation section 450-2 is referred to as a first feedback signal, and the feedback signal output to IQ separation section 450-3 is referred to as a second feedback signal.

[0127] Assume that the signals input from the up-conversion unit 430 to the complex waveform distortion estimation unit 440 are I(0), -Q(1), -I(2), Q(3), I(4), -Q(5), -I(6), .... Assume also that the signals output from the complex waveform distortion estimation unit 140 are e(0), e(1), e(2), e(3), e(4), e(5), e(6), .... In this case, e(0), e(2), e(4), e(6), ... are input to the IQ separation unit 450-2. Also, e(1), e(3), ..., e(5), ... are input to the IQ separation unit 450-3.

[0128] IQ separation unit 450-2 extracts the real part of the signal input from selection unit 450-1 and outputs the extracted signal to adder 450-4. IQ separation unit 450-2 also extracts the imaginary part of the signal input from selection unit 450-1 and outputs the extracted signal to adder 450-5.

[0129] IQ separation unit 450-3 extracts the real part of the signal input from selection unit 450-1 and outputs the extracted signal to adder 450-5. IQ separation unit 450-3 also extracts the imaginary part of the signal input from selection unit 450-1 and outputs the extracted signal to adder 450-4.

[0130] Adder 450-4 adds the signal (real part) input from IQ separation section 450-2 and the signal (imaginary part) input from IQ separation section 450-3, and outputs the added signal to multiplier 450-6.

[0131] Adder 450-5 subtracts the signal (real part) input from IQ separation section 450-3 from the signal (imaginary part) input from IQ separation section 450-2, and outputs the signal resulting from the subtraction to multiplier 450-7.

[0132] Multiplier 450-6 alternately multiplies the signal input from adder 450-4 by +1 and −1, and outputs the multiplied signal to delta-sigma modulation section 410. In addition, multiplier 450-7 alternately multiplies the signal input from adder 450-5 by +1 and −1, and outputs the multiplied signal to delta-sigma modulation section 420.

[0133] Here, it is assumed that e(2m)=a(m)+ib(m), e(2m+1)=c(m)+id(m) (m is an integer). In this case, the signal output from the adder 450-4 is expressed as (a(m)+d(m))(-1) m The signal output from the adder 450-5 can be expressed as (b(m)-c(m))(-1). m It can be expressed as:

[0134] As described above, in the delta-sigma modulation device 400 according to the first embodiment, the signal output from the down-conversion section 450 to the delta-sigma modulation section 410 is expressed as (a(m)+d(m))(−1). m In addition, the signal output from the down-conversion unit 450 to the delta-sigma modulation unit 420 is (b(m)-c(m))(-1).m That is, in the delta-sigma modulation apparatus 400 according to the second embodiment, the signal output from the down-conversion section 450 is the same as the signal output from the down-conversion section 150 in the delta-sigma modulation apparatus 100 according to the first embodiment. In this way, the down-conversion section 450 converts the feedback signal from a signal represented by a complex number to a signal represented by a real number.

[0135] 3-3. Feedback signal generation processing Next, a feedback signal generation process according to the second embodiment will be described. Fig. 12 shows an example of the feedback signal generation process executed by the delta-sigma modulation device 400. In the process shown in Fig. 12, the final output signal generated by the up-conversion section 430 is output as a feedback signal to the delta-sigma modulation section 410 and the delta-sigma modulation section 420. The feedback signal output to the delta-sigma modulation section 420 is expressed by a complex number, but is converted to a real value by the down-conversion section 450. The process shown in Fig. 12 is executed by logical components included in the delta-sigma modulation device 400 as the processor 101 executes a program stored in the memory 102.

[0136] In step S1201, the up-conversion unit 430 outputs the final output signal to the complex waveform distortion estimation unit 440. In step S1202, the complex waveform distortion estimation unit 440 estimates waveform distortion that the final output signal receives in the communication path 300, and applies the estimated waveform distortion amount to the final output signal to generate a feedback signal. The feedback signal is output to the down-conversion unit 450.

[0137] In step S1203, down-conversion section 450 performs IQ separation on one of the feedback signals output to IQ separation section 450-2 (first feedback signal), and extracts the real part and the imaginary part of the first feedback signal.

[0138] In step S1204, down-conversion section 450 performs IQ separation on one of the feedback signals output to IQ separation section 450-3 (second feedback signal), and extracts the real part and the imaginary part of the second feedback signal.

[0139] The first feedback signal and the second feedback signal each include a bit sequence selected such that each bit in the bit sequence in the feedback signal from the complex waveform distortion estimation unit 440 alternates. For example, the first feedback signal includes the 0th bit, the 2nd bit, the 4th bit, the 6th bit, etc. of the bit sequence in the feedback signal from the complex waveform distortion estimation unit 440. The second feedback signal includes the 1st bit, the 3rd bit, the 5th bit, the 7th bit, etc. of the bit sequence in the feedback signal from the complex waveform distortion estimation unit 440.

[0140] In step S1205, the down-conversion unit 450 adds the signal obtained by extracting the real part of the first feedback signal to the signal obtained by extracting the imaginary part of the second feedback signal, and multiplies the sum by +1 and −1 alternately. The multiplied signal is output to the delta-sigma modulation unit 410.

[0141] In step S1206, the down-conversion unit 450 subtracts the signal obtained by extracting the real part of the first feedback signal from the signal obtained by extracting the imaginary part of the second feedback signal, and multiplies the result by +1 and −1 alternately. The multiplied signal is output to the delta-sigma modulation unit 420.

[0142] In this manner, the delta-sigma modulator 400 can convert the feedback signal from a complex-valued signal to a real-valued signal.

[0143] As described above, an example of the delta-sigma modulation device according to the second embodiment has been described. According to the second embodiment, it is also possible to convert a complex feedback signal to which waveform distortion has been added into a real value by a simple method and feed the real value back to the delta-sigma modulation section.

[0144] The down-conversion section 450 of the delta-sigma modulation device 400 according to the second embodiment employs an adder 450-4, an adder 450-5, a multiplier 450-6, and a multiplier 450-7 as computing units. The multipliers 450-6 and 450-7 only multiply by ±1, respectively. That is, the multipliers 450-6 and 450-7 each either directly output the input signal or invert the sign.

[0145] According to the second embodiment, it is possible to realize a further simple configuration of the down-conversion unit 450. In particular, according to the second embodiment, it is possible to reduce the circuit scale when the down-conversion unit 450 is implemented in an integrated circuit such as an FPGA or an ASIC.

[0146] <<4. Third embodiment>> Next, a delta-sigma modulation device according to a third embodiment will be described. The delta-sigma modulation device according to the third embodiment is different from the delta-sigma modulation device according to the first embodiment and the delta-sigma modulation device according to the second embodiment in that the path along which the final output signal output from the up-conversion section is fed back is different.

[0147] 13 shows an example of a schematic logical configuration of a delta-sigma modulation device 500. The delta-sigma modulation device 500 is connected to a second device 600 via a communication path 300. The delta-sigma modulation device 500 includes a delta-sigma modulation section 510, a delta-sigma modulation section 520, an up-conversion section 530, and a down-conversion section 550. The delta-sigma modulation section 510, the delta-sigma modulation section 520, the up-conversion section 530, and the down-conversion section 550 are the same as the elements described in the first embodiment, and therefore description thereof will be omitted.

[0148] Delta-sigma modulation device 500 does not include complex waveform distortion estimating section 140 described in the first embodiment and complex waveform distortion estimating section 440 described in the second embodiment. As will be described later, in the third embodiment, a signal to which waveform distortion has actually been added is fed back via communication path 300, PF 610, and amplifier 620, so there is no need to estimate the waveform distortion.

[0149] The second device 600 includes a BPF 610, an amplifier 620, and an antenna 630. The BPF 610, the amplifier 620, and the antenna 630 are the same as the elements described in the first embodiment, and therefore description thereof will be omitted.

[0150] The up-conversion unit 130 outputs the final output signal to the communication path 300. In the second device 600, the amplifier 620 outputs the amplified signal to the antenna 630 as well as to the down-conversion unit 550. The signal output from the amplifier 620 to the down-conversion unit 550 may be via the communication path 300 or via another path.

[0151] In the third embodiment, the final output signal is fed back from the amplifier 620 to the down-conversion unit 550, but is not limited to such a form. The final output signal may be fed back from any position after the final output signal is transmitted through the communication path 300, such as after being output from the communication path 300 or after being output from the BPF 610.

[0152] In the third embodiment, the delta-sigma modulation device 500 does not feed back the final output signal as a feedback signal within the delta-sigma modulation device 500, but instead receives a feedback signal from a second device. With such a configuration, it is possible to more accurately reflect waveform distortion in the feedback signal. Furthermore, according to the third embodiment, it is not necessary to implement a complex waveform distortion estimating unit, and the circuit configuration can be further simplified.

[0153] <<4. Other embodiments>> Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. It will be understood by those skilled in the art that these embodiments are merely examples and that various modifications are possible without departing from the scope and spirit of the present invention.

[0154] For example, the steps in the processes described herein do not necessarily have to be performed chronologically according to the order depicted in the sequence diagrams. For example, the steps in the processes may be performed in an order different from that depicted in the sequence diagrams, or may be performed in parallel. Also, some of the steps in the processes may be deleted, and additional steps may be added to the processes.

[0155] Also, an apparatus (e.g., one or more apparatuses (or units) among the multiple apparatuses (or units) constituting the delta-sigma modulation apparatus, or a module for one of the multiple apparatuses (or units)) including components of the delta-sigma modulation apparatus described in this specification (e.g., a delta-sigma modulation section, an up-conversion section, a down-conversion section, etc.) may be provided.

[0156] Also, a method including the processing of the above-mentioned components may be provided, or a program for causing a processor to execute the processing of the above-mentioned components may be provided. Also, a non-transitory computer readable medium having the program recorded thereon may be provided. Naturally, such an apparatus, module, method, program, and non-transitory computer readable medium are also included in the present invention.

[0157] A part or all of the above-described embodiments may be described as, but is not limited to, the following supplementary notes.

[0158] (Appendix 1) a delta-sigma modulation unit that applies delta-sigma modulation to an input signal to generate an output signal; a feedback signal generating unit that receives the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; a feedback signal conversion unit that converts the feedback signal from a signal represented by a complex number to a signal represented by a real number and outputs the converted feedback signal to the delta-sigma modulation unit; A delta-sigma modulator comprising:

[0159] (Appendix 2) 2. The delta-sigma modulation device of claim 1, wherein the feedback signal conversion unit converts the feedback signal by interpolating zero values ​​in the feedback signal.

[0160] (Appendix 3) The feedback signal conversion unit is branching the feedback signal into a first feedback signal and a second feedback signal; Interpolating zero values ​​in the first feedback signal; and interpolating zero values ​​in the second feedback signal. multiplying the second feedback signal by an imaginary unit; adding the first feedback signal and the second feedback signal; 3. The delta-sigma modulation device of claim 1, wherein the feedback signal is converted by

[0161] (Appendix 4) The feedback signal conversion unit is extracting a real part from the added first feedback signal and the second feedback signal, and outputting the extracted signal to a first delta-sigma modulation unit of the delta-sigma modulation unit; extracting an imaginary part from the added first feedback signal and the second feedback signal, and outputting the extracted signal to a second delta-sigma modulation section of the delta-sigma modulation section; 4. The delta-sigma modulation device of claim 3.

[0162] (Appendix 5) The feedback signal conversion unit is Extracting a real part from the feedback signal; Extracting an imaginary part from the feedback signal; adding the feedback signal from which the real part has been extracted and the feedback signal from which the imaginary part has been extracted; subtracting the feedback signal from which the real part has been extracted, from the feedback signal from which the imaginary part has been extracted; 2. The delta-sigma modulation device of claim 1, wherein the feedback signal is converted by

[0163] (Appendix 6) The feedback signal conversion unit is outputting a first feedback signal and a second feedback signal from the feedback signal; Extracting a real part and an imaginary part from the first feedback signal; Extracting a real part and an imaginary part from the second feedback signal; adding the first feedback signal from which the real part has been extracted and the second feedback signal from which the imaginary part has been extracted; subtracting the second feedback signal from which the real part has been extracted, from the first feedback signal from which the imaginary part has been extracted; 6. The delta-sigma modulation device of claim 5, wherein the feedback signal is converted by

[0164] (Appendix 7) 7. The delta-sigma modulation device according to claim 6, wherein the feedback signal conversion unit outputs the first feedback signal and the second feedback signal from the feedback signal such that each bit of a bit sequence included in the first feedback signal and each bit of a bit sequence included in the second feedback signal alternate with each bit of a bit sequence included in the second feedback signal.

[0165] (Appendix 8) a first delta-sigma modulation unit of the delta-sigma modulation unit applying delta-sigma modulation to a real part of an input signal to generate a first output signal; a second delta-sigma modulation section of the delta-sigma modulation section applying delta-sigma modulation to an imaginary part of an input signal to generate a second output signal; the feedback signal generating unit rearranges a bit sequence included in the first output signal and a bit sequence included in the second output signal into a single string; 8. A delta-sigma modulation device according to any one of claims 1 to 7.

[0166] (Appendix 9) 9. The delta-sigma modulation device according to claim 1, wherein the feedback signal generation unit transmits the output signal to another device, estimates a waveform distortion suffered by the output signal from the output signal, and applies the amount of waveform distortion to the output signal to generate the feedback signal.

[0167] (Appendix 10) 9. The delta-sigma modulation device according to claim 1, wherein the feedback signal generation unit transmits the output signal to another device, receives the output signal from the other device, and generates the feedback signal from the received output signal.

[0168] (Appendix 11) applying delta-sigma modulation to an input signal to generate an output signal; receiving the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal; A method performed by a computing device, comprising:

[0169] (Appendix 12) 12. The method of claim 11, further comprising transforming the feedback signal by interpolating zero values ​​in the feedback signal.

[0170] (Appendix 13) branching the feedback signal into a first feedback signal and a second feedback signal; Interpolating zero values ​​in the first feedback signal; and interpolating zero values ​​in the second feedback signal. multiplying the second feedback signal by an imaginary unit; adding the first feedback signal and the second feedback signal; 13. The method of claim 11 or 12, further comprising converting the feedback signal by

[0171] (Appendix 14) extracting a real part from the summed first feedback signal and second feedback signal and outputting the extracted signal; extracting an imaginary part from the summed first feedback signal and second feedback signal, and outputting the extracted signal; 14. The method of claim 13, further comprising:

[0172] (Appendix 15) Extracting a real part from the feedback signal; Extracting an imaginary part from the feedback signal; adding the feedback signal from which the real part has been extracted and the feedback signal from which the imaginary part has been extracted; subtracting the feedback signal from which the real part has been extracted, from the feedback signal from which the imaginary part has been extracted; 12. The method of claim 11, further comprising converting the feedback signal by

[0173] (Appendix 16) outputting a first feedback signal and a second feedback signal from the feedback signal; Extracting a real part and an imaginary part from the first feedback signal; Extracting a real part and an imaginary part from the second feedback signal; adding the first feedback signal from which the real part has been extracted and the second feedback signal from which the imaginary part has been extracted; subtracting the second feedback signal from which the real part has been extracted, from the first feedback signal from which the imaginary part has been extracted; 16. The method of claim 15, further comprising converting the feedback signal by

[0174] (Appendix 17) 17. The method of claim 16, further comprising outputting the first feedback signal and the second feedback signal from the feedback signal such that each bit of a bit sequence included in the first feedback signal alternates with each bit of a bit sequence included in the second feedback signal.

[0175] (Appendix 18) applying delta-sigma modulation to a real portion of an input signal to generate a first output signal; applying delta-sigma modulation to an imaginary part of the input signal to generate a second output signal; rearrange a bit sequence included in the first output signal and a bit sequence included in the second output signal into a single string; 18. The method of any one of claims 11 to 17, further comprising:

[0176] (Appendix 19) 19. The method of any one of claims 11 to 18, further comprising: transmitting the output signal to another device; estimating a waveform distortion suffered by the output signal from the output signal; and applying the amount of waveform distortion to the output signal to generate the feedback signal.

[0177] (Appendix 20) 19. The method of any one of claims 11 to 18, further comprising transmitting the output signal to another device and receiving the output signal from the other device, and generating the feedback signal from the received output signal.

[0178] (Appendix 21) When executed, the method causes a processor in a computing device to: applying delta-sigma modulation to an input signal to generate an output signal; receiving the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal; A program to execute.

[0179] (Appendix 21) When executed, the method causes a processor in a computing device to: applying delta-sigma modulation to an input signal to generate an output signal; receiving the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal; A non-transitory recording medium that can be read by a computer and stores a program that causes the computer to execute the above. [Explanation of symbols]

[0180] 1. Wireless communication systems 100 Delta Sigma Modulator 110 Delta Sigma Modulation Section 120 Delta Sigma Modulation Section 130 Up-conversion section 140 Complex waveform distortion estimation unit 150 Down conversion section 200 Second Device 300 Communication Paths 400 Delta Sigma Modulator 410 Delta Sigma Modulation Section 420 Delta Sigma Modulation Section 430 Up-conversion section 440 Complex Waveform Distortion Estimation Unit 450 Down conversion section 500 Delta Sigma Modulator 510 Delta Sigma Modulation Section 520 Delta Sigma Modulation Section 530 Up-conversion section 550 Down conversion section 600 Second Device

Claims

1. a delta-sigma modulation unit that applies delta-sigma modulation to an input signal to generate an output signal; a feedback signal generating unit that receives the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; a feedback signal conversion unit that converts the feedback signal from a signal represented by a complex number to a signal represented by a real number and outputs the converted feedback signal to the delta-sigma modulation unit; A delta-sigma modulator comprising:

2. The delta-sigma modulation device according to claim 1 , wherein the feedback signal conversion section converts the feedback signal by interpolating zero values ​​in the feedback signal.

3. The feedback signal conversion unit is branching the feedback signal into a first feedback signal and a second feedback signal; Interpolating zero values ​​in the first feedback signal; and interpolating zero values ​​in the second feedback signal. multiplying the second feedback signal by an imaginary unit; adding the first feedback signal and the second feedback signal; 2. The delta-sigma modulator of claim 1, wherein the feedback signal is converted by:

4. The feedback signal conversion unit is extracting a real part from the added first feedback signal and the second feedback signal, and outputting the extracted signal to a first delta-sigma modulation unit of the delta-sigma modulation unit; extracting an imaginary part from the added first feedback signal and second feedback signal, and outputting the extracted signal to a second delta-sigma modulation section of the delta-sigma modulation section; 4. The delta-sigma modulation device according to claim 3.

5. The feedback signal conversion unit is Extracting a real part from the feedback signal; Extracting an imaginary part from the feedback signal; adding the feedback signal from which the real part has been extracted and the feedback signal from which the imaginary part has been extracted; subtracting the feedback signal from which the real part has been extracted, from the feedback signal from which the imaginary part has been extracted; 2. The delta-sigma modulator of claim 1, wherein the feedback signal is converted by:

6. The feedback signal conversion unit is outputting a first feedback signal and a second feedback signal from the feedback signal; Extracting a real part and an imaginary part from the first feedback signal; Extracting a real part and an imaginary part from the second feedback signal; adding the first feedback signal from which the real part has been extracted and the second feedback signal from which the imaginary part has been extracted; subtracting the second feedback signal from which the real part has been extracted, from the first feedback signal from which the imaginary part has been extracted; 6. The delta-sigma modulator of claim 5, wherein the feedback signal is converted by:

7. 7. The delta-sigma modulation device according to claim 6, wherein the feedback signal conversion unit outputs the first feedback signal and the second feedback signal from the feedback signal such that each bit of a bit sequence included in the first feedback signal and each bit of a bit sequence included in the second feedback signal alternate with each bit of a bit sequence included in the second feedback signal.

8. a first delta-sigma modulation section of the delta-sigma modulation section applying delta-sigma modulation to a real part of an input signal to generate a first output signal; a second delta-sigma modulation section of the delta-sigma modulation section applying delta-sigma modulation to an imaginary part of an input signal to generate a second output signal; the feedback signal generating unit rearranges a bit sequence included in the first output signal and a bit sequence included in the second output signal into a single string; 2. The delta-sigma modulation device according to claim 1.

9. applying delta-sigma modulation to an input signal to generate an output signal; receiving the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal; A method performed by a computing device, comprising:

10. When executed, the method causes a processor in a computing device to: applying delta-sigma modulation to an input signal to generate an output signal; receiving the output signal as a feedback signal, the output signal including a waveform distortion, and an amount of the waveform distortion being represented by a complex number; converting the feedback signal from a signal represented by a complex number to a signal represented by a real number, and outputting the converted feedback signal; A program to execute.

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