Photoelectric conversion device and method for driving the same

Abstract

To provide a photoelectric conversion device that can reduce the time required for reading pixel signals.SOLUTION: A photoelectric conversion device has a plurality of pixel circuits that are arranged to form a plurality of rows and a plurality of columns, and a control circuit that drives the plurality of pixel circuits. The plurality of pixel circuits each have: a signal generation circuit that has a photoelectric conversion part; a memory that holds a signal output from the signal generation circuit; and a sequential circuit that has a first input node to which the signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node. The plurality of pixel circuits include a first pixel circuit and a second pixel circuit arranged on the same row or the same column, and the output node in the sequential circuit of the first pixel circuit is connected with the third input node in the sequential circuit of the second pixel circuit.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] In recent years, image sensors and distance measuring systems have been improved in performance, such as by increasing the number of pixels and increasing the readout speed, and several proposals have been made for pixel information readout methods that correspond to the increase in the amount of information held by the entire pixel. Patent Documents 1 and 2 describe an image reading device that is configured to transfer image information from a light receiving unit to an image processing unit via another light receiving unit, thereby shortening the length of wiring connected to multiple light receiving units. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-070170 A [Patent Document 2] JP 2018-186478 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the technology described in Patent Document 1, when there are multiple pixel rows, the pixel signals must be processed in sequence outside the pixel circuit, which may require time to read out all the pixels. Also, in the technology described in Patent Document 2, a readout circuit outside the pixels is responsible for processing for each of multiple pixel columns, which essentially poses the same problem as Patent Document 1.

[0005] An object of the present invention is to provide a photoelectric conversion device and a driving method thereof that can shorten the time required to read out pixel signals. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, and a control circuit that drives the plurality of pixel circuits, each of the plurality of pixel circuits comprising a signal generation circuit having a photoelectric conversion unit, a memory that holds a signal output from the signal generation circuit, a sequential circuit having a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node, the plurality of pixel circuits including a first pixel circuit and a second pixel circuit arranged in the same row or the same column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, and a control circuit driving the plurality of pixel circuits, each of the plurality of pixel circuits including a signal generation circuit having a photoelectric conversion unit, a memory for holding a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory, the plurality of pixel circuits including a first group and a second group each including two or more pixel circuits arranged in the same row, the sequential circuits of the pixel circuits constituting each of the first group and the second group are connected in series along the row direction and are configured to sequentially transfer the signal held by each of the pixel circuits from one side to the other side along the row direction in response to a control signal from the control circuit, and the control circuit is configured to perform a signal transfer operation in the pixel circuits of the first group and a signal transfer operation in the pixel circuits of the second group in parallel by supplying a common control signal to the pixel circuits of the first group and the pixel circuits of the second group.

[0008] Furthermore, according to yet another disclosure of the present specification, there is provided a signal output device comprising a plurality of signal hold circuits arranged in a plurality of rows and a plurality of columns, and a control circuit driving the plurality of signal hold circuits, each of the plurality of signal hold circuits having a memory for holding a predetermined signal, and a sequential circuit to which the signal is transferred from the memory, the plurality of signal hold circuits including a first group and a second group each including two or more of the signal hold circuits arranged in the same row, the sequential circuits of the signal hold circuits constituting each of the first group and the second group are connected in series along the row direction and are configured to sequentially transfer the signal held by each of the signal hold circuits from one side to the other side along the row direction in response to a control signal from the control circuit, and the control circuit is configured to supply a common control signal to the signal hold circuits of the first group and the signal hold circuits of the second group, thereby performing a signal transfer operation in the signal hold circuits of the first group and a signal transfer operation in the signal hold circuits of the second group in parallel.

[0009] According to yet another disclosure of the present specification, there is provided a method for driving a photoelectric conversion device including a first group and a second group each including two or more pixel circuits arranged in the same row, the first group and the second group being connected in series along a row direction, the first group including a signal generation circuit having a photoelectric conversion unit, a memory for storing a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory ... sequential circuits of the pixel circuits constituting the first group and the second group being connected in series along a row direction, the method comprising the steps of: in each of the plurality of pixel circuits, storing in the memory a signal based on charges generated in the photoelectric conversion unit by incidence of light; and a step of sequentially transferring, in each of the pixel circuits of the first group and the second group, the signals held in the sequential circuits of the pixel circuits constituting each of the first and second groups from one side to the other along the row direction, wherein, in the sequential transfer step, a common control signal is supplied to the pixel circuits of the first group and the pixel circuits of the second group, and the signal transfer operation in the pixel circuits of the first group and the signal transfer operation in the pixel circuits of the second group are performed in parallel. Effect of the Invention

[0010] According to the present invention, in a photoelectric conversion device including a plurality of pixel circuits, it is possible to reduce the time required to read out pixel signals. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a signal output device according to a first embodiment of the present invention. [Diagram 2] 1 is a block diagram showing an example of the configuration of a signal holding circuit in a signal output device according to a first embodiment of the present invention. [Diagram 3] 1 is a block diagram (part 1) showing a configuration example of a clock buffer circuit in a signal output device according to a first embodiment of the present invention. FIG. [Figure 4]FIG. 2 is a block diagram (part 2) showing a configuration example of a clock buffer circuit in the signal output device according to the first embodiment of the present invention. [Diagram 5] FIG. 3 is a block diagram (part 3) showing a configuration example of a clock buffer circuit in the signal output device according to the first embodiment of the present invention. [Figure 6] FIG. 4 is a block diagram (part 4) showing a configuration example of a clock buffer circuit in the signal output device according to the first embodiment of the present invention. [Figure 7] 4 is a timing diagram showing a method for driving the signal output device according to the first embodiment of the present invention. FIG. [Figure 8] FIG. 11 is a circuit diagram showing a schematic configuration of a signal output device according to a second embodiment of the present invention. [Figure 9] FIG. 11 is a block diagram showing a schematic configuration of a signal output device according to a third embodiment of the present invention. [Figure 10] FIG. 11 is a circuit diagram showing another configuration example of the signal output device according to the third embodiment of the present invention. [Figure 11] FIG. 11 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 12] FIG. 13 is a block diagram showing a schematic configuration of a light detection system according to a fifth embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing a schematic configuration of a range image sensor according to a sixth embodiment of the present invention. [Figure 14] FIG. 13 is a schematic diagram showing an example of the configuration of an endoscopic surgery system according to a seventh embodiment of the present invention. [Figure 15] FIG. 13 is a schematic diagram showing a configuration example of a moving body according to an eighth embodiment of the present invention. [Figure 16] FIG. 13 is a block diagram showing a schematic configuration of a light detection system according to an eighth embodiment of the present invention. [Figure 17] FIG. 13 is a flow chart showing the operation of the light detection system according to the eighth embodiment of the present invention. [Figure 18] FIG. 13 is a schematic diagram showing a schematic configuration of a light detection system according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [First embodiment] A signal output device and a driving method thereof according to a first embodiment of the present invention will be described with reference to Figs. 1 to 7. Fig. 1 is a block diagram showing a schematic configuration of a signal output device according to this embodiment. Fig. 2 is a block diagram showing a configuration example of a signal holding circuit in the signal output device according to this embodiment. Figs. 3 to 6 are circuit diagrams showing a configuration example of a clock buffer circuit in the signal output device according to this embodiment. Fig. 7 is a timing chart showing a driving method of the signal output device according to this embodiment.

[0013] First, a schematic configuration of a signal output device according to the present embodiment will be described with reference to Fig. 1. A signal output device 50 according to the present embodiment has a signal holding area 10 and a clock buffer circuit 40, as shown in Fig. 1.

[0014] The signal holding region 10 is provided with a plurality of signal holding circuits 12 arranged in a matrix to form a plurality of rows and a plurality of columns. In FIG. 1, it is assumed that the signal holding region 10 is composed of a plurality of signal holding circuits 12 arranged in a matrix of M rows by N columns. Each of the plurality of signal holding circuits 12 is given a coordinate corresponding to the row number and column number. For example, the block of the signal holding circuit 12 arranged in the mth row and the nth column is given the coordinate (m, n) in addition to the reference number 12. Here, m is an integer from 1 to M, and n is an integer from 1 to N. The number of signal holding circuits 12 constituting the signal holding region 10 is not particularly limited as long as M is an integer equal to or greater than 1, and N is an integer equal to or greater than 2. Note that the rows and columns can be defined arbitrarily, and the rows described in this embodiment may be columns, and the columns described in this embodiment may be rows.

[0015] The N signal hold circuits 12 arranged in each row of the signal hold region 10 constitute a signal hold circuit group 14. In FIG. 1, the reference numerals of the signal hold circuit groups 14 in each row are given the corresponding row numbers. For example, the signal hold circuit group 14 arranged in the m-th row is denoted by reference numeral 14. mThe N signal hold circuits 12 constituting the signal hold circuit group 14 are connected in series. For example, m Taking the example of signal holding circuit 12(m,1) as an example, the input node of signal holding circuit 12(m,1) is connected to a ground voltage node, and the output node of signal holding circuit 12(m,1) is connected to an input node of signal holding circuit 12(m,2), not shown. The input node of signal holding circuit 12(m,n) is connected to an output node of signal holding circuit 12(m,n-1), and the output node of signal holding circuit 12(m,n) is connected to an input node of signal holding circuit 12(m,n+1). The input node of signal holding circuit 12(m,N) is connected to an output node of signal holding circuit 12(m,N-1), not shown, and the output node of signal holding circuit 12(m,N) is connected to an output line 18. m is connected to

[0016] A signal line 16 is arranged in each column of the signal holding region 10. In FIG. 1, the reference numerals of the signal lines 16 in each column are assigned corresponding column numbers. For example, the signal line 16 arranged in the n-th column is denoted by reference numeral 16. n Each of the signal lines 16 is connected to the signal hold circuits 12 arranged in the corresponding column. For example, the signal lines 16 n are connected to the signal hold circuits 12(1,n), ..., 12(m-1,n), 12(m,n), 12(m+1,n), ..., 12(M,n) arranged in the nth column. The signal line 16 is connected to a clock buffer circuit 40.

[0017] The clock buffer circuit 40 serves as a control circuit that drives the signal holding circuit 12. The clock buffer circuit 40 has one input node to which a clock signal is input, and output nodes TAP, the number of which corresponds to each column of the signal holding area 10. In FIG. 1, the reference numerals of the output nodes TAP of each column are assigned corresponding column numbers. For example, the output node TAP arranged in the nth column is designated by the reference numeral TAP. n Each of the output nodes TAP outputs a clock signal which is input to the clock buffer circuit 40 and processed by the internal circuitry thereof.

[0018] In FIG. 1, M signal holding circuit groups 141 to 14 M However, the clock buffer circuit 40 can be provided for any row unit. For example, a plurality of signal hold circuits 141 to 14 M Alternatively, one clock buffer circuit 40 may be provided for each of two or more arbitrary number of signal hold circuit groups 14. Reducing the number of clock buffer circuits 40 has the advantage of improving the power efficiency of the entire device.

[0019] Next, a configuration example of the signal holding circuit 12 will be described with reference to Fig. 2. Fig. 2 shows a signal holding circuit group 14 among the multiple signal holding circuits 12 constituting the signal holding area 10. m 2. The configuration and connection relationship of the internal circuits of the other signal holding circuits 12 are also similar to those of the signal holding circuit 12 shown in Fig. 2. Note that the circuits constituting the signal holding circuit 12 are not particularly limited as long as they have the function of holding a signal, but the following description will be given taking the pixel circuit of a photoelectric conversion device as an example.

[0020] The signal holding circuit 12 may be configured, for example, as shown in Fig. 2, by a signal generating circuit 24, a memory 26, and a sequential circuit 28. The signal generating circuit 24 is connected to the memory 26. The memory 26 is connected to the sequential circuit 28. The signal generating circuit 24 includes a photoelectric conversion element, generates a signal according to incident light on the photoelectric conversion element, and outputs the signal to the memory 26. The memory 26 holds a signal input from the signal generating circuit 24, and outputs the held signal to the sequential circuit 28 in response to an external control signal. The sequential circuit 28 is a circuit whose output state is determined by a combination of an external input signal and a held internal state, and may be configured, for example, by a D-type flip-flop with a set terminal.

[0021] A D-type flip-flop with a set terminal includes two input terminals (D terminal and S terminal), one clock input terminal (CK terminal), and one output terminal (Q terminal). When a signal is input to the S terminal, the data output from the Q terminal of sequential circuit 28 has the level of the signal input to the S terminal, regardless of the clock signal input to the CK terminal. When a signal is input to the D terminal, the data output from the Q terminal of sequential circuit 28 has the level of the signal input to the D terminal in synchronization with the level transition of the clock signal input to the CK terminal. The clock signal input to the CK terminal can also be considered a control signal for sequential circuit 28.

[0022] A D-type flip-flop in which the level of the signal output from the Q terminal changes in synchronization with the rising edge (positive edge) of the clock signal is called a positive edge triggered D-type flip-flop. A D-type flip-flop in which the level of the signal output from the Q terminal changes in synchronization with the falling edge (negative edge) of the clock signal is called a negative edge triggered D-type flip-flop. Sequential circuit 28 may be configured with either type of D-type flip-flop, but here it is assumed to be configured with a positive edge triggered D-type flip-flop.

[0023] An S terminal of the sequential circuit 28 is connected to an output node of the memory 26. A D terminal of the sequential circuit 28 is connected to an input node 20 of the signal holding circuit 12. A CK terminal of the sequential circuit 28 is connected to an input node 22 of the signal holding circuit 12. A Q terminal of the sequential circuit is connected to an output node 30 of the signal holding circuit 12.

[0024] The N signal hold circuits 12 arranged in the same row and constituting one signal hold circuit group 14 are connected in series as described above. For example, the input node 20 of the signal hold circuit 12(m,n) is connected to the output node 30 of the signal hold circuit 12(m,n-1), and the output node 30 of the signal hold circuit 12(m,n) is connected to the input node 20 of the signal hold circuit 12(m,n+1). The input node 22 of the signal hold circuit 12 is connected to the signal line 16 arranged in the corresponding column. For example, the input node 22 of the signal hold circuit 12(m,n) is connected to the output node TAP of the clock buffer circuit 40. n Signal line 16 connected to n As a result, the series connection of the sequential circuits 28 included in the signal hold circuits 12 in each column of the signal hold circuit group 14 constitutes a shift register.

[0025] It can be said that the signal hold circuit group 14 in each row has one input node and one output node as a whole. For example, the input node 20 of the signal hold circuit 12(m,1) is connected to the signal hold circuit group 14 m The output node 30 of the signal holding circuit 12(m,N) is the input node of the signal holding circuit group 14 m 1, the input node 20 of the signal holding circuit 12(m,1) is connected to the ground voltage node, but it is also possible to configure the signal holding circuit 12(m,1) to input any logic signal from the input node 20.

[0026] Next, a configuration example of the clock buffer circuit 40 will be described with reference to Fig. 3 to Fig. 6. As described above, the clock buffer circuit 40 has one input node CIN and N output nodes TAP1 to TAP2 corresponding to the number of columns constituting the signal holding area 10. N A clock signal is input to the input node CIN, and output nodes TAP1 to TAP NA clock signal shaped by an internal circuit is output from the clock buffer circuit 40. The clock buffer circuit 40 may be configured to include a plurality of buffer circuits 42 and a plurality of inverting buffer circuits 46, as shown in Figures 3 to 6, for example. The clock buffer circuit 40 may be configured with a buffer structure such as a tree type or a repeater type, but the following description will be given with a repeater type buffer structure in mind as an example.

[0027] 3 is configured by connecting N buffer circuits 42 in series, the number of which corresponds to the number of columns constituting the signal holding area 10. The output nodes of the N buffer circuits 42 are connected in series to the output node TAP of the clock buffer circuit 40 in order from the side closest to the input node CIN. N ,TAP N-1 ,…,TAP n+1 ,TAP n ,TAP n-1 , …, TAP2, TAP1.

[0028] 4 is a configuration example in which a logic circuit 44 is connected between the output node TAP of each column and the output node of a buffer circuit 42. Here, the logic circuit 44 is, for example, a circuit for improving the bluntness of a voltage waveform of a buffer, an inverter, etc. In other words, by providing the logic circuit 44, N This reduces the dependency between the voltage waveform and the output impedance of the buffer circuit 42, thereby improving the degree of freedom in circuit design.

[0029] 5, the buffer circuit 42 is replaced with an inverting buffer circuit 46. The clock buffer circuit 40 does not necessarily have to be a non-inverting buffer circuit, and may be an inverting buffer circuit. The inverting buffer circuit 46 may be applied to the configuration example of FIG.

[0030] 6 is configured by connecting (N / 2) buffer circuits 42 in series, where N is the number of columns constituting the signal holding area 10. Two output nodes TAP of the clock buffer circuit 40 are connected to the output nodes of each of the (N / 2) buffer circuits 42. For example, the output node of the buffer circuit 42 disposed closest to the input node CIN is the output node TAP. N and TAP N-1 . The output node of the (N / 2)th buffer circuit 42 from the input node CIN is connected to output nodes TAP2 and TAP1. Clock pulses are output at the same timing from the two output nodes TAP connected to the output node of the same buffer circuit 42. Note that, although an example in which two output nodes TAP are connected to the output node of the same buffer circuit 42 has been shown here, three or more output nodes TAP may be connected to the output node of the same buffer circuit 42. This configuration may be applied to the configuration example of FIG. 4 or FIG. 5.

[0031] Incidentally, the input node CIN of the clock buffer circuit 40 may be provided on the side of the first column of the signal hold circuit group 14, but from the viewpoint of timing design controllability, it is more preferable to provide it on the side of the Nth column of the signal hold circuit group 14 as shown in Figures 3 to 6. In this case, for example, the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the (n-1)th column of the signal hold circuit 12 passes will be greater than the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the nth column of the signal hold circuit 12 passes.

[0032] Next, the operation of the signal output device according to this embodiment will be described with reference to Fig. 7. Fig. 7 shows an outline of the operation of the signal output device in the Jth frame and the (J+1)th frame. The period from time t0 to time t2 is the Jth frame period, and the period from time t2 to time t4 is the (J+1)th frame period.

[0033] The period from time t1 to time t2 is the exposure period of the Jth frame. When light is incident on the signal holding region 10 during the exposure period, the signal generation circuit 24 of each signal holding circuit 12 generates a logic signal of logic H or logic L according to the incident light, and outputs the generated logic signal to the memory 26. The logic signal output from the signal generation circuit 24 is stored in the memory 26. The logic signal stored in the memory 26 during the exposure period of the Jth frame is read out during the next (J+1)th frame period.

[0034] After the logic signal of the signal generation circuit 24 of each signal holding circuit 12 is determined at time t2, the memory 26 of each signal holding circuit 12 outputs the held logic signal to the S terminal of the sequential circuit 28 in response to a control signal from a control circuit (not shown). As a result, the sequential circuit 28 holds the logic signal transferred from the memory 26 as its output.

[0035] During the period from time t3 to time t4 after the transfer of logic signals from the memory 26 to the sequential circuit 28 in each signal hold circuit 12 is completed, a control circuit (not shown) inputs a certain number or more of clock pulses from the input node CIN of the clock buffer circuit 40. As a result, clock pulses are output from each output node TAP of the clock buffer circuit 40 at a predetermined timing according to the input timing of the clock pulse to the input node CIN and the number of buffer circuits 42 to each output node TAP. Note that the number of clock pulses input to the clock buffer circuit 40 (the above-mentioned certain number or more) may be (N-1) or more, where N is the number (number of columns) of the signal hold circuits 12 constituting the signal hold circuit group 14.

[0036] The sequential circuit 28 of each column of the signal holding circuit 12 constituting the signal holding circuit group 14 is driven by a clock pulse output from the corresponding output node TAP of the clock buffer circuit 40. Each time the sequential circuit 28 receives a clock pulse, it sends out the logic signal that has been set to the sequential circuit 28 of the subsequent stage. For example, the logic signal that has been set in the sequential circuit 28 of the signal holding circuit 12(m,n) is set in the sequential circuit 28 of the subsequent stage signal holding circuit 12(m,n+1) upon receiving a clock pulse input to the signal holding circuit 12(m,n-1). Also, the logic signal that has been set in the sequential circuit 28 of the signal holding circuit 12(m,n-1) is set in the sequential circuit 28 of the subsequent stage signal holding circuit 12(m,n) upon receiving a clock pulse input to the signal holding circuit 12(m,n-1). As a result, the logic signals held in the signal holding circuits 12 of each column are sequentially transferred to the output line 18, and a number of logic signals corresponding to the number of clock pulses input to the clock buffer circuit 40 are output as a bit stream to the output line 18 of the signal holding circuit group 14.

[0037] In this way, by inputting a number of clock pulses corresponding to the number of signal holding circuits 12 constituting each signal holding circuit group 14, it is possible to output bit streams of all rows of signal holding circuit groups 14. That is, data of all signal holding circuits 12 constituting the signal holding area 10 can be read out and output to a downstream device (not shown). For example, if the signal holding area 10 is composed of signal holding circuits 12 arranged in a matrix of 1000 rows x 1000 columns, 1 Mbit of information held by the signal holding area 10 can be read out by inputting 999 clock pulses, thereby shortening the read time.

[0038] In addition, the output nodes TAP1 to TAP N The phases of the clock pulses output from the output nodes TAP are different from each other, and the timing at which the sequential circuits 28 of the signal hold circuits 12 of each column send out the logic signals to the subsequent stages also differs in time. n The phase of the clock pulse output from the output node TAP NThe phase of the clock pulse output from the nth column 28 lags behind that of the clock pulse output from the nth column 28. As a result, the drive timing of the sequential circuit 28 of the signal holding circuit 12 in the nth column 28 is slower than the drive timing of the sequential circuit 28 of the signal holding circuit 12 in the Nth column 28. Therefore, the power supply bounce caused by the read operation of the logic signal from the signal holding area 10 is a superposition of small voltage peaks with different phases over the entire read time. The effect of spreading the strength of this power supply bounce over time reduces obstacles to high-speed read operations.

[0039] Furthermore, when the input node CIN of the clock buffer circuit 40 is located on the Nth column side of the signal holding area 10, it becomes easy to control the timing of the phase of the clock signal input by a control circuit (not shown) and the phase of the bit stream output from the signal holding circuit group 14. Relaxing design constraints regarding timing is an advantage for increasing the read speed.

[0040] In addition, the transfer period for transferring the logic signal acquired during the exposure period of the Jth frame can be performed in parallel with the exposure period of the next frame (the (J+1)th frame), which can further increase the readout speed.

[0041] As described above, according to this embodiment, in a photoelectric conversion device including a plurality of pixel circuits, it is possible to reduce the time required to read out pixel signals.

[0042] [Second embodiment] A signal output device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Fig. 8. Components similar to those of the signal output device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 8 is a circuit diagram showing a schematic configuration of the signal output device according to this embodiment.

[0043] The schematic configuration of the signal output device according to the present embodiment will be described with reference to Fig. 8. Fig. 8 shows a signal holding circuit group 14 among the signal holding circuits 12 constituting the signal holding area 10. m1 shows two signal hold circuits 12(m, n) and 12(m, n+1) arranged in adjacent columns and a corresponding portion of the clock buffer circuit 40.

[0044] In the signal output device according to the present embodiment, the sequential circuits 28 in the signal retention circuits 12 arranged in adjacent columns in the same row are different in configuration. Specifically, one of the two adjacent signal retention circuits 12 is configured using a positive edge triggered D-type flip-flop (sequential circuit 28P), and the other is configured using a negative edge triggered D-type flip-flop (sequential circuit 28N). For example, when the signal retention circuit 12(m,n) is configured using a positive edge triggered sequential circuit 28P, the signal retention circuit 12(m,n-1) and the signal retention circuit 12(m,n+1) are configured using a negative edge triggered sequential circuit 28N. In addition, the clock buffer circuit 40 is configured using an inversion buffer circuit 46 to adapt to a clock drive suitable for the operation of the sequential circuits 28P and 28N.

[0045] The signal generating circuit 24 is assumed to be a SPAD (Single Photon Avalanche Diode) circuit, and outputs a logic signal of logic H when it detects the incidence of light. For example, as shown in FIG. 8, such a signal generating circuit 24 may be configured with an avalanche photodiode PD, a quenching element Mq, a waveform shaping circuit INV, and a logic circuit AND1. A voltage Vbias1 is supplied to the cathode of the avalanche photodiode PD via the quenching element Mq, and a voltage Vbias2 is supplied to the anode of the avalanche photodiode PD. An input node of the waveform shaping circuit INV is connected to a connection node between the cathode of the avalanche photodiode PD and the quenching element Mq. An output node of the waveform shaping circuit INV is connected to one input node of the logic circuit AND1, and a control signal sel is supplied to the other input node of the logic circuit AND1 from a control circuit not shown. An output node of the logic circuit AND1 becomes the output node of the signal generating circuit 24.

[0046] When light is incident on the avalanche photodiode PD with a reverse bias voltage equivalent to the potential difference between voltages Vbias1 and Vbias2 applied to it, electron-hole pairs are generated by photoelectric conversion, and an avalanche current flows using these charges as seeds. The waveform shaping circuit INV shapes the voltage change caused by the avalanche current flowing through the avalanche photodiode PD into a pulse signal, and outputs a logic signal of logic H according to the incident light. The logic circuit AND1 outputs a logic signal of logic H when the output signal of the waveform shaping circuit INV and the control signal sel are both logic H.

[0047] 8, the memory 26 may be composed of an RS flip-flop circuit FF and a logic circuit AND2. The RS flip-flop circuit FF includes two input terminals (S terminal and R terminal) and one output terminal (Q terminal). The S terminal of the RS flip-flop circuit FF is connected to the output node of the signal generating circuit 24, and the Q terminal of the RS flip-flop circuit FF is connected to one input node of the logic circuit AND2. A control signal clear is supplied to the R terminal of the RS flip-flop circuit FF from a control circuit not shown, and a control signal WRT is supplied to the other input node of the logic circuit AND2 from a control circuit not shown. The output node of the logic circuit AND2 becomes the output node of the memory 26.

[0048] The RS flip-flop circuit FF is bi-stable, and when it receives a logic signal of logic H from the signal generating circuit 24, it holds the logic signal and outputs it from the terminal Q. Furthermore, when the RS flip-flop circuit FF receives a control signal clear of logic H from a control circuit (not shown), it resets the logic signal it holds. The logic circuit AND1 outputs a logic signal of logic H when the output signal of the RS flip-flop circuit FF and the control signal WRT are both logic H.

[0049] The configuration and operation of the sequential circuits 28P and 28N are as described in the first embodiment. That is, the sequential circuit 28P may be configured by a positive edge triggered D-type flip-flop circuit, and the sequential circuit 28N may be configured by a negative edge triggered D-type flip-flop circuit. When the output of the memory 26 is logic H, the sequential circuits 28P and 28N output logic H at the Q terminal in response to a control signal at an appropriate timing from a control circuit (not shown). Before this appropriate timing, the Q terminals of the sequential circuits 28 of all the signal retention circuits 12 constituting the signal retention circuit group 14 must be logic L. This can be realized by inputting a clock pulse equal to or greater than the number of the signal retention circuits 12 constituting the signal retention circuit group 14 to the input node CIN of the clock buffer circuit 40 while fixing the input node of the signal retention circuit group 14 to logic L.

[0050] In the signal output device according to this embodiment, the design of the clock buffer circuit 40 and the sequential circuits 28P, 28N is simplified, making it possible to reduce the circuit area and power consumption. Even if the output driving force of the inverting repeat buffer of the clock buffer circuit 40 is unbalanced at the rising and falling edges of the signal, the driving force unbalance is offset during the inverting repeat propagation. This makes it possible to mitigate the adverse effect of the reduction or expansion of the duty of the voltage waveform propagating to the upstream tap of the signal hold circuit 12. The reduction in area and power consumption and the improvement in the designability of the buffer circuit are advantageous in terms of speeding up the read operation.

[0051] As described above, according to this embodiment, in a photoelectric conversion device including a plurality of pixel circuits, it is possible to reduce the time required to read out pixel signals.

[0052] [Third embodiment] A signal output device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Figs. 9 and 10. Components similar to those of the signal output device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 9 is a block diagram showing a schematic configuration of the signal output device according to this embodiment. Fig. 10 is a circuit diagram showing an example of the configuration of the signal output device according to this embodiment.

[0053] 9 shows a plurality of signal hold circuits 12 constituting one row among the components of the signal output device according to this embodiment. In this embodiment, the plurality of signal hold circuits 12 constituting one row (for example, the mth row) are divided into two signal hold circuit groups 14A m ,14B m The two signal holding circuit groups 14A m ,14B m The method of allocating the signal hold circuits 12 to the signal hold circuits 14A is not particularly limited. For example, m ,14B m The signal holding circuit group 14A can be arranged alternately for every two columns. m ,14B m 9, for example, the signal hold circuits 12(m,1), 12(m,2), ..., 12(m,N-3), 12(m,N-2) are assigned to the signal hold circuit group 14A m In addition, the signal holding circuits 12(m,3), 12(m,4), ..., 12(m,N-1), and 12(m,N) are grouped into a signal holding circuit group 14B. m In addition, the signal holding circuit group 14A m ,14B m The signal hold circuits 12 may be allocated to each row, or may be allocated to every predetermined number of columns, which may be three or more. Furthermore, the signal hold circuits 12 constituting one row may be allocated to three or more signal hold circuit groups 14.

[0054] The output lines 18m arranged in each row correspond to the signal holding circuit groups 14A and 14B. m ,18B mThe clock buffer circuit 40 is divided into the signal holding circuit group 14A. m ,14B m In the same manner as in the first embodiment, the clock signal output from each output node TAP is input to the signal hold circuit 12 in the corresponding column. m From the signal holding circuit 12 belonging to m and a signal holding circuit group 14B m From the signal holding circuit 12 belonging to m This allows the signal to be read out in parallel with the signal being input to the input terminal.

[0055] 10 shows a partial sequential circuit 28 of the multiple signal hold circuits 12 constituting two rows (the mth row and the (m+1)th row) of the components of the signal output device according to this embodiment. In the configuration example of FIG. 10, the signal hold circuits 12 including the sequential circuit 28P and the signal hold circuits 12 including the sequential circuit 28N are arranged alternately every four columns, and a common clock signal is input to every four columns. In addition, the multiple signal hold circuits 12 in each row are alternately assigned to the signal hold circuit groups 14A and 14B for each column. For example, the signal hold circuits 12 arranged in the odd-numbered columns belong to the signal hold circuit group 14A, and the signal hold circuits 12 arranged in the odd-numbered columns belong to the signal hold circuit group 14A.

[0056] In this embodiment, the number of signal hold circuits 12 included in each of the signal hold circuit groups 14A and 14B is half the number of signal hold circuits 12 included in the signal hold circuit group 14 of the first or second embodiment. Furthermore, reading of signals from the signal hold circuit group 14A and reading of signals from the signal hold circuit group 14B can be performed in parallel without newly rearranging the clock buffer circuit 40. Therefore, according to this embodiment, the time required to read signals from the signal hold circuits 12 of each row can be reduced by half compared to the signal output device according to the first or second embodiment. Furthermore, in this embodiment, the number of clock pulses required to read signals from the multiple signal hold circuits 12 constituting one row is also reduced by half. This allows for low power consumption in circuit signal processing.

[0057] As described above, according to this embodiment, in a photoelectric conversion device including a plurality of pixel circuits, it is possible to reduce the time required to read out pixel signals.

[0058] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Fig. 11. The same components as those in the signal output devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 11 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment.

[0059] In this embodiment, an example in which the configuration of the signal output device according to the first embodiment is applied to a photoelectric conversion device is shown. Note that, although an example in which the signal output device according to the first embodiment is applied is shown here, the same can be applied to the signal output device according to the second or third embodiment. Furthermore, the configuration of the signal output device according to the first to third embodiments is applicable not only to photoelectric conversion devices but also to various devices configured to output signals from a plurality of signal holding units.

[0060] The photoelectric conversion device 100 according to this embodiment may be composed of a pixel region 110, a vertical drive circuit 120, a control circuit 130, a clock buffer circuit 140, a signal processing circuit 150, and an output circuit 160, as shown in FIG.

[0061] The pixel region 110 includes a plurality of pixels 112 arranged in an array having a plurality of rows and a plurality of columns. Each pixel 112 is a functional block corresponding to the signal retention circuit 12 of the first to third embodiments, and may include a photoelectric conversion unit including a photoelectric conversion element and a pixel signal processing unit that processes a signal output from the photoelectric conversion unit. The number of pixels 112 constituting the pixel region 110 is not particularly limited. For example, the pixel region 110 may be constituted by a plurality of pixels 112 arranged in an array of several thousand rows and several thousand columns, as in a general digital camera. Alternatively, the pixel region 110 may be constituted by a plurality of pixels 112 arranged in one row or one column.

[0062] In each row of the pixel array of the pixel region 110, a control line 114 is arranged extending in a first direction (horizontal direction in FIG. 11). The control line 114 is connected to each of the pixels 112 arranged in the first direction, and serves as a signal line common to these pixels 112. The first direction in which the control lines 114 extend may be called the row direction or horizontal direction. Each of the control lines 114 may include a plurality of signal lines for supplying a plurality of types of control signals to the pixels 112. The control line 114 in each row is connected to a vertical drive circuit 120. The control signals supplied from the vertical drive circuit 120 to the pixels 112 may include, for example, the control signals sel, clear, and WRT described in the second embodiment.

[0063] The pixels 112 arranged in each row of the pixel array of the pixel region 110 are connected in series in a first direction. An output line 118 is connected to an output node of the pixel 112 located at the end of each row in the first direction. The output line 118 of each row is connected to a signal processing circuit 150.

[0064] In each column of the pixel array in the pixel region 110, a signal line 116 is arranged to extend in a second direction (vertical direction in FIG. 11) intersecting the first direction. The signal line 116 is connected to each of the pixels 112 aligned in the second direction, and serves as a common signal line for these pixels 112. The second direction in which the signal line 116 extends may be referred to as the column direction or vertical direction. The signal line 116 of each column is connected to a clock buffer circuit 140.

[0065] The clock buffer circuit 140, like the clock buffer circuits in the first to third embodiments, has a role of supplying clock pulses to the pixels 112 in each column at a predetermined timing.

[0066] The signal processing circuit 150 is a functional block that performs predetermined signal processing on pixel signals output from the output lines 118 of each row. The signal processing performed by the signal processing circuit 150 is not particularly limited, but examples thereof include correction processing, binning processing, and averaging processing.

[0067] The output circuit 160 has an external interface circuit and is a functional block for outputting the pixel signals processed by the signal processing circuit 150 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output circuit 160 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be applied to the external interface circuit.

[0068] The control circuit 130 is a control circuit for generating control signals for controlling the operations and timings of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing circuit 150, and supplying them to each functional block. Note that at least some of the control signals for controlling the operations and timings of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing circuit 150 may be supplied from outside the photoelectric conversion device 100. The control signals supplied from the control circuit 130 to the clock buffer circuit 140 may include the clock signals described in the first to third embodiments.

[0069] As described above, according to this embodiment, by applying the signal output device according to the first to third embodiments, it is possible to realize a photoelectric conversion device that enables high-speed readout of pixel signals.

[0070] [Fifth embodiment] A light detection system according to a fifth embodiment of the present invention will be described with reference to Fig. 12. Fig. 12 is a block diagram showing a schematic configuration of the light detection system according to this embodiment. In this embodiment, a light detection sensor to which the photoelectric conversion device 100 according to the fourth embodiment is applied will be described.

[0071] The photoelectric conversion device 100 described in the fourth embodiment is applicable to various photodetection systems. Examples of the applicable photodetection systems include imaging systems such as digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photodetection system. FIG. 12 illustrates a block diagram of a digital still camera as an example of these.

[0072] 12 includes a photoelectric conversion device 201, a lens 202 that forms an optical image of a subject on the photoelectric conversion device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the photoelectric conversion device 201. The photoelectric conversion device 201 is the photoelectric conversion device 100 described in the fourth embodiment, and converts the optical image formed by the lens 202 into image data.

[0073] The light detection system 200 also includes a signal processing unit 208 that processes an output signal output from the photoelectric conversion device 201. The signal processing unit 208 generates image data from a digital signal output from the photoelectric conversion device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The photoelectric conversion device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which the photon detection element of the photoelectric conversion device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photon detection element of the photoelectric conversion device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the photoelectric conversion device 201.

[0074] The light detection system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The light detection system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out the imaging data on the recording medium 214. The recording medium 214 may be built into the light detection system 200, or may be removable. Furthermore, communication between the recording medium control I / F unit 216 and the recording medium 214 and communication from the external I / F unit 212 may be performed wirelessly.

[0075] The light detection system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the photoelectric conversion device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the light detection system 200 only needs to include at least the photoelectric conversion device 201 and the signal processing unit 208 that processes the output signal output from the photoelectric conversion device 201. The timing generation unit 220 may be mounted on the photoelectric conversion device 201. Moreover, the overall control / calculation unit 218 and the timing generation unit 220 may be configured to implement a part or all of the control functions of the photoelectric conversion device 201.

[0076] The photoelectric conversion device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal. The signal processing unit 208 may be configured to perform distance measurement calculation on the signal output from the photoelectric conversion device 201.

[0077] As described above, according to this embodiment, by configuring a light detection system using the photoelectric conversion device of the fourth embodiment, it is possible to realize a light detection system capable of quickly acquiring an image.

[0078] [Sixth embodiment] A range image sensor according to a sixth embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a block diagram showing a schematic configuration of the range image sensor according to this embodiment. In this embodiment, the range image sensor will be described as an example of a light detection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0079] 13, the range image sensor 300 according to this embodiment may include an optical system 302, a photoelectric conversion device 304, an image processing circuit 306, a monitor 308, and a memory 310. This range image sensor 300 receives light (modulated light or pulsed light) that is irradiated from a light source device 320 toward a subject 330 and reflected by the surface of the subject 330, and obtains a range image according to the distance to the subject 330.

[0080] The optical system 302 is composed of one or more lenses, and serves to focus image light (incident light) from a subject 330 on the light receiving surface (sensor section) of the photoelectric conversion device 304 .

[0081] The photoelectric conversion device 304 is the photoelectric conversion device 100 described in the fourth embodiment, and has the function of generating a distance signal indicating the distance to the subject 330 based on the image light from the subject 330, and supplying the generated distance signal to the image processing circuit 306.

[0082] The image processing circuit 306 has a function of performing image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 304 .

[0083] The monitor 308 has a function of displaying a distance image (image data) obtained by image processing in the image processing circuit 306. In addition, the memory 310 has a function of storing (recording) the distance image (image data) obtained by image processing in the image processing circuit 306.

[0084] As described above, according to this embodiment, by configuring a range image sensor using the photoelectric conversion device of the fourth embodiment, it is possible to realize a range image sensor capable of quickly acquiring a range image.

[0085] [Seventh embodiment] An endoscopic surgery system according to a seventh embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a schematic diagram showing a configuration example of the endoscopic surgery system according to this embodiment. In this embodiment, the endoscopic surgery system will be described as an example of a light detection system to which the photoelectric conversion device 100 of the fourth embodiment is applied.

[0086] FIG. 14 shows a state in which an operator (doctor) 460 is performing surgery on a patient 472 lying on a patient bed 470 using an endoscopic surgery system 400.

[0087] The endoscopic surgery system 400 of this embodiment may include an endoscope 410, a surgical tool 420, and a cart 430 on which various devices for endoscopic surgery are mounted, as shown in Fig. 14. The cart 430 may be mounted with a CCU (camera control unit) 432, a light source device 434, an input device 436, a treatment tool control device 438, a display device 440, and the like.

[0088] The endoscope 410 includes a lens barrel 412, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 472, and a camera head 414 connected to a base end of the lens barrel 412. Although Fig. 14 illustrates the endoscope 410 configured as a so-called rigid lens barrel having a rigid lens barrel 412, the endoscope 410 may be configured as a so-called flexible lens barrel having a flexible lens barrel. The endoscope 410 is held in a movable state by an arm 416.

[0089] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 412. A light source device 434 is connected to the endoscope 410, and light generated by the light source device 434 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 412, and is irradiated via the objective lens toward an observation target in the body cavity of the patient 472. The endoscope 410 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0090] An optical system and a photoelectric conversion device (not shown) are provided inside the camera head 414, and reflected light (observation light) from an observation target is collected by the optical system onto the photoelectric conversion device. The photoelectric conversion device photoelectrically converts the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The photoelectric conversion device may be the photoelectric conversion device 100 described in the fourth embodiment. The image signal is transmitted to the CCU 432 as RAW data.

[0091] The CCU 432 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 410 and the display device 440. Furthermore, the CCU 432 receives an image signal from the camera head 414, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0092] Under the control of the CCU 432 , the display device 440 displays an image based on the image signal that has been subjected to image processing by the CCU 432 .

[0093] The light source device 434 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 410 with irradiation light when photographing an operation site or the like.

[0094] The input device 436 is an input interface for the endoscopic surgery system 400. A user can input various information and instructions to the endoscopic surgery system 400 via the input device 436.

[0095] The treatment tool control device 438 controls the driving of an energy treatment tool 450 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0096] The light source device 434 that supplies irradiation light to the endoscope 410 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 434. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 414 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0097] Furthermore, the light source device 434 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 414 in synchronization with the timing of the change in the light intensity to obtain images in a time-division manner and synthesizing the images, it is possible to generate an image with a high dynamic range that is free of so-called blackout and whiteout.

[0098] The light source device 434 may be configured to supply light in a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, the wavelength dependency of light absorption in body tissue is utilized. Specifically, a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast by irradiating light in a narrower band than the irradiation light (i.e., white light) in normal observation. Alternatively, the special light observation may be a fluorescent observation in which an image is obtained by fluorescence generated by irradiating excitation light. In the fluorescent observation, it is possible to irradiate excitation light to the body tissue and observe the fluorescence from the body tissue, or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 434 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0099] As described above, according to this embodiment, by configuring an endoscopic surgery system using the photoelectric conversion device of the fourth embodiment, it is possible to realize an endoscopic surgery system that can quickly acquire images.

[0100] [Eighth embodiment] A light detection system and a moving body according to an eighth embodiment of the present invention will be described with reference to Figs. 15 to 17. Fig. 15 is a schematic diagram showing a configuration example of a moving body according to this embodiment. Fig. 16 is a block diagram showing a schematic configuration of a light detection system according to this embodiment. Fig. 17 is a flow diagram showing the operation of the light detection system according to this embodiment. In this embodiment, an application example of a light detection system to which the photoelectric conversion device 100 of the fourth embodiment is applied, to an in-vehicle camera, is shown.

[0101] FIG. 15 is a schematic diagram showing a configuration example of a moving body (vehicle system) according to this embodiment. FIG. 15 shows the configuration of a vehicle 500 (automobile) as an example of a vehicle system incorporating a light detection system to which a photoelectric conversion device according to the fourth embodiment is applied. FIG. 15(a) is a schematic front view of the vehicle 500, FIG. 15(b) is a schematic plan view of the vehicle 500, and FIG. 15(c) is a schematic rear view of the vehicle 500. The vehicle 500 is provided with a pair of photoelectric conversion devices 502 on the front side. Here, the photoelectric conversion devices 502 are the photoelectric conversion devices 100 described in the fourth embodiment. The vehicle 500 also includes an integrated circuit 503, an alarm device 512, and a main control unit 513.

[0102] FIG. 16 is a block diagram showing a configuration example of a light detection system 501 mounted on a vehicle 500. The light detection system 501 includes a photoelectric conversion device 502, an image preprocessing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric conversion device 502 is the photoelectric conversion device 100 described in the fourth embodiment. The optical system 514 forms an optical image of a subject on the photoelectric conversion device 502. The photoelectric conversion device 502 converts the optical image of the subject formed by the optical system 514 into an electric signal. The image preprocessing unit 515 performs a predetermined signal processing on the signal output from the photoelectric conversion device 502. The function of the image preprocessing unit 515 may be incorporated in the photoelectric conversion device 502. The light detection system 501 is provided with at least two sets of the optical system 514, the photoelectric conversion device 502, and the image preprocessing unit 515, and the output from each set of the image preprocessing unit 515 is input to the integrated circuit 503.

[0103] The integrated circuit 503 is an integrated circuit for use in an imaging system, and includes an image processing unit 504, an optical distance measuring unit 506, a parallax calculation unit 507, an object recognition unit 508, and an abnormality detection unit 509. The image processing unit 504 processes an image signal output from an image pre-processing unit 515. For example, the image processing unit 504 performs image processing such as development processing and defect correction on the output signal of the image pre-processing unit 515. The image processing unit 504 includes a memory 505 that temporarily stores the image signal. For example, the positions of known defective pixels in the photoelectric conversion device 502 can be stored in the memory 505.

[0104] The optical distance measuring unit 506 performs focusing and distance measurement of a subject. The parallax calculation unit 507 calculates distance measurement information (distance information) from a plurality of image data (parallax images) acquired by a plurality of photoelectric conversion devices 502. Each of the photoelectric conversion devices 502 may have a configuration capable of acquiring various information such as distance information. The object recognition unit 508 recognizes subjects such as cars, roads, signs, and people. When the abnormality detection unit 509 detects an abnormality in the photoelectric conversion device 502, it notifies the main control unit 513 of the abnormality.

[0105] The integrated circuit 503 may be realized by dedicated hardware, a software module, or a combination of these. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or a combination of these.

[0106] The main control unit 513 supervises and controls the operations of the light detection system 501, the vehicle sensor 510, the control unit 520, etc. The vehicle 500 does not necessarily have to include the main control unit 513. In this case, the photoelectric conversion device 502, the vehicle sensor 510, and the control unit 520 transmit and receive control signals via a communication network. For example, the CAN standard may be applied to the transmission and reception of these control signals.

[0107] The integrated circuit 503 has a function of receiving a control signal from the main control unit 513 or transmitting a control signal or a set value to the photoelectric conversion device 502 by its own control unit.

[0108] The optical detection system 501 is connected to a vehicle sensor 510, and can detect the vehicle's driving state, such as vehicle speed, yaw rate, and steering angle, as well as the state of the environment outside the vehicle and other vehicles and obstacles. The vehicle sensor 510 is also a distance information acquisition means for acquiring distance information to an object. The optical detection system 501 is also connected to a driving assistance control unit 511 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the optical detection system 501 and the vehicle sensor 510. This allows for avoidance control when a collision is estimated, and activation of a safety device in the event of a collision.

[0109] The light detection system 501 is also connected to an alarm device 512 that issues an alarm to the driver based on the result of the determination by the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 513 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 512 warns the user by sounding an alarm, displaying alarm information on a display screen such as a car navigation system or a meter panel, vibrating a seat belt or steering wheel, etc.

[0110] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are photographed by the light detection system 501. Fig. 15(b) shows an example of the arrangement of the light detection system 501 when the light detection system 501 photographs the area in front of the vehicle.

[0111] As described above, the photoelectric conversion device 502 is disposed in front of the vehicle 500. Specifically, if the center line of the vehicle 500 with respect to its forward / backward direction or outer shape (for example, vehicle width) is regarded as an axis of symmetry, and the two photoelectric conversion devices 502 are disposed in line symmetry with respect to the axis of symmetry, this is preferable for obtaining distance information between the vehicle 500 and an object to be photographed and for determining the possibility of a collision. In addition, the photoelectric conversion device 502 is preferably disposed so as not to obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 500 from the driver's seat. The warning device 512 is preferably disposed so as to be easily within the driver's field of vision.

[0112] Next, a fault detection operation of the photoelectric conversion device 502 in the light detection system 501 will be described with reference to Fig. 17. The fault detection operation of the photoelectric conversion device 502 can be performed according to steps S110 to S180 shown in Fig. 17.

[0113] Step S110 is a step for performing startup settings of the photoelectric conversion device 502. That is, settings for the operation of the photoelectric conversion device 502 are transmitted from outside the photodetection system 501 (e.g., the main control unit 513) or from inside the photodetection system 501, and the image capturing operation and fault detection operation of the photoelectric conversion device 502 are started.

[0114] Next, in step S120, pixel signals are obtained from the valid pixels. In addition, in step S130, output values ​​are obtained from failure detection pixels provided for failure detection. The failure detection pixels have photoelectric conversion elements, just like the valid pixels. A predetermined voltage is written to the photoelectric conversion elements. The failure detection pixels output signals corresponding to the voltage written to the photoelectric conversion elements. Note that steps S120 and S130 may be reversed.

[0115] Next, in step S140, a judgment is made as to whether the output expected value of the fault detection pixel corresponds to the output value from the actual fault detection pixel. If the result of the judgment in step S140 indicates that the output expected value and the actual output value correspond to each other, the process proceeds to step S150, where it is judged that the imaging operation is performed normally, and the process proceeds to step S160. In step S160, the pixel signal of the scanning row is sent to the memory 505 and temporarily stored. Thereafter, the process returns to step S120, and the fault detection operation is continued. On the other hand, if the result of the judgment in step S140 indicates that the output expected value and the actual output value do not correspond to each other, the process proceeds to step S170. In step S170, it is judged that there is an abnormality in the imaging operation, and an alarm is notified to the main control unit 513 or the alarm device 512. The alarm device 512 displays the fact that an abnormality has been detected on the display unit. Thereafter, in step S180, the photoelectric conversion device 502 is stopped, and the operation of the light detection system 501 is terminated.

[0116] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S170 may be notified to the outside of the vehicle via a wireless network.

[0117] In addition, in this embodiment, the control to prevent collision with other vehicles has been described, but the control can also be applied to automatic driving control to follow other vehicles, automatic driving control not to go out of the lane, etc. Furthermore, the light detection system 501 is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the light detection system 501 is not limited to moving bodies, but can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0118] [Ninth embodiment] A light detection system according to a ninth embodiment of the present invention will be described with reference to Fig. 18. Fig. 18 is a schematic diagram showing a configuration example of the light detection system according to this embodiment. In this embodiment, an application example to glasses (smart glasses) will be described as a light detection system to which the photoelectric conversion device 100 of the first embodiment is applied.

[0119] 18(a) shows glasses 600 (smart glasses) according to one application example. The glasses 600 include a lens 601, a photoelectric conversion device 602, and a control device 603.

[0120] The photoelectric conversion device 602 is the photoelectric conversion device 100 described in the first embodiment, and is provided on the lens 601. There may be one or more photoelectric conversion devices 602. When a plurality of photoelectric conversion devices 602 are used, a combination of a plurality of types of photoelectric conversion devices 602 may be used. The arrangement position of the photoelectric conversion device 602 is not limited to that shown in FIG. 18(a). A display device (not shown) including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 601.

[0121] The control device 603 functions as a power source that supplies power to the photoelectric conversion device 602 and the display device. The control device 603 also has a function of controlling the operations of the photoelectric conversion device 602 and the display device. The lens 601 is provided with an optical system for collecting light on the photoelectric conversion device 602.

[0122] 18(b) shows glasses 610 (smart glasses) according to another application example. The glasses 610 include lenses 611 and a control device 612. The control device 612 may be equipped with a photoelectric conversion device (not shown) corresponding to the photoelectric conversion device 602 and a display device.

[0123] The lens 611 is provided with a photoelectric conversion device in the control device 612 and an optical system for projecting light from the display device, and an image is projected. The control device 612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and also has a function for controlling the operations of the photoelectric conversion device and the display device.

[0124] The control device 612 may further include a line-of-sight detection unit that detects the line of sight of the wearer. In this case, an infrared light emitting unit may be provided in the control device 612, and infrared light emitted from the infrared light emitting unit may be used to detect the line of sight. Specifically, the infrared light emitting unit emits infrared light toward the eyeball of the user gazing at the display image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By providing a reduction means for reducing the light from the infrared light emitting unit to the display unit in a planar view, it is possible to reduce degradation of image quality.

[0125] The user's line of sight with respect to the displayed image can be detected from a captured image of the eyeball obtained by capturing infrared light. Any known method can be applied to gaze detection using a captured image of the eyeball. As an example, a gaze detection method based on a Purkinje image formed by reflection of irradiated light on the cornea can be used. More specifically, a gaze detection process based on a pupil-corneal reflex method is performed. Using the pupil-corneal reflex method, a gaze vector representing the direction (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0126] The display device of this embodiment may be configured to include a photoelectric conversion device having a light receiving element, and to control a display image based on the user's line of sight information from the photoelectric conversion device. Specifically, the display device determines a first field of view area to which the user gazes and a second field of view area other than the first field of view area based on the line of sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device. When determined by an external control device, they are communicated to the display device via communication. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than the resolution of the first field of view area.

[0127] The display area may also be configured to have a first display area and a second display area different from the first display area, and to determine an area having a high priority from the first display area and the second display area based on line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device. When determined by an external control device, the determination is communicated to the display device via communication. The resolution of the area having a high priority may be controlled to be higher than the resolution of areas other than the area having a high priority. In other words, the resolution of an area having a relatively low priority may be lowered.

[0128] AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of the line of sight and the distance to an object at the end of the line of sight from the image of the eyeball, using as teacher data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0129] When display control is performed based on visual recognition detection, the present invention is preferably applicable to smart glasses further including a photoelectric conversion device for capturing an image of the outside world. The smart glasses can display captured outside information in real time.

[0130] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0131] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0132] In the first to third embodiments, for the sake of simplicity, the signals held by each of the signal holding circuits 12 constituting the signal holding area 10 are 1-bit signals, but they do not necessarily have to be 1-bit signals and may be multi-bit signals. For example, the pulse signals output from the signal holding circuits 12 may be counted and the count value may be held in the memory 26, and the multi-bit signal held in the memory 26 may be transferred to the sequential circuit 28.

[0133] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0134] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0135] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) A plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the pixel circuits, Each of the plurality of pixel circuits A signal generating circuit having a photoelectric conversion unit; a memory for storing a signal output from the signal generating circuit; a sequential circuit having a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node; The plurality of pixel circuits include a first pixel circuit and a second pixel circuit arranged in the same row or the same column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit. A photoelectric conversion device comprising: (Configuration 2) The plurality of pixel circuits include a group of the pixel circuits arranged in the same row or the same column, and the sequential circuits of the pixel circuits constituting the group are connected in series so as to connect the output node and the third input node of the sequential circuits of the adjacent pixel circuits. 2. The photoelectric conversion device according to configuration 1. (Configuration 3) The control circuit is configured to supply a common control signal to the pixel circuits of each column of two or more rows each including the group of pixel circuits or to the pixel circuits of each row of two or more columns each including the group of pixel circuits. 3. The photoelectric conversion device according to configuration 2. (Configuration 4) the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of a plurality of buffer circuits connected in series; The number of the buffer circuits through which the control signal supplied to the sequential circuit of the first pixel circuit passes is greater than the number of the buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes. 4. The photoelectric conversion device according to any one of configurations 1 to 3. (Configuration 5) Each of the plurality of buffer circuits is constituted by a non-inverting buffer circuit. 5. The photoelectric conversion device according to configuration 4. (Configuration 6) Each of the plurality of buffer circuits is constituted by an inverting buffer circuit, The sequential circuit of the first pixel circuit is configured to operate in synchronization with a rising edge of the control signal, and the sequential circuit of the second pixel circuit is configured to operate in synchronization with a falling edge of the control signal. 5. The photoelectric conversion device according to configuration 4. (Configuration 7) The control circuit further includes a logic circuit disposed between an output of each of the plurality of buffer circuits and the second input node of the sequential circuit of the pixel circuit. 7. The photoelectric conversion device according to any one of configurations 1 to 6. (Configuration 8) The plurality of pixel circuits include a first group and a second group of pixel circuits arranged in the same row or the same column, and the sequential circuits of the pixel circuits constituting each of the first group and the second group are connected in series so as to connect the output node and the third input node of the sequential circuits of the adjacent pixel circuits. 2. The photoelectric conversion device according to configuration 1. (Configuration 9) The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged alternately every predetermined number. 9. The photoelectric conversion device according to configuration 8. (Configuration 10) The control circuit is configured to output, in parallel, each signal of the pixel circuits constituting the first group and each signal of the pixel circuits constituting the second group. 10. The photoelectric conversion device according to configuration 8 or 9. (Configuration 11) the first group includes the first pixel circuit and the second pixel circuit, and the second group includes a third pixel circuit; the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of a plurality of buffer circuits connected in series; the number of the buffer circuits through which the control signals supplied to the sequential circuit of the first pixel circuit pass is greater than the number of the buffer circuits through which the control signals supplied to the sequential circuit of the second pixel circuit pass; The number of the buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes is equal to the number of the buffer circuits through which the control signal supplied to the sequential circuit of the third pixel circuit passes. 10. The photoelectric conversion device according to configuration 8 or 9. (Configuration 12) The pixel circuit, in which the output node of the sequential circuit is connected to the third input node of another pixel circuit, is configured to output a held signal via the other pixel circuit. 12. The photoelectric conversion device according to any one of configurations 1 to 11. (Configuration 13) The sequential circuit is configured to hold the signal input from the memory to the first input node, and to output the held signal from the output node. 13. The photoelectric conversion device according to any one of configurations 1 to 12. (Configuration 14) The sequential circuit is configured to hold a signal input from the third input node in response to the control signal input to the second input node, and to output the held signal from the output node. 14. The photoelectric conversion device according to any one of configurations 1 to 13. (Configuration 15) A plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the pixel circuits, Each of the plurality of pixel circuits includes a signal generation circuit having a photoelectric conversion unit, a memory that holds a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory; the plurality of pixel circuits include a first group and a second group each including two or more of the pixel circuits arranged in the same row; the sequential circuits of the pixel circuits constituting each of the first group and the second group are connected in series along a row direction, and are configured to sequentially transfer the signal held by each of the sequential circuits from one side to the other side along the row direction in response to a control signal from the control circuit; The control circuit is configured to supply a common control signal to the pixel circuits of the first group and the pixel circuits of the second group, thereby performing a transfer operation of the signal in the pixel circuits of the first group and a transfer operation of the signal in the pixel circuits of the second group in parallel. A photoelectric conversion device comprising: (Configuration 16) The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in different rows. 16. The photoelectric conversion device according to configuration 15. (Configuration 17) The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in the same row. 16. The photoelectric conversion device according to configuration 15. (Configuration 18) a plurality of signal hold circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the plurality of signal hold circuits, each of the plurality of signal holding circuits includes a memory that holds a predetermined signal, and a sequential circuit to which the signal is transferred from the memory; the plurality of signal holding circuits include a first group and a second group each including two or more of the signal holding circuits arranged in the same row; the sequential circuits of the signal hold circuits constituting each of the first group and the second group are connected in series along a row direction, and are configured to sequentially transfer the signals held by each of the sequential circuits from one side to the other side along the row direction in response to a control signal from the control circuit; The control circuit is configured to supply a common control signal to the signal hold circuits of the first group and the signal hold circuits of the second group, thereby performing a signal transfer operation in the signal hold circuits of the first group and a signal transfer operation in the signal hold circuits of the second group in parallel. A signal output device comprising: (Method 1) A method for driving a photoelectric conversion device including a first group and a second group each including two or more pixel circuits arranged in the same row, the first group and the second group being connected in series along a row direction, the first group including a signal generation circuit having a photoelectric conversion unit, a memory for holding a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory, the first group including a signal generation circuit having a photoelectric conversion unit, the second group including a signal generation circuit having a photoelectric conversion unit, a memory for holding a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory, the second group including two or more pixel circuits arranged in the same row, the sequential circuits of the pixel circuits constituting the first group and the second group being connected in series along a row direction, storing, in the memory, a signal based on charges generated in the photoelectric conversion unit in response to incidence of light, in each of the plurality of pixel circuits; transferring the signal held in the memory to the sequential circuit in each of the plurality of pixel circuits; sequentially transferring the signals held by the sequential circuits of the pixel circuits constituting each of the first group and the second group from one side to the other side along the row direction, In the step of sequentially transferring, a common control signal is supplied to the pixel circuits of the first group and the pixel circuits of the second group, and a transfer operation of the signal in the pixel circuits of the first group and a transfer operation of the signal in the pixel circuits of the second group are performed in parallel. A method for driving a photoelectric conversion device comprising the steps of: (Method 2) The step of sequentially transferring overlaps in time with the step of storing in a next frame. 2. A method for driving a photoelectric conversion device according to claim 1. (Configuration 19) A photoelectric conversion device according to any one of structures 1 to 17; a signal processing device that processes a signal output from the photoelectric conversion device; 1. An optical detection system comprising: (Configuration 20) The signal processing device generates a distance image representing distance information to an object based on the signal. 20. The optical detection system of claim 19. (Configuration 21) A mobile object, A photoelectric conversion device according to any one of structures 1 to 17; a distance information acquisition unit that acquires distance information to an object from a parallax image based on a signal output from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising: [Explanation of symbols]

[0136] 10...Signal holding area 12...Signal holding circuit 24...Signal generation unit 26…Memory 28…Sequential circuit 40...Clock buffer circuit 42...Buffer circuit 50...Signal output device 100...Photoelectric conversion device

Claims

1. A plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the pixel circuits, Each of the plurality of pixel circuits A signal generating circuit having a photoelectric conversion unit; a memory for storing a signal output from the signal generating circuit; a sequential circuit having a first input node to which a signal from the memory is input, a second input node to which a control signal from the control circuit is input, a third input node, and an output node; The plurality of pixel circuits include a first pixel circuit and a second pixel circuit arranged in the same row or the same column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit. A photoelectric conversion device comprising:

2. The plurality of pixel circuits include a group of the pixel circuits arranged in the same row or the same column, and the sequential circuits of the pixel circuits constituting the group are connected in series so as to connect the output node and the third input node of the sequential circuits of the adjacent pixel circuits.

2. The photoelectric conversion device according to claim 1.

3. The control circuit is configured to supply a common control signal to the pixel circuits of each column of two or more rows each including the group of pixel circuits or to the pixel circuits of each row of two or more columns each including the group of pixel circuits.

3. The photoelectric conversion device according to claim 2.

4. the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of a plurality of buffer circuits connected in series; The number of the buffer circuits through which the control signal supplied to the sequential circuit of the first pixel circuit passes is greater than the number of the buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. Each of the plurality of buffer circuits is constituted by a non-inverting buffer circuit.

5. The photoelectric conversion device according to claim 4.

6. Each of the plurality of buffer circuits is constituted by an inverting buffer circuit, The sequential circuit of the first pixel circuit is configured to operate in synchronization with a rising edge of the control signal, and the sequential circuit of the second pixel circuit is configured to operate in synchronization with a falling edge of the control signal.

5. The photoelectric conversion device according to claim 4.

7. The control circuit further includes a logic circuit disposed between an output of each of the plurality of buffer circuits and the second input node of the sequential circuit of the pixel circuit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

8. The plurality of pixel circuits include a first group and a second group of the pixel circuits arranged in the same row or the same column, and the sequential circuits of the pixel circuits constituting each of the first group and the second group are connected in series so as to connect the output node and the third input node of the sequential circuits of the adjacent pixel circuits.

2. The photoelectric conversion device according to claim 1.

9. The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged alternately every predetermined number.

9. The photoelectric conversion device according to claim 8.

10. The control circuit is configured to output, in parallel, each signal of the pixel circuits constituting the first group and each signal of the pixel circuits constituting the second group.

10. The photoelectric conversion device according to claim 8 or 9.

11. the first group includes the first pixel circuit and the second pixel circuit, and the second group includes a third pixel circuit; the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or the same column via at least a part of a plurality of buffer circuits connected in series; the number of the buffer circuits through which the control signals supplied to the sequential circuit of the first pixel circuit pass is greater than the number of the buffer circuits through which the control signals supplied to the sequential circuit of the second pixel circuit pass; The number of the buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes is equal to the number of the buffer circuits through which the control signal supplied to the sequential circuit of the third pixel circuit passes.

10. The photoelectric conversion device according to claim 8 or 9.

12. The pixel circuit, in which the output node of the sequential circuit is connected to the third input node of another pixel circuit, is configured to output a held signal via the other pixel circuit.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

13. The sequential circuit is configured to hold the signal input from the memory to the first input node, and to output the held signal from the output node.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

14. The sequential circuit is configured to hold a signal input from the third input node in response to the control signal input to the second input node, and to output the held signal from the output node.

4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

15. A plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the pixel circuits, Each of the plurality of pixel circuits includes a signal generation circuit having a photoelectric conversion unit, a memory that holds a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory; the plurality of pixel circuits include a first group and a second group each including two or more of the pixel circuits arranged in the same row; the sequential circuits of the pixel circuits constituting each of the first group and the second group are connected in series along a row direction, and are configured to sequentially transfer the signal held by each of the sequential circuits from one side to the other side along the row direction in response to a control signal from the control circuit; The control circuit is configured to supply a common control signal to the pixel circuits of the first group and the pixel circuits of the second group, thereby performing a transfer operation of the signal in the pixel circuits of the first group and a transfer operation of the signal in the pixel circuits of the second group in parallel. A photoelectric conversion device comprising:

16. The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in different rows.

16. The photoelectric conversion device according to claim 15.

17. The pixel circuits constituting the first group and the pixel circuits constituting the second group are arranged in the same row.

16. The photoelectric conversion device according to claim 15.

18. a plurality of signal hold circuits arranged in a plurality of rows and a plurality of columns; A control circuit that drives the plurality of signal hold circuits, each of the plurality of signal holding circuits includes a memory that holds a predetermined signal, and a sequential circuit to which the signal is transferred from the memory; the plurality of signal holding circuits include a first group and a second group each including two or more of the signal holding circuits arranged in the same row; the sequential circuits of the signal hold circuits constituting each of the first group and the second group are connected in series along a row direction, and are configured to sequentially transfer the signals held by each of the sequential circuits from one side to the other side along the row direction in response to a control signal from the control circuit; The control circuit is configured to supply a common control signal to the signal hold circuits of the first group and the signal hold circuits of the second group, thereby performing a signal transfer operation in the signal hold circuits of the first group and a signal transfer operation in the signal hold circuits of the second group in parallel. A signal output device comprising:

19. A method for driving a photoelectric conversion device including a first group and a second group each including two or more pixel circuits arranged in the same row, the first group and the second group being connected in series along a row direction, the first group including a signal generation circuit having a photoelectric conversion unit, a memory for holding a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory, the first group including a signal generation circuit having a photoelectric conversion unit, the second group including a signal generation circuit having a photoelectric conversion unit, a memory for holding a signal generated by the signal generation circuit, and a sequential circuit to which the signal is transferred from the memory, the second group including two or more pixel circuits arranged in the same row ... storing, in the memory, a signal based on charges generated in the photoelectric conversion unit in response to incidence of light, in each of the plurality of pixel circuits; transferring the signal held in the memory to the sequential circuit in each of the plurality of pixel circuits; sequentially transferring the signals held by the sequential circuits of the pixel circuits constituting each of the first group and the second group from one side to the other side along the row direction, In the step of sequentially transferring, a common control signal is supplied to the pixel circuits of the first group and the pixel circuits of the second group, and a transfer operation of the signal in the pixel circuits of the first group and a transfer operation of the signal in the pixel circuits of the second group are performed in parallel. A method for driving a photoelectric conversion device comprising the steps of:

20. The step of sequentially transferring overlaps in time with the step of storing in a next frame.

20. The method for driving a photoelectric conversion device according to claim 19.

21. The photoelectric conversion device according to claim 1 , a signal processing device that processes a signal output from the photoelectric conversion device; 1. An optical detection system comprising:

22. The signal processing device generates a distance image representing distance information to an object based on the signal.

22. The optical detection system of claim 21.

23. A mobile object, The photoelectric conversion device according to claim 1 , a distance information acquisition unit that acquires distance information to an object from a parallax image based on a signal output from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

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