Serial communication reception circuit

Abstract

To provide a reception circuit of a serial communication, capable of improving a noise tolerance.SOLUTION: A reception circuit of a serial communication comprises: a data conversion part that converts serial data into parallel data; a start mark detection part that outputs a clock phase when a start pattern is detected from the parallel data as a sta_point signal; a timing generation part that specifies a data comparison period; and a selection part that compares the parallel data with a plurality of comparison patterns that are previously regulated in the data comparison period, selects one comparison pattern on the basis of the comparison result and outputs the clock phase when a representative value of a comparison result of the selected comparison pattern as a fix_point signal. The timing generation part contains a fixing region determination part for specifying the data comparison period on the basis of the comparison result of the fix_point signal and the sta_point signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This specification discloses a serial communication receiving circuit. [Background technology]

[0002] A low-pass filter or the like is inserted into the communication signal to remove noise components from the communication signal and ensure the reliability of the communication signal. Summary of the Invention [Problem to be solved by the invention]

[0003] Serial communication is often used to send and receive data between units installed inside machines such as machine tools. However, the communication path is often wired near noise sources such as power lines inside the machine, and noise inside the machine can be an obstacle to communication. [Means for solving the problem]

[0004] The receiving circuit for serial communication disclosed in this specification includes a clock phase generation unit that outputs a clock phase of a sampling clock, a data conversion unit that converts serial data into parallel data, a start mark detection unit that detects a predetermined communication start pattern from the parallel data and outputs the clock phase when the start pattern is detected as a sta_point signal, a timing generation unit that specifies a data comparison period after the sta_point signal is output, a comparison unit that compares the parallel data with each of a plurality of predefined comparison patterns during the data comparison period and outputs a representative value of the comparison result for each of the plurality of comparison patterns, a selection unit that selects a comparison pattern corresponding to the parallel data based on a comparison between representative values ​​of the plurality of comparison results, and outputs the clock phase when the representative value of the comparison result of the selected comparison pattern is obtained as a fix_point signal, and a data storage unit that stores a data value corresponding to the comparison pattern selected by the selection unit, and the timing generation unit includes a defined area determination unit that specifies the data comparison period based on a comparison result between the fix_point signal and the sta_point signal. Effect of the Invention

[0005] According to the serial communication receiving circuit disclosed in this specification, noise immunity can be improved. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a block diagram showing a configuration of a serial communication receiving circuit. [Diagram 2] 2 is a detailed block diagram of a comparison unit shown in FIG. 1. [Diagram 3] 2 is a detailed block diagram of a timing generating unit shown in FIG. 1. [Figure 4] 4 is a timing chart showing an example of operation in the present embodiment. [Diagram 5] 5 is a timing chart showing a detailed operation of point 1 shown in FIG. 4. [Figure 6] 5 is a timing chart showing a detailed operation of point 2 shown in FIG. 4. [Figure 7] 11 is a timing chart showing an output timing adjustment operation of fix_area in the embodiment. [Figure 8] 13 is a correspondence table of encoding patterns for hexadecimal data used in this embodiment. [Figure 9] 3 is a correspondence table of comparison patterns for each data used in the determination unit shown in FIG. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The configuration of a serial communications receiving circuit is shown in Fig. 1. The serial communications receiving circuit shown in Fig. 1 may be configured, for example, as a circuit board combining a plurality of semiconductor elements. In another embodiment, the serial communications receiving circuit shown in Fig. 1 may be configured as a computer including a processor and a memory in which a program for executing the processing described below is installed.

[0008] In this embodiment, sampling is performed four times for one bit.

[0009] The clock phase generating unit 1 is a 2-bit clock counter, and outputs the count value of this clock counter as a phase signal ckc. The phase signal ckc represents the clock phase of the sampling clock. The data converting unit 2 is a 48-bit shift register, and converts the serial input signal rx into 48-bit parallel data rd as needed. The parallel data rd is input to the start mark detecting unit 3. As shown in FIG. 5, the start mark detecting unit 3 compares the parallel data rd with a comparison value. At this time, the comparison value is the "start" data shown in FIG. 9. In the timing chart of FIG. 5, the values ​​of the "start" data (i.e., the comparison value) and the parallel data rd are expressed in binary. The start mark detecting unit 3 performs an XOR operation on the parallel data rd and the "start" data, and detects the number of bits where the XOR output is 1 as the number of differences.

[0010] If the comparison shows that the number of differences between the parallel data rd and the comparison value is six or less, the start mark detection unit 3 turns the sta signal ON, and then turns the sta signal OFF when it confirms that the decrease in the number of differences has stopped. Figure 5 shows, as an example, the comparison results between the parallel data rd and the comparison value in sections P1 to P3. In section P1, the five points surrounded by dashed lines are the differences. In this case, since the number of differences is six or less, the sta signal turns ON immediately after section P1.

[0011] When the number of differences is decreased from the previous number of differences during the period when the sta signal is ON, the start mark detection unit 3 outputs the value of ckc at that time as sta_point. The sta signal is turned OFF when the comparison result starts to increase. As a result, the value of ckc at the time when the comparison result shows the minimum value is set as sta_point. In the example of FIG. 5, the number of differences in the section P2 is "2", which is smaller than the number of differences "5" in the section P1, so "1", which is the ckc in the section P2, is set as sta_point. Then, in the section P3, the number of differences increases to "5", so the sta signal is turned OFF. The sta_point is a signal indicating the clock phase when the start pattern ("start" data) is detected. A detailed configuration diagram of the timing generation unit 4 in FIG. 1 is shown in FIG. 3. The timing generation unit 4 specifies a data comparison period in which the parallel data rd is compared with each of a plurality of comparison patterns described later. The timing generation unit 4 outputs the fix_area signal during the data comparison period.

[0012] The counter 42 of the timing generating unit 4 is a counter that circulates at a value that is an integer multiple of the number of samples, and in this example, it is a counter that repeats counting from 0 to 23. Therefore, when the count value c of the counter 42 reaches "23", it is reset to "0". Also, exceptionally, when the sta signal is ON, the count value c of the counter 42 is reset to 0. The count value c of the counter 42 is input to the determined area determining unit 41 and the data control unit 44. The determined area determining unit 41 turns on the fix_area signal during a period in which the count value is within a predetermined range. In principle, the reference value of the "predetermined range" is the count value c between 21 and 23. However, this "predetermined range", that is, the range of the count value in which the fix_area signal is output, is changed depending on the input status of the fix_point signal. For example, when the sta_point signal is 1 and the fix_point signal is 0, the determined area determining unit 41 turns on the fix_area signal during a period in which the count value c is 20 to 22. The details of this operation will be described later.

[0013] The fix_area signal is input to the operation state determination unit 43. The operation state determination unit 43 turns on the busy signal at the timing when the fix_area signal is turned on for the first time after the sta signal is turned on. For example, in the example of FIG. 4, after the sta signal is turned on at point PT1, the fix_area signal is turned on for the first time at point PT2. The operation state determination unit 43 turns on the busy signal at this point PT2. The busy signal is input to the data control unit 44. The data control unit 44 enables the output signals wa, wd, and wp while the busy signal is on.

[0014] The fix_area signal is also input to the comparison unit 5. FIG. 2 is a diagram showing a detailed configuration of the comparison unit 5. The comparison unit 5 compares the parallel data rd with each of a plurality of comparison patterns. The comparison unit 5 outputs a representative value of the comparison result for each of the plurality of comparison patterns. As shown in FIG. 2, the comparison unit 5 has 17 judgment units 50-516. Each of the judgment units 50-516 corresponds to one of the 17 types of comparison patterns other than start shown in FIG. 9, and compares the corresponding comparison pattern with the parallel data rd. Since the configurations of the plurality of judgment units 50-516 are almost the same, the following description will be given taking the judgment unit 50 as an example.

[0015] The judgment unit 50 has a collation unit 501, a holding unit 502, and a selection unit 503. The collation unit 501 receives a corresponding comparison pattern as an enc input. The collation unit 501 compares the input comparison pattern with the parallel data rd, and outputs the number of differences as the number of differences ccon. The collation unit 501 performs an XOR operation between the parallel data rd and the corresponding comparison pattern, and detects the number of bits whose XOR output is 1 as the number of differences. The value of the number of differences ccon is updated as needed while the fix_area signal is ON. Furthermore, the holding unit 502 outputs values ​​obtained by adding the value of ckc corresponding to the number of differences ccon as upper bits as con0, con1, and con2. That is, the value obtained by adding the value of ckc when the count value c=21 as the upper bits of the number of differences ccon when c=21 to the number of differences ccon is set as con0. Also, the value of ckc when count value c=22 is added to the number of differences ccon as the most significant bits of the number of differences ccon when c=22, and this value is defined as con1. Also, the value of ckc when count value c=23 is added to the number of differences ccon as the most significant bits of the number of differences ccon when c=23, and this value is defined as con2. con0, con1, and con2 are input to the selection unit 503. The selection unit 503 outputs the input with the smallest number of differences among the values ​​indicated by con0, con1, and con2 as con. For example, the number of differences when count value c=i is ccon i , ckc i Then, con0=[ckc 21 +ccon 21 ], con1=[ckc 22 +ccon 22 ], con2=[ckc 23 +ccon 23 ]. For example, ccon 21 , ccon 22 , ccon 23 Of these, ccon 21 is smallest, the selection unit 503 selects con0=[ckc 21 +ccon 21 ] is output as con. con_0 and con_1, which will be described later, are the con output here. This con is the representative value of the comparison result.

[0016] This comparison is performed simultaneously by 17 pairs of judgment units, and is output as con_0 to con_f and stop_mark, respectively. con_0 to con_f and stop_mark are input to the selection unit 6 shown in FIG. 1. The selection unit 6 selects a comparison pattern corresponding to the parallel data rd based on a comparison between representative values ​​of the comparison results (i.e., con_0 to con_f and stop_mark). The selection unit 6 also outputs the value of ckc when the representative value of the comparison results of the selected comparison pattern is obtained as a fix_point signal.

[0017] Specifically, the selection unit 6 compares the number of differences indicated by con_0 to con_f and stop_mark to identify the signal with the fewest number of differences. Then, the selection unit 6 outputs the value of the data number (see FIG. 9) of the comparison pattern corresponding to that signal as data_no. The selection unit 6 also outputs the portion indicating the value of ckc (i.e., the clock phase) as fix_point.

[0018] For example, in Fig. 4, the con with the dashed circle indicates the con with the fewest number of differences. For example, if con_1 has the fewest number of differences, "01" is output as data_no. Also, the value of ckc added as the upper bits to con_1 is output as fix_point.

[0019] The data_no and fix_point are input to the timing generation unit 4. As shown in FIG. 3, the fix_point is input to a defined region determination unit 41, and the data_no is input to a motion state determination unit 43 and a data control unit .

[0020] The fixed area determination unit 41 compares sta_point with fix_point, and adjusts the output timing of fix_area according to the difference. Specifically, when there is no difference between sta_point and fix_point, fix_area is output when the count value c is between 21 and 23. On the other hand, when there is a difference between sta_point and fix_point, the output timing of fix_area is shifted by the difference value. For example, when sta_point is "1" and fix_point is "0", fix_area is output when the count value c is between 20 and 22. As a result, when a difference occurs between sta_point, which is the point where the start mark is fixed, and fix_point, which is the point where the subsequent received data is fixed, the output timing of fix_area is adjusted to be one clock before and after fix_point.

[0021] In the example of Figure 7, sta_point is "1". Meanwhile, fix_point is "1" in section P4, but becomes "0" in section P5. In this case, the output timing of fix_area is adjusted so that the timing when ckc becomes 0 in section P5 is at the center of fix_area. This corrects the data phase shift caused by the error in the communication frequencies of the transmitter and receiver.

[0022] Furthermore, when data_no is 16 indicating stop_mark, the operation state determination unit 43 turns off the busy signal at the timing when the fix_area signal turns on.

[0023] Moreover, the data control unit 44 outputs data_no shown in Fig. 9 to wd. The wa, wd, and wp output by the data control unit 44 are connected to the data storage unit 7, which stores the received data as needed.

[0024] FIG. 6 is a diagram showing detailed operations at point 2 in FIG. 4. As shown in FIG. 6, when noise is not superimposed, the number of differences indicated by con_0 output from the judgment unit 50 is "0". Since this is smaller than the number of differences indicated by the other con_n, the value of the input data is judged to be "0". Furthermore, when noise is superimposed, the number of differences indicated by con_0 output from the judgment unit 50 is "2". Even in this case, as shown in FIG. 4, the number of differences indicated by con_0 is smaller than the number of differences compared to the judgment results of the other judgment units, so the input data is judged to be "0" in the same way as when noise is not superimposed.

[0025] The data received in this manner is stored in the data storage unit 7 after noise has been removed. [Explanation of symbols]

[0026] 1: Clock phase generator 2: Data conversion section 3: Start mark detector 4: Timing generation section 41: Determined area determination section 42: Counter 43: Operation state determination unit 44: Data control section 5: Comparison section 50: Judgment part 0 501: Matching section 502: Holding part 503: Selection section 51: Judgment part 1 52: Judgment part 2 516: Judgment part 16 6: Selection section 7: Data Storage Department

Claims

1. In a serial communication receiving circuit, a clock phase generating unit that outputs a clock phase of a sampling clock; a data conversion unit that converts serial data into parallel data; a start mark detection unit that detects a preset communication start pattern from the parallel data and outputs a clock phase when the start pattern is detected as a sta_point signal; a timing generation unit that specifies a data comparison period after the sta_point signal is output; a comparison unit that compares the parallel data with each of a plurality of predefined comparison patterns during the data comparison period and outputs a representative value of a comparison result for each of the plurality of comparison patterns; a selection unit that selects a comparison pattern corresponding to the parallel data based on a comparison between representative values ​​of a plurality of the comparison results, and outputs the clock phase when the representative value of the comparison result of the selected comparison pattern is obtained as a fix_point signal; a data storage unit that stores a data value corresponding to the comparison pattern selected by the selection unit; Equipped with The timing generation unit includes a determined region determination unit that specifies the data comparison period based on a comparison result between the fix_point signal and the sta_point signal.

2. A serial communication receiving circuit comprising:

2. 2. The serial communication receiving circuit according to claim 1, the data conversion unit includes a shift register having a predetermined number of bits, and converts the serial data into parallel data having the predetermined number of bits; The start mark detection unit The parallel data and the start pattern are XORed, The number of bits whose output of the XOR is 1 is detected as the number of differences. determining a timing at which the number of differences does not decrease after the number of differences becomes equal to or less than a predetermined value as a timing at which the start pattern is detected; 2. A serial communication receiving circuit comprising:

3. 2. The serial communication receiving circuit according to claim 1, the data conversion unit includes a shift register having a predetermined number of bits, and converts the serial data into parallel data having the predetermined number of bits; the comparison unit includes a plurality of determination units corresponding to the plurality of comparison patterns, Each of the plurality of determination units is XORing the parallel data with the corresponding comparison pattern; The number of bits whose output of the XOR is 1 is detected as the number of differences. outputting data representing a combination of the clock phase and the number of differences when the number of differences is minimum during the data comparison period as a representative value of the comparison result; 2. A serial communication receiving circuit comprising:

4. 4. The serial communication receiving circuit according to claim 1, the clock phase generating unit is a clock counter that cycles at a sampling number per one bit of the serial data, and outputs a count value of the clock counter as a clock phase; the timing generation unit includes a counter that cycles by a value that is an integer multiple of the number of samples and is reset at a timing when it is determined that the start pattern has been detected; The determined region determination unit is A period during which the count value of the counter is within a predetermined range is specified as the data comparison period; The predetermined range is shifted from a predetermined range by a difference value between the fix_point signal and the sta_point signal.

2. A serial communication receiving circuit comprising:

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