Ion current droop compensation

Abstract

To provide a pulse generator that compensates for voltage drops across a wafer in a plasma chamber due to an ion current.SOLUTION: A pulse generator includes a DC power supply, a plurality of switches, a transformer T1, and a pulsing output. The pulse generator may be coupled to the plasma chamber. The pulsing output outputs a high voltage pulse. The high voltage pulse has a peak-to-peak voltage greater than 1 kV, and a voltage portion between successive high voltage bipolar pulses has a negative slope, which approximately cancels the voltage drop on the wafer in the plasma chamber due to ion current. The resulting voltage at the wafer may be approximately flat between successive pulses.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 087,150, filed October 2, 2020, entitled "ION CURRENT DROOP COMPENSATION," which is incorporated by reference in its entirety.

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 049,907, filed July 9, 2020, entitled "ION CURRENT DROOP COMPENSATION," which is incorporated by reference in its entirety, and is a continuation-in-part of U.S. Nonprovisional Patent Application No. 17 / 372,398, filed July 9, 2021, entitled "ION CURRENT DROOP COMPENSATION," which is incorporated by reference in its entirety. [Background technology]

[0003] Some plasma systems include at least two power supplies: one power supply that generates a radio frequency waveform that can be used to generate a plasma in the plasma chamber, and another power supply that generates high voltage pulses that accelerate charged plasma particles in the plasma chamber toward the wafer. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made to solve the problems in the conventional techniques described above. [Means for solving the problem]

[0005] A nanosecond pulser is disclosed that may include one or more solid-state switches, a transformer coupled to the one or more solid-state switches, a snubber circuit coupled to the one or more switches, and an output coupled to the transformer to generate high voltage pulses having a pulse repetition frequency, a pulse width, a peak voltage greater than 1 kV, and a voltage portion between successive high voltage pulses having a negative slope.

[0006] The voltage portion may, for example, include more than 50% of the period between successive pulses. The voltage portion may be the voltage between an inflection point during the fall of one pulse and an inflection point during the rise of the following pulse. The voltage portion may be the voltage between the end of one pulse and the start of the following pulse.

[0007] The high voltage pulse may be, for example, a non-sinusoidal pulse.

[0008] The magnitude of the negative gradient may be, for example, greater than 100,000 kV / s.

[0009] The snubber circuit may include a snubber resistor having a resistance of about 7.5 mΩ to 1.25 Ω and a snubber capacitor having a capacitance of about 2 μF to 35 μF.

[0010] The pulse width may have a duration of about 100 to 500 ns.

[0011] A semiconductor processing system is also disclosed, which includes a plasma chamber and a nanosecond pulser coupled to the plasma chamber to introduce a high voltage pulse into the plasma chamber. A voltage fraction between two successive high voltage pulses measured at at least one point in the plasma chamber can vary, for example, by less than 1 V / ns. The negative slope can, for example, be approximately the same in magnitude as the ratio of an ion current generated in the plasma chamber to a chuck capacitance of the plasma chamber, and the sign of the negative slope can, for example, be approximately the same in magnitude as the ratio of an ion current generated in the plasma chamber to a chuck capacitance of the plasma chamber, and the sign of the negative slope can, for example, be approximately the same in magnitude as the ratio of an ion current generated in the plasma chamber to a chuck capacitance of the plasma chamber, and the sign of the negative slope can, for example, be approximately offset by a voltage drop on a wafer in the plasma chamber due to an ion current.

[0012] The plasma chamber may include a chuck having a capacitance of, for example, less than about 20 nF.

[0013] A pulse generator is disclosed that may include a DC power source, a transformer including a transformer core, a primary winding wound on at least a portion of the transformer core, the primary winding having a first lead and a second lead, and a secondary winding wound on at least a portion of the transformer core. The pulse generator may also include a droop compensation circuit electrically coupled to a first lead of the primary winding, a first switch electrically connected to the droop compensation circuit and the DC power source, a second switch electrically connected to a second lead of the primary winding and the DC power source, the first switch and the second switch being opened and closed at different time intervals, and a pulsing output electrically coupled to the secondary winding of the transformer, the pulsing output outputting high voltage bipolar pulses, the high voltage bipolar pulses having a peak-to-peak voltage greater than 1 kV and a voltage portion between successive high voltage bipolar pulses having a negative slope. The pulsing output may, for example, output a bipolar pulse with a pulse frequency greater than 1 kHz.

[0014] The voltage portion may, for example, include more than 50% of the period between successive high-voltage bipolar pulses. The voltage portion may be the voltage between an inflection point during the fall of one high-voltage bipolar pulse and an inflection point during the rise of the following high-voltage bipolar pulse. The voltage portion may be the voltage between the end of one high-voltage bipolar pulse and the start of the following high-voltage bipolar pulse.

[0015] The magnitude of the negative gradient may be, for example, greater than 100,000 kV / s.

[0016] The droop compensation circuit may include, for example, a droop diode biased to allow current to flow through the first switch and the transformer. The droop compensation circuit may include, for example, a first inductor and a first resistor arranged in series and electrically coupled across the droop diode. The first inductor may be, for example, a variable inductor. The first inductor may have, for example, an inductance less than about 100 μH. The first resistor may have, for example, a resistance less than about 5 Ω. The droop circuit may include, for example, a second inductor electrically coupled to the droop diode and a first lead of the primary winding. The second inductor may have, for example, an inductance less than about 50 nH.

[0017] The pulse generator may include, for example, a third resistor and a third inductor arranged in series between the second switch and the second lead of the primary winding. The third inductor may have an inductance less than about 35 nH. The third resistor may have a resistance less than about 1 Ω.

[0018] A semiconductor processing system is also disclosed that includes a plasma chamber and a pulser generator coupled to the plasma chamber to introduce high voltage pulses into the plasma chamber.

[0019] The voltage fraction between two successive high voltage pulses measured at at least one point in the plasma chamber can vary by less than 1 V / ns. The negative slope can, for example, be approximately the same in magnitude as the ratio of the ion current generated in the plasma chamber to the chuck capacitance of the plasma chamber, and the opposite in sign to that ratio. The magnitude of the negative slope can, for example, approximately cancel the voltage drop on the wafer in the plasma chamber due to the ion current.

[0020] A pulse generator is disclosed. The pulse generator may include a DC power source and a transformer including a transformer core, a primary winding wound on at least a portion of the transformer core, the primary winding having a first lead and a second lead, and a secondary winding wound on at least a portion of the transformer core. The pulse generator may also include a plurality of switches arranged in a full bridge configuration. A first portion of the plurality of switches may be electrically connected to a droop compensation circuit and a DC power source. A second portion of the plurality of switches may be electrically connected to a second lead of the primary winding and to the DC power source. The first portion of the plurality of switches and the second portion of the plurality of switches may be opened and closed at different time intervals. The pulse generator may also include a droop compensation circuit electrically arranged between the first portion of the plurality of switches and / or the second portion of the plurality of switches and the transformer. The pulse generator may also include a pulsing output electrically coupled to the secondary winding of the transformer, the pulsing output outputting a first high-voltage bipolar pulse having a peak-to-peak voltage greater than about 1 kV, a pulse frequency greater than 1 kHz, and a voltage portion between successive high-voltage bipolar pulses having a negative slope. The pulsing output may, for example, output a bipolar pulse having a pulse frequency greater than 1 kHz.

[0021] The voltage portion may, for example, include more than 50% of the period between successive high-voltage bipolar pulses. The voltage portion may be the voltage between an inflection point during the fall of one high-voltage bipolar pulse and an inflection point during the rise of the following high-voltage bipolar pulse. The voltage portion may be the voltage between the end of one high-voltage bipolar pulse and the start of the following high-voltage bipolar pulse.

[0022] The magnitude of the negative gradient may be, for example, greater than 100,000 kV / s.

[0023] The droop compensation circuit may include, for example, a droop diode biased to allow current to flow through the first switch and the transformer. The droop compensation circuit may include, for example, a first inductor and a first resistor arranged in series and electrically coupled across the droop diode. The first inductor may, for example, have an inductance less than about 100 μH. The first resistor may, for example, have a resistance less than about 5 Ω. The droop circuit may include, for example, a second inductor electrically coupled to the droop diode and a first lead of the primary winding. The second inductor may, for example, have an inductance less than about 50 nH.

[0024] The pulse generator may include, for example, a third resistor and a third inductor arranged in series between the second switch and the second lead of the primary winding. The third inductor may have an inductance less than about 35 nH. The third resistor may have a resistance less than about 1 Ω.

[0025] A semiconductor processing system is also disclosed that includes a plasma chamber and a pulser generator coupled to the plasma chamber to introduce high voltage pulses into the plasma chamber.

[0026] The voltage fraction between two successive high voltage pulses measured at at least one point in the plasma chamber can vary by less than 1 V / ns. The negative slope can, for example, be approximately the same in magnitude as the ratio of the ion current generated in the plasma chamber to the chuck capacitance of the plasma chamber, and the opposite in sign to that ratio. The magnitude of the negative slope can, for example, approximately cancel the voltage drop on the wafer in the plasma chamber due to the ion current.

[0027] A pulsing power supply is disclosed that delivers multiple high voltage pulses with no substantial voltage droop measured at a single point in the load (e.g., on a wafer in a plasma chamber) between two successive pulses.

[0028] A pulsing power supply is disclosed that delivers a time-dependent voltage waveform having multiple high voltage pulses, the high voltage pulses having a voltage greater than 1 kV and a voltage measured at a point within a load (e.g., on a wafer in a plasma chamber) that is approximately constant between pulses.

[0029] A pulsing power supply is disclosed that provides a timed voltage waveform having a plurality of high voltage pulses, the high voltage pulses having a voltage greater than 1 kV and a voltage measured at the output of the pulsing power supply having a negative slope between the pulses.

[0030] A pulsing power supply is disclosed that provides a timed voltage waveform having multiple high voltage pulses greater than 1 kV in voltage and generates a negative slope voltage during a portion of the output pulse that substantially offsets the voltage drop across a wafer in a plasma chamber due to ion current.

[0031] A pulse generator is disclosed. The pulse generator includes a DC power supply, a plurality of switches, a transformer, and a pulsing output. The pulse generator may be coupled to a plasma chamber. The pulsing output outputs a high voltage pulse, the high voltage pulse having a peak-to-peak voltage greater than 1 kV, and a voltage portion between successive high voltage bipolar pulses having a negative slope, which approximately cancels the voltage drop on the wafer in the plasma chamber due to ion current. The resulting voltage at the wafer may be approximately flat between successive pulses. [Brief description of the drawings]

[0032] [Figure 1] FIG. 2 is a circuit diagram of a power supply system driving a load stage according to some embodiments. [Diagram 2] 1 is a circuit diagram of a power supply system having a resistive output stage driving a load stage according to some embodiments. [Diagram 3] 1 is an example of two waveforms generated by a power system without an RF power source according to some embodiments. [Figure 4] 1 is an example of two waveforms generated by a power system with an RF power source according to some embodiments. [Diagram 5] 1 is an example of two waveforms generated by a power system without an RF power source according to some embodiments. [Figure 6] 1 is an example of two waveforms generated by a power system with an RF power source according to some embodiments. [Figure 7] 1 is an example of two waveforms generated by a power system without an RF power source according to some embodiments. [Figure 8] 1 is an example of two waveforms generated by a power system with an RF power source according to some embodiments. [Figure 9] 1 is an example of a side-by-side waveform generated by a nanosecond pulser without a system with and without droop compensation according to some embodiments. [Figure 10A] ~ [Figure 10B]1 is a histogram of the voltage in a plasma chamber without and with droop correction according to some embodiments. [Figure 11] 1 is a circuit diagram of a power supply system having a droop compensation circuit driving a load circuit according to some embodiments. [Figure 12] FIG. 1 is a circuit diagram of a power supply system having a droop compensation circuit driving a load stage according to some embodiments. [Figure 13] FIG. 2 is a circuit diagram of a pulser and plasma system according to some embodiments. [Figure 14] FIG. 1 is a circuit diagram of a pulser and plasma system in combination with an energy recovery circuit. [Figure 15] This is the waveform from a pulser without droop compensation, as shown in Figure 13 or Figure 14. [Figure 16] The waveform from a pulser with droop compensation shown in FIG. 13 or FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Some embodiments include a power supply system (eg, a nanosecond pulser, a pulse generator, etc.) that generates high voltage pulses, where the voltage between two successive high voltage pulses has a negative slope.

[0034] The power supply system may be coupled to the plasma chamber. The negative gradient may, for example, be approximately the same in magnitude as, and opposite in sign to, the ratio of an ion current generated in the plasma chamber to a chuck capacitance of the plasma chamber. The magnitude of the negative gradient may, for example, approximately cancel a voltage drop on a wafer in the plasma chamber due to the ion current.

[0035] The power supply system and / or plasma chamber, for example, may not be coupled with a conventional matching network.

[0036] The power system may include a snubber circuit that includes a circuit element that counteracts the ion current in the plasma that occurs after the pulse is completed.

[0037] 1 is a circuit diagram of a pulser and plasma system 100 for driving pulses to a plasma chamber 106 according to some embodiments. These pulses may include, for example, square wave pulses. A pulser stage 101 may generate a number of pulses that may be injected into the plasma chamber 106. An RF generator 108 may generate an RF signal (e.g., a sinusoidal signal). A filter circuit 103 may prevent the RF signal and the pulses from interfering with each other. The values ​​of the components of the snubber circuit, for example, snubber resistor R3, snubber inductor L3, and / or snubber capacitor C5, may be selected to reduce droop of the pulses injected into the plasma chamber 106.

[0038] For example, snubber resistor R3 may have a resistance less than about 100 mΩ, such as 75, 50, 25, 10, 5, 1, 0.5 mΩ, etc. Alternatively or additionally, snubber resistor R3 may have a resistance between about 7.5 mΩ and 1.25 Ω. For example, snubber capacitor may have a capacitance less than about 50 μF, such as between about 2 and 35 μF.

[0039] In some embodiments, plasma chamber 106 may represent an ideal or effective circuit of a semiconductor processing chamber (e.g., a plasma deposition system, a semiconductor fabrication system, a plasma sputtering system, etc.). Capacitor 12 may represent, for example, the capacitance of an electrostatic chuck on which a semiconductor process wafer may be placed. The chuck may include, for example, a dielectric material (e.g., aluminum oxide or other ceramic material and a conductor encased within the dielectric material). The chuck may have, for example, a capacitance less than about 20, 10, 5 nF, etc. For example, capacitor 11 may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0040] Capacitor 13 may represent, for example, a sheath capacitance between the plasma and the wafer. Resistor 56 may represent, for example, a sheath resistance between the plasma and the wafer. Inductor 40 may represent, for example, a sheath inductance between the plasma and the wafer. Current source I2 may represent, for example, an ion current through the sheath. For example, capacitor 11 or capacitor 13 may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0041] Capacitor 18 may represent, for example, the plasma sheath capacitance to the chamber wall. Resistor 57 may represent, for example, the resistance between the plasma and the chamber wall. Current source I1 may represent, for example, the ion current through the sheath and / or between the chamber wall and the plasma. For example, capacitor 11 or capacitor 18 may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0042] In some embodiments, the plasma voltage may be the voltage at circuit point 123 measured from ground, the wafer voltage is the voltage at circuit point 122 measured from ground and may represent the voltage at the wafer surface, the chuck voltage is the voltage at circuit point 121 measured from ground, the electrode voltage (or nanosecond pulser output voltage) is the voltage at circuit point 124 (e.g., on the electrode) measured from ground, and the input voltage is the voltage at circuit point 125 measured from ground.

[0043] In some embodiments, the pulser and plasma system 100 may include a DC bias circuit 104 as shown in FIG.

[0044] In some embodiments, bias capacitor 20 can isolate (or separate) the DC bias voltage from other circuit elements. Bias capacitor 20 can, for example, allow a potential shift from one portion of the circuit to another. In some embodiments, this potential shift may be done to keep the electrostatic force holding the wafer in place on the chuck below a voltage threshold to prevent damage to the wafer. Resistor R2 can isolate the DC bias power supply from the high voltage pulse output from pulser stage 101.

[0045] Bias capacitor 20 may, for example, have a capacitance less than about 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, 1 μF, etc. Resistor R2 may, for example, have a high resistance, for example, a resistance of about 1 kΩ, 10 kΩ, 100 kΩ, 1 MΩ, 10 MΩ, 100 MΩ, etc.

[0046] Circuit 105 may represent a transmission line from the circuit to plasma chamber 106. Resistor 63 may represent, for example, the resistance of a lead or transmission line leading from the output of a high voltage power supply system to an electrode (e.g., plasma chamber 106). Capacitor 11 may represent, for example, stray capacitance in a lead or transmission line.

[0047] In some embodiments, the pulser stage 101 may generate pulses having a high pulse voltage (e.g., greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high frequency (e.g., greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., a rise time shorter than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), a fast fall time (e.g., a fall time shorter than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), and / or a short pulse width (e.g., a pulse width shorter than about 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0048] For example, pulser stage 101 may include any or all portions of any of the apparatus described in U.S. patent application Ser. No. 14 / 542,487, entitled "High Voltage Nanosecond Pulser," which is incorporated herein by reference for all purposes, or any or all portions of any of the apparatus described in U.S. patent application Ser. No. 14 / 635,991, entitled "Galvanically Isolated Output Variable Pulse Generator Disclosure," which is incorporated herein by reference for all purposes, or any or all portions of any of the apparatus described in U.S. patent application Ser. No. 14 / 798,154, entitled "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency," which is incorporated herein by reference for all purposes.

[0049] In some embodiments, the pulser stage 101 may include one or more nanosecond pulsers coupled together in any of a variety of ways.

[0050] In some embodiments, the pulser stage 101 may include a DC power supply that outputs a constant DC voltage, and the DC power supply is switched by a switch S6 to provide switched power to a transformer T1. The DC power supply may include a voltage source V5 and an energy storage capacitor C7. If the transformer T1 has a turns ratio of 1:10, the transformer can generate 10 kV to the load.

[0051] In some embodiments, if the load capacitance (e.g., capacitor 13 and capacitor 18) is small compared to the capacitance of the energy storage capacitor C7, then there may (or may not) be voltage doubling at the input of the transformer or at the secondary side of the transformer. For example, if the energy storage capacitor C7 provides 500V, then 1kV may be measured at the input of the transformer T1.

[0052] Switch S6 may include, for example, one or more solid-state switches, such as an IGBT, a MOSFET, a SiC MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. Switch S6 may be switched based on signals Sig6+ and Sig6− from the controller.

[0053] In some embodiments, switch S6 may switch fast enough so that the switched voltage is not the full voltage (e.g., the voltage of energy storage capacitor C7 and / or voltage source V1.) In some embodiments, a gate resistor associated with switch S6 may be set with a short turn-on pulse.

[0054] In some embodiments, the pulser stage 101 may include a freewheeling diode D2. In some embodiments, the freewheeling diode D2 may be used in combination with an inductive load so that energy stored in the inductive load may be able to dissipate after the switch S6 opens by allowing current to continue to flow through the inductor in the same direction, and so that the energy is dissipated in a resistive element of the circuit. If the freewheeling diode D2 is not included, for example, a reverse voltage may develop across the switch S6.

[0055] In some embodiments, the pulser stage 101 may include a stray inductance L1 and / or a stray resistance R1. The stray inductance L1 may be, for example, less than about 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc. The stray resistance R1 may be, for example, less than about 1 Ω, 100 mΩ, 10 mΩ, etc.

[0056] In some embodiments, the energy recovery circuit 110 may be electrically coupled to the secondary side of the transformer and / or the energy storage capacitor C7. The energy recovery circuit 110 may include, for example, a crowbar diode 130 across the secondary side of the transformer T1. The energy recovery circuit 110 may include, for example, an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series) to allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7. The energy recovery diode 120 and the energy recovery inductor 115 may be electrically connected to the secondary side of the transformer T1 and the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 may include the crowbar diode 130 and / or an inductor 140 electrically coupled to the secondary side of the transformer T1. The inductor 140 may represent and / or include a stray inductance of the transformer T1.

[0057] In some embodiments, the energy recovery inductor 115 may include any type of inductor, such as a ferrite core inductor or an air core inductor. In some embodiments, the energy recovery inductor 115 may have any type of geometry, such as a solenoidal winding, a toroidal winding, etc. In some embodiments, the energy recovery inductor 115 may have an inductance greater than about 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 115 may have an inductance between about 1 μH and about 100 mH.

[0058] In some embodiments, the order of the energy recovery inductor 115 and the energy recovery diode 120 can be reversed. For example, the energy recovery inductor 115 can be followed by the energy recovery diode 120, or the energy recovery inductor 115 can be followed by the energy recovery diode 120.

[0059] In some embodiments, when the nanosecond pulser is turned on, current can charge the plasma chamber 106 (e.g., charging capacitor 13, capacitor 12, or capacitor 18). For example, when the voltage on the secondary side of transformer T1 becomes higher than the charging voltage of energy storage capacitor C7, some current can flow through energy recovery inductor 115. When the nanosecond pulser is turned off, current can flow from a capacitor in the chamber (e.g., capacitor 11) through energy recovery inductor 115 to charge energy storage capacitor C7 until the voltage across energy recovery inductor 115 is zero. The crowbar diode 130 can prevent the voltage at the output of the NSP (e.g., at circuit point 124) from going below ground and / or can provide a path for current to continue to flow.

[0060] The energy recovery diode 120 may, for example, prevent charge from flowing from the energy storage capacitor C7 to a capacitor within the plasma chamber 106.

[0061] The value of the energy recovery inductor 115 may be selected to control the fall time of the current. In some embodiments, the energy recovery inductor 115 may have an inductance value between 1 and 600 μH. In some embodiments, the energy recovery inductor 115 may have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 115 may have an inductance less than about 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

[0062] For example, if the energy storage capacitor C7 provides 500V, 1 kV will be measured at the input of the transformer T1 (e.g., by voltage doubling as described above). The 1 kV at the transformer T1 may be divided among the components of the energy recovery circuit 110 when the switch S6 is open. If their values ​​are appropriately selected (e.g., if the inductance of the snubber inductor L3 is smaller than the inductance of the energy recovery inductor 115), the voltage across the energy recovery diode 120 and the energy recovery inductor 115 may be greater than 500V. Current may then flow through the energy recovery diode 120 and / or charge the energy storage capacitor C7. Current may also flow through the diode D3 and the inductor L8. Once the energy storage capacitor C7 is charged, current may no longer flow through the diode D3 and the energy recovery inductor 115.

[0063] In some embodiments, the energy recovery circuit 110 may transfer energy (or charge) from the plasma chamber 106 on a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The stray resistance of the energy recovery circuit may be small so that the pulse across the plasma chamber 106 has a fast fall time tf. The stray resistance of the energy recovery circuit 110 may be, for example, less than about 1 Ω, 100 mΩ, 10 mΩ, etc. In some embodiments, the efficiency of energy transfer from the plasma chamber 106 may be high, for example, greater than about 60%, 70%, 80%, or 90%, etc.

[0064] Any number of the components shown in FIG. 1 may or may not be required, for example, diode 135 or crowbar diode 130 or inductor 140 may or may not be required.

[0065] In some embodiments, a diode may be placed between the DC power source V1 and where the energy recovery circuit 110 connects to the DC power source V1 and / or the energy storage capacitor C7. The diode may be positioned, for example, to allow current to flow from the DC power source V1 to the energy storage capacitor C7, but may not allow current to flow from the energy recovery circuit to the energy storage capacitor C7.

[0066] In some embodiments, the energy recovery circuit 110 may be eliminated. In some embodiments, a resistive output stage or bias compensation circuit may be included. Various other circuits or circuit elements may be included.

[0067] In some embodiments, the pulser and plasma system 100 may include a filter circuit 103. In this example, the filter circuit includes a filter capacitor 185 and / or a filter inductor 180. The filter capacitor 185 may, for example, filter low frequency signals from the pulser stage 101. These low frequency signals may, for example, have frequencies (e.g., most of the spectral content) of about 100 kHz and 10 MHz (e.g., about 10 MHz, etc.). The filter capacitor 185 may, for example, have a value between about 1 pF and 1 nF, for example, less than about 100 pF.

[0068] In some embodiments, the filter inductor 180 may filter high frequency signals, for example from the RF generator 108. These high frequency signals may have a frequency, for example, between about 1 MHz and 200 MHz, for example, between about 1 MHz and greater than 10 MHz. The filter inductor 180 may have a value, for example, between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance across it. In some embodiments, the coupling capacitance may be less than 1 nF.

[0069] In some embodiments, one or both of the filter capacitor 185 and the filter inductor 180 can isolate the pulses generated by the RF generator 108 from the pulses generated by the pulser stage 101 and / or the pulses generated by the pulser stage 101 from the pulses generated by the RF generator 108. For example, the filter capacitor 185 can isolate the pulses generated by the pulser stage 101 from the pulses generated by the RF generator 108. The filter inductor 180 can isolate the pulses generated by the RF generator 108 from the pulses generated by the pulser stage 101.

[0070] 2 is a circuit diagram of a power supply system 200 having a resistive output stage 220 driving a load stage, according to some embodiments. In this embodiment, the energy recovery circuit 110 is eliminated from the pulser and plasma system 100 and replaced with a resistive output stage 220.

[0071] Resistive output stage 220 may include any resistive output stage known in the art, for example, any of the resistive output stages described in U.S. patent application Ser. No. 16 / 178,538, entitled "HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT," which is incorporated herein in its entirety for all purposes.

[0072] For example, resistive output stage 220 may include an inductor L11, a resistor R10, a resistor R11, and a capacitor C11. In some embodiments, inductor L11 may have an inductance between about 5 μH and about 25 μH. In some embodiments, resistor R11 may have a resistance between about 50 Ω and about 250 Ω. In some embodiments, resistor R10 may comprise a stray resistance of resistive output stage 220.

[0073] In some embodiments, resistor R11 may include multiple resistors arranged in series and / or parallel. Capacitor C11 may represent a stray capacitance of resistor R11, including the capacitance of a series and / or parallel resistor arrangement. The capacitance of stray capacitance C11 may be, for example, less than 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. The capacitance of stray capacitance C11 may be, for example, less than the load capacitance, for example, less than the capacitance of capacitor 12, capacitor 13, and / or capacitor 18, etc.

[0074] In some embodiments, resistor R11 may discharge a load (e.g., plasma sheath capacitance). In some embodiments, resistive output stage 220 may be configured to deliver more than about 1 kilowatt of average power during each pulse period and / or less than or equal to 1 Joule of energy in each pulse period. In some embodiments, resistor R11 of resistive output stage 220 may have a resistance less than 200 Ω. In some embodiments, resistor R11 may include multiple resistors in series or parallel, whose combined capacitance (e.g., capacitor 111) is less than about 200 pF.

[0075] In some embodiments, resistive output stage 220 may include a collection of circuit elements that can be used to control the shape of a voltage waveform on a load. In some embodiments, resistive output stage 220 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, resistive output stage 220 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, resistive output stage 220 may be used to control, for example, the voltage rise time of a waveform and / or the voltage fall time of a waveform.

[0076] In some embodiments, the resistive output stage 220 may discharge capacitive loads (e.g., the wafer and / or plasma). For example, these capacitive loads may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0077] In some embodiments, the resistive output stage 220 may be used in circuits where the pulse voltage of the pulses is high (e.g., greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.) and / or the pulse frequency is high (e.g., greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.) and / or the pulse frequency is approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0078] In some embodiments, the resistive output stage 220 may be selected to handle high average power, high peak power, fast rise times, and / or fast fall times, for example, an average power rating of greater than about 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and / or a peak power rating of greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.

[0079] In some embodiments, resistive output stage 220 may include a series or parallel network of passive components. For example, resistive output stage 220 may include a series resistor, a capacitor, and an inductor. As another example, resistive output stage 220 may include a parallel combination of a capacitor and an inductor in series with a resistor. For example, L11 may be selected to be large enough to prevent significant energy from being injected into resistive output stage 220 when there is an output voltage from the rectifier. The values ​​of R10 and R11 may be selected to allow the appropriate capacitor in the load to discharge faster than the RF frequency in L / R time.

[0080] In some embodiments, the pulser stage 101 of either the pulser and plasma system 100 or the power supply system 200 may include a snubber circuit. In some embodiments, the snubber circuit may include a snubber capacitor C5. In some embodiments, the snubber circuit may include a snubber capacitor C5 and a snubber resistor R3. In some embodiments, the snubber circuit may include a snubber capacitor C5, a snubber inductor L3, and a snubber resistor R3.

[0081] In some embodiments, the snubber circuit may include a snubber resistor R3, and / or a snubber inductor L3 may be arranged in parallel with a snubber diode D4. The arrangement of the snubber inductor L3, the snubber resistor R3, and the snubber diode D4 may be arranged in series with a snubber capacitor C5. In some embodiments, the snubber resistor R3 and / or the snubber diode D4 may be placed between the collector of the switch S6 and the primary winding of the transformer T1. The snubber diode D4 may be used to buffer overvoltages that occur during switching. A large and / or high-speed snubber capacitor C5 may be coupled to the emitter or collector side of the switch S6. A freewheeling diode D2 may also be coupled to the emitter side of the switch S1. Various other components not shown may also be included. One or more switches and / or circuits may be arranged in parallel or in series.

[0082] In some embodiments, a positive current may be caused to flow out of the pulser stage 101 after the pulse ends to counter the ion current in the chamber. This can be accomplished, for example, by adjusting the inductance of the snubber inductor L3 (which may be absent, for example), the resistance of the snubber resistor R3, and / or the capacitance of the snubber capacitor C5, so that the snubber capacitor C5 can be discharged during the pulse and / or not fully charged before the next pulse. This can, for example, allow the current flowing in the same direction from the energy storage capacitor C7 and / or the DC power supply V1 to decay as the current flows during the pulse. This can result in a waveform shape generated on the wafer that does not include a droop between pulses in the plasma chamber.

[0083] Droop may manifest as a rising voltage between pulses generated by pulser stage 101. Droop may include a voltage rising by 0.2 V / ns (e.g., if the chuck capacitance is about 5 nF and the ion current is 1 Amp) or 1 V / ns (e.g., if the chuck capacitance is about 5 nF and the ion current is 5 Amp).

[0084] Alternatively, droop compensation may include a negative voltage gradient between rising pulses generated by the pulser stage 101, which may offset the droop voltage caused by the ion flux to the wafer in the vapor chamber. Droop compensation may, for example, have a voltage gradient between pulses of about 0.2 V / ns (e.g., when the chuck capacitance is about 5 nF and the ion current is 1 Amp) or about 1 V / ns (e.g., when the chuck capacitance is about 5 nF and the ion current is 5 Amp). As another example, droop compensation may include a negative voltage gradient between rising pulses of greater than about 100,000, 10,000, 1,000, or 100 kV / s.

[0085] An RF generator 108 may be electrically coupled to the plasma chamber 106. The RF generator 108 may, for example, introduce a high frequency RF signal into the plasma chamber, which may generate a plasma from components within the chamber.

[0086] The RF generator 108 may include any type of device that generates RF power to be applied to the cathode. The RF generator 108 may include, for example, a nanosecond pulser, a resonant system driven by a half-bridge circuit or a full-bridge circuit, an RF amplifier, a nonlinear transmission line, an RF plasma generator, etc. In some embodiments, the RF generator 108 may include an impedance matching network.

[0087] In some embodiments, the RF generator 108 may include one or more RF drivers capable of generating RF power signals having different RF frequencies (e.g., 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz, etc.). Typical RF frequencies may include, for example, frequencies between 200 kHz and 800 MHz. In some embodiments, the RF generator 108 may generate and sustain a plasma in the plasma chamber. The RF generator 108 may, for example, provide an RF signal to a cathode (and / or an antenna) to excite various gases and / or ions in the chamber to generate a plasma.

[0088] In some embodiments, the RF generator 108 may be coupled to or may include an impedance matching circuit that can match a non-standard output impedance of the RF generator 108 to the industry standard characteristic impedance of a 50 Ω coaxial cable or any cable.

[0089] In some embodiments, the RF generator 108 may generate bursts at an RF frequency that is higher than the pulse repetition frequency of the pulses generated by the pulser stage 101 .

[0090] In some embodiments, the pulser and plasma system 100 may include a filter capacitor 185 and / or a filter inductor 180. The filter capacitor 185 may, for example, filter low frequency signals from the pulser stage 101. These low frequency signals may, for example, have frequencies (e.g., most of the spectral content) between about 100 kHz and 10 MHz (e.g., about 10 MHz, etc.). The filter capacitor 185 may, for example, have a value between about 1 pF and 1 nF, for example, less than about 100 pF.

[0091] In some embodiments, the filter inductor 180 may filter high frequency signals, for example from the RF generator 108. These high frequency signals may have a frequency, for example, between about 1 MHz and 200 MHz, for example, between about 1 MHz and greater than 10 MHz. The filter inductor 180 may have a value, for example, between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance across it. In some embodiments, the coupling capacitance may be less than 1 nF.

[0092] In some embodiments, one or both of the filter capacitor 185 and the filter inductor 180 can isolate the pulses generated by the RF generator 108 from the pulses generated by the pulser stage 101 and / or the pulses generated by the pulser stage 101 from the pulses generated by the RF generator 108. For example, the filter capacitor 185 can isolate the pulses generated by the pulser stage 101 from the pulses generated by the RF generator 108. The filter inductor 180 can isolate the pulses generated by the RF generator 108 from the pulses generated by the pulser stage 101.

[0093] 3 is an example of two waveforms generated by a power system without an RF power source (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 305 is the chuck voltage (e.g., circuit node 121) and wafer waveform 310 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 75 mΩ, snubber capacitor C5 has a capacitance of 12 μF, the pulse width is 100 ns, and the inductance of filter inductor 180 may be, for example, about 100 nH. The DC voltage provided by DC power supply V1 is 500 V. As shown, wafer waveform 310 is approximately flat between pulses. For example, the slope of wafer waveform 810 between pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0094] 4 is an example of two waveforms generated by a power system with an RF power source (e.g., an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 405 is the chuck voltage (e.g., circuit node 121) and wafer waveform 410 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 75 mΩ, snubber capacitor C5 has a capacitance of 12 μF, a pulse width of 100 ns, and filter inductor 180 has an inductance of 100 nH. The DC voltage provided by DC power supply V1 is 500 V. As shown, wafer waveform 410 is approximately flat from pulse to pulse. Wafer waveform 410 may vary, for example, from successive pulses with a successive pulse-to-pulse change of less than 1 V / ns.

[0095] 5 is an example of two waveforms generated by a power system without an RF power source (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 505 is the chuck voltage (e.g., circuit node 121) and wafer waveform 510 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, a pulse width of 150 ns, and a filter inductor 180 has an inductance of 0 nH. The DC voltage provided by DC power supply V1 is 750 V. As shown, wafer waveform 510 is approximately flat between pulses. For example, the slope of wafer waveform 510 between pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0096] 6 is an example of two waveforms generated by a power system with an RF power source (e.g., an RF signal from RF generator 108) according to some embodiments. In this example, chuck waveform 605 is the chuck voltage (e.g., circuit node 121) and wafer waveform 610 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, a pulse width of 150 ns, and a filter inductor 180 has an inductance of 0 nH. The DC voltage provided by DC power supply V1 is 750 V. As shown, wafer waveform 610 is approximately flat between pulses. For example, the slope of wafer waveform 610 between pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0097] 7 is an example of two waveforms generated by a power system without an RF power source (e.g., without an RF signal from RF generator 108), according to some embodiments. In this example, chuck waveform 705 is the chuck voltage (e.g., circuit node 121) and wafer waveform 710 is the voltage measured on the wafer (e.g., circuit node 122). In this example, snubber resistor R3 has a resistance of 10 mΩ, snubber capacitor C5 has a capacitance of 35 μF, a pulse width of 250 ns, and a filter inductor 180 has an inductance of 0 nH. The DC voltage provided by DC power supply V1 is 700 V. As shown, wafer waveform 710 is approximately flat between pulses. For example, the slope of wafer waveform 710 between pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0098] 8 is an example of two waveforms generated by a power system with an RF power source (e.g., an RF signal from RF generator 108) in accordance with some embodiments. In this example, chuck waveform 805 is the chuck voltage (e.g., circuit point 121) and wafer waveform 810 is the voltage measured at a point on the wafer or in the plasma chamber (e.g., circuit point 122).

[0099] In this example, the resistance of snubber resistor R3 is 10 mΩ, the capacitance of snubber capacitor C5 is 35 μF, the pulse width is 250 ns, and the inductance of filter inductor 180 is 0 nH. The DC voltage provided by DC power source V1 is 800 V.

[0100] As shown in Figure 8, the chuck waveform (or output voltage from the pulser) has a negative slope between successive pulses. This negative slope can, for example, compensate for the voltage drop across the wafer in the plasma chamber due to ion current. This negative slope can, for example, be approximately the same in magnitude as the ratio of the ion current generated in the plasma chamber to the chuck capacitance of the plasma chamber, but opposite in sign to that ratio.

[0101] 8, the wafer waveform 810 is approximately flat between successive pulses. For example, the slope of the wafer waveform 810 between successive pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0102] 9 is an example of a side-by-side waveform with and without droop compensation generated by a nanosecond pulser without a system according to some embodiments. In this example, chuck waveform 905 is the chuck voltage without droop compensation and chuck waveform 915 is the chuck voltage with droop compensation. In this example, wafer waveform 910 is the wafer voltage without droop compensation and wafer waveform 920 is the voltage with droop compensation. In this example, without droop compensation, snubber resistor R3 has a resistance of 1.25 Ω and snubber capacitor C5 has a capacitance of 2 μF, and with droop compensation, snubber resistor R3 has a resistance lowered to 75 Ω and snubber capacitor C5 has a capacitance of 12 μF.

[0103] 9, the chuck waveform 915 (or the output voltage from the pulser) has a negative slope between successive pulses. This negative slope can, for example, compensate for the voltage drop across the wafer in the plasma chamber due to ion current. This negative slope can, for example, be approximately the same in magnitude as the ratio of the ion current generated in the plasma chamber to the chuck capacitance of the plasma chamber, but opposite in sign to that ratio.

[0104] 9, the wafer waveform 920 is approximately flat between successive pulses. For example, the slope of the wafer waveform 810 between successive pulses is less than 1 V / ns, 0.5 V / ns, 0.2 V / ns, 0.1 V / ns, etc.

[0105] 10A and 10B are histograms of wafer potential without and with droop compensation, respectively, according to some embodiments.

[0106] FIG. 11 is a circuit diagram of a power supply system 1100 with a droop compensation circuit 165 for driving a plasma chamber 106, according to some embodiments. In some embodiments, the droop compensation circuit 165 may include a crowbar diode 130 and a droop capacitor 170. The droop capacitor 170 may have a capacitance between about 1 nF and about 100 nF. In this example, the addition of the droop capacitor 170 allows the current flowing through the crowbar diode 130 and the energy recovery circuit 110 to cause a change in the voltage across the droop capacitor 170, which may counteract any droop. The droop capacitor 170 may limit the flow of current until the droop capacitor 170 charges up and eliminates the drop. A switch 171 may be used to drain charge from the droop capacitor 170 to ground during pulsing. The switch 171 may be switched at the same switching frequency and / or switching period as the switch 171 (e.g., using the same signal). For example, when switch 171 is closed, pulser stage 101 generates a pulse and switch 171 is closed to discharge droop capacitor 170 .

[0107] In some embodiments, the DC power supply 174 can allow for a DC offset or DC bias if needed. In some embodiments, the DC power supply 174 can also be charged when charge is drained from the droop capacitor 170.

[0108] In some embodiments, inductor 172 can be a current-limiting inductor. Inductor 172 can have, for example, an inductance between about 10 nH and about 500 nH. Diode 173 and / or diode 175 can be crowbar diodes. Diode 175 can, for example, allow current to flow when switch 171 is open and can allow voltage spikes to flow to ground.

[0109] In some embodiments, inductor 172, diode 173, and / or diode 175 may be replaced with resistors.

[0110] Switch 171 may include any type of switch capable of switching high voltages at high frequencies. In some embodiments, switch 171 includes a high voltage switch as described in U.S. Patent Application No. 62 / 717,637, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," and / or U.S. Patent Application No. 16 / 178,565, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," both of which are incorporated herein in their entirety for all purposes.

[0111] In some embodiments, the energy recovery circuit 110 may be eliminated or replaced with a primary sink circuit and / or a resistive output stage. In some embodiments, the energy recovery circuit 110 may be connected to ground after the energy recovery inductor 115.

[0112] In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset power supply voltage V5, which may, for example, positively or negatively bias the output voltage. In some embodiments, the offset power supply voltage V5 is adjustable to vary the potential between the wafer voltage and the chuck voltage. In some embodiments, the offset power supply voltage V5 may be approximately ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV, etc. The DC bias circuit 104 may or may not be included in the power supply system 1100.

[0113] The power supply system 1100 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high frequency signals from the RF generator 108. These high frequency signals may, for example, have a frequency between about 1 MHz and 200 MHz, for example, between about 1 MHz and greater than 10 MHz. The filter inductor 180 may, for example, have a value between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance across it. In some embodiments, the coupling capacitance may be less than 1 nF.

[0114] 12 is a circuit diagram of a pulser and plasma system 1200 having a droop compensation circuit 190 for driving a plasma chamber 106, according to some embodiments. The droop compensation circuit 190 may include a negative DC power supply 182, a switch 181, and a current limiting resistor 183 or a current limiting inductor 184. The current limiting resistor 183 may have, for example, a resistance of about 0.1 Ω to about 50 Ω or about 10 mΩ to about 500 Ω. The current limiting inductor 184 may have, for example, an inductance of about 1 nH to about 100 nH. When the switch 181 is closed, the negative DC power supply 182 can pull down the voltage to eliminate or limit the droop.

[0115] Switch 181 may include any type of switch capable of switching high voltages at high frequencies. In some embodiments, switch 181 includes a high voltage switch as described in U.S. Patent Application No. 62 / 717,637, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," and / or U.S. Patent Application No. 16 / 178,565, entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING," both of which are incorporated herein in their entirety for all purposes.

[0116] In some embodiments, the pulser and plasma system 1200 may include an energy recovery circuit (eg, the energy recovery circuit 110) rather than a resistive output stage 220.

[0117] The pulser and plasma system 1200 may include an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high frequency signals from the RF generator 108. These high frequency signals may, for example, have a frequency between about 1 MHz and 200 MHz, for example, between about 1 MHz and greater than 10 MHz. The filter inductor 180 may, for example, have a value between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance across it. In some embodiments, the coupling capacitance may be less than 1 nF.

[0118] 13 is a circuit diagram of a pulser and plasma system 1300 according to some embodiments. The pulser and plasma system 1300 may include, for example, a pulse driver 1305 (which is shown in a full-bridge configuration but may also be a half-bridge configuration), a droop compensation circuit 1310, a transformer 1345, and a DC power supply V1. The droop compensation circuit 1310 may, for example, mitigate or reduce voltage droop in the plasma chamber (e.g., on a wafer in the plasma chamber).

[0119] The pulse driver 1305 can generate, for example, a bipolar pulse. The bipolar pulse can include, for example, a rising pulse followed by a falling pulse. The peak-to-peak voltage between the rising and falling pulses can be greater than about 500V, 1 kV, 2 kV, 5 kV, 10 kV, 15 kV, 20 kV, etc.

[0120] In this example, the pulser and plasma system 1300 may include a pulse driver 1305. The pulse driver 1305 may be, for example, a half-bridge driver or a full-bridge driver. The pulse driver 1305 may include a DC power supply V1, which may be a DC power supply (e.g., a capacitive power supply, an AC-DC converter, etc.). In some embodiments, the pulse driver 1305 may include four bridge switches 661, 662, 663, 664. In some embodiments, the pulse driver 1305 may include multiple switches 661, 662, 663, and 664 in series or parallel. These switches 661, 662, 663, and 664 may include, for example, any type of solid-state switch, such as an IGBT, a MOSFET, a SiC MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. These switches 661, 662, 663, and 664 may be switched at high frequencies and / or generate high voltage pulses, which may include, for example, frequencies of about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0121] Each of the switches 661, 662, 663, and 664 may be coupled in parallel with a respective bridge diode and may include a stray inductance. In some embodiments, the stray inductances of the bridge switches may be equal. In some embodiments, the stray inductances of the bridge switches may be less than about 50 nH, 100 nH, 150 nH, 500 nH, 1,000 nH, etc. The combination of the switch (661, 662, 663, or 664) and the respective bridge diode may be coupled in series with a respective bridge inductor. For example, the bridge inductors associated with the switches 663 and 664 may be connected to ground. For example, the bridge inductor associated with the switch 661 may be electrically connected to the bridge switch 664 and the resistor 1315 and / or the inductor 1316 of the droop compensation circuit 1310. The bridge inductor associated with switch 662 may then be electrically connected to bridge switch 663 as well as diode 1313 of droop compensation circuit 1310, for example.

[0122] The switch in the pulse driver 1305 is set to the resonant frequency (f resonant ), the output voltage at the transformer 1345 is amplified. In some embodiments, the resonant frequency may be approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0123] In some embodiments, transformer 1345 (or transformer T1) may include a transformer such as that disclosed in U.S. patent application Ser. No. 15 / 365,094, entitled "High Voltage Transformer," which is incorporated herein by reference for all purposes.

[0124] For example, the duty cycle of the switches can be adjusted by changing the duty cycle of signal Sig1 that opens and closes bridge switch 661, by changing the duty cycle of signal Sig2 that opens and closes bridge switch 662, by changing the duty cycle of signal Sig3 that opens and closes bridge switch 663, and by changing the duty cycle of signal Sig4 that opens and closes bridge switch 664.

[0125] In some embodiments, each bridge switch 661, 662, 663, or 664 of the pulse driver 1305 may be switched independently of one another or in conjunction with one or more of the other switches. For example, the signal Sig1 may be the same signal as the signal Sig3. As another example, the signal Sig2 may be the same signal as the signal Sig4. As another example, each signal may be independent of one another and may control each bridge switch 661, 662, 663, or 664 independently or separately.

[0126] In some embodiments, the output of the droop compensation circuit 1310 may be coupled to a half-wave rectifier (which may include a blocking diode), which may be located on the secondary side of the transformer 1345 or on the primary side of the transformer 1345.

[0127] In some embodiments, the output of the droop compensation circuit 1310 may be coupled to a resistive output stage (e.g., resistive output stage 220 shown in FIG. 12). The resistive output stage may include any resistive output stage known in the art. For example, the resistive output stage may include any resistive output stage described in U.S. patent application Ser. No. 16 / 178,538, entitled "HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT," which is incorporated herein in its entirety for all purposes.

[0128] The pulser and plasma system 1300 does not include a conventional matching network, such as a 50 Ω matching network, an external matching network, or a stand-alone matching network. In fact, the embodiments described herein do not require a 50 Ω matching network to tune the switching power applied to the wafer chamber. Additionally, the embodiments described herein include a variable output impedance RF generator without a conventional matching network. This allows for the power drawn into the plasma chamber to be changed quickly. Typically, this tuning of the matching network can take at least 100-200 μs. In some embodiments, the change in power can occur within 1-2 RF cycles, e.g., within 2.5-5.0 μs at 400 kHz.

[0129] In some embodiments, the pulse driver 1305 may include switches arranged in a full-bridge topology as shown, or a half-bridge topology with two switches. Switches 661, 662, 663, 664 may switch a DC charge stored in an energy storage capacitor C7. A DC power supply V1, which may be a DC power supply (e.g., a capacitive power supply, an AC-DC converter, etc.), may charge the energy storage capacitor C7. The pulse driver 1305 may or may not drive the droop compensation circuit 1310 at a pulse frequency that is, for example, approximately equal to or not equal to the resonant frequency of the droop compensation circuit 1310.

[0130] In some embodiments, the pulse driver 1305 may be replaced with a half-bridge topology having two switches.

[0131] The droop compensation circuit 1310 may include a diode 1313, an inductor 1312, an inductor 1314, an inductor 1316, a resistor 1315, and / or a resistor 1311. The diode 1313 may be forward biased between the pulse driver 1305 and the transformer 1345. The resistor 1315 may be, for example, very small. For example, the resistor 1315 may have a resistance less than about 1 Ω, such as less than about 50, 25, 10, 5 mΩ, etc. As another example, the resistor 1315 may be as small as 0 Ω. The resistor 1311 may be, for example, very small. For example, the resistor 1311 may have a resistance less than about 5 Ω, such as less than about 10, 5, 2, 1, 0.75, 0.5, 0.25 Ω, etc. Inductor 1316 and / or inductor 1314 may, for example, have an inductance less than about 100 nH, such as less than about 75, 50, 25, 10, 5 nH, etc.

[0132] The inductor 1312 may, for example, have an inductance less than about 100 μH, such as less than about 100, 50, 25, 10, 5, 2.5, 1 μH, etc.

[0133] The pulser and plasma system 1300 may include, for example, an RF generator 108 and a filter inductor 180. The filter inductor 180 may, for example, filter high frequency signals from the RF generator 108. These high frequency signals may, for example, have a frequency between about 1 MHz and 200 MHz, for example, between about 1 MHz and greater than 10 MHz. The filter inductor 180 may, for example, have a value between about 10 nH and 10 μH, for example, greater than about 1 μH. In some embodiments, the filter inductor 180 may have a low coupling capacitance across it. In some embodiments, the coupling capacitance may be less than 1 nF.

[0134] DC power source V1 may include, for example, multiple DC power sources, where, for example, one DC power source may be coupled to one or two switches and another DC power source may be coupled to another one or two switches.

[0135] 14 is a circuit diagram of a pulser and plasma system 1400 in which the energy recovery circuit 110 is combined with the pulser and plasma system 1300. The energy recovery circuit 110 may include, for example, an energy recovery diode 120 and / or an energy recovery inductor 115. When the switches 661, 662, 663, and 664 are open, excess charge may flow, for example, from the secondary side of the transformer 1345 to charge the DC power supply V1. As another example, instead of combining the energy recovery circuit 110 with the pulser and plasma system 1300, the droop compensation circuit 190 may be combined with the pulser and plasma system 1300.

[0136] Unless otherwise specified, the term "substantially" means within 5-10% of the stated value, or within a manufacturing tolerance. Unless otherwise specified, the term "about" means within 5-10% of the stated value, or within a manufacturing tolerance.

[0137] FIG. 15A illustrates a bipolar waveform 1505 (e.g., resulting from a pulse driver 1305 without droop compensation (e.g., without all or a portion of the droop compensation circuit 1310). This waveform shows a voltage over time recorded at point 1330 in FIG. 13. FIG. 15B illustrates a bipolar waveform 1510 (e.g., from a pulse driver 1305 without droop compensation, measured at any point in the plasma chamber (e.g., point 1335 in FIG. 13 (e.g., in the plasma chamber, at the chuck, or on the wafer)). As shown in FIG. 15B, the waveform 1510 has a rising droop 1515 between positive pulse 1520 and positive pulse 1521. This droop 1515 may be repeated between any pulses of the waveform 1510. This droop 1515 may reduce the magnitude of the voltage over time between pulses 1520 and 1521 at a point in the plasma chamber to a nearly flat voltage over time.

[0138] As shown in waveform 1505, a bipolar pulse is a high voltage pulse having a rising portion 1540 and a falling portion 1541. The rising portion 1540 may be, for example, a triangular pulse, a square pulse, a Gaussian shaped pulse, a sinusoidal pulse, etc. The falling portion 1541 may be, for example, a triangular pulse, a square pulse, a Gaussian shaped pulse, a sinusoidal pulse, etc.

[0139] Figure 16A shows a bipolar waveform 1605 (e.g., originating from pulse driver 1305 with droop compensation). This waveform shows the voltage over time recorded at point 1330 in Figure 13. Figure 16B shows a bipolar waveform 1630 (e.g., from pulse driver 1305 with droop compensation, measured at some point in the plasma chamber (e.g., point 1335 in Figure 13 (e.g., at the chuck or on the wafer)).

[0140] 16A, droop compensation introduces a negative slope 1641 in the portion of the waveform generated by the pulse driver 1305 between two successive rising pulses (e.g., rising pulse 1610 and rising pulse 1611). The magnitude of the negative slope may be, for example, greater than about 10,000,000, 1,000,000, 500,000, 100,000, 50,000, 10,000 kV / s, etc. The period between successive positive pulses may be, for example, less than about 10,000, 1,000, 100, 10 ns, etc.

[0141] As shown in FIG. 16B, droop correction results in a substantially flat slope 1651 in the portion between successive pulses 1620, 1621 of the bipolar waveform measured in the plasma chamber. The magnitude of the substantially flat slope 1651 (e.g., as measured from an inflection point during the fall time of pulse 1620 to an inflection point during the rise time of pulse 1621) may be, for example, less than about 100, 10, 1 kV / s, etc. The magnitude of the substantially flat slope 1651 may, for example, generate a substantially constant negative potential on the wafer between the positive portions of pulse 1620 and pulse 1621. The portion of the period between successive bipolar pulses that includes a substantially flat slope may, for example, include more than 50%, more than 60%, more than 70%, or more than 80% of the period between successive bipolar pulses.

[0142] 9, the chuck waveform 915 (or the output voltage from the pulser) has a negative slope between successive pulses. This negative slope can, for example, compensate for the voltage drop across the wafer in the plasma chamber due to ion current. This negative slope can, for example, be approximately the same in magnitude as the ratio of the ion current generated in the plasma chamber to the chuck capacitance of the plasma chamber, but opposite in sign to that ratio.

[0143] The conjunction "or" is inclusive.

[0144] The terms "first," "second," "third," and the like are used to distinguish between elements and are not used to imply a particular order of those elements unless otherwise stated or an order is explicitly indicated or required.

[0145] Numerous specific details are described to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will recognize that the claimed subject matter may be practiced without these specific details. In other instances, methods, apparatus, or systems that would be well known to those skilled in the art have not been described in detail so as to avoid obscuring the claimed subject matter.

[0146] The disclosed method embodiments may be implemented in operation of such a computing device. The order of the blocks shown in the above examples may be changed, for example, the order of the blocks may be changed, blocks may be combined, and / or blocks may be divided into sub-blocks. Some blocks or processes may be performed in parallel.

[0147] The use of "adapted to" or "configured to" is intended to be open and inclusive language that does not exclude apparatus adapted or configured to perform additional tasks or steps. Additionally, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more recited conditions or values ​​may in fact be based on additional conditions or values ​​beyond those recited conditions or values. The included headings, lists, and numbering are for ease of description only and are not intended to be limiting.

[0148] While the subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon understanding the foregoing, will be able to readily produce modifications, variations, and equivalents of such embodiments. It will be appreciated, therefore, that the present disclosure has been presented for purposes of illustration and not limitation, and is not intended to exclude the inclusion of such modifications, variations, and / or additions to the subject matter of the present invention as would be readily apparent to those skilled in the art.

Claims

1. one or more solid-state switches; a transformer coupled to the one or more solid-state switches; a snubber circuit coupled to the one or more switches; an output coupled to the transformer for generating high voltage pulses having a pulse repetition frequency, a pulse width, a peak voltage greater than 1 kV, and a voltage portion between successive high voltage pulses having a negative slope; Includes a nanosecond pulser.

2. 2. The nanosecond pulser of claim 1, wherein the voltage portion comprises more than 50% of the period between successive pulses.

3. 2. The nanosecond pulser of claim 1, wherein the voltage portion is the voltage between an inflection point during the fall of one pulse and an inflection point during the rise of the following pulse.

4. 2. The nanosecond pulser of claim 1, wherein the voltage portion is the voltage between the end of one pulse and the beginning of a subsequent pulse.

5. 10. The nanosecond pulser of claim 1, wherein said high voltage pulse comprises a non-sinusoidal pulse.

6. 2. The nanosecond pulser of claim 1, wherein the magnitude of said negative gradient is greater than 100,000 kV / s.

7. The snubber circuit comprises: a snubber resistor having a resistance between about 7.5 mΩ and 1.25 Ω; a snubber capacitor having a capacitance of about 2 μF to 35 μF; Including, 2. The nanosecond pulser of claim 1.

8. 2. The nanosecond pulser of claim 1, wherein said pulse width has a duration of about 100-500 ns.

9. A plasma chamber; 10. A nanosecond pulser as recited in claim 1 coupled to said plasma chamber for injecting a high voltage pulse into said plasma chamber; 13. A semiconductor processing system comprising:

10. 10. The semiconductor processing system of claim 9, wherein a voltage fraction measured at at least one point in the plasma chamber between two successive high voltage pulses varies by less than 1 V / ns.

11. 10. The semiconductor processing system of claim 9, wherein the plasma chamber includes a chuck having a capacitance less than about 20 nF.

12. 10. The semiconductor processing system of claim 9, wherein said negative slope is approximately the same in magnitude as and opposite in sign to a ratio of an ion current generated in said plasma chamber to a chuck capacitance of said plasma chamber.

13. 10. The semiconductor processing system of claim 9, wherein the magnitude of the negative gradient approximately cancels a voltage drop across a wafer in the plasma chamber due to ion current.

14. A DC power source; 1. A transformer comprising: A transformer core; a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; The transformer comprising: a droop compensation circuit electrically coupled to the first lead of the primary winding; a first switch electrically connected to the droop compensation circuit and to the DC power source; a second switch electrically connected to the second lead of the primary winding and to the DC power source, the first switch and the second switch being opened and closed at different time intervals; a pulsing output electrically coupled to the secondary winding of the transformer, the pulsing output outputting high voltage bipolar pulses, the high voltage bipolar pulses having a peak-to-peak voltage greater than 1 kV and a voltage portion between successive high voltage bipolar pulses having a negative slope; 2. A pulse generator including:

15. 15. The pulse generator of claim 14, wherein the pulsing output outputs bipolar pulses having a pulse frequency greater than 1 kHz.

16. 15. The pulse generator of claim 14, wherein the voltage portion comprises more than 50% of the period between successive high voltage bipolar pulses.

17. 15. The pulse generator of claim 14, wherein the voltage portion is a voltage between an inflection point during a falling edge of one high voltage bipolar pulse and an inflection point during a rising edge of a subsequent high voltage bipolar pulse.

18. 15. The pulse generator of claim 14, wherein the voltage portion is the voltage between the end of one high voltage bipolar pulse and the beginning of a subsequent high voltage bipolar pulse.

19. 15. The pulse generator of claim 14, wherein the magnitude of the negative gradient is greater than 100,000 kV / s.

20. 15. The pulse generator of claim 14, wherein the droop compensation circuit includes a droop diode biased to allow current to flow through the first switch and the transformer.

21. 21. The pulse generator of claim 20, wherein the droop compensation circuit includes a first inductor and a first resistor arranged in series and electrically coupled across the droop diode.

22. 22. The pulse generator of claim 21, wherein the first inductor has an inductance less than about 100 μH.

23. 22. The pulse generator of claim 21, wherein the first resistor has a resistance less than about 5 ohms.

24. 22. The pulse generator of claim 21, wherein the droop compensation circuit further comprises a second inductor electrically coupled to the droop diode and to the first lead of the primary winding.

25. 25. The pulse generator of claim 24, wherein the second inductor has an inductance less than about 50 nH.

26. 25. The pulse generator of claim 24, further comprising a third resistor and a third inductor arranged in series between the second switch and the second lead of the primary winding.

27. 27. The pulse generator of claim 26, wherein the third inductor has an inductance less than about 35 nH.

28. 27. The pulse generator of claim 26, wherein the third resistor has a resistance less than about 1 ohm.

29. A plasma chamber; 15. A pulse generator as claimed in claim 14, coupled to the plasma chamber to introduce high voltage pulses into the plasma chamber; 13. A semiconductor processing system comprising:

30. 30. The semiconductor processing system of claim 29, wherein a voltage fraction between two successive high voltage pulses measured at at least one point in the plasma chamber varies by less than 1 V / ns.

31. 30. The semiconductor processing system of claim 29, wherein the plasma chamber includes a chuck having a capacitance less than about 20 nF.

32. 30. The semiconductor processing system of claim 29, wherein said negative slope is approximately the same in magnitude as and opposite in sign to a ratio of an ion current generated in said plasma chamber to a chuck capacitance of said plasma chamber.

33. 30. The semiconductor processing system of claim 29, wherein the magnitude of the negative gradient approximately cancels a voltage drop across a wafer in the plasma chamber due to ion current.

34. 1. A transformer comprising: A transformer core; a primary winding wound around at least a portion of the transformer core, the primary winding having a first lead and a second lead; a secondary winding wound around at least a portion of the transformer core; The transformer comprising: a plurality of switches arranged in a full bridge configuration, a first portion of the plurality of switches electrically connected to a droop compensation circuit and the DC power source, a second portion of the plurality of switches electrically connected to the second lead of the primary winding and the DC power source, the first portion of the plurality of switches and the second portion of the plurality of switches being opened and closed at different time intervals; the droop compensation circuit electrically arranged between the first portion of the plurality of switches and / or the second portion of the plurality of switches and the transformer; a pulsing output electrically coupled to the secondary winding of the transformer, the pulsing output outputting first high voltage bipolar pulses, the first high voltage bipolar pulses having a peak-to-peak voltage greater than about 1 kV, a pulse frequency greater than 1 kHz, and a voltage portion between successive high voltage bipolar pulses having a negative slope; 2. A pulse generator including:

35. 35. The pulse generator of claim 34, wherein the voltage portion comprises more than 50% of the period between successive high voltage bipolar pulses.

36. 15. The pulse generator of claim 14, wherein the voltage portion is a voltage between an inflection point during a falling edge of one high voltage bipolar pulse and an inflection point during a rising edge of a subsequent high voltage bipolar pulse.

37. 35. The pulse generator of claim 34, wherein the voltage portion is the voltage between the end of one high voltage bipolar pulse and the beginning of a subsequent high voltage bipolar pulse.

38. 35. The pulse generator of claim 34, wherein the magnitude of the negative gradient is greater than 100,000 kV / s.

39. 35. The pulse generator of claim 34, wherein the droop compensation circuit includes a droop diode biased to allow current to flow through the first switch and the transformer.

40. 35. The pulse generator of claim 34, wherein the pulsing output outputs a bipolar pulse, the bipolar pulse having a peak-to-peak voltage less than the peak-to-peak voltage of the first high voltage bipolar pulse and greater than about 500 V and a pulse frequency greater than 1 kHz.

41. The droop compensation circuit includes: a diode biased from the first portion of the plurality of switches toward the first lead; a first resistor disposed between the diode and the first lead; A first inductor; a second resistor disposed in series with the first inductor and electrically coupled across the diode; 35. The pulse generator of claim 34, comprising:

42. 42. The pulse generator of claim 41, wherein the first inductor has an inductance less than about 100 μH.

43. 42. The pulse generator of claim 41, wherein the first resistor has a resistance less than about 5 ohms.

44. 42. The pulse generator of claim 41, wherein the second resistor has a resistance less than about 5 ohms.

45. 42. The pulse generator of claim 41, further comprising a second inductor and a third resistor arranged in series between the second portion of the plurality of switches and the second lead.

46. A plasma chamber; 35. A pulse generator as claimed in claim 34, coupled to the plasma chamber to introduce high voltage pulses into the plasma chamber; 13. A semiconductor processing system comprising:

47. 47. The semiconductor processing system of claim 46, wherein a voltage fraction between two successive high voltage pulses measured at at least one point in the plasma chamber varies by less than 1 V / ns.

48. 47. The semiconductor processing system of claim 46, wherein said plasma chamber includes a chuck having a capacitance less than about 20 nF.

49. 47. The semiconductor processing system of claim 46, wherein said negative slope has a magnitude approximately equal to and an opposite sign to a ratio of an ion current generated in said plasma chamber to a chuck capacitance of said plasma chamber.

50. 47. The semiconductor processing system of claim 46, wherein the magnitude of said negative gradient approximately cancels a voltage drop across a wafer in said plasma chamber due to ion current.

Images