Data processing apparatus, program, and data processing method

Abstract

To reduce a memory use amount required upon calculation of an assignment problem.SOLUTION: A data processing apparatus according to the present invention has: a storage unit 11 for storing either of a flow matrix and a distance matrix of an assignment problem having an evaluation function represented by using matrix operation of the flow matrix and the distance matrix; and a processing unit 12 for selecting a first element and a second element among a plurality of elements assigned to a plurality of allocation destinations, reading out either of first matrix elements as the flow matrix and the distance matrix which respectively correspond to the first element and the second element from the storage unit 11, generating, based on the first element and the second element, a second matrix element as the other pattern matrix of the flow matrix and the distance matrix, calculating, by using the first matrix element and the second matrix element, a change amount of a value of the evaluation function obtained when the allocation change of changing the allocation destination of the first element or the second element is caused, determining, based on the change amount, whether or not the allocation change is allowed, and updating allocation states if it is determined that the allocation change is allowed.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a data processing device, a program, and a data processing method. [Background technology]

[0002] The quadratic assignment problem (QAP) is an example of an assignment problem, which is a type of combinatorial optimization problem. The quadratic assignment problem is a problem of finding an assignment that minimizes the sum of the products of the flow volume between elements (cost of transporting materials between facilities, etc.) and the distance between the destinations to which each element is assigned, when assigning n elements (facilities, etc.) to n destinations. In other words, the quadratic assignment problem is a problem of searching for an assignment that minimizes the value of the evaluation function expressed by the following formula (1). The evaluation function represents the cost according to the assignment state, and is also called the cost function.

[0003]

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[0004] In formula (1), f i,j is the amount of flow between elements with identification numbers i and j, and d φ(i),φ(j) b indicates the distance between the assignment destinations to which the elements with identification numbers i and j are assigned. i,φ(i) is the bias coefficient. Bias coefficient b i,φ(i) represents a fixed cost for assigning an element with identification number=i to an assignment destination with identification number=φ(i).

[0005] Incidentally, there is an Ising device (also called a Boltzmann machine) that uses an Ising-type evaluation function (also called an energy function, etc.) as a device for calculating large-scale discrete optimization problems, which von Neumann-type computers are not good at.

[0006] An Ising machine converts a combinatorial optimization problem into an Ising model that represents the behavior of spin in a magnetic material. Then, the Ising machine searches for the state of the Ising model that minimizes the value of the Ising-type evaluation function (corresponding to energy) by using Markov chain Monte Carlo methods such as simulated annealing and replica exchange (also known as parallel tempering). The state of the Ising model can be expressed by a combination of the values ​​of multiple state variables. The value of each state variable can be 0 or 1.

[0007] A technique has been proposed for solving quadratic assignment problems using such Boltzmann machines. The Ising-type evaluation function for the quadratic assignment problem can be expressed as follows:

[0008]

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[0009] In formula (2), x is a vector of state variables, and represents the allocation state of n elements to n allocation destinations. T is (x 1,1 ,…,x 1,n ,x 2,1 ,…,x 2,n ,……,x n,1 ,…,x n,n ) can be expressed as x i,j = 1 indicates that the element with identification number = i is assigned to the element with identification number = j, and x i,j =0 indicates that the element with identification number=i is not assigned to the assignment destination of identification number=j.

[0010] W is a matrix of weight values, and is expressed by a matrix operation of the flow matrix, which is a matrix of the flow amount between elements, and the matrix of the distance between the allocation destinations. The weight matrix W is expressed by the matrix of the flow amount between elements, which is a matrix of the flow amount between elements, and the matrix of the distance between the allocation destinations. i,j Using the distance matrix D, this can be expressed as the following equation (3).

[0011]

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[0012] When the scale of the assignment problem becomes large, the amount of information in the weight matrix W becomes huge and it may not be possible to store it all in memory. For this reason, a method has been proposed in which the weight matrix W is not directly stored, but the weight values ​​used for calculating the amount of change in the value of the evaluation function are calculated from the flow amount and distance (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] US Patent Application Publication No. 2021 / 0326679 Summary of the Invention [Problem to be solved by the invention]

[0014] As the scale of the assignment problem increases, the amount of flow and distance information that must be stored in memory also increases. Therefore, the conventional method of calculating weights from flow and distance may not be able to reduce memory usage sufficiently.

[0015] In one aspect, the present invention has an object to provide a data processing device, a program, and a data processing method that can reduce the memory usage when calculating an assignment problem. [Means for solving the problem]

[0016] In one embodiment, there is provided a data processing device having: a memory unit that stores one of the flow matrix and the distance matrix for an assignment problem having an evaluation function expressed using matrix operations on the flow matrix and the distance matrix; and a processing unit that selects a first element and a second element from a plurality of elements to be assigned to a plurality of assignment destinations, reads out a first matrix element of one of the flow matrix and the distance matrix corresponding to the first element and the second element from the memory unit, generates a second matrix element of a patterned matrix that is the other of the flow matrix and the distance matrix based on the first element and the second element, calculates an amount of change in the value of the evaluation function when an assignment change occurs in which the assignment destination of the first element or the second element changes, and determines whether or not to allow the assignment change based on the amount of change, and updates the assignment state if it is determined that the assignment change is allowed.

[0017] Also, in one embodiment, a program is provided. Also provided in one embodiment is a method for processing data. Effect of the Invention

[0018] In one aspect, the present invention can reduce memory usage when computing an assignment problem. [Brief description of the drawings]

[0019] [Figure 1] FIG. 13 is a diagram illustrating an example of calculating a QAP. [Diagram 2] FIG. 13 is a diagram illustrating an example of calculation of GQAP. [Diagram 3] FIG. 13 is a diagram illustrating an example of update calculation of a cache matrix. [Figure 4] FIG. 1 illustrates an example of a data processing device according to a first embodiment; [Diagram 5] FIG. 1 is a diagram showing examples of types of assignment problems and flow matrices F or distance matrices D that can be generated. [Figure 6] FIG. 1 illustrates an example of a data processing device according to a second embodiment. [Figure 7]FIG. 1 illustrates an example of a replica circuit. [Figure 8] FIG. 2 is a diagram illustrating an example of an F / D matrix element generation circuit. [Figure 9] FIG. 13 is a diagram illustrating an example of a ΔC calculation circuit. [Figure 10] FIG. 13 is a diagram illustrating an example of an allocation change permission determination circuit. [Figure 11] FIG. 13 is a diagram illustrating an example of a constraint violation detection circuit. [Figure 12] FIG. 2 illustrates an example of a local field update circuit. [Figure 13] FIG. 2 is a diagram illustrating an example of a difference matrix generating circuit. [Figure 14] 13 is a flowchart illustrating an example of a processing procedure of the data processing device according to the second embodiment. [Figure 15] 13 is a flowchart illustrating an example of a procedure for replica initialization processing. [Figure 16] 13 is a flowchart illustrating an example of a procedure for a search process (replacement). [Figure 17] 13 is a flowchart showing an example of a procedure for a search process (relocation). [Figure 18] 13 is a flowchart showing an example of a procedure for generating F / D matrix elements. [Figure 19] FIG. 13 illustrates an example of a replica circuit in a data processing device according to a third embodiment; [Figure 20] FIG. 1 illustrates an example of hardware of a computer that is an example of a data processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, an embodiment of the invention will be described with reference to the drawings. The data processing device of this embodiment searches for a solution to the assignment problem by local search. Examples of the assignment problem include the quadratic assignment problem (QAP), the generalized quadratic assignment problem (GQAP), and the quadratic semi-assignment problem (QSAP). QAP, GQAP, QSAP, and local search are explained below.

[0021] (QAP) Figure 1 shows an example of the calculation of QAP. QAP is a problem to find an allocation that minimizes the sum of the products of the flow rates between elements and the distances between the destinations to which each element is assigned, when allocating n elements (such as facilities) to n destinations.

[0022] FIG. 1 shows an example in which four facilities, each having an identification number of 1 to 4, are assigned to four allocation destinations (L1 to L4). A flow matrix representing the amount of flow between n elements is expressed by the following equation (4).

[0023]

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[0024] The flow matrix F is a matrix with n rows and n columns. i,j is the flow amount in row i, column j, and represents the flow amount between elements with identification numbers = i, j. For example, the flow amount between facility with identification number = 1 and facility with identification number = 2 in Figure 1 is f 1,2 This can be expressed as:

[0025] The distance matrix indicating the distance between n allocation destinations is expressed by the following formula (5).

[0026]

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[0027] The distance matrix D is an n-row, n-column matrix. d i,jis the distance in row i, column j, and represents the distance between the assignees of identification numbers i and j. For example, the distance between the assignee (L1) of identification number 1 and the assignee (L2) of identification number 2 in Figure 1 is d 1,2 This can be expressed as:

[0028] The bias matrix representing n×n bias coefficients is expressed by the following equation (6).

[0029]

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[0030] The QAP is calculated by searching for an assignment that minimizes the above equation (1). The assignment state of n elements to n destinations is represented by an integer assignment vector φ or a binary state matrix X. φ is a set Φ n is an element of Φ n is the set of all permutations of the set N = {1, 2, 3, ..., n}. Let x be the binary variable contained in the binary state matrix X. i,j is expressed by the following equation (7).

[0031]

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[0032] FIG. 1 shows an example in which a facility with identification number 1 is assigned to an assignee with identification number 2, a facility with identification number 2 is assigned to an assignee with identification number 3, a facility with identification number 3 is assigned to an assignee with identification number 4, and a facility with identification number 4 is assigned to an assignee with identification number 1. The integer assignment vectors φ are φ(1)=2, φ(2)=3, φ(3)=4, and φ(4)=1. The binary state matrix X is expressed as x 1,2 , x 2,3 , x 3,4 , x 4,1 are each 1, and the other x i,j is set to 0.

[0033] A QAP may have either a symmetric flow matrix or a distance matrix, or both of them may be asymmetric. A QAP with a symmetric matrix can be directly converted to a QAP with an asymmetric matrix.

[0034] (GQAP) Figure 2 shows an example of calculation of GQAP. GQAP is a problem to find an assignment that minimizes the sum of the products of the flow amount between elements and the distance between the assignment destinations to which each element is assigned when assigning n elements to m assignment destinations. In GQAP, the number of elements n and the number of assignment destinations m may be different. In GQAP, assignment of multiple elements to each assignment destination may be allowed in some cases.

[0035] FIG. 2 shows an example in which four facilities, each having an identification number of 1 to 4, are assigned to one of four assignment destinations (L1 to L4). The flow matrix F that represents the amount of flow between n elements is expressed in the same manner as in the above-mentioned equation (4).

[0036] In GQAP, the binary state matrix X, the distance matrix D, and the bias matrix B are expressed by the following equations (8), (9), and (10), respectively.

[0037]

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[0038]

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[0039]

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[0040] The distance matrix D in equation (9) has non-zero diagonal elements to take into account routing within the allocation destination. The GQAP is also calculated by searching for an allocation that minimizes the above equation (1). However, each element in the GQAP (for example, a facility as shown in Figure 2) has a unique size, and each allocation destination has a capacity limit. The size is expressed by the following equation (11), and the capacity limit is expressed by the following equation (12).

[0041]

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[0042]

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[0043] When allocating one or more elements to a single destination, a vector representing unused capacity as shown in the following equation (13) is introduced to ensure that the cumulative size of those elements does not exceed the upper limit of the destination's capacity.

[0044]

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[0045] Allocation is performed using the unused capacity so that the inequality constraint expressed by the following equation (14) is satisfied (so that the unused capacity does not fall below 0).

[0046]

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[0047] FIG. 2 shows an example in which two facilities with identification numbers 1 and 2 are assigned to the one with identification number 1, a facility with identification number 3 is assigned to the one with identification number 4, and a facility with identification number 4 is assigned to the one with identification number 2. In other words, the number of elements and the number of assignees are different. The integer assignment vector φ is φ(1)=1, φ(2)=1, φ(3)=4, and φ(4)=2. The binary state matrix X is expressed as x 1,1 , x 2,1 , x3,4 , x 4,2 are each 1, and the other x i,j is set to 0.

[0048] (QSAP) QSAP is a variation of GQAP. Like GQAP, QSAP can have different number of elements n and number of destinations m. However, since the size of each element (for example, the facilities in Figure 2) in QSAP is all 0 and the capacity of each destination is also all 0, there are no inequality constraints.

[0049] The QSAP is also calculated by searching for an assignment that minimizes the above equation (1). (Local Search) In local search, a candidate solution is searched for within a nearby state that can be reached by changing the current state. One method of performing local search on GQAP is pairwise exchange between elements. In this method, two elements are selected and their assignment destinations are swapped. The change in the value of the evaluation function (Equation (1)) due to the swapping of the assignment destinations (represented by identification numbers = φ(a), φ(b)) of two elements (represented by identification numbers = a, b) can be expressed by the following equations (15) and (16).

[0050]

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[0051]

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[0052] In GQAP, an element can be relocated (reassigned) to another assignment destination regardless of whether the element is assigned to a certain assignment destination or not. The change in the value of the evaluation function when reassigning an element with identification number = b from its current assignment destination to an assignment destination with identification number = a (identification number = φ(a)) is expressed by the following equations (17) and (18).

[0053]

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[0054]

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[0055] The calculation of ΔC in GQAP occupies a large part of the total processing time in the data processor when the data processor searches for a solution to the assignment problem. The calculation of ΔC in equation (15) can be easily vectorized using inner product calculations, unless there is a condition to skip the calculation of i=a,b.

[0056] As shown in the following equations (19) and (20), this condition can be eliminated by performing compensation by adding an additional product of the flow amount and the distance as a compensation term (comp).

[0057]

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[0058]

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[0059] In local search, based on ΔC calculated as above, it is decided whether to accept or not accept a proposal for an allocation change that causes a change in the value of the evaluation function of ΔC. The decision to accept or not accept a proposal is based on predefined criteria, for example, a greedy method. If a greedy method is used, an allocation change that reduces the value of the evaluation function is accepted. If a greedy method is used, the proposal acceptance rate (PAR) is high at the beginning of the search, but tends to approach 0 later because the search gets stuck in a local minimum of the evaluation function and no further improvement moves are found.

[0060] Instead of the greedy method, a stochastic local search method such as simulated annealing can be used. In the stochastic local search method, the temperature parameter (T) is used to add randomness to the change in allocation, and the acceptance probability (P acc ) can be used.

[0061]

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[0062] As T increases towards infinity, P acc and PAR increases, and all proposals are accepted regardless of the value of ΔC. As T is lowered and approaches 0, proposal acceptance becomes greedy and PAR tends to 0 as the search eventually gets stuck in a local minimum of the evaluation function.

[0063] (Vectorization of ΔC calculation) In QAP, there is a method called the Boltzmann Machine Caching method (BM$ method) for vectorizing the ΔC calculation. The BM$ method is a method for calculating and caching local fields, which are partial ΔC values ​​corresponding to bit inversions in the binary state matrix. In the case of QAP, when a proposal for reassignment is accepted, n 2 The n-row, n-column local field matrix (hereafter referred to as cache matrix H) is updated in a time proportional to n. However, the calculation of ΔC can be performed in a time that does not depend on n. Below, we will explain the case where the BM$ method is extended to GQAP.

[0064] In the case of GQAP, the cache matrix H is calculated as m × n 2 is generated in a time proportional to

[0065]

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[0066] Equation (19), which expresses ΔC due to allocation swapping, and equation (17), which expresses ΔC due to rearrangement, can be expressed as the following equations (23) and (24) using the preserved local fields.

[0067]

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[0068]

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[0069] When the allocation change proposal is accepted, the cache matrix H is updated by using the Kronecker product as shown in Fig. 3. First, the ΔF vector and the ΔD vector are calculated based on the following equations (25) and (26). Then, the cache matrix H is updated based on the equation (27).

[0070]

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[0071]

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[0072]

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[0073] FIG. 3 is a diagram illustrating an example of update calculation of the cache matrix. As shown in Figure 3, the update is performed one row at a time of the cache matrix H. Processing for rows corresponding to zero elements of the vector ΔF is skipped.

[0074] Similarly, when a proposal to change the allocation of a relocation is accepted, the cache matrix H is updated by equation (28). Since the allocation destination of a single element is moved in the relocation, the update of the cache matrix H does not require the ΔF vector, but instead the flow amount of one row (F a,* ) is used.

[0075]

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[0076] Note that depending on the dimension of the assignment problem and the topology of the flow matrix F and the distance matrix D, instead of the cache matrix H, we can store the transposed matrix of H. An example where this is useful is an instance where n>m. In this case, the transposed cache matrix H allows more row elements to be updated per clock cycle, if there are enough parallel computing units. Another example is when the contents of the distance matrix D generate a vector ΔD that is, on average, sparser than the vector ΔF. In this case, we can skip updating a large number of transposed rows. This may reduce the computation time required to update the cache matrix H.

[0077] As with the local field, the unused capacity shown in equation (13) can be treated as a constraint field. Proposals for swapping or relocation of allocations affect the constraint field. Using the constraint field is expected to simplify the calculations to check whether a proposal will violate constraints. First, the net change in required element size, ΔS, due to a proposal for swapping or relocation of allocations is calculated based on equations (29) and (30).

[0078]

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[0079]

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[0080] Next, the value of ΔS is added to both constraint fields based on the following equations (31) and (32) to obtain the constraint field if the proposal is accepted.

[0081]

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[0082]

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[0083] A flag value (violated?) is then set to indicate whether a constraint has been violated, based on Equation (33): If the proposed allocation change would result in overcapacity of any of the constraint fields, then the flag value is set to 1.

[0084]

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[0085] If the flag value is 1, the reassignment proposal is rejected regardless of the value of ΔC. To simplify the calculation, the acceptance probability P acc Instead of θ, a tolerance threshold (θ) can be used.

[0086]

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[0087] The proposal acceptance criterion using θ is expressed as follows:

[0088]

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[0089] However, as the scale of the assignment problem increases, the amount of flow and distance information stored in memory also increases. A data processing device according to a first embodiment described below does not store either the flow matrix F or the distance matrix D in memory, and generates the other matrix element by a method described below when calculating ΔC or updating the local field. This makes it possible to reduce the memory capacity used when calculating the assignment problem.

[0090] (First embodiment) FIG. 4 illustrates an example of the data processing device according to the first embodiment. The data processing device 10 of the first embodiment includes a storage unit 11 and a processing unit 12.

[0091] The storage unit 11 may include a volatile semiconductor memory such as a RAM (Random Access Memory), or may include a non-volatile storage such as a HDD (Hard Disk Drive) or a flash memory. The storage unit 11 may also include both a volatile semiconductor memory and a non-volatile storage.

[0092] The storage unit 11 includes an F / D holding memory 11a, a local field holding memory 11b, an element size holding memory 11c, and an unused capacity holding memory 11d. The F / D holding memory 11a stores one of the flow matrix F and the distance matrix D of an assignment problem having an evaluation function expressed using a matrix operation of the flow matrix F and the distance matrix D. In other words, the F / D holding memory 11a does not need to store the other of the flow matrix F and the distance matrix D.

[0093] The local field storage memory 11b stores a cache matrix H including n×m local fields expressed by the above-mentioned equation (22). Note that the local field storage memory 11b may not be necessary if the local fields are not used in the calculation of ΔC.

[0094] The element size storage memory 11c stores the size of each element (facility, luggage, etc.) used to determine whether or not the inequality constraints are satisfied. The unused capacity holding memory 11d stores the unused capacity of each allocation destination, which is expressed by the above-mentioned formula (13).

[0095] The processing unit 12 can be realized by an electronic circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). However, the processing unit 12 can also be realized by a processor such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). The processor executes a program stored in a memory such as a RAM (which may be the storage unit 11). A collection of processors may be called a multiprocessor or simply a "processor." Furthermore, the processing unit 12 may include a processor and an electronic circuit such as an ASIC or an FPGA.

[0096] In a process of searching for a solution to the assignment problem, the processing unit 12 selects a first element and a second element as candidates for replacement of the assignment destinations from among a plurality of elements assigned to a plurality of assignment destinations. Then, the processing unit 12 reads out from the storage unit 11 a first matrix element of one of the flow matrix F and the distance matrix D corresponding to the first element and the second element.

[0097] For example, when ΔC is calculated based on the above-mentioned formula (19), the processing unit 12 calculates the matrix element (flow amount) f b,* ,f a,* , or the matrix element (distance) d of the distance matrix D φ(a),* ,d φ(b),* When ΔC is calculated based on the above-mentioned equation (23) using a local field, the processing unit 12 reads out f a,b Or, d φ(a),φ(b) ,d φ(a),φ(a) ,d φ(b),φ(b) Read out.

[0098] The processing unit 12 generates a second matrix element of a patterned matrix, which is the other of the flow matrix F and the distance matrix D, corresponding to the first element and the second element according to the type of assignment problem. b,* ,f a,* , or the matrix element (distance) d of the distance matrix D φ(a),* ,d φ(b),* When one of the f is read, the other is generated. a,b Or, d φ(a),φ(b) ,d φ(a),φ(a) ,d φ(b),φ(b) When one of the matrixes is read, the other is generated. Depending on the type of assignment problem, which of the flow matrix F and the distance matrix D is used as a pattern matrix and its matrix elements are generated will be described later (see FIG. 5).

[0099] The processing unit 12 calculates the amount of change in the value of the evaluation function (the above-mentioned ΔC) when an allocation change occurs in which the allocation destination of the first element or the second element is changed, based on the matrix elements that have been read out or generated. Then, the processing unit 12 determines whether or not to permit the allocation change based on ΔC, and updates the allocation state when it determines that the first allocation change is permitted. An allocation change that swaps the allocation destinations of the first element and the second element is, for example, an acceptance probability (P acc ) is permitted. When the allocation problem has an inequality constraint, whether or not an allocation change is permitted is determined, for example, according to the above-mentioned equation (33). When ΔC is calculated based on equation (23) using a local field, the processing unit 12 updates the cache matrix H when an allocation change is permitted. The update of the cache matrix H is performed, for example, based on equation (27). When one of the flow matrix F and the distance matrix D is stored in the memory unit 11, the matrix elements of the other of the flow matrix F and the distance matrix D used to update the cache matrix H are generated by the processing unit 12.

[0100] When an allocation change is made due to element rearrangement, whether or not to permit the rearrangement is determined based on, for example, ΔC in the above-mentioned formula (17). When calculating ΔC at this time, the matrix element read out from the storage unit 11 (one of the matrix elements of the flow matrix F and the distance matrix D) and the generated matrix element (the other of the matrix elements of the flow matrix F and the distance matrix D) can be used.

[0101] The processing unit 12 repeats the above-mentioned process. When the simulated annealing method is performed, the processing unit 12 decreases the temperature parameter (T) according to a predetermined temperature change schedule, and searches for a minimum value of the evaluation function. For example, when the processing is completed a predetermined number of times, the allocation state in which the minimum evaluation function value is obtained is output as a solution. When the parallel tempering is performed, the above-mentioned process is repeated for each of a plurality of replicas in which different values ​​of T are set. Then, the allocation states (or T) between the replicas are exchanged in a predetermined cycle according to a predetermined exchange allowance probability. For example, when the processing is completed a predetermined number of times, the allocation state of the replica in which the minimum evaluation function value is obtained is output as a solution.

[0102] An example of the processing unit 12 that performs the above-mentioned processing is shown in Fig. 1. The processing unit 12 includes a controller 12a and a circuit unit 12b. The controller 12a controls the operation of the circuit unit 12b. The controller 12a also holds the current allocation state and the value of the evaluation function, the smallest value of the evaluation function so far, and the allocation state at that time. The controller 12a selects the first element and the second element as replacement candidates for the allocation destination, updates the allocation state, and so on. The controller 12a also controls the reading and writing of data from and to the storage unit 11.

[0103] The circuit unit 12b includes an F / D matrix element generating circuit 12b1, a ΔC calculating circuit 12b2, a constraint violation detecting circuit 12b3, an allocation change possibility determining circuit 12b4, a local field updating circuit 12b5, and a selecting circuit 12b6.

[0104] Under the control of the controller 12a, the F / D matrix element generation circuit 12b1 supplies either the matrix elements of the flow matrix F or the distance matrix D stored in the F / D holding memory 11a to the ΔC calculation circuit 12b2 and the local field update circuit 12b5. Furthermore, under the control of the controller 12a, the F / D matrix element generation circuit 12b1 generates the other matrix elements of the flow matrix F or the distance matrix D that are not stored in the F / D holding memory 11a. Then, the F / D matrix element generation circuit 12b1 supplies the generated matrix elements to the ΔC calculation circuit 12b2 and the local field update circuit 12b5.

[0105] The ΔC calculation circuit 12b2 calculates ΔC due to the allocation replacement or rearrangement. The constraint violation detection circuit 12b3 detects whether or not a constraint violation resulting in a capacity overrun occurs when the allocation destinations of the first element and the second element are swapped, based on the sizes of the first element and the second element and the unused capacities of their allocation destinations read from the storage unit 11. The constraint violation detection circuit 12b3 may also update the unused capacities of each allocation destination when the allocation destinations of the first element and the second element are swapped.

[0106] The allocation change permission determination circuit 12b4 inputs ΔC and θ shown in equation (34) and determines whether or not to permit the allocation change according to equation (35). Note that if the constraint violation detection circuit 12b3 detects a constraint violation, the allocation change is not permitted.

[0107] If the allocation change is permitted, the local field update circuit 12b5 updates the cache matrix H including n×m local fields according to equation (27) or equation (28). The selection circuit 12b6 selects the local field used when the ΔC calculation circuit 12b2 calculates ΔC based on the equation (23) or (24), and supplies it to the ΔC calculation circuit 12b2.

[0108] More specific examples of these circuits will be described in the second embodiment. (Types of assignment problems and examples of flow matrices F or distance matrices D that can be generated) 5 is a diagram showing an example of a type of assignment problem and a generateable flow matrix F or distance matrix D. (A) is a diagram showing an example of a distance matrix D that the processing unit 12 can generate in the Quadratic Multiple Knapsack Problem (QMKP). (B) is a diagram showing an example of a flow matrix F that the processing unit 12 can generate in the Traveling Salesman Problem (TSP). (C) is a diagram showing an example of a distance matrix D that the processing unit 12 can generate in the Linear Ordering Problem (LOP).

[0109] The knapsack problem is a problem of finding the way to place items, each with a given value and weight (or capacity), into a knapsack with a weight (or capacity) limit in such a way that the total profit is maximized. In other words, the knapsack problem is an allocation problem in which the above elements (facilities, etc.) are the items and the allocation destinations (locations, etc.) are the knapsacks. In addition to the value of the item itself (primary value), QMKP also deals with the value (secondary value) that arises when two items selectable from all items are placed in the same knapsack.

[0110] In QMKP, the evaluation function that represents the total profit is expressed by the following equation (36).

[0111]

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[0112] In equation (36), V i,j is the value generated when items with identification numbers = i, j are put into the same knapsack, and v i is the value of the item with identification number i itself. Also, φ(i) represents the identification number of the knapsack containing the item with identification number i, and φ(j) represents the identification number of the knapsack containing the item with identification number j. When φ(i)=φ(j), V i,j is added to the total profit.

[0113] In addition, the weight restriction of QMKP is expressed by an inequality constraint such as the following equation (37).

[0114]

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[0115] In equation (37), w i is the weight of the item with identification number = j, and L j is the upper limit of the weight of an item that can be placed in the knapsack with identification number j among the k knapsacks.

[0116] To map QMKP to the GQAP format, we simply map the weight of each item to the size of the element. A dummy knapsack is used because there is no direct way to track items that are not in the knapsack. If an item is in the knapsack, its value is not added to the total profit. When mapping QMKP to the GQAP format, such a dummy knapsack is added, so the number of allocations m is k+1.

[0117] The weight limit of k knapsacks can be directly mapped to the upper limit of the GQAP destination capacity shown in (12). To avoid violating the weight limit of the dummy knapsack, we set the weight limit L of the dummy knapsack with ID=m to be equal to the total weight of all items, as shown in (38) below. m is set.

[0118]

number

[0119] L m is the vector L of the upper limit of the capacity of the final GQAP allocation destination, as shown in the following equation (39). KP This is concatenated to the end of a vector L of the k knapsack weight limits to obtain

[0120]

number

[0121] The value of each item is added to the total profit if it is placed in any knapsack other than the dummy knapsack, so we can use the bias matrix shown in equation (6) as a row vector containing the value of each item multiplied by a column vector with m rows, all of whose elements are 1 except for the last one, which is set to 0, as shown in equation (40) below.

[0122]

number

[0123] The flow matrix F of QMKP corresponds to the flow matrix F of GQAP. KP is expressed as the above-mentioned quadratic value (V i,j ) as an n × n matrix element.

[0124]

number

[0125] V i,j contributes to the total profit only if both items with identification numbers = i, j are in the same knapsack other than the dummy knapsack. Therefore, the distance matrix D of QMKP corresponding to the distance matrix D of GQAP is KP can be expressed by the following equation (42).

[0126]

number

[0127] k×k identity submatrix I k×k In, the distances between different knapsacks are set to 0, and the distances within the same knapsack are set to 1. The distance matrix D KPThe last row and column of corresponds to the dummy knapsack, so the distances between other knapsacks and the dummy knapsack and the distances within the dummy knapsack are all set to 0.

[0128] In other words, the distance matrix D(=D KP ) is used. When the processing unit 12 proposes an allocation change such that items with identification numbers = i, j are allocated to the same knapsack (allocation destination), it generates 1 as a matrix element of the distance matrix D used to calculate ΔC. When the processing unit 12 proposes any other allocation change, it generates 0 as a matrix element of the distance matrix D used to calculate ΔC.

[0129] It should be noted that the identification number of the dummy knapsack is not limited to m and may be 0. Therefore, when searching for a solution of QMKP, the distance matrix D does not need to be stored in the storage unit 11.

[0130] In addition to QMKP, in various assignment problems, the matrix elements of the flow matrix F or the distance matrix D can be patterned and expressed with relatively simple functions. In TSP, the distance matrix D includes the distance between cities as a matrix element. The flow matrix can be patterned as an adjacency matrix of a Hamiltonian cycle with vertices where the number of facilities is N, and can be expressed, for example, as shown in Figure 5(B). In LOP, the distance matrix D can be patterned so that the matrix elements of the upper triangle are 1, and the matrix elements of the lower triangle and the diagonal elements are 0, as shown in Figure 5(C).

[0131] The data processing device 10 of the first embodiment generates matrix elements of a patterned matrix from the above-mentioned flow matrix F or distance matrix D, and uses them to calculate ΔC and update the local field. This eliminates the need to store the flow matrix F or distance matrix D in the storage unit 11, thereby reducing the memory capacity used.

[0132] (Second embodiment) FIG. 6 illustrates an example of a data processing device according to the second embodiment. The data processing device 20 of the second embodiment searches for a solution to the assignment problem by the parallel tempering method.

[0133] The data processing device 20 includes replica circuits 21a1, 21a2, ..., 21a32, an MCU (Master Control Unit) 22, and an interface circuit 23. Such a data processing device 20 can be realized by an electronic circuit such as an FPGA, for example.

[0134] The replica circuits 21a1 to 21a32 search in parallel for a solution to the assignment problem by local searches based on different temperature parameter values. Note that the number of replica circuits 21a1 to 21a32 is just an example and is not limited to 32.

[0135] The MCU 22 controls the parallel tempering. The MCU 22 controls the adjacent temperature parameter values ​​(T k , T k+1 ) is set between the replicas, the evaluation function value (C k , C k+1 ) and T k , T k+1 Based on this, the exchange acceptance probability SAP is expressed by the following formula (43), T k , T k+1 Exchange the values ​​of

[0136]

number

[0137] Moreover, the MCU 22 transmits θ (see equation (34)) based on 32 mutually different temperature parameter (T) values ​​to the replica circuits 21a1 to 21a32 together with a control signal. The MCU 22 can generate θ using, for example, a pseudo-random number generator such as a PCG (Permuted Congruential Generator). The MCU 22 also transmits and receives data to and from a processing device (for example, a host CPU) external to the data processing device 20 via the interface circuit 23. For example, the MCU 22 receives and holds problem information, calculation conditions, etc. of the assignment problem.

[0138] The problem information includes, for example, the flow matrix F or the distance matrix D, the size of each element expressed in equation (11), the size (n) of the assignment problem, and so on. The calculation conditions include, for example, the initial values ​​of the local field and unused capacity mentioned above, the initial value of T, and the target evaluation function value (C target ), the seed of the random number used when the pseudorandom number generator generates the random value rand(0,1) in equation (34), etc.

[0139] The MCU 22 writes the flow matrix F or the distance matrix D, the size of each element, and the initial values ​​of the local field and unused capacity to the memory described later in the replica circuits 21a1 to 21a32. In addition, the MCU 22 writes the initial value of the allocation state (φ) and the minimum value of the evaluation function (C min ) indicating the allocation state (φ min ) and supplies them to the replica circuits 21a1 to 21a32. min The minimum value of φ min is output via the interface circuit 23.

[0140] The interface circuit 23 transmits and receives data between the MCU 22 and a processing device (for example, a host CPU) external to the data processing device 20. As the interface circuit 23, for example, a PCIe (Peripheral Component Interconnect express) or the like can be used.

[0141] (An example of a replica circuit) Fig. 7 is a diagram showing an example of a replica circuit. Although Fig. 7 shows an example of the replica circuit 21a1, the replica circuits 21a2 to 21a32 can also be realized with a similar configuration.

[0142] The replica circuit 21a1 includes a controller 30, a local field memory 31, an element size memory 32, an unused capacity memory 33, an F / D memory 34, and a D I The replica circuit 21a1 further includes a holding memory 35. The replica circuit 21a1 further includes an F / D matrix element generating circuit 36, a ΔC calculating circuit 37, an allocation change permission determining circuit 38, a constraint violation detecting circuit 39, a local field updating circuit 40, and a selecting circuit 41.

[0143] The controller 30 controls the operation of the replica circuit 21a1. The controller 30 also controls the current allocation state (φ t ) and the current evaluation function value (C t ), the smallest evaluation function value so far (C min ) and the allocation state at that time (φ min ) to hold the information. Therefore, the controller 30 may include a memory (for example, SRAM (Static RAM) or the like) for holding such information. In addition, the controller 30 selects the first element and the second element as replacement candidates for the allocation destination, updates the allocation state, and so on.

[0144] The functions of the controller 12a in FIG. 4 can be realized by, for example, the above-mentioned controller 30 and MCU 22. The local field holding memory 31 stores a cache matrix H including n×m local fields expressed by the above-mentioned equation (22).

[0145] The element size memory 32 stores the size of each element expressed by the above-mentioned equation (11). The unused capacity holding memory 33 stores the unused capacity of each allocation destination, which is expressed by the above-mentioned formula (13).

[0146] The F / D holding memory 34 stores either the flow matrix F or the distance matrix D of an assignment problem having an evaluation function expressed using a matrix operation of the flow matrix F and the distance matrix D. However, when a mode is used in which the matrix elements of the other of the flow matrix F and the distance matrix D are not generated, both the flow matrix F and the distance matrix D may be stored.

[0147] In the following description, the F / D holding memory 34 is divided into a left half storage area and a right half storage area. For example, if the F / D holding memory 34 can store a flow matrix F or a distance matrix D with a maximum of 128 rows and 128 columns, these matrices are stored separately in a left 64 column area and a right 64 column area. In this case, if each matrix has 64 columns or less, the right half storage area does not need to be used. By reducing the row width by half in this way, the amount of circuitry used to read and process row data of the flow matrix F or the distance matrix D can be reduced. In addition, with this configuration, by using dual ports, writing and reading can be performed simultaneously on any two half rows. Therefore, an entire row can be read at once per clock cycle, and matrix elements of any two half rows can be accessed. Hereinafter, the two ports of the F / D holding memory 34 may be represented by "y" and "z". In addition, data in the left half storage area of ​​the F / D holding memory 34 may be represented by "l", and data in the right half storage area may be represented by "r".

[0148] D I The holding memory 35 stores the diagonal elements of the distance matrix D used to calculate ΔC. I By using the holding memory 35, d for calculating comp in equation (20) φ(a),φ(b) In parallel with the process of reading or generating φ(a),φ(a) , d φ(b),φ(b) can be read out, and ΔC can be calculated quickly.

[0149] When the F / D matrix element generation circuit 36 ​​also generates the diagonal elements of the distance matrix D, D I The retention memory 35 may be omitted. ISince the holding memory 35 only stores the diagonal elements, the increase in memory capacity required is small.

[0150] Each memory other than the F / D holding memory 34 can also be realized using, for example, a dual port SRAM, etc. Also, each memory may have a switch so that data can be stored in the appropriate location.

[0151] Under the control of the controller 30, the F / D matrix element generation circuit 36 ​​supplies one of the matrix elements of the flow matrix F or the distance matrix D stored in the F / D holding memory 34 to the ΔC calculation circuit 37 and the local field update circuit 40. Furthermore, under the control of the controller 30, the F / D matrix element generation circuit 36 ​​generates the other of the matrix elements of the flow matrix F or the distance matrix D that are not stored in the F / D holding memory 34. Then, the F / D matrix element generation circuit 36 ​​supplies the generated matrix elements to the ΔC calculation circuit 37 and the local field update circuit 40.

[0152] The ΔC calculation circuit 37 calculates ΔC due to the allocation replacement or rearrangement. The constraint violation detection circuit 39 reads the sizes of the first and second elements from the element size holding memory 32, and the unused capacity of their allocation destinations from the unused capacity holding memory 33. The constraint violation detection circuit 39 then detects whether or not a constraint violation resulting in capacity overrun occurs when the allocation destinations of the first and second elements are swapped. The constraint violation detection circuit 39 may also update the unused capacity of each allocation destination when the allocation destinations of the first and second elements are swapped.

[0153] The allocation change permission determination circuit 38 inputs ΔC and θ shown in equation (34) and determines whether or not to permit the allocation change according to equation (35). Note that if the constraint violation detection circuit 39 detects a constraint violation, the allocation change is not permitted.

[0154] When an allocation change is permitted, the local field update circuit 40 updates the cache matrix H including n×m local fields according to equation (27) or equation (28). The selection circuit 41 selects the local field used when the ΔC calculation circuit 37 calculates ΔC based on the equation (23) or (24), and supplies it to the ΔC calculation circuit 37.

[0155] (An example of the F / D matrix element generation circuit 36) FIG. 8 is a diagram illustrating an example of an F / D matrix element generating circuit. The F / D matrix element generation circuit 36 ​​includes a first matrix element generation circuit 36a and a second matrix element generation circuit 36b.

[0156] The first matrix element generation circuit 36a includes selection circuits 36a1 and 36a2, and a decoder 36a3. The selection circuit 36a1 selects and outputs the matrix element in the j column from among the matrix elements in the i row of the flow matrix F or the distance matrix D read out from the left or right half storage area of ​​the F / D holding memory 34. j is specified by the controller 30.

[0157] The selection circuit 36a2 selects and outputs either 0, α, β, or the output of the selection circuit 36a1 in response to a selection signal generated by the decoder 36a3. For example, α=1, β=-1. The matrix elements output by the selection circuit 36a2 are represented as F / D[l / r][i,j].

[0158] The decoder 36a3 receives the identification numbers a, b of the first and second elements to be replaced and the identification numbers φ(a), φ(b) of their allocation destinations from the controller 30. The decoder 36a3 further receives from the controller 30 the row number i, column number j to be read out in the flow matrix F or distance matrix D, information l / r indicating whether the storage area is in the left half or right half of the F / D holding memory 34, and a control signal control.

[0159] Then, the decoder 36a3 generates a selection signal for the selection circuit 36a2 based on the received information or signal. When the selection circuit 36a2 is to output one of the matrix elements of the flow matrix F or the distance matrix D stored in the F / D holding memory 34, the decoder 36a3 generates a selection signal for the selection circuit 36a2 to select the output of the selection circuit 36a1. When the other matrix element of the flow matrix F or the distance matrix D not stored in the F / D holding memory 34 is to be generated, the decoder 36a3 generates a selection signal for the selection circuit 36a2 to select one of the values ​​0, α, or β. A specific process procedure for generating matrix elements according to an assignment problem will be described later (see FIG. 18).

[0160] Although not shown in the figure, the second matrix element generation circuit 36b is realized by a configuration similar to that of the first matrix element generation circuit 36a. However, in the second matrix element generation circuit 36b, k is used instead of i. Therefore, the matrix elements output by the second matrix element generation circuit 36b are expressed as F / D[l / r][k,j].

[0161] The first matrix element generation circuit 36a calculates f in the formula (20) based on the matrix elements read from the port y of the F / D holding memory 34. a,b When outputting, the second matrix element generating circuit 36b outputs d φ(a),φ(b) The first matrix element generating circuit 36a generates d φ(a),φ(b) When generating f in equation (20), the second matrix element generation circuit 36b calculates f in equation (20) based on the matrix elements read from the port z of the F / D holding memory 34. a,b may be output.

[0162] The F / D matrix element generating circuit 12b1 shown in FIG. 4 can also be realized by a circuit configuration as shown in FIG. (An example of ΔC calculation circuit 37) FIG. 9 is a diagram illustrating an example of a ΔC calculation circuit.

[0163] The ΔC calculation circuit 37 includes selection circuits 37a1, 37a2, and 37a3, addition circuits 37b1, 37b2, 37b3, and 37b4, a subtraction circuit 37c, a 1-bit left shift circuit 37d, an inverter circuit 37e, and a DSP 37f.

[0164] The selection circuit 37a1 reads out the local field holding memory 31 and selects h a,φ(b) or 0 is selected and output based on the flag value "EX?". "EX?" is 1 when calculating ΔC due to an allocation change in which the first element and the second element are swapped, and is 0 when calculating ΔC due to an allocation change of rearrangement.

[0165] When "EX?"=1, the selection circuit 37a1 selects a,φ(b) If “EX?”=0, select and output 0. The selection circuit 37a2 reads out the local field holding memory 31 and selects h b,φ(b) The selection circuit 37a2 selects and outputs either one of "EX?" and "0" based on the flag value "EX?". b,φ(b) If “EX?”=0, select and output 0.

[0166] The adder circuit 37b1 reads out the local field storage memory 31 and selects h b,φ(a) and outputs the sum of the outputs of the selection circuit 37a1. The adder circuit 37b2 reads out the local field storage memory 31 and selects h a,φ(a) Then, the addition circuit 37a1 outputs the sum of the outputs of the selection circuit 37a2.

[0167] The subtraction circuit 37c outputs the result of subtracting the addition result output by the addition circuit 37b2 from the addition result output by the addition circuit 37b1. The 1-bit left shift circuit 37d shifts the d φ(a),φ(b) Shift the number 1 bit to the left and output the result. φ(a),φ(b) The result of shifting it left by one bit is 2dφ(a),φ(b) is equivalent to.

[0168] The adder circuit 37b3 is D I d read from the holding memory 35 φ(a),φ(a) and d φ(b),φ(b) The sum of the two is output. The inverter circuit 37e is φ(a),φ(a) and d φ(b),φ(b) The sign of the sum of the two is inverted and the result is output.

[0169] The DSP 37f receives the output of the 1-bit left shift circuit 37d (2d φ(a),φ(b) ) and the f generated or output by the F / D matrix element generating circuit 36 a,b and the product of the output of the inverter circuit 37e and f a,b Then, the DSP37f calculates the product of the two products (f a,b (2d φ(a),φ(b) -d φ(a),φ(a) -d φ(b),φ(b) )).

[0170] The selection circuit 37a3 selects and outputs either the calculation result of the DSP 37f or 0 based on the flag value "EX?". When "EX?"=1, the selection circuit 37a3 selects and outputs the calculation result of the DSP 37f, and when "EX?"=0, the selection circuit 37a3 selects and outputs 0.

[0171] The adder circuit 37b4 outputs ΔC which is the sum of the subtraction result output by the subtracter circuit 37c and the output of the selection circuit 37a3. The ΔC calculation circuit 12b2 shown in FIG. 4 can also be realized by a circuit configuration as shown in FIG.

[0172] (An example of the allocation change determination circuit 38) FIG. 10 is a diagram illustrating an example of an allocation change permission determination circuit. The allocation change permission determination circuit 38 includes an adder circuit 38a, a comparator circuit 38b, an inverter circuit 38c, and an AND (logical product) circuit 38d.

[0173] The adder circuit 38 a outputs the result of adding θ supplied from the MCU 22 and ΔC calculated by the ΔC calculation circuit 37 . The comparator circuit 38b outputs 1 when the sum output by the adder circuit 38a is smaller than 0, and outputs 0 when the sum output by the adder circuit 38a is 0 or greater.

[0174] The inverter circuit 38c inverts the value of the flag value "violated?", which is 1 or 0 and is output by the constraint violation detection circuit 39, to 0 or 1. When a constraint violation occurs, the value of "violated?" is 1, and when a constraint violation does not occur, the value of "violated?" is 0.

[0175] The AND circuit 38d outputs the logical product of the output of the inverter circuit 38c and the comparison result of the comparator circuit 38b as a flag value "accept?". "accept?"=1 indicates that the allocation change is permitted, and "accept?"=0 indicates that the allocation change is not permitted.

[0176] It should be noted that ΔC input to the allocation change permission determination circuit 38 is output as is and supplied to the controller 30. The allocation change permission determination circuit 12b4 shown in FIG. 4 can also be realized by a circuit configuration as shown in FIG.

[0177] (An example of the constraint violation detection circuit 39) FIG. 11 is a diagram illustrating an example of a constraint violation detection circuit. The constraint violation detection circuit 39 includes selection circuits 39a1 and 39a2, subtraction circuits 39b1 and 39b2, an addition circuit 39c, comparison circuits 39d1 and 39d2, and an OR (logical sum) circuit 39e.

[0178] The selection circuit 39a1 selects s ​​read from the element size storage memory 32. b The selection circuit 39a1 selects and outputs either (the size of the element with the identification number b) or 0 based on the flag value "EX?". When "EX?"=1, the selection circuit 39a1 selects and outputs s b If “EX?”=0, select and output 0.

[0179] The subtraction circuit 39b1 calculates s read from the element size storage memory 32. a The output of the selection circuit 39a1 is subtracted from (identification number=size of element a) and the result is output. The subtraction circuit 39b2 subtracts the current unused capacity U t φ(a) The subtraction result of the subtraction circuit 39b1 is subtracted from the updated unused capacity U t+1 φ(a) It is.

[0180] The adder circuit 39c calculates the current unused capacity U of the allocation destination φ(b) read from the unused capacity holding memory 33. t φ(b) The subtraction circuit 39b1 adds the subtraction result to the updated unused capacity U t+1 φ(b) It is.

[0181] The comparator circuit 39d1 outputs 1 when the subtraction result output by the subtractor circuit 39b2 is smaller than 0, and outputs 0 when the subtraction result is 0 or greater. The comparator circuit 39d2 outputs 1 when the sum output by the adder circuit 39c is smaller than 0, and outputs 0 when the sum is equal to or greater than 0.

[0182] The OR circuit 39e outputs the logical sum of the comparison results of the comparison circuits 39d1 and 39d2. Selection circuit 39a2 selects and outputs either the output of OR circuit 39e or 0 based on the flag value "constrained?" of 1 or 0. The flag value "constrained?" becomes 1 when searching for a solution to an allocation problem in which the allocation destination has a capacity limit. When "constrained?"=1, selection circuit 39a2 selects and outputs the output of OR circuit 39e, and when "constrained?"=0, selection circuit 39a2 selects and outputs 0 as the flag value "violated?".

[0183] The constraint violation detection circuit 39 detects the calculated U t+1 φ(a) and U t+1 φ(b) Also outputs. The constraint violation detection circuit 12b3 shown in FIG. 4 can also be realized by a circuit configuration as shown in FIG.

[0184] (An example of the local field update circuit 40) FIG. 12 is a diagram illustrating an example of a local field update circuit. The local field update circuit 40 includes a difference matrix generation circuit 40a, a register 40b, a selection circuit 40c, a subtraction circuit 40d, a multiplication circuit 40e, and an addition circuit 40f.

[0185] The difference matrix generating circuit 40a generates ΔF or ΔD used to update the cache matrix H. FIG. 13 is a diagram illustrating an example of a difference matrix generating circuit.

[0186] The difference matrix generating circuit 40a has subtraction circuits 45a1, 45a2, ..., 45am, selection circuits 45b1, 45b2, ..., 45bm, and a decoder 45c. m is the number of columns of a matrix that can be held in each of the left and right half storage areas of the F / D holding memory 34.

[0187] The subtraction circuits 45a1 to 45am receive F / D[l / r][y][:] and F / D[l / r][z][:]. F / D[l / r][y][:] is one of the matrix elements of the flow matrix F or the distance matrix D stored in the left or right half of the storage area of ​​the F / D holding memory 34 that is read out from port y. F / D[l / r][z][:] is one of the matrix elements of the flow matrix F or the distance matrix D stored in the left or right half of the storage area of ​​the F / D holding memory 34 that is read out from port z.

[0188] Based on the input matrix elements, the subtraction circuits 45a1 to 45am perform the difference calculation of equation (25) or equation (26) in parallel for a maximum of m pairs of matrix elements. The selection circuits 45b1, 45b2, ..., 45bm select and output 0, α, β, or one of the outputs of the subtraction circuits 45a1 to 45am in response to a selection signal generated by the decoder 45c. For example, α=1, β=-1.

[0189] The decoder 45c receives from the controller 30 the identification numbers a, b of the first and second elements to be replaced, the identification numbers φ(a), φ(b) of their allocation destinations, and a control signal control. Furthermore, the decoder 45c receives from the controller 30 information y, z indicating from which of ports y, z of the F / D holding memory 34 the matrix elements have been read. Furthermore, the decoder 45c receives from the controller 30 information l / r indicating from which of the storage areas of the left half or right half of the F / D holding memory 34 the matrix elements have been read.

[0190] Then, the decoder 45c generates selection signals for the selection circuits 45b1-45bm based on the received information or signal. When the selection circuits 45b1-45bm are to output difference calculation results based on matrix elements stored in the F / D hold memory 34, the decoder 45c causes the selection circuits 45b1-45bm to select the outputs of the subtraction circuits 45a1-45am. When the selection circuits 45b1-45bm are to output difference calculation results based on matrix elements not stored in the F / D hold memory 34, the decoder 45c causes the selection circuits 45b1-45bm to select any one of the values ​​0, α, or β.

[0191] The register 40b in FIG. 12 holds ΔF / D[l][:] which is ΔF or ΔD generated based on the matrix elements stored in the left half storage area of ​​the F / D holding memory 34.

[0192] The selection circuit 40c selects and outputs either F / D[l / r][k,j] output by the F / D matrix element generation circuit 36 ​​or 0 based on the flag value "EX?". When "EX?"=1, the selection circuit 40c selects and outputs F / D[l / r][k,j], and when "EX?"=0, the selection circuit 40c selects and outputs 0.

[0193] The subtraction circuit 40d outputs a subtraction result obtained by subtracting the output of the selection circuit 40c from F / D[l / r][i,j] output by the F / D matrix element generation circuit 36. The multiplication circuit 40e acquires ΔF / D[r][:], which is ΔF or ΔD generated based on the matrix elements stored in the right half of the storage area of the F / D holding memory 34, from the difference matrix generation circuit 40a. Then, the multiplication circuit 40e concatenates ΔF / D[r][:] and ΔF / D[l][:] held in the register 40b to obtain ΔF or ΔD. Then, the multiplication circuit 40e calculates ΔH[:] by multiplying the subtraction result of the subtraction circuit 40d by each matrix element of ΔF or ΔD.

[0194] The addition circuit 40f adds ΔH[:] to the current cache matrix H t [j,:] to output the updated cache matrix H t+1 [j,:]. The local field update circuit 12b5 shown in FIG. 4 can also be realized with a circuit configuration as shown in FIG. 12.

[0195] (An example of the processing procedure of the data processing apparatus 20) FIG. 14 is a flowchart showing an example of the processing procedure of the data processing apparatus according to the second embodiment. In FIG. 14, the overall processing flow of local search by parallel tempering based on the control of the MCU 22 is shown.

[0196] First, an initialization loop (steps S10 to S14) is performed while incrementing i one by one from i = 0 to i < M - 1. M is the number of replicas. In the case of the data processing apparatus 20 as shown in FIG. 6, M = 32.

[0197] In the initialization loop, for each replica, an initial temperature (temperature ladder) is set (T[i] ← T 0[i]) is performed (step S11). The MCU 22 generates and supplies θ based on mutually different initial temperatures to each of the replica circuits 21a1 to 21a32. Also, in the initialization loop, identification number setting (rid[i] ← i) is performed for each replica (step S12). Then, the replica initialization process (see FIG. 15) described later is performed (step S13).

[0198] Next, the search replica loop (steps S15 to S17) is performed while incrementing i one by one from i = 0 to i < M - 1. In the search replica loop, search processing for the solution of the assignment problem is performed by changing the assignment by swapping the elements (step S16). In the search processing, each of the replica circuits 21a1 to 21a32 performs local search a predetermined number of times using the set θ.

[0199] Thereafter, the MCU 22 performs replica exchange processing based on the above-described formula (43) (step S18). In the process of step S18, the MCU 22 further updates θ based on the value of the changed temperature parameter and supplies it to the replica circuits 21a1 to 21a32.

[0200] Next, the search replica loop (steps S19 to S21) is performed again while incrementing i one by one from i = 0 to i < M - 1. In this search replica loop, search processing for the solution of the assignment problem is performed by changing the assignment by the above-described rearrangement (step S20). In the search processing, each of the replica circuits 21a1 to 21a32 performs local search a predetermined number of times using the set θ.

[0201] Thereafter, the MCU 22 performs replica exchange processing based on the above-described formula (43) (step S22). In the process of step S22, the MCU 22 further updates θ based on the value of the changed temperature parameter and supplies it to the replica circuits 21a1 to 21a32.

[0202] After that, the MCU 22 determines whether to end the search (step S23). For example, the MCU 22 determines whether to end the search by using a preset BKS (Best Known Solution) cost (C BKS ) or C target If it is found or the timeout limit is reached, it is determined that the search is complete and the search ends. If it is determined that the search should not be completed, the process repeats from step S15.

[0203] When the search is completed, the data processing device 20 outputs the search results (for example, the C min The smallest value of and its corresponding φ min ) may be output via the interface circuit 23. The search results may be displayed on a display device connected to the data processing device 20, for example.

[0204] Although FIG. 14 shows an example in which the initialization loop and the search replica loop are processed in order for each replica, the processes can be executed in parallel by, for example, 32 replica circuits 21a1 to 21a32.

[0205] Next, an example of the procedure for initializing the replica in step S13 will be described. FIG. 15 is a flowchart of an example of a procedure for replica initialization processing. First, the MCU 22 initializes the integer allocation vector φ (step S30). In the process of step S30, the MCU 22 randomly determines an allocation destination of the element (a knapsack in QMKP), for example.

[0206] Then, the MCU 22 calculates the initial cost (C) by the calculation of the formula (1) (step S31). The initial cost is stored in the memory in the controller 30 of each of the replica circuits 21a1 to 21a32.

[0207] Moreover, the MCU 22 calculates an initial value (initial local field) of the local field included in the cache matrix H as expressed by the formula (22) (step S32). The initial local field is stored in the local field holding memory 31 of each of the replica circuits 21a1 to 21a32.

[0208] Furthermore, the MCU 22 calculates an initial value (initial unused capacity) of the unused capacity (U) as expressed by equation (13) (step S33). The initial unused capacity is stored in the unused capacity holding memory 33 of each of the replica circuits 21a1 to 21a32.

[0209] In addition, the MCU 22 calculates the minimum value (C min and φ min ) is initialized (step S34). min and φ min are stored in the memory in the controller 30 of each of the replica circuits 21a1 to 21a32.

[0210] Furthermore, the MCU 22 initializes the elements that are candidates for allocation change (step S35). In the process of step S35, the identification numbers=a, b (a, b for replacement) of the allocation candidates when performing an allocation change that replaces the allocation destination are initialized. In the process of step S35, the identification numbers=a, b (a, b for rearrangement) of the allocation candidates when performing an allocation change by rearrangement are initialized. The initialized identification numbers of the allocation candidates are set in the controllers 30 of each of the replica circuits 21a1 to 21a32.

[0211] The MCU 22 also stores the flow matrix F or the distance matrix D, and the size of each element in the memories (F / D holding memory 34, D I The element size is stored in the element size holding memory 35 and the element size holding memory 32).

[0212] Then, the process returns to the flowchart shown in FIG. FIG. 16 is a flowchart illustrating an example of a procedure for a search process (replacement). In the exploration process (swap), the iteration loop (Steps S40 to S54) is performed while incrementing i by one at a time from i = 1 to i < I.

[0213] First, the controller 30 selects two elements (represented by identification numbers = a, b) that are candidates for swapping the assignment destination (Step S41). The ΔC calculation circuit 37 calculates ΔC when the assignment destinations of the two selected elements are swapped (Step S42). ΔC when the assignment destinations of the two elements are swapped is represented by Equation (23).

[0214] The constraint violation detection circuit 39 calculates ΔS due to the swap of the assignment destination (Step S43). ΔS due to the swap of the assignment destination is represented by Equation (29). Also, the constraint violation detection circuit 39 calculates U t+1 Φ(a) 、U t+1 Φ(b) を計算する(ステップS44)。U t+1 Φ(a) 、U t+1 Φ(b) は、式(31),(32)で表される。

[0215] The constraint violation detection circuit 39 determines whether the constraint conditions are satisfied (Step S45). The determination of whether the constraint conditions are satisfied is made based on Equation (33). If it is determined that the constraint conditions are satisfied, the process of Step S46 is performed.

[0216] In the process of Step S46, the assignment change permission determination circuit 38 performs the calculation of the assignment change permission determination. Then, the assignment change permission determination circuit 38 determines whether to allow the assignment change (Step S47). If it is determined to allow the assignment change, the process of Step S48 is performed.

[0217] In the process of Step S48, the local field update circuit 40 updates the cache matrix H. The update of the cache matrix H when the assignment destinations of the two elements are swapped is performed based on Equation (27).

[0218] Also, the controller 30 updates the value of the evaluation function (step S49). The update of the value of the evaluation function is performed by adding ΔC to the original value of the evaluation function (C). Also, the constraint violation detection circuit 39 calculates U in the process of step S44 t+1 Φ(a) , U t+1 Φ(b) by, and updates U Φ(a) , U Φ(b) (step S50). Further, the controller 30 updates the allocation state by swapping the destinations (φ(a), φ(b) ← φ(b), φ(a)) (step S51).

[0219] After that, the controller 30 determines whether C < C min (step S52). If it is determined that C < C min , the minimum value is updated (C min ← C, φ min ← φ) (step S53).

[0220] After the process of step S53, the process from step S41 is repeated until i = I. If it is determined in the process of step S45 that the constraint condition is not satisfied, if it is determined in the process of step S47 that the assignment change is not allowed, or if it is determined in the process of step S52 that C < C min is not true, the same applies. When i = I, the process returns to the flowchart shown in FIG. 14

[0221] FIG. 17 is a flowchart showing an example of the procedure of the search process (relocation). Also in the search process (relocation), an iteration loop (steps S60 to S74) is performed while incrementing i one by one from i = 1 to i < I

[0222] First, the controller 30 selects two elements (represented by identification numbers = a, b) that are candidates for relocation (step S61). The ΔC calculation circuit 37 calculates ΔC when the element with the identification number=b is arranged (assigned) to φ(a) (step S62). ΔC when the element with the identification number=b is arranged to φ(a) is expressed by the formula (24).

[0223] The constraint violation detection circuit 39 calculates ΔS due to the replacement of the allocation destinations (step S63). ΔS due to the rearrangement is expressed by the formula (30). The processing of steps S64 to S67 is the same as the processing of steps S44 to S47 in FIG.

[0224] In the process of step S68, the local field update circuit 40 updates the cache matrix H. The update of the cache matrix H by rearrangement is performed based on equation (28). The processes of steps S69 and S70 are the same as the processes of steps S49 and S50 in FIG.

[0225] The controller 30 updates the allocation state due to the rearrangement (φ(a)←b) (step S71). The processes of steps S72 and S73 are the same as the processes of steps S52 and S53 in FIG.

[0226] After the process of step S73, the process from step S61 is repeated until i=I. If it is determined in the process of step S65 that the constraint condition is not satisfied, if it is determined in the process of step S67 that the allocation change is not permitted, or if C <C min The same applies if it is determined that i=I. If i=I, the process returns to the flowchart shown in FIG.

[0227] FIG. 18 is a flowchart illustrating an example of a procedure for generating F / D matrix elements. 8, the decoder 36a3 of the F / D matrix element generation circuit 36 ​​judges whether or not the mode is the bypass mode based on the control signal "control" received from the controller 30 (step S80). If the decoder 36a3 judges that the mode is the bypass mode, it performs the process of step S81, and if it judges that the mode is not the bypass mode, it performs the process of step S94.

[0228] In the process of step S81, the decoder 36a3 determines whether the type of the assignment problem is QMKP or not based on the control signal "control." If the decoder 36a3 determines that the type of the problem is QMKP, it performs the process of step S82, and if it determines that the type of the problem is not QMKP, it performs the process of step S86.

[0229] In the process of step S82, the decoder 36a3 judges whether or not a matrix element other than the m-th row of the distance matrix D is requested from the received φ(a) and φ(b). m=k+1 (k is the number of knapsacks) and is the identification number of the dummy knapsack. When φ(a)=m or φ(b)=m, the decoder 36a3 judges that a matrix element in the m-th row of the distance matrix D is requested. Note that the distance matrix D in QMKP can be expressed, for example, as shown in FIG. 5(A).

[0230] If the decoder 36a3 determines that a matrix element other than the m-th row of the distance matrix D is requested, it performs processing of step S83, and if it determines that the matrix element of the m-th row is requested, it performs processing of step S85.

[0231] In the process of step S83, the decoder 36a3 determines whether the row address and column address of the requested matrix element are the same from the received φ(a) and φ(b). If φ(a)=φ(b), the decoder 36a3 determines that the row address and column address are the same.

[0232] If the decoder 36a3 determines that the row address and the column address are the same, it performs the process of step S84, otherwise it performs the process of step S85. In the process of step S84, the decoder 36a3 causes the selection circuit 36a2 to select and output 1. In the process of step S85, the decoder 36a3 causes the selection circuit 36a2 to select and output 0.

[0233] In the process of step S86, the decoder 36a3 determines whether the type of the assignment problem is TSP or not based on the control signal "control." If the decoder 36a3 determines that the type of the problem is TSP, it performs the process of step S87, and if it determines that the type of the problem is not TSP, it performs the process of step S90.

[0234] In the process of step S87, the decoder 36a3 obtains row addresses and column addresses of the matrix elements of the requested flow matrix F from the controller 30. In the case of a matrix with m rows and m columns, the row addresses and column addresses are specified as 0 to m-1. The decoder 36a3 determines whether or not the remainder when the address of the column address+1 is divided by the number of facilities=N is equal to the row address, or whether or not the remainder when the address of the row address+1 is divided by N is equal to the column address. The flow matrix F in the TSP can be expressed, for example, as shown in FIG. 5(B).

[0235] If the decoder 36a3 determines that the remainder when the address of the column address+1 is divided by N is equal to the row address, or if the decoder 36a3 determines that the remainder when the address of the row address+1 is divided by N is equal to the column address, the decoder 36a3 performs the process of step S88. Otherwise, the decoder 36a3 performs the process of step S89.

[0236] In the process of step S88, the decoder 36a3 causes the selection circuit 36a2 to select and output 1. In the process of step S89, the decoder 36a3 causes the selection circuit 36a2 to select and output 0.

[0237] In the process of step S90, the decoder 36a3 determines whether the type of the assignment problem is LOP or not based on the control signal "control." If the decoder 36a3 determines that the type of the problem is LOP, it performs the process of step S91, and if it determines that the type of the problem is not LOP, it performs the process of step S94.

[0238] In the process of step S91, the decoder 36a3 judges whether or not the column address of the matrix element of the requested distance matrix D is larger than the row address from the received φ(a) and φ(b). Note that the distance matrix D in the LOP can be expressed, for example, as shown in FIG. 5(C).

[0239] If the decoder 36a3 determines that the column address is greater than the row address, it performs the process of step S92. Otherwise, the decoder 36a3 performs the process of step S93.

[0240] In the process of step S92, the decoder 36a3 causes the selection circuit 36a2 to select and output 1. In the process of step S93, the decoder 36a3 causes the selection circuit 36a2 to select and output 0.

[0241] In the process of step S94, the decoder 36a3 does not generate matrix elements, but causes the selection circuit 36a2 to select and output the data (matrix elements) read out from the F / D holding memory 34.

[0242] After the processes of steps S84, S85, S88, S89, S92, S93, and S94, the process by the decoder 36a3 ends. As for the decoder 45c included in the difference matrix generating circuit 40a of the local field updating circuit 40 shown in FIG. 13, the differences between matrix elements can be generated by appropriately modifying the process shown in FIG.

[0243] Although the above describes examples of generating matrix elements for QMKP, TSP, and LOP, applicable types of assignment problems are not limited to these. Moreover, the order of the processes shown in FIGS. 14 to 18 is just an example, and the order of the processes may be changed as appropriate.

[0244] For example, the process of calculating ΔC in step S42 in FIG. 16 may be performed between the processes of steps S45 and S46. In this case, if it is determined that the constraint condition is not satisfied, the calculation of ΔC is skipped. If the constraint condition is not satisfied, the calculation of ΔC is not necessary. By skipping the calculation of ΔC, which has a high calculation load, the processing time can be shortened. Similarly, the process of calculating ΔC in step S62 in FIG. 17 may be performed between the processes of steps S65 and S66.

[0245] As described above, in the data processing device 20 of the second embodiment, among the flow matrix F or the distance matrix D as described above, the matrix elements of the patterned matrix are generated and used for calculating ΔC and updating the local field. This eliminates the need to store the flow matrix F or the distance matrix D in the F / D holding memory 34, thereby reducing the memory capacity used.

[0246] For example, if the data size of one matrix element in a 128x128 distance matrix D is 4 bytes, the data size of distance matrix D is 4x128. 2 = 64KB. If the number of replicas is 32, the total memory usage can be reduced by 64KB x 32 = 2MB.

[0247] Furthermore, since the memory capacity required to store the distance matrix D or the flow matrix F can be reduced in this manner, it becomes possible to handle larger problems with the same memory size. (Third embodiment) The data processing devices 10 and 20 according to the first and second embodiments have local field storage memories 11b and 31 in order to calculate ΔC using the local field. However, to further reduce the memory usage, they may be configured to calculate ΔC without using the local field.

[0248] Fig. 19 is a diagram illustrating an example of a replica circuit in a data processing device according to the third embodiment. Note that in Fig. 19, elements that perform processing related to constraint conditions, such as an element size holding memory 32 and an unused capacity holding memory 33, are omitted from the illustration.

[0249] In the following, for the sake of simplicity, it is assumed that both the flow matrix and the distance matrix are symmetric (diagonal elements are 0 (biasless)). As mentioned above, such QAPs are the majority of instances, and this is to simplify the calculation. A QAP using a symmetric matrix can be directly converted into a QAP using an asymmetric matrix.

[0250] The evaluation function of QAP using only symmetric matrices can be expressed as shown in the following equation (44).

[0251]

number

[0252] When the evaluation function expressed by equation (44) is used, ΔC used in calculating the QAP can be expressed by the following equations (45) and (46).

[0253]

number

[0254]

number

[0255] D in Equation (46) X More on this later. The replica circuit 50 includes a flow matrix memory 51a, a state-ordered D matrix memory 51b, difference calculation circuits 52a and 52b, multiplexers 53a, 53b1, and 53b2, an inner product calculation circuit 54, a register 55, a multiplication circuit 56, an addition circuit 57, and a selection circuit 58.

[0256] The flow matrix memory 51a stores the flow matrix F. The state alignment D matrix memory 51b stores the state alignment D matrix (D X ) is memorized. D Xis a permutation of columns according to the current allocation state to minimize the computational cost of generating ΔD with the appropriate matrix element order. For example, in the case of QAP, D X is the transposed matrix X of the binary state matrix X that represents the current allocation state. T can be expressed by multiplying by the original distance matrix D.

[0257] Such a D X By using this, ΔD can be calculated without rearranging the matrix elements. In the example of FIG. 19, the flow matrix memory 51a and the state-ordered D matrix memory 51b are dual-port memories having two ports.

[0258] The difference calculation circuit 52a calculates Δ b a Calculate F. The difference calculation circuit 52b calculates D φ(a),* , D φ(b),* Instead of D X φ(a),* , D X φ(b),* By using Δ φ(a) φ(b) D X Calculate.

[0259] The multiplexer 53a is F a,* From f a,b Select and output. Multiplexers 53b1 and 53b2 are D X φ(a),* From d φ(a),b Select and output.

[0260] The inner product calculation circuit 54 calculates Δ b a F and Δ φ(a) φ(b) D X The inner product calculation circuit 54 can be realized, for example, by a plurality of multipliers connected in parallel. The register 55 holds the coefficient "2".

[0261] The multiplication circuit 56 is 2f a,b d φ(a),b Calculate. The adder circuit 57 multiplies the result of the inner product by 2f a,b d φ(a),b Calculate and output ΔC by adding

[0262] The selection circuit 58 selects the distance matrix D supplied from the MCU 22 and the d φ(a),b and supplies it to the state sorting D matrix memory 51b. In such a configuration, when a replacement (allocation change) of the allocation destination of the element that generates ΔC is proposed and accepted, the columns of the state alignment matrix D are rearranged so as to correspond to the accepted allocation state. The rearrangement can be performed, for example, by using a switch (not shown).

[0263] For example, the multiplexer 53b1 sequentially selects and outputs the first column value of each row of the state alignment D matrix read from the state alignment D matrix memory 51b for replacement. The multiplexer 53b2 sequentially selects and outputs the second column value of each row of the state alignment D matrix read from the state alignment D matrix memory 51b.

[0264] The switch writes the value output from the multiplexer 53b1 in the state-ordered D-matrix memory 51b by switching the memory locations so that the value output from the multiplexer 53b2 is stored in the location where the value output from the multiplexer 53b1 was stored. Also, the switch writes the value output from the multiplexer 53b2 in the state-ordered D-matrix memory 51b by switching the memory locations so that the value output from the multiplexer 53b2 is stored in the location where the value output from the multiplexer 53b1 was stored.

[0265] In the replica circuit 50 described above, by applying the F / D matrix element generation circuit 36 ​​shown in FIG. 8 as the multiplexers 53a, 53b1, and 53b2, it is possible to generate matrix elements used in the calculation of ΔC. Also, by applying the difference matrix generation circuit 40a shown in FIG. 12 as the difference calculation circuits 52a and 52b, it is possible to generate the differences of the matrix elements used in the calculation of ΔC. As a result, the flow matrix F or the distance matrix D (or D X ) does not need to be held in memory, further reducing memory usage.

[0266] Incidentally, the processing contents of the data processing device of each of the above-mentioned embodiments (eg, FIGS. 14 to 18) can also be realized by software by making a computer execute a program.

[0267] The program may be recorded on a computer-readable recording medium. For example, a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory may be used as the recording medium. Magnetic disks include flexible disks (FDs) and HDDs. Optical disks include compact discs (CDs), recordable CD-Rs (recordable) / rewritable RWs (rewritable), digital versatile discs (DVDs) and DVD-Rs / RWs. The program may be recorded on a portable recording medium and distributed. In that case, the program may be copied from the portable recording medium to another recording medium and executed.

[0268] FIG. 20 is a diagram illustrating an example of hardware of a computer, which is an example of a data processing device. The computer 60 includes a processor 61, a RAM 62, a HDD 63, a GPU 64, an input interface 65, a media reader 66, and a communication interface 67. The above units are connected to a bus.

[0269] The processor 61 is a processor including an arithmetic circuit that executes program instructions. The processor 61 is, for example, a CPU, a GPU, or a DSP. The processor 61 loads at least a part of the program and data stored in the HDD 63 into the RAM 62 and executes the program. The processor 61 may include multiple processor cores in order to execute the processes of the multiple replica circuits 21a1 to 21a32 in parallel, as shown in FIG. 6. The computer 60 may include multiple processors. A set of multiple processors (multiprocessor) may be called a "processor."

[0270] The RAM 62 is a volatile semiconductor memory that temporarily stores programs executed by the processor 61 and data used in calculations by the processor 61. Note that the computer 60 may include a type of memory other than the RAM 62, or may include multiple memories.

[0271] The HDD 63 is a non-volatile storage device that stores software programs such as an OS (Operating System), middleware, and application software, as well as data. The programs include, for example, a program that causes the computer 60 to execute a process for searching for a solution to the assignment problem as described above. The computer 60 may be provided with other types of storage devices such as a flash memory or an SSD (Solid State Drive), or may be provided with multiple non-volatile storage devices.

[0272] The GPU 64 outputs an image (for example, an image showing a calculation result of an assignment problem) to a display 64a connected to the computer 60 in accordance with an instruction from the processor 61. As the display 64a, a CRT (Cathode Ray Tube) display, a liquid crystal display (LCD: Liquid Crystal Display), a plasma display (PDP: Plasma Display Panel), an organic EL (OEL: Organic Electro-Luminescence) display, or the like can be used.

[0273] The input interface 65 acquires an input signal from an input device 65a connected to the computer 60 and outputs it to the processor 61. As the input device 65a, a pointing device such as a mouse, a touch panel, a touch pad, or a trackball, a keyboard, a remote controller, a button switch, etc. may be used. In addition, a plurality of types of input devices may be connected to the computer 60.

[0274] The medium reader 66 is a reading device that reads programs and data recorded on a recording medium 66a. For example, a magnetic disk, an optical disk, a magneto-optical disk (MO: Magneto-Optical disk), a semiconductor memory, etc. can be used as the recording medium 66a. Magnetic disks include FDs and HDDs. Optical disks include CDs and DVDs.

[0275] The medium reader 66 copies the program and data read from the recording medium 66a to another recording medium such as the RAM 62 or the HDD 63. The read program is executed by the processor 61, for example. The recording medium 66a may be a portable recording medium, and may be used for distributing the program and data. The recording medium 66a and the HDD 63 may also be referred to as computer-readable recording media.

[0276] The communication interface 67 is an interface that is connected to a network 67a and communicates with other information processing devices via the network 67a. The communication interface 67 may be a wired communication interface that is connected to a communication device such as a switch by a cable, or may be a wireless communication interface that is connected to a base station by a wireless link.

[0277] While one aspect of the data processing device, the program, and the data processing method of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0278] 10 Data Processing Device 11 Storage section 11a F / D retention memory 11b Local Field Retention Memory 11c Element size retention memory 11d Unused capacity retention memory 12 Processing section 12a Controller 12b Circuit section 12b1 F / D matrix element generation circuit 12b2 ΔC calculation circuit 12b3 Constraint violation detection circuit 12b4 Assignment change decision circuit 12b5 Local Field Update Circuit 12b6 Selection circuit

Claims

1. a storage unit for storing one of a flow matrix and a distance matrix for an assignment problem having an evaluation function expressed using a matrix operation of the flow matrix and the distance matrix; a processing unit that selects a first element and a second element from among a plurality of elements allocated to a plurality of allocation destinations, reads out from the storage unit first matrix elements of one of the flow matrix and the distance matrix corresponding to the first element and the second element, generates a second matrix element of a patterned matrix that is the other of the flow matrix and the distance matrix based on the first element and the second element, calculates an amount of change in a value of the evaluation function when an allocation change occurs in which an allocation destination of the first element or the second element is changed, and determines whether or not to allow the allocation change based on the amount of change, and updates an allocation state when it is determined that the allocation change is allowed; A data processing device having:

2. 2 . The data processing device according to claim 1 , wherein the second matrix elements are matrix elements used in calculating the amount of change when the allocation change occurs by swapping the allocation destinations of the first elements and the second elements.

3. 2 . The data processing apparatus according to claim 1 , wherein the second matrix elements are matrix elements used in calculating the amount of change when the allocation change occurs by allocating the second elements to the first allocation destinations of the first elements.

4. the storage unit includes a first memory that stores one of the flow matrix and the distance matrix, and a second memory that stores diagonal elements of the distance matrix; the processing unit calculates the amount of change based on the first matrix element, the second matrix element, and a third matrix element read from the second memory.

2. A data processing apparatus according to claim 1.

5. If the assignment problem is a QMKP, the distance matrix is ​​patterned such that all but one of the diagonal elements is 1 and the other matrix elements are 0; the processing unit generates the second matrix element of the distance matrix, which is 1 or 0, based on a first allocation destination of the first element and a second allocation destination of the second element.

2. A data processing apparatus according to claim 1.

6. storing one of the flow matrix and the distance matrix in a memory for an assignment problem having an evaluation function expressed using a matrix operation of the flow matrix and the distance matrix; Selecting a first element and a second element from among a plurality of elements to be assigned to a plurality of destinations; reading from the memory a first matrix element of one of the flow matrix and the distance matrix, the first matrix element corresponding to the first element and the second element; generating a second matrix element of a patterned matrix, the other of the flow matrix and the distance matrix, based on the first element and the second element; calculating a change in a value of the evaluation function when an allocation change occurs in which an allocation destination of the first element or the second element is changed, using the first matrix element and the second matrix element; determining whether or not to permit the allocation change based on the amount of change; If it is determined that the allocation change is permitted, the allocation state is updated. A program that causes a computer to carry out processing.

7. a storage unit stores one of a flow matrix and a distance matrix for an assignment problem having an evaluation function expressed using a matrix operation of the flow matrix and the distance matrix; The processing unit: Selecting a first element and a second element from among a plurality of elements to be assigned to a plurality of destinations; reading, from the storage unit, a first matrix element of one of the flow matrix and the distance matrix, which corresponds to the first element and the second element; generating a second matrix element of a patterned matrix, the other of the flow matrix and the distance matrix, based on the first element and the second element; calculating a change in a value of the evaluation function when an allocation change occurs in which an allocation destination of the first element or the second element is changed, using the first matrix element and the second matrix element; determining whether or not to permit the allocation change based on the amount of change; If it is determined that the allocation change is permitted, the allocation state is updated. Data processing methods.

Images