Solar cell and preparation method thereof

Abstract

To provide an IBC solar cell and a preparation method thereof, the IBC solar cell being capable of realizing excellent electric contact effect between an electrode and a transport layer, thereby realizing a higher photoelectric conversion efficiency.SOLUTION: A solar cell comprises: a semiconductor substrate 10 having a first surface and a second surface that are provided opposite to each other; a positive hole transport layer 21 and an electron transport layer 40 that are disposed on the first surface at interval, a material of the positive hole transport layer 21 containing vanadium oxide, and a material of the electron transport layer 40 containing titanium oxide; a first passivation layer 22 that is positioned on a surface separated away from the semiconductor substrate 10, of the positive hole transport layer 21; and a second passivation layer 50 that covers a surface separated away from the semiconductor substrate 10, of the first passivation layer 22, a surface separated away from the semiconductor substrate 10, of the electron transport layer 40, and the first surface.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present application relates to the technical field of solar cells, and in particular to solar cells and methods for manufacturing the same. [Background technology]

[0002] Compared with emitter rear passivation cells (PERC cells) and heterojunction cells (HJT cells), interdigitated back contact solar cells (IBC solar cells) have no grid lines on their front surface, and positive and negative electrodes are fabricated on the back surface of the cell in a cross-arranged manner, which can avoid the shading loss caused by the grid lines on the front surface in the solar cell. In conventional IBC solar cells, n-type doped semiconductor regions and p-type doped semiconductor regions are formed in a staggered manner by diffusion, and holes are drilled in the dielectric layer to realize the connection by electrical contact between the electrodes and the emission regions. In the conventional IBC solar cells, the quality of the electrical contact between the electrodes and the semiconductor regions is low, which restricts further improvement of the photoelectric conversion efficiency of the IBC solar cells. Summary of the Invention

[0003] According to various embodiments of the present application, a solar cell and a method for manufacturing the same are provided.

[0004] In a first aspect, the present application provides a method for producing a method for manufacturing a semiconductor device comprising: a semiconductor substrate having a first surface and a second surface disposed opposite to each other; a hole transport layer and an electron transport layer spaced apart from each other on the first surface, the hole transport layer being made of vanadium oxide and the electron transport layer being made of titanium oxide; a first passivation layer located on a surface of the hole transport layer away from the semiconductor substrate; A solar cell is provided that comprises a surface of the first passivation layer remote from the semiconductor substrate, a surface of the electron transport layer remote from the semiconductor substrate, and a second passivation layer covering the first surface.

[0005] In some embodiments, the hole transport layer has a thickness of 20 to 30 nm.

[0006] In some embodiments, the electron transport layer has a thickness of 45 to 55 nm.

[0007] In some embodiments, the material of the first passivation layer comprises aluminum oxide.

[0008] In some embodiments, the material of the second passivation layer includes at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0009] In some embodiments, the second surface is suede.

[0010] In some embodiments, the second surface is provided with a third passivation layer.

[0011] In some embodiments, a fourth passivation layer is further provided on a surface of the third passivation layer facing away from the semiconductor substrate, the fourth passivation layer and the third passivation layer being of different materials.

[0012] In a second aspect, the present application provides a method for producing a method for manufacturing a semiconductor device comprising: providing a semiconductor substrate having opposed first and second surfaces; producing a hole transport layer and an electron transport layer spaced apart on the first surface, the hole transport layer material comprising vanadium oxide and the electron transport layer material comprising titanium oxide; producing a first passivation layer located on a surface of the hole transport layer facing away from the semiconductor substrate; There is provided a method for producing a solar cell described in any one of the above claims, comprising the step of producing a second passivation layer covering a surface of the first passivation layer facing away from the semiconductor substrate, a surface of the electron transport layer facing away from the semiconductor substrate, and the first surface.

[0013] In some embodiments, the process for preparing a hole transport layer includes: The method includes the steps of preparing the hole transport layer from a vanadium source and a first oxidant at 120-130°C using atomic layer deposition, or preparing the hole transport layer from a vanadium source and a second oxidant at 380-420°C using plasma enhanced chemical vapor deposition.

[0014] In some embodiments, the process for preparing an electron transport layer includes: The method includes the steps of preparing the electron transport layer from a titanium source and a first oxidant at 100-160°C using atomic layer deposition, or preparing the electron transport layer from a titanium source and a second oxidant at 380-420°C using plasma enhanced chemical vapor deposition.

[0015] The details of one or more embodiments of the application are set forth in the drawings and description below. Other features, objects, and advantages of the application will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0016] To better describe and explain the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings, in which additional details or examples for illustrating the drawings should not be deemed to limit the scope of the disclosed inventions, either of the presently described embodiments and / or examples, or the best modes of these inventions as currently understood. [Figure 1] FIG. 1 is a structural schematic diagram of fabricating a hole transport layer and a first passivation layer on a surface of a semiconductor substrate in one or more embodiments of the present application. [Diagram 2] FIG. 2 is a structural schematic diagram of a method for manufacturing a first mask layer and a second mask layer based on the structure shown in FIG. [Diagram 3] FIG. 3 is a schematic diagram of the structure shown in FIG. 2 from which a part of the hole transport layer and the dielectric layer have been removed. [Figure 4] FIG. 4 is a schematic diagram of the structure shown in FIG. 3 from which the first mask layer has been removed. [Diagram 5] FIG. 5 is a schematic diagram of a structure for manufacturing an electron transport layer based on the structure shown in FIG. [Figure 6]FIG. 6 is a structural schematic diagram of manufacturing a first passivation layer based on the structure shown in FIG. [Figure 7] FIG. 7 is a structural schematic diagram of manufacturing a third passivation layer and a fourth passivation layer based on the structure shown in FIG. [Figure 8] FIG. 8 is a schematic diagram of a structure for manufacturing the first electrode and the second electrode based on the structure shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In order to make the above objects, features and advantages of the present invention more clear, specific embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, many specific details will be described in order to fully understand the present invention. However, the present invention can be embodied in many ways different from those described herein, and those skilled in the art can make similar improvements without departing from the scope of the present invention, so the present invention is not limited to the specific embodiments disclosed below.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present application. The terms used in the specification of the present application herein are for the purpose of describing specific examples only and are not intended to be limiting of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] In one embodiment of the present application, there is provided a solar cell comprising: a semiconductor substrate 10 having a first surface and a second surface disposed opposite to each other; a hole transport layer 21 and an electron transport layer 40 disposed at a distance from each other on the first surface, the hole transport layer 21 being made of a material containing vanadium oxide, and the electron transport layer 40 being made of a material containing titanium oxide; a first passivation layer 22 located on the surface of the hole transport layer 21 facing away from the semiconductor substrate 10; and a second passivation layer 50 covering the surface of the first passivation layer 22 facing away from the semiconductor substrate 10, the surface of the electron transport layer 40 facing away from the semiconductor substrate 10, and the first surface.

[0020] In the above solar cell, the material of the hole transport layer 21 includes vanadium oxide, which exhibits a hole selective type state. The material of the electron transport layer 40 includes titanium oxide, which exhibits an electron selective type state. The hole transport layer 21 and the electron transport layer 40 in this application are combined with each other, and the contact barrier between them and the electrodes is small, so that the conduction effect of the photo-generated carriers can be realized. At the same time, the surface of the hole transport layer 21 is passivated by vapor deposition of two different materials, which can improve the surface contact effect between the hole transport layer 21 and the electrodes after passivation. The solar cell achieves a good electrical contact effect between the electrodes and the hole transport layer 21 and the electron transport layer 40, and further achieves a high photoelectric conversion efficiency of the IBC solar cell.

[0021] In some embodiments, the material of hole transport layer 21 is vanadium oxide.

[0022] In some embodiments, the material of the electron transport layer 40 is titanium dioxide.

[0023] In some embodiments, the thickness of the hole transport layer 21 is 20 to 30 nm. In this range of thickness of the hole transport layer 21, the film formation quality of the hole transport layer 21 is good, and the selective contact effect of the obtained battery is good. Preferably, the thickness of the hole transport layer 21 is 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm.

[0024] In some embodiments, the thickness of the electron transport layer 40 is 45 to 55 nm. In this range of thickness of the electron transport layer 40, the film formation quality of the electron transport layer 40 is good, and the selective contact effect of the obtained battery is good. Preferably, the thickness of the electron transport layer 40 is 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm, or 55 nm.

[0025] In some embodiments, the material of the first passivation layer 22 includes aluminum oxide, which has a good matching effect with the n-type semiconductor material, and can passivate the hole transport layer 21 well, thereby obtaining a solar cell with good contact effect.

[0026] In some embodiments, the material of the first passivation layer 22 is aluminum oxide.

[0027] In some embodiments, the material of the second passivation layer 50 includes at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0028] In some embodiments, the second surface is suede. It can be appreciated that the suede can be textured with different patterns. For example, the suede can be a pyramid texture.

[0029] In some embodiments, the second surface is further provided with a third passivation layer 61. Smoothing the front surface of the cell can further improve the photovoltaic performance of the solar cell.

[0030] In some embodiments, the material of the third passivation layer 61 includes at least one of aluminum oxide, silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0031] In some embodiments, a fourth passivation layer 62 is further provided on the surface of the third passivation layer 61 facing away from the semiconductor substrate 10, and the fourth passivation layer 62 and the third passivation layer 61 are made of different materials. Passivating the front side of the cell by deposition can further improve the photovoltaic performance of the solar cell.

[0032] In some embodiments, the material of the fourth passivation layer 62 includes at least one of aluminum oxide, silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0033] In some embodiments, the third passivation layer 61 and the fourth passivation layer 62 are made of different materials.

[0034] In some embodiments, the material of the semiconductor substrate 10 is an n-type single crystal silicon wafer.

[0035] In some embodiments, the solar cell further comprises a first electrode 71 located on a surface of the second passivation layer 50 facing away from the semiconductor substrate 10, covering the first passivation layer 22, and a second electrode 72 located on a surface of the second passivation layer 50 facing away from the semiconductor substrate 10, covering the electron transport layer 40.

[0036] In another embodiment of the present application, there is provided a method for manufacturing a solar cell according to any one of the above claims, comprising the steps of: providing a semiconductor substrate 10 having a first surface and a second surface disposed opposite to each other; fabricating a hole transport layer 21 and an electron transport layer 40 spaced apart from each other on the first surface, wherein the material of the hole transport layer 21 includes vanadium oxide and the material of the electron transport layer 40 includes titanium oxide; fabricating a first passivation layer 22 located on a surface of the hole transport layer 21 facing away from the semiconductor substrate 10; and fabricating a second passivation layer 50 covering the surface of the first passivation layer 22 facing away from the semiconductor substrate 10, the surface of the electron transport layer 40 facing away from the semiconductor substrate 10, and the first surface.

[0037] In some examples of the embodiment, the method for manufacturing a solar cell includes steps S100 to S500, and is specifically as follows.

[0038] S100: Providing a semiconductor substrate 10 having a first surface and a second surface disposed opposite each other.

[0039] In some embodiments, the method further includes cleaning the semiconductor substrate 10 to remove impurities on the surface of the semiconductor substrate 10 .

[0040] In some embodiments, cleaning the semiconductor substrate 10 includes cleaning the semiconductor substrate 10 with a mixture of potassium hydroxide solution and hydrogen peroxide solution.

[0041] In some embodiments, the method further includes texturing the cleaned semiconductor substrate 10 to form a suede on the surface of the semiconductor substrate 10 .

[0042] In some embodiments, texturing the cleaned semiconductor substrate 10 includes anisotropically etching the semiconductor substrate 10 with an etchant to form a pyramidal texture on the surface of the semiconductor substrate 10 .

[0043] In some embodiments, the etching solution comprises a potassium hydroxide solution.

[0044] S200: Producing a hole transport layer 21 and an electron transport layer 40 spaced apart from each other on a first surface, the material of the hole transport layer 21 including vanadium oxide, and the material of the electron transport layer 40 including titanium oxide.

[0045] In some embodiments, the step of preparing the hole transport layer 21 includes preparing the hole transport layer 21 by atomic layer deposition using a vanadium source and a first oxidant at 120-130°C. In the temperature range of the atomic layer deposition, the deposition can obtain a high film formation effect and a high density hole transport layer 21, while the low deposition temperature can reduce the destruction of the passivation stability caused by high temperature. Preferably, the temperature of the atomic layer deposition is 120°C, 121°C, 122°C, 123°C, 124°C, 125°C, 126°C, 127°C, 128°C, 129°C or 130°C. For example, the vanadium source of the atomic layer deposition includes tetraethylmethylamino vanadium (VTIP). For example, the first oxidant of the atomic layer deposition includes deionized water.

[0046] In some embodiments, the number of cycles of atomic layer deposition is 160 to 240. A hole transport layer 21 having an appropriate thickness can be obtained within the number of cycles of atomic layer deposition. Preferably, the number of cycles of atomic layer deposition is 160, 170, 180, 190, 200, 210, 220, 230, or 240.

[0047] In some embodiments, the step of preparing the hole transport layer 21 includes preparing the hole transport layer 21 by plasma enhanced chemical vapor deposition with a vanadium source and a second oxidant at 380-420°C. In the range of temperatures of the plasma enhanced chemical vapor deposition, the deposition can obtain a high film formation effect and a high density hole transport layer 21, while the low deposition temperature can reduce the destruction of the passivation stability caused by high temperatures. Preferably, the temperature of the plasma enhanced chemical vapor deposition is 380°C, 385°C, 390°C, 395°C, 400°C, 405°C, 410°C, 415°C or 420°C. For example, the vanadium source of the plasma enhanced chemical vapor deposition includes VTIP. The second oxidant of the plasma enhanced chemical vapor deposition includes N2O.

[0048] In some embodiments, preparing electron transport layer 40 includes preparing electron transport layer 40 using atomic layer deposition at 100-160° C. with a titanium source and a first oxidant.

[0049] In some embodiments, fabricating electron transport layer 40 includes fabricating electron transport layer 40 using plasma enhanced chemical vapor deposition at 380-420° C. with a titanium source and a second oxidant.

[0050] S300: A first passivation layer 22 is formed on the surface of the hole transport layer 21 facing away from the semiconductor substrate 10.

[0051] In some embodiments, referring to FIGS. 1 to 5, FIG. 1 is a structural schematic diagram of a hole transport layer 21 and a first passivation layer 22 on the surface of a semiconductor substrate 10, FIG. 2 is a structural schematic diagram of a first mask layer 31 and a second mask layer 32 based on the structure shown in FIG. 1, FIG. 3 is a structural schematic diagram of a structure in which a part of the hole transport layer 21 and a dielectric layer are removed based on the structure shown in FIG. 2, FIG. 4 is a structural schematic diagram of a structure in which the first mask layer 31 is removed based on the structure shown in FIG. 3, and FIG. 5 is a structural schematic diagram of a structure in which an electron transport layer 40 is manufactured based on the structure shown in FIG. 4, in which the hole transport layer 21, the electron transport layer 40 and The process of manufacturing the first passivation layer 22 includes the steps of manufacturing a hole transport layer 21 and a first passivation layer 22, which are sequentially stacked on the semiconductor substrate 10; manufacturing a first mask layer 31 and a second mask layer 32 on the surface of the first passivation layer 22, where the first mask layer 31 cannot be removed by a developer and the second mask layer 32 can be removed by a developer; removing the second mask layer 32 and etching the exposed first passivation layer 22 and hole transport layer 21; and removing the first mask layer 31 and manufacturing an electron transport layer 40 on the surface of the semiconductor substrate 10.

[0052] In some embodiments, the material of the first mask layer 31 comprises a photosensitive polyimide. In some embodiments, the material of the second mask layer 32 comprises a photosensitive polyimide.

[0053] S400: Fabricate a second passivation layer 50 covering the surface of the first passivation layer 22 facing away from the semiconductor substrate 10, the surface of the electron transport layer 40 facing away from the semiconductor substrate 10, and the first surface.

[0054] FIG. 6 is a structural schematic diagram of manufacturing the first passivation layer 22 based on the structure shown in FIG. 5. As shown in FIG. 6, the second passivation layer 50 covers the surface of the first passivation layer 22 facing away from the semiconductor substrate 10, the surface of the electron transport layer 40 facing away from the semiconductor substrate 10, and the first surface.

[0055] S500: Fabricate a first electrode 71 located on a surface of the second passivation layer 50 facing away from the semiconductor substrate 10, covering the first passivation layer 22, and a second electrode 72 located on a surface of the second passivation layer 50 facing away from the semiconductor substrate 10, covering the electron transport layer 40.

[0056] Fig. 8 is a structural schematic diagram of a first electrode 71 and a second electrode 72 manufactured based on the structure shown in Fig. 6. As shown in Fig. 8, the first electrode 71 is located on a surface of the second passivation layer 50 that covers the first passivation layer 22 and is away from the semiconductor substrate 10, and the second electrode 72 is located on a surface of the second passivation layer 50 that covers the electron transport layer 40 and is away from the semiconductor substrate 10.

[0057] In some embodiments, the materials of the first electrode 71 and the second electrode 72 are each independently selected from any available metal electrode in the art. For example, the material of the first electrode 71 is a silver electrode. For example, the material of the second electrode 72 includes nickel and aluminum.

[0058] In some embodiments, the method further comprises fabricating a third passivation layer 61 on the second surface.

[0059] In some embodiments, the method further comprises the step of fabricating a fourth passivation layer 62 on the surface of the third passivation layer 61 .

[0060] Fig. 7 is a structural schematic diagram of manufacturing a third passivation layer 61 and a fourth passivation layer 62 based on the structure shown in Fig. 6. As shown in Fig. 7, the third passivation layer 61 is provided on the second surface of the semiconductor substrate 10, and the fourth passivation layer 62 is provided on the surface of the third passivation layer 61 that is away from the semiconductor substrate 10.

[0061] The following is a specific example. Example 1

[0062] Next, referring to FIG. 1 to FIG. 8, the method for manufacturing a solar cell includes the following steps.

[0063] (1) The semiconductor substrate 10 is cleaned for about 90 seconds using a mixed solution of potassium hydroxide solution and hydrogen peroxide solution at 70° C. to remove impurities from the silicon wafer surface.

[0064] (2) Chain texturing is performed on the front surface of the silicon wafer using a potassium hydroxide solution and an additive at 78°C for approximately 450 seconds to form a pyramid pattern texture as an optical trapping structure on the front surface of the silicon wafer.

[0065] (3) Using an ALD machine under the condition of 120-130° C., VTIP and deionized water are adopted as precursor and oxidant, and 160-240 cycles are carried out to fabricate a vanadium oxide film with a thickness of 20-30 nm as the hole transport layer 21.

[0066] (4) At 190-210° C., using an ALD machine, employing trimethylaluminum (TMA) and deionized water as precursor and oxidant, cycle 450-550 times to produce an aluminum oxide film with a thickness of 45-55 nm as the first passivation layer 22.

[0067] (5) A patterned mask layer is manufactured using photosensitive polyimide, and a first mask layer 31 and a second mask layer 32 are obtained by a photochemical reaction, respectively, and the hole transport layer 21 and the first passivation layer 22 covering the second mask layer 32 are removed by dry etching.

[0068] (6) The first mask layer 31 is removed.

[0069] (7) At 100-160° C., using an ALD machine, titanium tetraisopropoxide and deionized water are employed as precursor and oxidant, and 225-275 cycles are performed to fabricate a titanium oxide film with a thickness of 22.5-27.5 nm as the electron transport layer 40.

[0070] (8) The second passivation layer 50 is a silicon carbide film with a deposition thickness of 20 nm, using silane and methane as the silicon source and carbon source, and H2 as the carrier gas.

[0071] (9) Using the same conditions as in step (4) and step (8), an aluminum oxide film is produced as a third passivation layer 61 and a silicon carbide film is produced as a fourth passivation layer 62 on the front side of the silicon wafer.

[0072] (10) Anneal at 380 to 420 °C for 10 minutes to activate the surface passivation.

[0073] (11) A first electrode 71 of silver and a second electrode 72 of nickel aluminum are fabricated. Example 2

[0074] In this embodiment, the method for manufacturing the solar cell is almost the same as in Example 1, except for the following points.

[0075] In step (3), a vanadium oxide film with a thickness of 20-30 nm is fabricated as the hole transport layer 21 using VTIP and N2O as precursor and oxidant in a plasma enhanced chemical vapor deposition apparatus at 400°C.

[0076] In step (7), a titanium oxide film with a thickness of 22.5 to 27.5 nm is fabricated as the electron transport layer 40 using an ALD equipment, a plasma enhanced chemical vapor deposition equipment, at 400° C., and titanium tetraisopropoxide and N2O as precursor and oxidant. Comparative Example 1

[0077] (1) The semiconductor substrate 10 is cleaned for about 90 seconds using a mixed solution of potassium hydroxide solution and hydrogen peroxide solution at 70° C. to remove impurities from the silicon wafer surface.

[0078] (2) Chain texturing is performed on the front surface of the silicon wafer using a potassium hydroxide solution and an additive at 78°C for approximately 450 seconds to form a pyramid pattern texture as an optical trapping structure on the front surface of the silicon wafer.

[0079] (3) Depositing a layer of intrinsic amorphous silicon on the backside of the silicon wafer by low pressure chemical vapor deposition at 600°C.

[0080] (4) Boron diffusion is performed at 1000° C. to form P-type polysilicon as the P area, that is, the hole transport layer 21.

[0081] (5) A patterned mask layer is manufactured using photosensitive polyimide, and a first mask layer 31 and a second mask layer 32 are obtained by a photochemical reaction, and the hole transport layer 21 covering the second mask layer 32 is removed by dry etching.

[0082] (6) The first mask layer 31 is removed.

[0083] (7) Phosphorus diffusion is performed at 900° C. to form N-type polysilicon as the N area, that is, the electron transport layer 40.

[0084] (8) The second passivation layer 50 is a silicon carbide film with a deposition thickness of 20 nm, using silane and methane as the silicon source and carbon source, and H2 as the carrier gas.

[0085] (9) Using the same conditions as in step (4) and step (8) in Example 1, an aluminum oxide film is prepared as a third passivation layer 61 and a silicon carbide film is prepared as a fourth passivation layer 62 on the front side of a silicon wafer.

[0086] (10) Anneal at 38 to 420°C for 10 minutes to activate the surface passivation.

[0087] (11) A first electrode 71 of silver and a second electrode 72 of nickel aluminum are fabricated.

[0088] The solar cells manufactured in Examples 1 and 2 and Comparative Example 1 were subjected to performance tests, and the open circuit voltage U oc , short circuit current I sc , fill factor FF and conversion efficiency E ta The test results, including the above, are shown in Table 1 below. JPEG2025023825000002.jpg41170

[0089] As can be seen, the photoelectric conversion efficiency and open circuit voltage of the solar cells in Examples 1 and 2 are higher than those in Comparative Example 1. At the same time, the yields of Examples 1 and 2 are also higher than those in Comparative Example 1, which indicates that the yield in Comparative Example 1 is low because the high temperature process affects the warping of the silicon wafer. Furthermore, the solar cell in Example 2 has a relatively smaller open circuit voltage than that in Example 1, and the passivation effect is not as good as that of the film produced by atomic layer deposition in Example 1, because the film grown by plasma enhanced chemical vapor deposition is not dense enough.

[0090] The technical features of the above-mentioned embodiments may be combined in any desired manner. For the sake of brevity, not all possible combinations of the technical features in the above-mentioned embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, any combination should be considered to be within the scope of the present specification.

[0091] The above examples only show some embodiments of the present invention, and the description is specific and detailed, but it should not be understood as limiting the patent scope of the present invention. It should be noted that those skilled in the art can make some modifications and improvements without departing from the idea of ​​the present application, all of which are within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application should be based on the appended claims, and the specification and drawings are used to explain the content of the claims. [Explanation of symbols]

[0092] 10. Semiconductor substrate 21. Hole transport layer 22, first passivation layer 31, first mask layer 32, second mask layer 40, electron transport layer 50, second passivation layer 61, third passivation layer 62, 4th passivation layer 71, 1st electrode 72, second electrode

Claims

1. A solar cell comprising: a semiconductor substrate having a first surface and a second surface disposed opposite to each other; a hole transport layer and an electron transport layer spaced apart from each other on the first surface, the hole transport layer being made of vanadium oxide and the electron transport layer being made of titanium oxide; a first passivation layer located on a surface of the hole transport layer remote from the semiconductor substrate; a second passivation layer, the second passivation layer being made of a material different from that of the first passivation layer, the second passivation layer covering a surface of the first passivation layer facing away from the semiconductor substrate, the second passivation layer covering a surface of the electron transport layer facing away from the semiconductor substrate, and the first surface; A solar cell characterized by:

2. The thickness of the hole transport layer is 20 to 30 nm. The solar cell according to claim 1 .

3. The thickness of the electron transport layer is 45 to 55 nm. The solar cell according to claim 1 .

4. the material of the first passivation layer comprises aluminum oxide; and / or the material of the second passivation layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride. The solar cell according to claim 1 .

5. The second surface is suede. The solar cell according to any one of claims 1 to 4.

6. The second surface is provided with a third passivation layer. The solar cell according to claim 5 .

7. A fourth passivation layer is further provided on a surface of the third passivation layer that is away from the semiconductor substrate, and the fourth passivation layer and the third passivation layer are made of different materials. The solar cell according to claim 6 .

8. providing a semiconductor substrate having opposed first and second surfaces; producing a hole transport layer and an electron transport layer spaced apart on the first surface, the hole transport layer material comprising vanadium oxide and the electron transport layer material comprising titanium oxide; producing a first passivation layer located on a surface of the hole transport layer facing away from the semiconductor substrate; and producing a second passivation layer covering a surface of the first passivation layer facing away from the semiconductor substrate, a surface of the electron transport layer facing away from the semiconductor substrate, and the first surface. The method for manufacturing a solar cell according to any one of claims 1 to 4.

9. The step of producing the hole transport layer comprises: Producing the hole transport layer from a vanadium source and a first oxidant by deposition at 120-130° C. using atomic layer deposition, or producing the hole transport layer from a vanadium source and a second oxidant by plasma enhanced chemical vapor deposition at 380-420° C. The method for producing a solar cell according to claim 8 .

10. The process for producing the electron transport layer is specifically preparing the electron transport layer from a titanium source and a first oxidant at 100-160° C. using atomic layer deposition; or preparing the electron transport layer from a titanium source and a second oxidant at 380-420° C. using plasma enhanced chemical vapor deposition. The method for producing a solar cell according to claim 8 .

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