Chip system, method for processing virtual interrupt, and corresponding device

Abstract

To provide a chip system, a method for processing virtual interrupt and a corresponding device.SOLUTION: A chip system includes a source physical processor, a control apparatus, an intermediate apparatus, a sending apparatus, and a target physical processor. A virtual environment is created on the system. A host machine or a virtual machine runs on the source physical processor. The host machine or virtual machine writes information used to trigger virtual interrupt to a register in the control apparatus, and the control apparatus receives it. The intermediate apparatus triggers the virtual interrupt based on the information when the control apparatus sends the information to the intermediate apparatus, and sends the virtual interrupt to the sending apparatus. The sending apparatus sends the virtual interrupt to the target physical processor. This solution is used to reduce overheads of switching from the virtual machine to the host machine or from a user mode of the host machine to a kernel mode of the host machine that are generated due to the virtual interrupt.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present application relates to the field of virtualization technology, and in particular to a chip system, a virtual interrupt handling method, and a corresponding device. [Background technology]

[0002] Virtual interrupts are a necessary part of virtualization technology. A virtual machine (VM) runs on a computing device. Notifications sent to the virtual machine by hardware devices such as disks or input / output (I / O) devices in the computing device and various types of synchronization and coordination within the virtual machine depend on virtual interrupts. Virtual interrupts are events. Such events can have various sources and the handling process for the events varies depending on the source. However, such events from each source are notified to the virtual machine in the form of interrupts that are received when the virtual machine is running.

[0003] Regardless of the source of the virtual interrupt, before the virtual interrupt finally arrives at the virtual machine, the host machine must complete the delivery of the virtual interrupt from the source to the target virtual machine using various mechanisms on the host machine. In the process of delivering a virtual interrupt, the processor control flow must be switched from the running virtual machine to the host machine, or from the user mode of the host machine to the kernel mode of the host machine. This causes a relatively large switching overhead. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a chip system, a virtual interrupt processing method, and a corresponding apparatus for reducing switching overhead caused by virtual interrupts when switching from a virtual machine to a host machine or from a user mode of a host machine to a kernel mode of a host machine. The present application also provides a corresponding computer device, a computer storage medium, a computer program product, etc. [Means for solving the problem]

[0005] A first aspect of the present application provides a chip system. The chip system includes a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt may come from the host machine or the virtual machine. The control device is configured to: transmit the information used to trigger the virtual interrupt to the intermediate device, which is in the register; The intermediate device is configured to: trigger a virtual interrupt based on the information used to trigger the virtual interrupt, and transmit the virtual interrupt to the sending device; The sending device is configured to: receive a virtual interrupt from the intermediate device, and transmit the virtual interrupt to the target physical processor.

[0006] In the present application, the chip system may be a system on chip (SOC), and the source physical processor and the target physical processor may each be a processing unit, for example, a physical core. The control device, the intermediate device, and the sending device may all be implemented using hardware circuits or may be implemented using software. The source physical processor and the target physical processor may be physical cores in a multi-core processor. The multi-core processor includes multiple physical cores. The physical core is a core integrated in a processor. The physical core is a processing unit. For example, a dual-core processor may be understood as a processor with two physical cores. The control device and the sending device may be deployed in the multi-core processor and are coupled to the source physical processor and the target physical processor. The intermediate device may be deployed in the multi-core processor or on a peripheral device / peripheral component coupled to the multi-core processor. The system on chip may include a multi-core processor and a peripheral device / peripheral component coupled to the multi-core processor. Any physical processor in the chip system may be used as the source physical processor or as the target physical processor.

[0007] For the purposes of this application, a virtual interrupt is an interrupt sent to a virtual machine (VM) by a computing device, a host machine, the virtual machine's clock, the virtual machine's virtual processor, etc. A hardware device that generates a virtual interrupt can be a disk, a network adapter, an audio adapter, a mouse, a hard disk, etc. in a computing device. A physical interrupt is an interrupt sent to a physical processor by a hardware device. Physical interrupts are handled by the host machine and virtual interrupts are handled by the virtual machine.

[0008] It should be noted that the specific implementation of the virtual processor referred to in the embodiments of the present application may be a virtual central processing unit (vCPU). The "vCPU" described below can be replaced with "virtual processor" for ease of understanding.

[0009] In this application, a virtual interrupt may include a virtual local interrupt, a virtual software interrupt, a virtual device interrupt, and a direct peripheral interrupt. A virtual local interrupt refers to an interrupt sent by a virtual local device simulated by a virtual machine or a local device of a vCPU of a virtual machine, for example, a clock interrupt sent by a timer of the vCPU of a virtual machine. A virtual software interrupt is an interrupt triggered by software and generally sent by a vCPU of a virtual machine to another vCPU of the virtual machine. A virtual machine may have multiple vCPUs, and these vCPUs may run on different physical processors at a given moment to perform different tasks of the virtual machine. A virtual software interrupt occurs when tasks performed by different vCPUs are interdependent or need to be scheduled. A virtual device interrupt refers to an interrupt triggered by a host machine simulating a hardware device, for example, an interrupt generated by a host machine simulating a virtual machine disk controller or simulating another hardware device.

[0010] In the present application, the control device may include at least one register, and each register may be configured to receive one type of information used to trigger a virtual interrupt. For example, three registers are included, one register configured to receive information used to trigger a virtual local interrupt, one register configured to receive information used to trigger a virtual software interrupt, and one register configured to receive information used to trigger a virtual device interrupt. Of course, in the control device, only one register may be configured for virtual interrupts, and the information used to trigger each type of virtual interrupt is different. The type of virtual interrupt may be identified using the information received by the registers.

[0011] There may be one or more intermediate devices. The sending devices may be one for each physical processor, or multiple physical processors may share one sending device.

[0012] From the first aspect, it can be seen that in the first aspect, a register dedicated to handling virtual interrupts is located in the control device. In this way, the host machine or virtual machine in user mode or kernel mode can directly write information used to trigger the virtual interrupt to the register. The control device may send information used to trigger the virtual interrupt to an intermediate device, which triggers the virtual interrupt. The intermediate device also sends the virtual interrupt to a sending device, which sends the virtual interrupt to the target physical processor. In the solution provided in the present application, the host machine or virtual machine may directly access the register and write information used to trigger the virtual interrupt to the register, so that the virtual interrupt is sent. Therefore, compared to the prior art, in the solution provided in the present application, the source physical processor does not need to switch from the virtual machine to the host machine, and the source physical processor does not need to switch from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead generated when handling the virtual interrupt and improving the performance of the chip system.

[0013] In one possible implementation of the first aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The sending device is configured to: send the virtual local interrupt to a first virtual processor vCPU of the virtual machine, where the first vCPU runs on the source physical processor.

[0014] In this possible implementation, the virtual local interrupt is an in-core interrupt, so the target physical processor and the source physical processor are the same physical processor. The intermediate device may be a timer, and the virtual local interrupt may be a clock interrupt. One physical processor runs only one vCPU of one virtual machine at a given moment, and the operation of sending a virtual local interrupt to a virtual machine can be completed by sending a virtual local interrupt to the vCPU. From this possible implementation, it can be seen that in the process of handling the virtual local interrupt, the source physical processor does not need to switch from the virtual machine to the host machine, thus reducing the switching overhead incurred during the handling of the virtual local interrupt and improving the performance of the chip system.

[0015] In one possible implementation of the first aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of a virtual machine, the second vCPU being a vCPU of a virtual machine running on a target physical processor. The control device is configured to: read the identifier of the second vCPU from the register to obtain an identifier of the virtual machine; and transmit the identifier of the virtual machine and the identifier of the second vCPU to an intermediate device. The intermediate device is configured to: determine a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, the first correspondence being used to record a correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and transmit the virtual software interrupt to a transmitting device corresponding to the target physical processor. The transmitting device is configured to transmit the virtual software interrupt to the second vCPU running on the target physical processor.

[0016] In this possible implementation, the virtual software interrupt is an interrupt sent by the first vCPU of the virtual machine to the second vCPU of the virtual machine. Therefore, when the first vCPU of the virtual machine needs to trigger the virtual software interrupt, it needs to write the identifier of the second vCPU into a register. One virtual machine can have multiple vCPUs, and the vCPUs belonging to one virtual machine can run in a time-division multiplexed manner on one physical processor. For example, vCPU1 of virtual machine 1 may run on physical processor 1 first, and after physical processor 1 finishes the operation of vCPU1, vCPU2 of virtual machine 1 may run. Also, multiple vCPUs belonging to one virtual machine may run on different physical processors, and different vCPUs may run on different physical processors simultaneously. For example, vCPU1 of virtual machine 1 runs on physical processor 1, and vCPU2 of virtual machine 1 runs on physical processor 2. In the virtual software interrupt scenario, the first vCPU runs on the source physical processor, and the second vCPU runs on the target physical processor. The controller may obtain the identifiers of the virtual machines from a dedicated register that stores the identifiers of the virtual machines running on the source physical processor. Each virtual machine can have multiple vCPUs, and the identifiers of the vCPUs of different virtual machines may be the same. Therefore, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The intermediate device may store the first correspondence. The first correspondence may be located in an imposition vCPU identifier group. The imposition vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPUs running on each physical processor, and the virtual machine to which the running vCPU belongs. In the present application, the physical processor may be determined by searching the imposition vCPU identifier group. From this possible implementation, it can be seen that in the process of handling the virtual software interrupt, the source physical processor does not need to switch from the virtual machine to the host machine, thus reducing the switching overhead occurring during the handling of the virtual software interrupt and improving the performance of the chip system.

[0017] In one possible implementation of the first aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier written to a register by the host machine, where the target interrupt number is an identifier of an interrupt triggered when the host machine simulates a hardware device. The control device is configured to read the target interrupt number and the virtual machine identifier from the register and send the virtual machine identifier and the target interrupt number to the intermediate device. The intermediate device is configured to perform: searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, the second correspondence being used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record the correspondence between the target physical processor and the first vCPU and the virtual machine running on the target processor; and sending the virtual device interrupt to a sending device corresponding to the target physical processor. The sender is configured to send a virtual device interrupt to a first vCPU running on the target physical processor.

[0018] In this possible implementation, the virtual device interrupt is an interrupt triggered by a hardware device simulated by the host machine in user mode when simulating a hardware device. There may be multiple types of hardware devices, and the interrupt number for each type of hardware device is different. If the host machine simulates a disk, the target interrupt number is the interrupt number of the disk. Since the host machine may manage multiple virtual machines, the host machine needs to write the virtual machine identifier and the target interrupt number to a register. The second correspondence may be located in an interrupt affinity table. The interrupt affinity table may be configured by the virtual machine. Thus, there is an interrupt affinity table for each virtual machine. In this way, the virtual machine's interrupt affinity table may be found based on the virtual machine's identifier, and the corresponding vCPU is determined from the virtual machine's interrupt affinity table based on the target interrupt number. The target interrupt number is 10. If the interrupt number 10 in the interrupt affinity table corresponds to vCPU ID 1, it may be determined that the vCPU ID corresponding to the target interrupt number is 1. After determining that the vCPU ID is 1, the routing device may find a physical processor corresponding to vCPU ID1 based on the inposition vCPU identifier group. For the meaning of the inposition vCPU identifier group, please refer to the description of the virtual software interrupt for understanding. For the third correspondence, please refer to the first correspondence for understanding. From this possible implementation, it can be seen that in a process of handling a virtual device interrupt, the source physical processor does not need to switch from the user mode of the host machine to the kernel mode of the host machine, thus reducing the switching overhead occurring during the handling of the virtual device interrupt and improving the performance of the chip system.

[0019] In one possible implementation of the first aspect, the intermediate device includes an address register configured to store an address of the second correspondence in memory and an identifier of a virtual machine, the intermediate device further configured to: search the address register based on the identifier of the virtual machine, and retrieve the second correspondence from the memory based on the address in the address register.

[0020] In this possible implementation, the interrupt affinity table may be stored in the intermediate device or may be stored in memory. The intermediate device may provide an address register for each physical processor. The address register may be a base address register, which may store the address of the interrupt affinity table in memory and the identifier of the virtual machine. This avoids occupying excessive storage space in the intermediate device.

[0021] In one possible implementation of the first aspect, the sending device is configured to write a virtual interrupt to a pending register of the target physical processor, the pending register being configured to receive a command for a procedure to be executed by the target physical processor.

[0022] In this possible implementation, the pending register is configured to receive a command to be subsequently executed by the target physical processor and to write a virtual interrupt to the pending register so that the target physical processor subsequently executes the virtual interrupt. In this way, the currently executed process is interrupted, thereby interrupting the switch-to-host machine action in existing solutions. This reduces the overhead of switching the target physical processor from the virtual machine to the host machine.

[0023] A second aspect of the present application provides a chip system, the chip system including a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor, the source physical processor configured to execute a host machine or a virtual machine, the chip system further including a hardware device for direct communication between the virtual machine and the target physical processor. The intermediate device is configured to: receive a direct peripheral interrupt triggered by a hardware device; search a virtual interrupt table for a corresponding virtual machine identifier and virtual interrupt number based on a physical interrupt number of the direct peripheral interrupt, the virtual interrupt table recording a correspondence between the physical interrupt number, the virtual machine identifier, and the virtual interrupt number; determine a corresponding interrupt affinity table based on the virtual machine identifier, and determine from the interrupt affinity table a virtual machine identifier and a target virtual processor vCPU identifier corresponding to the virtual interrupt number, the interrupt affinity table recording a correspondence between the virtual interrupt number and the virtual processor; determine a target physical processor from an imposition vCPU identifier group based on the target vCPU identifier, the target physical processor corresponding to the target vCPU identifier; and transmit the direct peripheral interrupt to a transmitting device corresponding to the target physical processor. The transmitting device transmits the direct peripheral interrupt to a virtual machine running on the target physical processor.

[0024] In the second aspect, a direct peripheral interrupt refers to an interrupt triggered by a peripheral device directly connected to a virtual machine, for example, an interrupt generated by a graphics card directly connected to a virtual machine. In the process of handling a direct peripheral interrupt, a virtual interrupt table, an interrupt affinity table, and an imposition vCPU identifier group are used in order. For an understanding of the interrupt affinity table and the imposition vCPU identifier group, please refer to the description in the possible implementations of the first aspect. The following describes the virtual interrupt table. The virtual interrupt table maintains a mapping relationship between a physical interrupt number, a virtual machine identifier, and a virtual interrupt number. When a physical interrupt number is input, a virtual machine identifier and a virtual interrupt number can be output. In the process of handling a direct peripheral interrupt, an intermediate device receives a physical interrupt number sent by the direct peripheral device, and searches the virtual interrupt table for a corresponding virtual machine identifier and virtual interrupt number based on the physical interrupt number. For example, when a physical interrupt number 100 is input, a virtual machine identifier 1 and a virtual interrupt number 10 may be output. Then, based on the virtual machine identifier 1 and the virtual interrupt number 10, the interrupt affinity table is searched to find a corresponding vCPU ID. For example, the vCPU ID is found to be 1. Further, based on the vCPU ID, the imposition vCPU identifier group is searched for a corresponding physical processor. For example, if physical processor 1 is found, the intermediate device may send the peripheral interrupt directly to the sending device corresponding to physical processor 1, and the sending device may send the peripheral interrupt directly to the vCPU corresponding to vCPU ID 1.

[0025] In the process of handling direct peripheral interrupts provided in the second aspect, the sending process can be completed by searching for three correspondences, thereby improving the flexibility of handling direct peripheral interrupts.

[0026] A third aspect of the present application provides a control device. The control device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, and a sending device. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The control device is configured to: read the information used to trigger the virtual interrupt from the register; and send the information used to trigger the virtual interrupt to the intermediate device. The information used to trigger the virtual interrupt is used to enable the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent to the target physical processor by the sending device.

[0027] In one possible implementation of the third aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the control device is configured to: send the information used to trigger the virtual local interrupt to the intermediate device, the information used to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0028] In one possible implementation of the third aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The control device is configured to read the identifier of the second vCPU from the register to obtain an identifier of the virtual machine; and to transmit the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt. The virtual software interrupt is transmitted by the transmitting device to the second vCPU of the target physical processor.

[0029] In one possible implementation of the third aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier written to a register by the host machine, the target interrupt number being an identifier of an interrupt to be triggered when the host machine simulates the hardware device. The control device is configured to: read the target interrupt number and the virtual machine identifier from the register; and send the target interrupt number and the virtual machine identifier to the intermediate device. The virtual machine identifier and the target interrupt number are used by the intermediate device to determine a target physical processor to trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to a first vCPU of the target physical processor.

[0030] A fourth aspect of the present application provides an intermediate device. The intermediate device is applied to a chip system. The chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The intermediate device is configured to: receive information used to trigger the virtual interrupt from the control device, trigger a virtual interrupt based on the information used to trigger the virtual interrupt, and transmit the virtual interrupt to the transmitting device. The virtual interrupt is transmitted to the target physical processor by the transmitting device.

[0031] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The intermediate device is configured to: trigger the virtual local interrupt based on the information used to trigger the virtual local interrupt and send the virtual local interrupt to the sending device. The virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0032] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The intermediate device is configured to perform the steps of: receiving from the control device an identifier of the virtual machine and an identifier of the second vCPU; determining a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, the first correspondence being used to record a correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; triggering the virtual software interrupt; and transmitting the virtual software interrupt to a transmitting device corresponding to the target physical processor. The virtual software interrupt is transmitted by the transmitting device to the second vCPU of the target physical processor.

[0033] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier written to a register by the host machine. The target interrupt number is an identifier of an interrupt triggered when the host machine simulates a hardware device. The intermediate device is configured to perform the following steps: receive from the control device a virtual machine identifier and a target interrupt number; search a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, the second correspondence being used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determine a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; trigger a virtual device interrupt; and send the virtual device interrupt to a sending device corresponding to the target physical processor. The virtual device interrupt is sent by a sending unit to a first vCPU of a target physical processor.

[0034] In one possible implementation of the fourth aspect, the intermediate device includes an address register configured to store an address of the second correspondence in memory and an identifier of a virtual machine, the intermediate device further configured to: search the address register based on the identifier of the virtual machine; and retrieve the second correspondence from the memory based on the address in the address register.

[0035] A fifth aspect of the present application provides a transmitting device. The transmitting device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a target physical processor, and a control device. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The transmitting device is configured to receive the virtual interrupt from the intermediate device and transmit the virtual interrupt to the target physical processor.

[0036] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The sending device is configured to: receive the virtual local interrupt from the intermediate device and send the virtual local interrupt to a first virtual processor vCPU of the virtual machine. The first vCPU runs on the source physical processor.

[0037] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The sending device is configured to: receive the virtual software interrupt from the intermediate device; and send the virtual software interrupt to the second vCPU running on the target physical processor.

[0038] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by a host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt that is triggered when the host machine simulates the hardware device. The sending device is configured to: receive the virtual device interrupt from the intermediate device and send the virtual device interrupt to a first vCPU running on the target physical processor.

[0039] In one possible implementation of the fifth aspect, the sending device is configured to write the virtual interrupt to a pending register of the target physical processor, the pending register being configured to receive a command for a procedure to be executed by the target physical processor.

[0040] For the matters described in the third aspect to the fifth aspect, and possible implementations of any of the third aspect to the fifth aspect, and corresponding intended effects, please refer to the description in the first aspect and possible implementations of any of the first aspect for understanding, and the details will not be described again here.

[0041] A sixth aspect of the present application provides a virtual interrupt processing method. The method is applied to a control device of a chip system. The chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The method includes: reading the information used to trigger the virtual interrupt from the register; and sending the information used to trigger the virtual interrupt to the intermediate device. The information used to trigger the virtual interrupt is used to enable the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent to the target physical processor by the sending device.

[0042] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0043] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of a virtual machine running on the target physical processor. The method further includes: obtaining an identifier of the virtual machine; and transmitting the identifier of the virtual machine and the identifier of the second vCPU to an intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt. The virtual software interrupt is transmitted by the transmitting device to the second vCPU of the target physical processor.

[0044] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by a host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt to be triggered when the host machine simulates the hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine a target physical processor to trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to a first vCPU of the target physical processor.

[0045] A seventh aspect of the present application provides a virtual interrupt processing method. The method is applied to an intermediate device of a chip system. The chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The method includes receiving information used to trigger the virtual interrupt from the control device; triggering a virtual interrupt based on the information used to trigger the virtual interrupt; and sending the virtual interrupt to the sending device. The virtual interrupt is sent to the target physical processor by the sending device.

[0046] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to trigger a virtual local interrupt, and the virtual local interrupt is sent by a sending unit to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0047] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The step of triggering the virtual interrupt based on the information used to trigger the virtual interrupt includes: determining a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, the first correspondence being used to record a correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and triggering the virtual software interrupt. The virtual software interrupt is transmitted by a transmitting device to the second vCPU of the target physical processor.

[0048] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier written to a register by the host machine, the target interrupt number being an identifier of an interrupt triggered when the host machine simulates a hardware device. The step of triggering the virtual interrupt based on the information used to trigger the virtual interrupt includes: searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, the second correspondence being used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; determining a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and triggering the virtual device interrupt. The virtual device interrupt is transmitted to the first vCPU of the target physical processor by a transmitting device.

[0049] In one possible implementation of the seventh aspect, the method further includes: finding an address register based on the virtual machine identifier; and obtaining the second correspondence from a memory based on an address in the address register, the address register configured to store an address of the second correspondence in the memory and the virtual machine identifier.

[0050] An eighth aspect of the present application provides a virtual interrupt processing method. The method is applied to a sending device of a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger the virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The method includes receiving a virtual interrupt from the intermediate device and sending the virtual interrupt to the target physical processor.

[0051] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The above step of sending the virtual interrupt to the target physical processor includes: sending the virtual local interrupt to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0052] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The above step of sending the virtual interrupt to the target physical processor includes: sending the virtual software interrupt to the second vCPU running on the target physical processor.

[0053] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by a host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt triggered when the host machine simulates the hardware device. The step of sending the virtual interrupt to the target physical processor includes sending the virtual device interrupt to a first vCPU running on the target physical processor.

[0054] In one possible implementation of the eighth aspect, the method further includes: writing the virtual interrupt to a pending register of the target physical processor, the pending register configured to receive a command for a procedure to be executed by the target physical processor.

[0055] For the matters described in the sixth to eighth aspects, and possible implementations of any of the sixth to eighth aspects, and corresponding intended effects, please refer to the description in the first aspect and any possible implementations of the first aspect for understanding, and the details will not be described again here.

[0056] A ninth aspect of the present application provides a control device. The control device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The control device includes a reading unit configured to read the information used to trigger the virtual interrupt from the register; and a sending unit configured to send the information used to trigger the virtual interrupt to the intermediate device. The information used to trigger the virtual interrupt is used by the intermediate device to trigger the virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

[0057] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0058] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The control device further includes: a processing unit configured to obtain the identifier of the virtual machine; and a sending unit configured to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt. The virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0059] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by a host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt to be triggered when the host machine simulates the hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine a target physical processor to trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to a first vCPU of the target physical processor.

[0060] A tenth aspect of the present application provides an intermediate device. The intermediate device is applied to a chip system. The chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The intermediate device includes a receiving unit configured to receive information used to trigger the virtual interrupt from the control device; a processing unit configured to trigger the virtual interrupt based on the information used to trigger the virtual interrupt; and a transmitting unit configured to transmit the virtual interrupt to the transmitting device. The virtual interrupt is transmitted to the target physical processor by the transmitting device.

[0061] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to trigger a virtual local interrupt, and the virtual local interrupt is sent by a sending unit to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0062] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor. The processing unit is configured to perform: determining a target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, the first correspondence being used to record a correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and triggering the virtual software interrupt. The virtual software interrupt is transmitted by a transmitting device to the second vCPU of the target physical processor.

[0063] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier written to a register by the host machine, the target interrupt number being an identifier of an interrupt triggered when the host machine simulates the hardware device. The processing unit is configured to perform: searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, the second correspondence being used to record a correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record a correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and triggering a virtual device interrupt. The virtual device interrupt is transmitted to the first vCPU of the target physical processor by a transmitting device.

[0064] In one possible implementation of the tenth aspect, the processing unit is further configured to: find an address register based on a virtual machine identifier; and retrieve the second correspondence from a memory based on an address in the address register, the address register configured to store an address of the second correspondence in the memory and the virtual machine identifier.

[0065] An eleventh aspect of the present application provides a transmitting device. The transmitting device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or the virtual machine. The transmitting device includes a receiving unit configured to receive a virtual interrupt from the intermediate device, and a transmitting unit configured to transmit the virtual interrupt to the target physical processor.

[0066] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The sending unit is configured to: send the virtual local interrupt to a first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0067] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second vCPU written to a register by a first vCPU of a virtual machine, the second vCPU being a vCPU of a virtual machine running on a target physical processor, and the sending unit is configured to: send the virtual software interrupt to the second vCPU running on the target physical processor.

[0068] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by a host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt triggered when the host machine simulates the hardware device. The sending unit is configured to send the virtual device interrupt to a first vCPU running on the target physical processor.

[0069] In one possible implementation of the eleventh aspect, the sending unit is further configured to: write a virtual interrupt to a pending register of the target physical processor, the pending register being configured to receive a command for a procedure to be executed by the target physical processor.

[0070] For the matters described in the ninth aspect to the eleventh aspect, and possible implementations of any of the ninth aspect to the eleventh aspect, and the corresponding intended effects, please refer to the description in the first aspect and any possible implementations of the first aspect for understanding, and the details will not be described again here.

[0071] A twelfth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions which, when executed by a processor, cause the processor to perform a method according to the sixth aspect or any possible implementation of the sixth aspect.

[0072] A thirteenth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions which, when executed by a processor, cause the processor to perform a method according to the seventh aspect or any possible implementation of the seventh aspect.

[0073] A fourteenth aspect of the present application provides a computer-readable storage medium storing one or more computer-executable instructions which, when executed by a processor, cause the processor to perform a method according to the eighth aspect or any possible implementation of the eighth aspect.

[0074] A fifteenth aspect of the present application provides a computer program product storing one or more computer-executable instructions that, when executed by a processor, cause the processor to perform a method according to the sixth aspect or any possible implementation of the sixth aspect.

[0075] A sixteenth aspect of the present application provides a computer program product storing one or more computer-executable instructions that, when executed by a processor, cause the processor to perform a method according to the seventh aspect or any possible implementation of the seventh aspect.

[0076] A seventeenth aspect of the present application provides a computer program product storing one or more computer-executable instructions that, when executed by a processor, cause the processor to perform a method according to the eighth aspect or any possible implementation of the eighth aspect.

[0077] An eighteenth aspect of the present application provides a computing device, the computing device including a chip system according to the first aspect or any possible implementation of the first aspect.

[0078] A nineteenth aspect of the present application provides a chip system, the chip system including a source physical processor, a control device, a transmitting device, and a target physical processor, the control device being according to the third aspect, the ninth aspect, any of the possible implementations of the third aspect, or any of the possible implementations of the ninth aspect, and the transmitting device being according to the fifth aspect, the eleventh aspect, any of the possible implementations of the eleventh aspect, or any of the possible implementations of the fifth aspect.

[0079] In some implementations, the chip system may further include an intermediate device according to the fourth aspect, the tenth aspect, any of the possible implementations of the tenth aspect, or any of the possible implementations of the fourth aspect.

[0080] In one implementation, the chip system according to the nineteenth aspect is a processor, the source physical processor and the target physical processor are physical cores within the processor, the controller is a component located within the processor and coupled to the source physical processor, and the transmitter is a component located within the processor and coupled to the target physical processor. It will be appreciated that any physical core of the processor may be used as a receiver of a virtual interrupt. Thus, a physical core may be used as both a source physical processor and a target physical processor. Correspondingly, what is coupled to a physical core may include both a controller and a transmitter.

[0081] According to the chip system provided in this embodiment of the present application, a register dedicated to processing virtual interrupts is arranged in the control device. In this way, the host machine or virtual machine in user mode can directly write information used to trigger the virtual interrupt to the register. The control device may send information for triggering the virtual interrupt to the intermediate device, which triggers the virtual interrupt. The intermediate device also sends the virtual interrupt to the sending device, which sends the virtual interrupt to the target physical processor. In the solution provided in the present application, the host machine or virtual machine can directly access the register and write information used to trigger the virtual interrupt to the register, so that the virtual interrupt is sent. Therefore, in the solution provided in the present application, compared to the prior art, the source physical processor does not need to switch from the virtual machine to the host machine or from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead generated during virtual interrupt processing and improving the performance of the chip system. [Brief description of the drawings]

[0082] [Figure 1] 1 is a schematic diagram of the structure of a computing device according to an embodiment of the present application.

[0083] [Diagram 2] FIG. 2 is a schematic diagram of types of virtual interrupts according to an embodiment of the present application;

[0084] [Diagram 3] 1 is a schematic diagram of the structure of a chip system according to an embodiment of the present application.

[0085] [Figure 4] 1 is a schematic diagram of another structure of a chip system according to an embodiment of the present application.

[0086] [Diagram 5]FIG. 2 is a schematic diagram of a virtual clock interrupt according to an embodiment of the present application;

[0087] [Figure 6] FIG. 2 is a schematic diagram of an example of an inposition virtual processor identifier group according to an embodiment of the present application;

[0088] [Figure 7] FIG. 2 is a schematic diagram of an example of a virtual software interrupt according to an embodiment of the present application.

[0089] [Figure 8] 1 is a schematic diagram of the structure of a routing device according to an embodiment of the present application;

[0090] [Figure 9] FIG. 2 is a schematic diagram of an example of a direct peripheral interrupt according to an embodiment of the present application.

[0091] [Figure 10] 1 is a schematic diagram of a chip system structure in a RISC-V microarchitecture according to an embodiment of the present application.

[0092] [Figure 11] FIG. 1 is a schematic diagram of a process for handling virtual clock interrupts in a RISC-V microarchitecture according to an embodiment of the present application.

[0093] [Figure 12] FIG. 1 is a schematic diagram of a process for handling virtual software interrupts in a RISC-V microarchitecture according to an embodiment of the present application.

[0094] [Figure 13] FIG. 1 is a schematic diagram of a process for handling virtual device interrupts in a RISC-V microarchitecture according to an embodiment of the present application.

[0095] [Figure 14]FIG. 1 is a schematic diagram of another process for handling virtual device interrupts in a RISC-V microarchitecture according to an embodiment of the present application.

[0096] [Figure 15] FIG. 1 is a schematic diagram of a process for handling direct peripheral interrupts in a RISC-V microarchitecture according to an embodiment of the present application.

[0097] [Figure 16] 2 is a schematic diagram of an embodiment of a virtual interrupt processing method according to an embodiment of the present application;

[0098] [Figure 17] FIG. 2 is a schematic diagram of an embodiment of a control device according to an embodiment of the present application.

[0099] [Figure 18] FIG. 2 is a schematic diagram of an embodiment of an intermediate device according to an embodiment of the present application.

[0100] [Figure 19] 1 is a schematic diagram of an embodiment of a transmitting device according to an embodiment of the present application;

[0101] [Figure 20] 1 is a schematic diagram of another configuration of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0102] The following describes the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments rather than all embodiments of the present application. Those skilled in the art may know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the present application can also be applied to similar technical problems.

[0103] In the present specification, claims, and accompanying drawings, the terms "first," "second," and the like are intended to distinguish between similar objects, but do not necessarily indicate a particular order or sequence. Such designated data are interchangeable under appropriate circumstances, and thus it should be understood that the embodiments described herein may be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprise," "include," and any other variations are meant to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, system, product, or device.

[0104] The embodiments of the present application provide a chip system, a virtual interrupt processing method, and a corresponding apparatus that reduce switching overhead caused by virtual interrupts when switching from a virtual machine to a host machine or from a user mode of a host machine to a kernel mode of a host machine. The embodiments of the present application further provide corresponding computer devices, computer storage media, computer program products, etc., which will be described in detail later.

[0105] Virtualization is the virtualization of hardware resources (e.g., processors, storage space in memory, network resources, etc.) at the hardware layer of a computing device and sharing the virtualized hardware resources for use by multiple virtual computers. A virtual computer is a general term for the software-virtualized execution environment on any type of virtualized device, and this concept includes virtual machines and containers.

[0106] 1, the computer device 100 includes a hardware layer 112, a host layer 109, and a virtualization layer. The virtualization layer includes virtual machines 101 and 102. The number of virtual machines may be more or less, and here, the case where the number of virtual machines is two is used as an example. The hardware layer 112 includes a processor system 114, a memory 113, a communication interface 115, and an interrupt controller 116.

[0107] A virtual machine (VM) is simulated on a computing device using virtualization software. A guest operating system (105 and 106 in FIG. 1) may be installed on the virtual machine (101 and 102 in FIG. 1), and one or more applications (103 and 104 in FIG. 1) run on the guest operating system. The virtual machine may also have access to network resources. Applications running on the virtual machine behave as if the applications were running on a real computer.

[0108] A virtual processor (e.g., 107 and 108 in FIG. 1) represents a processing unit, such as a virtual central processing unit (vCPU), provided to a virtual computer for use in a shared or sliced ​​manner in virtualization technology. A virtual computer may be served by one or more virtual processors. When there are multiple virtual processors, typically, one virtual processor is a primary virtual processor and the other virtual processors are secondary virtual processors. Other virtual hardware resources, such as virtual memory, included in the virtual machine are not shown in FIG. 1. The virtual processor is obtained through virtualization using virtualization software. The execution of a virtual processor is actually implemented as follows: A host processor or physical core reads and executes a software program. For example, a physical core reads a software program and executes the software program in a specific mode of hardware-assisted virtualization of the physical core (e.g., non-root mode of x86) to implement a virtual processor. Multiple virtual processors of a virtual machine may be located on different physical cores. It should be noted that the vCPU referred to in the embodiments of this application is an arbitrary concrete implementation of a virtual processor. The "vCPU" referred to in each embodiment may be replaced with a "virtual processor" for ease of understanding.

[0109] Virtual processor trap in and trap out: A virtual system includes two modes: host mode and guest mode. The host mode may also be called the host privilege level, e.g., the host user mode or the host kernel mode. The guest mode may also be called the VM privilege level, e.g., the VM user mode or the VM kernel mode. When a physical processor enters the guest mode, it is called trap in (virtual), and the trap in process may be understood as the physical processor switching from the host machine execution to the virtual machine execution. When a physical processor leaves the guest mode, it is called trap out (virtual), and the trap out process may be understood as the physical processor switching from the virtual machine execution to the host machine execution. After the trap out, the physical processor temporarily stops executing the code of the virtual processor. Therefore, in this case, it may be understood that the virtual processor is not running. When a virtual machine runs on a physical processor, the virtual processor of the virtual machine runs. One virtual machine may have multiple virtual processors. A physical processor executes only one virtual processor of a virtual machine at a time. Multiple virtual processors belonging to the same virtual machine may be executed on physical processors in a time-multiplexed manner. For example, vCPU 1 of virtual machine 1 may be executed first on physical processor 1, and vCPU 2 of virtual machine 1 may be executed after physical processor 1 finishes executing vCPU 1. Multiple vCPUs belonging to the same virtual machine may alternatively be executed on different physical processors, or different vCPUs may be executed simultaneously on different physical processors. For example, vCPU 1 of virtual machine 1 may be executed on physical processor 1, and vCPU 2 of virtual machine 1 may be executed on physical processor 2.As a management layer, the host machine (host) layer 109 is configured to complete the management and allocation of hardware resources and provide various virtual hardware resources for virtual machines, such as virtual processors (107, 108), virtual memory, virtual disks, virtual network adapters, and may further implement scheduling and isolation of virtual machines. In some implementations, the host layer 109 includes a host operating system 111 and a virtual monitoring device, such as a virtual machine monitor (VMM) 110. The virtual machine monitor 110 may be deployed inside the host operating system 111 or outside the host operating system 111. In another virtualization architecture, the virtual monitoring device may be called a hypervisor or another type of virtual monitoring device. The host layer 109 may also be called a virtualization platform, and sometimes the host layer may be called a host for short. The privilege levels of the host machine include user mode and kernel mode.

[0110] The hardware layer 112 is a hardware platform on which the virtualized environment runs. The hardware layer may include multiple types of hardware. As shown in FIG. 1, the hardware layer may include a processor system 114 and a memory 113, and may further include a communication interface 115, such as a network interface card (NIC), an interrupt controller 116, input / output (I / O) devices, etc. The processor system 114 may include one or more processors, such as processor 1 and processor 2 shown in FIG. 1. Each processor may include multiple physical cores, and the processor may further include multiple registers, such as general-purpose registers and floating-point registers.

[0111] The processor system 114 may include multiple processors, for example, processor 1 and processor 2 in FIG. 1. Both processor 1 and processor 2 in FIG. 1 are physical processors, such as a source physical processor and a target physical processor. Each physical processor may be understood as a physical core. The processor system 114 may specifically be a multi-core processor, which includes a source physical processor and a target physical processor. A virtual processor may be bound to a physical core. That is, a virtual processor always executes on a specific physical core and cannot be scheduled for execution on another physical core. In this case, the virtual processor is a core bound. If the virtual processor is scheduled to different physical cores for execution depending on the requirements, the virtual processor is not a core bound.

[0112] The interrupt controller 116 is disposed between the hardware that triggers the interrupt request and the processor, and is mainly configured to collect the interrupt requests generated by the hardware and send them to the processor based on a certain priority or according to another rule. For example, the interrupt controller is an advanced programmable interrupt controller (APIC).

[0113] An interruption suspends the execution of the current program's instructions and executes an interrupt service routine. Interrupts can include virtual and physical interrupts. A virtual interrupt is an interrupt that is signaled to a virtual machine (VM) by a hardware device in a computing device, the host machine, the virtual machine's clock, the virtual central processing unit (vCPU) of the virtual machine, etc. The hardware devices that generate virtual interrupts can be disks, network adapters, audio adapters, mice, hard disks, etc. in a computing device. A physical interrupt is an interrupt that is signaled to a physical processor by a hardware device. Physical interrupts are handled by the host machine, and virtual interrupts are handled by the virtual machine.

[0114] An interrupt service routine (ISR), sometimes called an interrupt handling function, is a program used to handle interrupt requests. Upon receiving an interrupt request, the processor suspends execution of the current program and runs the interrupt service routine that corresponds to the interrupt request.

[0115] The storage space (address space) provided by memory 113 is assigned to the virtual machines and the host for use. A host physical address (HPA) is the physical address space available to the local host (host). A host virtual address (HVA) is the virtual address space available to the local host (host). A guest physical address (GPA) is the physical address space available to the virtual machine's guest operating system. A guest virtual address (GVA) is the virtual address space available to the virtual machine's guest operating system.

[0116] The computing device 100 is a physical device such as a server or a terminal device. The terminal device may be a handheld device with wireless connectivity or another processing device connected to a wireless modem. For example, the terminal device may be a mobile phone, a computer (personal computer, PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), a wearable device, an e-book reader, a portable mobile device, a pocket-sized mobile device, a handheld mobile device, a mobile device with a built-in computer, or a mobile device mounted in a vehicle.

[0117] A virtual machine or a host machine in the computer device 100 may send information used to trigger a virtual interrupt, so that the chip system provided in this embodiment of the present application completes a corresponding process of handling the virtual interrupt. The chip system provided in this embodiment of the present application may include the interrupt controller and the processor system in FIG. 1, or may include the interrupt controller or the processor system in FIG.

[0118] In this embodiment of the present application, as shown in FIG. 2, the virtual interrupt may include a virtual local interrupt, a virtual software interrupt, a virtual device interrupt, and a direct peripheral interrupt. A virtual local interrupt refers to an interrupt sent by a virtual local device, such as a virtual timer or a virtual mouse, simulated by a virtual machine, or an interrupt sent by a local device of a vCPU of a virtual machine, for example, an interrupt sent by a timer of a vCPU of a virtual machine. An interrupt sent by a timer is also called a clock interrupt. A clock interrupt refers to an interrupt sent by a timer in a timed manner when a time point configured by the virtual machine is reached. A virtual software interrupt is an interrupt triggered by software and generally sent by a vCPU of a virtual machine to another vCPU of the virtual machine. For example, FIG. 2 shows an interrupt sent by a first vCPU to a second vCPU of the same virtual machine as the first vCPU. A virtual machine may have multiple vCPUs, which may run simultaneously on different physical processors to execute different tasks of the virtual machine. Virtual software interrupts are raised when tasks performed by different vCPUs are interdependent or need to be scheduled. Virtual device interrupts are interrupts triggered by the host machine simulating a hardware device. For example, an interrupt generated by the host machine simulating a disk controller or another hardware device in the virtual machine. Direct peripheral interrupts are triggered by peripheral devices that are directly connected to the virtual machine. For example, an interrupt generated by a graphics card that is directly connected to the virtual machine.

[0119] In the above-mentioned four types of virtual interrupts, for the process of processing the virtual local interrupt, the virtual software interrupt, and the virtual device interrupt, the physical processor running the virtual machine needs to switch from the virtual machine to the host machine, or switch from the user mode of the host machine to the kernel mode of the host machine, which causes a relatively high switching overhead. Therefore, the embodiment of the present application provides a chip system. In the process of processing the virtual interrupt, the physical processor running the virtual machine does not need to switch from the virtual machine to the host machine, or switch from the user mode of the host machine to the kernel mode of the host machine, which can reduce the switching overhead. The following describes the chip system provided in an embodiment of the present application with reference to the accompanying drawings.

[0120] As shown in FIG. 3, a chip system provided in an embodiment of the present application includes a source physical processor, a control device, an intermediate device, a sending device, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt may come from the host machine or the virtual machine. The control device is configured to send the information in the register used to trigger the virtual interrupt to the intermediate device. The intermediate device is configured to trigger a virtual interrupt based on the information used to trigger the virtual interrupt and send the virtual interrupt to the sending device. The sending device is configured to receive the virtual interrupt from the intermediate device and send the virtual interrupt to the target physical processor.

[0121] The chip system may be applied to the computer device shown in FIG. 1, and the chip system may be the interrupt controller or the processor system in FIG.

[0122] The chip system provided in this embodiment of the present application may be a system on chip (SOC), and the source physical processor and the target physical processor may each be a processing unit. The source physical processor or the target physical processor may be a physical core and located in the same processor. Alternatively, the source physical processor and the target physical processor may be different processors located in the same chip system. The control device, the intermediate device, and the sending device may all be implemented using hardware circuits. The control device and the sending device may be deployed in a multi-core processor and coupled to the source physical processor and the target physical processor. The intermediate device may be deployed in the multi-core processor or on a peripheral device / peripheral component coupled to the multi-core processor. The system on chip may include a multi-core processor and a peripheral device / peripheral component coupled to the multi-core processor. Any physical processor in the chip system may be used as the source physical processor or the target physical processor.

[0123] In this application, a source physical processor and a target physical processor are used. It should be noted that the source physical processor and the target physical processor may be two physical cores in one multi-core processor or may be two physical cores located in different processors. In some implementations, the source physical processor and the target physical processor may be the same physical entity. For example, in a virtual local interrupt scenario, the source physical processor and the target physical processor may be the same physical processor.

[0124] In the present application, the control device may include at least one register, and each register may be configured to receive one type of information used to trigger a virtual interrupt. For example, three registers are included, one register configured to receive information used to trigger a virtual local interrupt, one register configured to receive information used to trigger a virtual software interrupt, and one register configured to receive information used to trigger a virtual device interrupt. Of course, in the control device, only one register may be configured for virtual interrupts, and the information used to trigger each type of virtual interrupt may be different. The type of virtual interrupt may be identified using the information received by the registers.

[0125] There may be one or more intermediate devices. The sending devices may be one for each physical processor, or multiple physical processors may share one sending device.

[0126] In the chip system provided in this embodiment of the present application, a register dedicated to processing virtual interrupts is set in the control device. In this way, the host machine or virtual machine in user mode can directly write information used to trigger the virtual interrupt to the register. The control device transmits the information used to trigger the virtual interrupt to the intermediate device, which triggers the virtual interrupt. The intermediate device also transmits the virtual interrupt to the transmitting device, which transmits the virtual interrupt to the target physical processor. The source physical processor does not need to switch from the virtual machine to the host machine, or from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead generated when processing the virtual interrupt and improving the performance of the chip system.

[0127] In Figure 3, the intermediate device may be a virtual local interrupt generating device or may be a routing device. If the virtual interrupt is a virtual local interrupt, the intermediate device may be called a local interrupt generating device (e.g., a timer). If the virtual interrupt is a virtual software interrupt or a virtual device interrupt, the intermediate device may be called a routing device.

[0128] Four types of virtual interrupts are shown in Figure 2. The following describes the process of handling the four types of virtual interrupts with reference to Figure 4, using an example in which the control device includes register 1, register 2 and register 3. Register 1 is configured to receive information used to trigger a virtual device interrupt, register 2 is configured to receive information used to trigger a virtual software interrupt, and register 3 is configured to receive information used to trigger a virtual local interrupt.

[0129] In the chip system shown in FIG. 4, the source physical processor is configured to run a host machine or a virtual machine, and the host machine or the virtual machine may have a permission level 1 and a permission level 2. The permission level 1 may be a user mode, and the permission level 2 may be a kernel mode. In different virtualization architectures, the states corresponding to the permission level 1 and the permission level 2 may be different. This is not limited in this embodiment of the present application.

[0130] In Figure 4 of the present application, four different lines are used to mark four types of virtual interrupts: the line marked with number 1 represents the process of handling virtual local interrupts, the line marked with number 2 represents the process of handling virtual software interrupts, the line marked with number 3 represents the process of handling virtual device interrupts, and the line marked with number 4 represents the process of handling direct peripheral interrupts.

[0131] 1. Virtual local interrupt

[0132] As shown in Figure 4, in the process of handling a virtual local interrupt, the relevant register is register 3, and the intermediate device may be called a local interrupt generating device. Because the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor, and the sending device corresponds to the source physical processor.

[0133] The register is configured to receive information that is written by the virtual machine and used to trigger a virtual local interrupt.

[0134] The local interrupt generating device is configured to generate a virtual local interrupt based on the information used to trigger the virtual local interrupt.

[0135] The sending unit is configured to send the virtual local interrupt to a first virtual processor vCPU of a virtual machine, the first vCPU running on the source physical processor.

[0136] According to the process of handling virtual local interrupts provided in this embodiment of the present application, one physical processor only runs one vCPU of one virtual machine at a time, and the operation of sending virtual local interrupts to the virtual machine can be completed by sending the virtual local interrupt to the vCPU. The local interrupt generating device in FIG. 4 may be a timer, and the virtual local interrupt may be a clock interrupt. In a clock interrupt scenario, one implementation of the process can be understood with reference to FIG. 5. As shown in FIG. 5, the virtual machine writes an interrupt time to the control device (the process can be understood with reference to register 3 in FIG. 4). The control device writes the interrupt time to the timer, and the timer is started accordingly. When the preset time is reached, the timer sends a clock interrupt. After receiving the clock interrupt, the sending device determines that the first vCPU of the virtual machine is running, and sends a clock interrupt to the first vCPU.

[0137] From the process of Figures 4 and 5, it can be seen that in the process of handling the virtual local interrupt, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead occurring during handling the virtual local interrupt and improving the performance of the chip system.

[0138] 2. Virtual Software Interrupts

[0139] As shown in Figure 4, in the process of handling the virtual software interrupt, the relevant register is register 2, and the intermediate device may be called a routing device. A first vCPU of the virtual machine runs on the source physical processor, and a second vCPU of the virtual machine runs on the target physical processor.

[0140] The register is configured to receive an identifier of the second vCPU written by the first vCPU.

[0141] The control device is configured to read the identifier of the second vCPU from the register to obtain an identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0142] The intermediate device is configured to perform a step of determining a target physical processor corresponding to the virtual machine identifier and the second vCPU identifier from the first correspondence based on the virtual machine identifier and the second vCPU identifier, the first correspondence being used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and a step of sending a virtual software interrupt to a sending device corresponding to the target physical processor.

[0143] The sending unit is configured to send the virtual software interrupt to a second vCPU executing on the target physical processor.

[0144] In the process of handling the virtual software interrupt in this embodiment of the present application, the control device may obtain the identifier of the virtual machine from a dedicated register that stores the identifier of the virtual machine running on the source physical processor. Each virtual machine may have multiple vCPUs, and the identifiers of the vCPUs of different virtual machines may be the same. Therefore, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The intermediate device may store the first correspondence. The first correspondence may be located in an imposition vCPU identifier group. The imposition vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPUs running on each physical processor, and the virtual machine to which the running vCPU belongs. In the present application, the target physical processor may be determined by searching the imposition vCPU identifier group. From the above description, it can be seen that in the process of handling the virtual software interrupt, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead occurring during the processing of the virtual software interrupt and improving the performance of the chip system.

[0145] The imposition vCPU identifier group may be understood with reference to FIG. 6. The meaning shown in FIG. 6 is as follows: vCPU 1 of VM1 runs on physical processor 1, vCPU 2 of VM1 runs on physical processor 2, vCPU 1 of VM2 runs on physical processor 3, and vCPU 2 of VM2 runs on physical processor 4. When the routing device receives the identifier of VM1 and the identifier of vCPU 2 from the control device, it can determine that vCPU 2 runs on physical processor 2 based on the imposition vCPU identifier group shown in FIG. 6. That is, a virtual software interrupt may be sent to a sending device corresponding to physical processor 2, and the sending device corresponding to physical processor 2 sends the virtual software interrupt to vCPU 2 running on physical processor 2.

[0146] If the second vCPU is not found by using the imposition vCPU identifier group, it indicates that the second vCPU is not currently running. In this case, the routing device may send the virtual software interrupt to the sending device of the source physical processor, which sends the virtual software interrupt to the host machine, and after the second vCPU is online and running, the host machine sends the virtual software interrupt to the second vCPU.

[0147] Because a physical processor may run different vCPUs at different times, the correspondence within the imposition vCPU identifier group may change. The imposition vCPU identifier group within the routing device may be managed by the host machine on the source physical processor.

[0148] The process of handling a virtual software interrupt in this embodiment of the present application can be understood with reference to FIG. 7. A virtual machine runs on a source physical processor, and a first vCPU of the virtual machine runs on the source physical processor. A second vCPU runs on another physical processor, and the first vCPU needs to send a virtual software interrupt to the second vCPU. In this case, the first vCPU of the virtual machine writes an identifier of the second vCPU to register 2 of the control device. The control device finds an identifier of the virtual machine, and sends the identifier of the virtual machine and the identifier of the second vCPU to a routing device. The routing device searches the imposition vCPU identifier group, for example, shown in FIG. 6, based on the identifier of the virtual machine and the identifier of the second vCPU, and determines that the physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU is the target physical processor. Then, the routing device sends the virtual software interrupt to a sending device corresponding to the target physical processor, and the sending device corresponding to the target physical processor sends the virtual software interrupt to the second vCPU, which is a virtual machine running on the target physical processor.

[0149] From the processes in Figures 4, 6 and 7, it can be seen that in the process of processing the virtual software interrupt provided in this embodiment of the present application, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead occurring during the processing of the virtual software interrupt and improving the performance of the chip system.

[0150] 3. Virtual Device Interrupts

[0151] As shown in Figure 4, in the process of handling a virtual device interrupt, the relevant register is register 1 and the intermediate device is the routing device. The host machine runs on the source physical processor and the host machine is in user mode.

[0152] The registers are configured to receive a target interrupt number and a virtual machine identifier written by the host machine. The target interrupt number is the identifier of the interrupt that will be triggered when the host machine simulates the hardware device.

[0153] The controller is configured to read the target interrupt number and the virtual machine identifier from the register and to send the virtual machine identifier and the target interrupt number to the intermediate device.

[0154] The intermediate device is configured to perform the steps of: searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, where the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, where the third correspondence is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and sending the virtual device interrupt to a sending device corresponding to the target physical processor.

[0155] The sending unit is configured to send the virtual device interrupt to a first vCPU executing on the target physical processor.

[0156] In this embodiment of the present application, the virtual device interrupt is an interrupt triggered when the host machine in user mode simulates a hardware device. There may be multiple types of hardware devices, and the interrupt number for each type of hardware device is different. If the host machine simulates a disk, the target interrupt number is the interrupt number of the disk. Since the host machine may manage multiple virtual machines, the host machine needs to write the virtual machine identifier and the target interrupt number to a register. The second correspondence may be located in an interrupt affinity table. The interrupt affinity table may be configured by the virtual machine. Therefore, there is an interrupt affinity table for each virtual machine. In this way, the interrupt affinity table of the virtual machine may be found based on the virtual machine identifier, and then the corresponding vCPU is determined from the interrupt affinity table of the virtual machine based on the target interrupt number. The target interrupt number is 10. If the interrupt number 10 in the interrupt affinity table corresponds to vCPU ID 1, it may be determined that the vCPU ID corresponding to the target interrupt number is 1. After determining that the vCPU ID is 1, the routing device may find a physical processor corresponding to the vCPU ID 1 based on the inposition vCPU identifier group. For the meaning of the inposition vCPU identifier group, please refer to the description of the virtual software interrupt for understanding. For the third correspondence, please refer to the first correspondence for understanding.

[0157] The following describes the virtual machine interrupt affinity table with reference to Table 1. [Table 1]

[0158] Table 1 is merely an example, and the correspondence is not limited to the few types listed in Table 1. Alternatively, there may be other representational correspondences, and the amount may be greater. An additional column may be added to Table 1, and the additional column is used to store the identifiers of the virtual machines in FIG. 4.

[0159] The interrupt affinity table may be stored in the routing device or may be stored in memory. The routing device may provide an address register for each physical processor. The address register may be a base address register. The base address register may store an address of the interrupt affinity table in memory and an identifier of the virtual machine. As shown in FIG. 8, base address register 1 on the routing device corresponds to physical processor 1, base address register 2 corresponds to physical processor 2, base address register 3 corresponds to physical processor 3, and base address register 4 corresponds to physical processor 4. The address in each base address register points to one interrupt affinity table. For example, base address register 1 points to interrupt affinity table 1, base address register 2 points to interrupt affinity table 2, base address register 3 points to interrupt affinity table 3, and base address register 4 points to interrupt affinity table 4. If the same virtual machine is running on two physical processors, the addresses of the base address registers corresponding to the two physical processors may be the same, and the interrupt affinity table pointed to may be the same table.

[0160] Thus, in the process of handling the virtual device interrupt, the virtual machine writes the target interrupt number to register 1, the controller reads the identifier of the currently running virtual machine from a dedicated register that stores the virtual machines running on the source physical processor, and then the controller sends the target interrupt number and the identifier of the virtual machine to the routing device. The routing device determines a corresponding interrupt affinity table based on the identifier of the virtual machine, and then uses the target interrupt number to search the interrupt affinity table for the identifier of the corresponding vCPU. If the target interrupt number is 10, it may be determined that the identifier of the corresponding vCPU is 1. After determining that the identifier of the vCPU is 1, the routing device may find that the processor corresponding to vCPU 1 is physical processor 1 based on the imposition vCPU identifier group shown in FIG. 6. The routing device may send the virtual device interrupt to a sending device corresponding to physical processor 1, and the sending device may send the virtual device interrupt to the first vCPU corresponding to vCPU 1.

[0161] If the first vCPU is not found by using the imposition vCPU identifier group, it indicates that the first vCPU is not currently running, in which case the routing device sends a virtual software interrupt to the sending device of the source physical processor, which sends the virtual software interrupt to the host machine, and after the first vCPU is online and running, the host machine sends the virtual software interrupt to the first vCPU.

[0162] From the processes in Figure 4, Table 1, Figure 8 and Figure 6, it can be seen that in the process of handling the virtual device interrupt provided in this embodiment of the present application, the source physical processor does not need to switch from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead occurring in handling the virtual device interrupt and improving the performance of the chip system.

[0163] 4. Direct Peripheral Interrupts

[0164] As shown in FIG. 4, a direct peripheral interrupt is an interrupt triggered by a hardware device that is directly connected to a virtual machine, for example, a graphics card that is directly connected to a virtual machine. The intermediate device may be called a routing device. For a direct peripheral interrupt, this type of interrupt handling process may be implemented by using a routing device and a sending device. This process includes the following steps:

[0165] The intermediate device is configured to perform the steps of: receiving a direct peripheral interrupt triggered by a hardware device; searching a virtual interrupt table for a corresponding virtual machine identifier and virtual interrupt number based on a physical interrupt number of the direct peripheral interrupt, where the virtual interrupt table records a correspondence between the physical interrupt number, the virtual machine identifier, and the virtual interrupt number; determining a corresponding interrupt affinity table based on the virtual machine identifier and determining an identifier of a target virtual processor vCPU corresponding to the virtual machine identifier and the virtual interrupt number from the interrupt affinity table, where the interrupt affinity table records a correspondence between the virtual processor and the virtual interrupt number; determining a target physical processor corresponding to the identifier of the target vCPU from an imposition vCPU identifier group based on the identifier of the target vCPU; and sending the direct peripheral interrupt to a sending device corresponding to the target physical processor.

[0166] The sender is configured to send a peripheral interrupt directly to a virtual machine running on the target physical processor.

[0167] In this embodiment of the present application, in the process of handling direct peripheral interrupts, the virtual interrupt table, the interrupt affinity table, and the imposition vCPU identifier group are used in order. For the interrupt affinity table and the imposition vCPU identifier group, please refer to the above description. The following describes the virtual interrupt table.

[0168] The virtual interrupt table maintains a mapping relationship between a physical interrupt number, a virtual machine identifier, and a virtual interrupt number. When a physical interrupt number is input, a virtual machine identifier and a virtual interrupt number can be output. The virtual interrupt table can be understood with reference to Table 2. [Table 2]

[0169] As shown in Table 2, if a physical interrupt number of 100 is input, a virtual machine identifier of 1 and a virtual interrupt number of 10 may be output. The virtual interrupt table herein may be stored in a routing device or may be stored in memory, with the location of the virtual interrupt table in memory indicated using another register similar to the base address register.

[0170] In the process of handling the direct peripheral interrupt, as shown in FIG. 9, the routing device receives the physical interrupt number sent by the direct peripheral device, and uses the physical interrupt number to search the virtual interrupt table for a corresponding virtual machine identifier and virtual interrupt number. For example, if the physical interrupt number 100 is input, the virtual machine identifier 1 and virtual interrupt number 10 may be output. Then, based on the virtual machine identifier 1 and the virtual interrupt number 10, the interrupt affinity table in Table 1 is searched to find the corresponding vCPU identifier. For example, it is found that the vCPU identifier is 1. Furthermore, based on the vCPU 1, the imposition vCPU identifier group shown in FIG. 6 is searched for a corresponding physical processor. For example, if the physical processor 1 is found, the routing device sends the direct peripheral interrupt to the sending device corresponding to the physical processor 1, and the sending device sends the direct peripheral interrupt to the first vCPU corresponding to the vCPU 1.

[0171] If the first vCPU is not found by using the imposition vCPU identifier group, it indicates that the first vCPU is not currently running, in which case the routing device may send a virtual software interrupt to a sending device of the source physical processor, the sending device of the source physical processor may send a virtual software interrupt to a host machine, and after the first vCPU is online and running, the host machine may send a virtual software interrupt to the first vCPU.

[0172] From the process in Figure 4, Table 2, Table 1, Figure 6 and Figure 9, it can be seen that in the process of handling direct peripheral interrupts provided in this embodiment of the present application, the sending process can be completed by searching for three correspondences, thereby improving the flexibility of handling direct peripheral interrupts.

[0173] In the process of handling the above four types of virtual interrupts, after receiving any of the above four types of virtual interrupts from the intermediate device, the sending device sends the virtual interrupt to the corresponding target physical processor. The sending process may write the above types of virtual interrupts to a pending register, which is configured to receive a command to be executed by the target physical processor thereafter. After the virtual interrupt is written to the pending register, the target physical processor executes the virtual interrupt. In this way, the currently executed procedure may be interrupted. If the target vCPU is running, the target vCPU is interrupted and the interrupt is sent to the target vCPU. If the host machine is running, the host machine is interrupted and the interrupt is sent directly to the running host machine. When the corresponding target vCPU is online, the host machine transfers the interrupt to the target vCPU. The target vCPU may be the first vCPU or the second vCPU described above. In this way, the solution provided in this embodiment of the present application can shield the switching action to the host machine in the existing solution, thereby reducing the overhead of switching the target physical processor from the virtual machine to the host machine.

[0174] The chip system provided in this embodiment of the present application may be applied to RISC-V microarchitecture. RISC is reduced instruction set computing. Figure 10 is a schematic diagram of the structure of the chip system on RISC-V.

[0175] As shown in Fig. 10, the chip system includes a control device and a transmission device configured to interact with the physical processor, and an interrupt router, which includes the routing device described in the previous embodiments.

[0176] In Figure 10, RISC-V-CPU represents the central processing unit in the RISC-V architecture, V=0 represents the host machine, V=1 represents the virtual machine, HU mode represents the user mode of the host machine, HS mode represents the kernel mode of the host machine, VU mode represents the user mode of the virtual machine, and VS mode represents the kernel mode of the virtual machine. The supervisor generate inter-processor interrupt logic (sgenipi) is used to trigger the virtual software interrupt information, and the supervisor time compare logic (stimecmp) is used to trigger the register of the virtual local interrupt information. When V=1, i.e., the virtual machine is running on a RISC-V-CPU, the information used to trigger the virtual software interrupt may be sent to the controller's virtual supervisor generate inter-processor interrupt (vsgenipi) register through sgenipi, where the vsgenipi register is a register used to receive information used to trigger the virtual software interrupt as described in the previous embodiment, e.g., register 2. The information used to trigger the virtual local interrupt may be sent to the controller's virtual supervisor time compare (vstimecmp) register through stimecmp, where the vstimecmp register is a register used to receive information used to trigger the virtual local interrupt as described in the previous embodiment, e.g., register 3.The user generate virtual supervisor external interrupt (ugenvsei) register is a register configured to receive information used to trigger a virtual device interrupt, such as register 1 described in the previous embodiment. The information used to trigger a virtual device interrupt may be sent directly to the ugenvsei register through user mode virtual device simulation logic in the host machine.

[0177] An implementation of an interrupt router includes a virtual hart shared interrupt mapping (vhsimap) register, a group of virtual table base (vtblbase)(1-n) registers, and a group of interrupt control interface mapping (ifmap) registers. The vhsimap(1-n) registers are used to point to a virtual interrupt table stored in memory. Each vtblbase register in the group of vtblbase(1-n) registers corresponds to a physical processor in the RISC-V system and is used to point to a virtual interrupt affinity table defined by the virtual machine to which the vCPU running on the physical processor belongs. A group of ifmap(1-n) registers is provided, each of which corresponds to a physical processor in the system and is used to record the identifier of the vCPU running on the physical processor and the identifier of the virtual machine to which the vCPU belongs.

[0178] In the RISC-V architecture shown in FIG. 10, the process of handling virtual clock interrupts can be understood with reference to FIG. 11.

[0179] As shown in Figure 11, the virtual machine writes the interrupt time to the vstimecmp register through stimecmp, and the control device writes the time to trigger the next virtual clock interrupt to the virtual machine's dedicated clock device. When the interrupt time arrives, the virtual machine's dedicated clock device triggers a virtual clock interrupt. The virtual clock interrupt is sent to the sending device.

[0180] The sender makes the decision based on the current virtualization state V of the CPU: if V=1, the sender sends the local interrupt directly to the virtual machine in VS mode; if V=0, the sender sends the local interrupt to the host machine in HS mode, which processes it on behalf of the virtual machine, i.e., the host machine forwards the virtual clock interrupt to the virtual machine after it comes online.

[0181] In the RISC-V architecture shown in FIG. 10, the process of handling virtual software interrupts can be understood with reference to FIG. 12.

[0182] As shown in FIG. 12, the vCPU of the virtual machine (which may be referred to as the source vCPU in this scenario) runs on CPU 1. CPU 1 may be the source physical processor in the previous embodiment. The source vCPU of the virtual machine writes the identifier of the target vCPU to sgenipi, and uses sgenipi to write the identifier of the target vCPU to the vsgenipi register in the controller. The controller obtains the identifier of the virtual machine and sends the identifier of the virtual machine and the identifier of the target vCPU (vhartid: identifier of the vCPU in RISC-V) to the interrupt router. The interrupt router searches ifmapx, and the sequence number x of the ifmapx register containing the VM ID and vhartid is the identifier of the corresponding physical processor (mhartid: identifier of the physical processor in RISC-V). In this scenario, the identifier of the physical processor is CPU 2 in FIG. 12. CPU 2 may be understood with reference to the target physical processor in the previous embodiment. The interrupt router sends a virtual software interrupt to the sending device of the physical processor of mhartid. The sending device determines the current virtualization state of the physical processor. When V=1, the sender sends the virtual software interrupt directly to the virtual machine. When V=0, the sender sends the virtual software interrupt to the host machine for processing, i.e., the host machine sends the virtual software interrupt to the virtual machine after the virtual machine is online.

[0183] In the RISC-V architecture shown in FIG. 10, the process of handling virtual device interrupts can be understood with reference to FIG. 13.

[0184] As shown in Figure 13, the host machine in user mode writes the virtual machine identifier and virtual interrupt number to ugenvsei. The controller sends the virtual machine identifier and virtual interrupt number to the interrupt router. The interrupt router searches the vtblbasex registers to find the vtblbasex register with the virtual machine identifier among the vtblbasex registers. The interrupt affinity table stored in memory that the register points to is searched. The vhartid of the vCPU that will handle the interrupt is obtained from the interrupt affinity table. The interrupt router searches ifmapx to find the physical processor sequence number x that corresponds to the register with VM ID and vhartid, where x is the mhartid of the target physical processor. The interrupt router sends the virtual device interrupt to the sender of the physical processor with mhartid. The sender determines the current virtualization state of the CPU. If V=1, the sender sends the device interrupt directly to the virtual machine. Otherwise, if V=0, the sender sends the device interrupt to the host machine for handling. That is, after the virtual machine is brought online, the host machine sends a virtual device interrupt to the virtual machine.

[0185] In the RISC-V architecture shown in FIG. 10, another process for handling virtual device interrupts can be understood with reference to FIG. 14.

[0186] As shown in Figure 14, the host machine writes the virtual machine's identifier and virtual interrupt number to ugenvsei. The controller sends the virtual machine's identifier and virtual interrupt number to the interrupt router. The interrupt router does not implement vtblbasex and by default sends the virtual interrupt to any vCPU with the virtual machine. The interrupt router then looks up ifmapx and finds the physical processor sequence number x that corresponds to the register with the virtual machine's identifier, where x is the mhartid of the target physical processor. The interrupt router sends the virtual device interrupt to the sender of the physical processor with mhartid. The sender determines the current virtualization state of the physical processor. If V=1, the sender sends the virtual device interrupt directly to the virtual machine. Otherwise, if V=0, the sender sends the virtual device interrupt to the host machine for processing. That is, the host machine sends the virtual device interrupt to the virtual machine after the virtual machine is online.

[0187] In the RISC-V architecture shown in FIG. 10, the process of handling direct peripheral interrupts can be understood with reference to FIG. 15.

[0188] As shown in FIG. 15, when a hardware device that directly communicates with a virtual machine triggers a direct peripheral interrupt, the interrupt router searches the virtual interrupt table pointed to by vhlimap to find the identifier of the virtual machine to which the interrupt is directly connected and the virtual interrupt number to be considered in the virtual machine after the interrupt is directly connected. The interrupt router searches the vtblbasex registers, finds one among them with a VM ID, and searches the virtual interrupt affinity table stored in memory to which it points. The vhartid of the vCPU that will handle the interrupt is obtained from the interrupt affinity table. The interrupt router searches ifmapx to find the sequence number x of the physical processor that corresponds to the register with the VM ID and vhartid, where x is the mhartid of the target physical processor. The interrupt router sends the direct peripheral interrupt to the sender of the physical processor with mhartid. The sender determines the current virtualization state of the CPU. If V=1, the sender sends the direct peripheral interrupt directly to the virtual machine. Alternatively, if V=0, the sender directly sends the peripheral interrupt to the host machine for processing, i.e., the host machine directly sends the peripheral interrupt to the virtual machine after the virtual machine comes online.

[0189] According to the above-mentioned solution provided in this embodiment of the present application, a virtual local interrupt is implemented using a controller, an intermediate device, and a sending device, so that the whole process does not trap out to the host machine from the local interrupt device to the vCPU. By using a controller, a routing device, and a sending device, a virtual software interrupt is implemented without software cooperation between the virtual machine and the host machine, so that the whole process does not trap out to the host machine from the sending end vCPU to the receiving end vCPU. By using a controller, a routing device, and a sending device, a virtual device interrupt is implemented, so that the whole process does not switch context / trap out to the host machine from the host machine analog logic to the receiving end host vCPU. Therefore, the solution provided in this embodiment of the present application can accelerate the performance of the virtual machine in terms of I / O, clock, scheduling, etc. Simulation data shows that when the virtual local interrupt is handled using this solution, Redis is improved by 80% and the handling of the virtual software interrupt is increased by 6%.

[0190] The above describes a process of handling a virtual interrupt using a hardware circuit. The process of handling a virtual interrupt provided in this embodiment of the present application may be implemented using software. The process implemented using software may be combined in the aforementioned chip system. The chip system includes a source physical processor, a control device, an intermediate device, and a sending device. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The functions of the control device, the intermediate device, and the sending device may be implemented in the form of software code. The following provides a description with reference to the accompanying drawings.

[0191] As shown in FIG. 16, an embodiment of a virtual interrupt processing method according to an embodiment of the present application includes the following steps.

[0192] 101: The controller reads information from a register that is used to trigger a virtual interrupt.

[0193] The information used to trigger the virtual interrupt originates from a virtual machine or a host machine running on a source physical processor.

[0194] 102: The control device transmits information used to trigger a virtual interrupt to the intermediate device. In response, the intermediate device receives the information used to trigger a virtual interrupt.

[0195] 103: The intermediate device triggers a virtual interrupt based on the information used to trigger the virtual interrupt.

[0196] 104: The intermediate device sends a virtual interrupt to the sending device. In response, the sending device receives the virtual interrupt.

[0197] 105: The sending unit sends the virtual device interrupt to the target physical processor.

[0198] According to the solution provided in this embodiment of the present application, a register dedicated to handling virtual interrupts is placed in the control device. In this way, the virtual machine or the host machine in user mode can directly write the information used to trigger the virtual interrupt to the register. The control device sends the information used to trigger the virtual interrupt to the intermediate device, which triggers the virtual interrupt. The intermediate device also sends the virtual interrupt to the sending device, which sends the virtual interrupt to the target physical processor. In the solution provided in the present application, the host machine or the virtual machine may directly access the register and write the information used to trigger the virtual interrupt to the register. The virtual interrupt is then sent. Therefore, compared with the conventional technology, in the solution provided in the present application, the source physical processor does not need to switch from the virtual machine to the host machine, or the source physical processor does not need to switch from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead generated during virtual interrupt handling and improving the performance of the chip system.

[0199] If the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor. The register receives information written by the virtual machine that is used to trigger the virtual local interrupt.

[0200] The intermediate device generates a virtual local interrupt based on the information used to trigger the virtual local interrupt.

[0201] The sending device sends a virtual local interrupt to a first virtual processor vCPU of a virtual machine, the first vCPU running on the source physical processor.

[0202] If the virtual interrupt is a virtual software interrupt, the information read from the register in step 101 and used to trigger the virtual interrupt includes an identifier of a second vCPU written to the register by the first vCPU of the virtual machine, where the second vCPU is a vCPU of a virtual machine running on the target physical processor.

[0203] Before step 102, the control device obtains the identifier of the virtual machine. In this case, step 103 specifically includes: sending the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0204] Step 103 specifically includes the following steps: the intermediate device determines, based on the virtual machine identifier and the second vCPU identifier, from the first correspondence, a target physical processor corresponding to the virtual machine identifier and the second vCPU identifier, where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and triggering a virtual software interrupt.

[0205] Step 104 includes: the intermediate device sending a virtual software interrupt to a sending device corresponding to the target physical processor.

[0206] Step 105 includes: a sending device sending a virtual software interrupt to a second vCPU running on the target physical processor.

[0207] If the virtual interrupt is a virtual device interrupt, the information read from the register in step 101 and used to trigger the virtual interrupt includes the target interrupt number written to the register by the host machine and an identifier of the virtual machine. The target interrupt number is the identifier of the interrupt that is to be triggered when the host machine simulates the hardware device.

[0208] Step 102 includes: the controller sending the virtual machine identifier and the target interrupt number to the intermediate device.

[0209] Step 103 includes: the intermediate device searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, where the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining a target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, where the third correspondence is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and generating a virtual device interrupt.

[0210] Step 104 includes: the intermediate device sends a virtual device interrupt to a sending device corresponding to the target physical processor.

[0211] Step 105 includes: a sending device sends a virtual device interrupt to a first vCPU running on a target physical processor.

[0212] The functions of the control device, intermediate device, and transmitting device implemented using software can be understood by referring to the corresponding contents in the embodiments corresponding to Figures 2 to 15, and the details will not be described again here.

[0213] The above describes a method for handling virtual interrupts implemented using software. The following describes an apparatus for implementing the above method for handling virtual interrupts with reference to the accompanying drawings.

[0214] As shown in FIG. 17, an embodiment of the control device 20 provided in this embodiment of the present application includes: the control device 20 applies to a chip system, and the chip system further includes a source physical processor, an intermediate device, a sending device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register, and the register is configured to receive information used to trigger a virtual interrupt, and the information used to trigger a virtual interrupt is from the host machine or the virtual machine. The control device 20 includes: a read unit 201 configured to read information from the register that is used to trigger a virtual interrupt; and A sending unit 202 configured to send information read by the reading unit 201 and used to trigger a virtual interrupt to an intermediate device, where the information used to trigger a virtual interrupt is used by the intermediate device to trigger a virtual interrupt, and the virtual interrupt is sent by the sending unit to a target physical processor.

[0215] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU executing on the source physical processor.

[0216] Optionally, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes an identifier of a second vCPU written by the first vCPU of the virtual machine, where the second vCPU is a vCPU of the virtual machine running on the target physical processor. The control device 20 further includes a processing unit 203.

[0217] The processing unit 203 is configured to obtain an identifier of the virtual machine.

[0218] The sending unit 202 is configured to send an identifier of the virtual machine to the intermediate device, where the identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine a target physical processor and trigger a virtual software interrupt, and the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0219] Optionally, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number written to a register by the host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt triggered when the host machine simulates a hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine a target physical processor to trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to a first vCPU of the target physical processor.

[0220] As shown in FIG. 18, an embodiment of the intermediate device 30 according to an embodiment of the present application includes: the intermediate device 30 is applied to a chip system, and the chip system further includes a source physical processor, a control device, a sending device, and a target physical processor. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register, and the register is configured to receive information used to trigger a virtual interrupt, and the information used to trigger a virtual interrupt is from the host machine or the virtual machine. The intermediate device 30 includes: a receiving unit 301 configured to receive information from a control device, which is used to trigger a virtual interrupt; a processing unit 302 configured to trigger a virtual interrupt based on the information used to trigger the virtual interrupt; and A sending unit 303 configured to send a virtual interrupt to a sending device, the virtual interrupt being sent by the sending device to a target physical processor.

[0221] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt, the information used to trigger the virtual local interrupt is used to trigger a virtual local interrupt, and the virtual local interrupt is sent by the sending device to a first virtual processor vCPU of the virtual machine, the first vCPU executing on the source physical processor.

[0222] Optionally, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes an identifier of a second vCPU written by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor.

[0223] The processing unit 302 is configured to perform the steps of: determining a target physical processor corresponding to the virtual machine identifier and the second vCPU identifier from the first correspondence based on the virtual machine identifier and the second vCPU identifier, where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; and triggering a virtual software interrupt, where the virtual software interrupt is sent by a sending device to the second vCPU of the target physical processor.

[0224] Optionally, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number written to a register by the host machine and an identifier of the virtual machine, the target interrupt number being an identifier of the interrupt that is to be triggered when the host machine simulates the hardware device.

[0225] The processing unit 302 is configured to perform: searching a second correspondence for an identifier of a first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number based on the virtual machine identifier and the target interrupt number, where the second correspondence is used to record a correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining a target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence based on the virtual machine identifier and the identifier of the first vCPU, where the third correspondence is used to record a correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and triggering a virtual device interrupt, where the virtual device interrupt is sent to the first vCPU of the target physical processor by a sending device.

[0226] Optionally, the processing unit 302 is further configured to find an address register based on the identifier of the virtual machine, and retrieve a second correspondence from a memory based on an address in the address register, where the address register is configured to store an address of the second correspondence in the memory and the identifier of the virtual machine.

[0227] As shown in FIG. 19, an embodiment of the sending device 40 according to an embodiment of the present application includes: the sending device 40 is applied to a chip system, and the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes a register, and the register is configured to receive information used to trigger a virtual interrupt, and the information used to trigger a virtual interrupt is from the host machine or the virtual machine. The sending device 40 includes: a receiving device 401 configured to receive a virtual interrupt from an intermediate device; and A sending unit 402 configured to send a virtual interrupt to a target physical processor.

[0228] Optionally, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The sending unit 402 is configured to send the virtual local interrupt to a first virtual processor vCPU of the virtual machine, where the first vCPU runs on the source physical processor.

[0229] Optionally, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes an identifier of a second vCPU written by a first vCPU of the virtual machine, the second vCPU being a vCPU of the virtual machine running on the target physical processor.

[0230] The sending unit 402 is configured to: send the virtual software interrupt to a second vCPU running on the target physical processor.

[0231] Optionally, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number written to a register by the host machine and an identifier of the virtual machine, the target interrupt number being an identifier of the interrupt to be triggered when the host machine simulates the hardware device.

[0232] The sending unit 402 is configured to: send a virtual device interrupt to a first vCPU running on the target physical processor.

[0233] Optionally, the sending unit 402 is configured to write the virtual interrupt to a pending register of the target physical processor, the pending register being configured to receive a command for a procedure to be executed by the target physical processor.

[0234] For the solutions described in Figures 17 to 19, please refer to the corresponding contents in the embodiments corresponding to Figures 2 to 15 for understanding, and the details will not be described again here.

[0235] FIG. 20 is a schematic diagram of a possible logical structure of a computing device 50 according to an embodiment of the present application. The computing device 50 may include a control device, an intermediate device, or a transmission device as described in FIG. 17 to FIG. 19. The computing device 50 includes a processor 501, a communication interface 502, a memory 503, and a bus 504. The processor 501, the communication interface 502, and the memory 503 are interconnected through the bus 504. In this embodiment of the present application, the processor 501 is configured to control and manage the actions of the computing device 50. For example, the processor 501 is configured to execute step 101 or 103 in the method embodiment of FIG. 16. The memory 503 is configured to store program codes and data for the computing device 50. The communication interface 502 may be configured to execute step 102, 104, or 105 in the method embodiment of FIG. 16.

[0236] Furthermore, the processor 501 may be a central processing unit, a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The processor may implement or execute various exemplary logic blocks, modules, and circuits described with reference to the contents disclosed in this application. Alternatively, the processor 501 may be a combination of processors that implement computing functions, such as a combination of one or more microprocessors, or a combination of a digital signal processor and a microprocessor. The bus 504 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be classified into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line represents the bus in FIG. 20, but this does not mean that there is only one bus or only one type of bus.

[0237] In another embodiment of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores computer-executable instructions. When the processor of the device executes the computer-executable instructions, the device executes the virtual interrupt handling scheme executed by the control device, intermediate device, or sending device of FIG. 16.

[0238] In another embodiment of the present application, a computer program product is further provided. The computer program product includes computer-executable instructions, the computer-executable instructions being stored in a computer-readable storage medium. When a processor of a device executes the computer-executable instructions, the device performs the virtual interrupt handling method performed by the control device, intermediate device, or transmitting device of FIG. 16.

[0239] Another embodiment of the present application further provides a chip system, which includes a source physical processor, a control device, a sending device, and a target physical processor, wherein the control device is the control device described in the embodiment of Figures 2 to 15, and the sending device is the sending device described in the embodiment of Figures 2 to 15.

[0240] In one possible embodiment, the chip system may further include the intermediate devices described in the embodiments of Figures 2 to 15.

[0241] In one possible embodiment, the chip system is a processor, the source physical processor and the target physical processor are physical cores within the processor, the controller is a component located within the processor and coupled to the source physical processor, and the transmitter is a component located within the processor and coupled to the target physical processor. It can be understood that any physical core of a processor can be used as a receiver of a virtual interrupt. Thus, a physical core can be used as both a source physical processor and a target physical processor. Correspondingly, what is coupled to a physical core can include both a controller and a transmitter.

[0242] Those skilled in the art may recognize that the units and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware in combination with the examples described in the embodiments disclosed in this specification. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use various methods to implement the described functions for each specific application, but the implementation should not be considered to go beyond the scope of the embodiments of this application.

[0243] For the purpose of convenient description, the detailed operation processes of the above systems, devices, and units may refer to the corresponding processes in the above method embodiments, and details will not be described again here, as can be clearly understood by those skilled in the art.

[0244] In some embodiments provided in the present application, it should be understood that the disclosed system, device and method may be implemented in other ways. For example, the described device embodiment is merely an example. For example, the division into units is merely a logical division of functions, and may be divided in other ways in actual implementation. For example, multiple units or components may be combined or integrated into other systems, or some functions may be ignored or not performed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. Indirect couplings or communication connections between devices or units may be implemented electrically, mechanically, or in another way.

[0245] The units described as separate parts may or may not be physically separate. The parts shown as units may or may not be physical units. In other words, they may be in one location or distributed over multiple network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0246] Furthermore, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

[0247] When functions are implemented in the form of a software functional unit and sold or used as an independent product, those functions may be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may essentially, or the part that contributes to the prior art, or part of the technical solutions may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes some instructions for instructing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, etc.

[0248] The above description is merely a specific implementation of the embodiments of the present application, and is not intended to limit the scope of protection of the embodiments of the present application. Any variations or replacements that are easily determined by those skilled in the art within the technical scope disclosed in the embodiments of the present application fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application should be subject to the scope of protection of the claims.

Claims

1. a source physical processor, the source physical processor configured to act as a host machine or to run a virtual machine; A control device, the control device having a register, the register configured to receive information used to trigger a virtual interrupt, the information used to trigger the virtual interrupt originating from the host machine or the virtual machine; a control unit configured to transmit information in the register to the intermediate unit, the information being used to trigger the virtual interrupt; an intermediate device configured to transmit the virtual interrupt to a transmitting device; the sending device being configured to receive the virtual interrupt from the intermediate device and to send the virtual interrupt to the target physical processor; Chip system.

2. the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt; the sending device is configured to send the virtual local interrupt to a first virtual processor of the virtual machine, the first virtual processor running on the source physical processor; The chip system of claim 1 .

3. the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second virtual processor written to the register by a first virtual processor of the virtual machine, the second virtual processor being a virtual processor of the virtual machine running on the target physical processor; the control device is configured to read an identifier of the second virtual processor from the register to obtain an identifier of the virtual machine; and to transmit the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device: determining the target physical processor corresponding to the virtual machine identifier and the second virtual processor identifier from a first correspondence based on the virtual machine identifier and the second virtual processor identifier, the first correspondence being used to record the correspondence between the target physical processor, the second virtual processor running on the target processor, and the virtual machine; sending the virtual software interrupt to the sending device corresponding to the target physical processor; the sending device is configured to send the virtual software interrupt to the second virtual processor running on the target physical processor. The chip system of claim 1 .

4. the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number written to the register by the host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt that is triggered when the host machine simulates a hardware device; the control device is configured to read the target interrupt number and the virtual machine identifier from the register and send the virtual machine identifier and the target interrupt number to the intermediate device; The intermediate device: searching a second correspondence for an identifier of a first virtual processor of the virtual machine that corresponds to the identifier of the virtual machine and the target interrupt number based on the identifier of the virtual machine and the target interrupt number, the second correspondence being used to record a correspondence between the virtual machine, the target interrupt number, and the first virtual processor; determining the target physical processor corresponding to the virtual machine identifier and the first virtual processor identifier from a third correspondence based on the virtual machine identifier and the first virtual processor identifier, the third correspondence being used to record the correspondence between the target physical processor, the first virtual processor running on the target processor, and the virtual machine; sending the virtual device interrupt to the sending device corresponding to the target physical processor; the sending unit is configured to send the virtual device interrupt to the first virtual processor running on the target physical processor. The chip system of claim 1 .

5. the intermediate device having an address register configured to store the second corresponding address in memory and an identifier of the virtual machine; The intermediate device is further configured to: find the address register based on an identifier of the virtual machine; and obtain the second correspondence from the memory based on the address in the address register. The chip system according to claim 4.

6. A virtual interrupt processing method, the method being applied to a control device in a chip system, the chip system further comprising a source physical processor, an intermediate device, a sending device, and a target physical processor, the source physical processor being configured to act as a host machine or to run a virtual machine, the control device having a register, the register being configured to receive information used to trigger a virtual interrupt, the information used to trigger the virtual interrupt originating from the host machine or the virtual machine, the method comprising: reading information from the register used to trigger the virtual interrupt; and transmitting information used to trigger the virtual interrupt to the intermediate device, the information used to trigger the virtual interrupt being used to enable the intermediate device to transmit the virtual interrupt to the sending device, the virtual interrupt being transmitted by the sending device to the target physical processor. method.

7. the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt; the information used to trigger the virtual local interrupt is used by the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to a first virtual processor of the virtual machine, the first virtual processor running on the source physical processor; The method according to claim 6.

8. the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second virtual processor written to the register by a first virtual processor of the virtual machine, the second virtual processor being a virtual processor of the virtual machine running on the target physical processor; The method further comprises: obtaining an identifier for the virtual machine; and transmitting an identifier of the virtual machine to the intermediate device, the identifier of the virtual machine and the identifier of the second virtual processor being used by the intermediate device to determine the target physical processor and to trigger the virtual software interrupt, the virtual software interrupt being transmitted by the transmitting device to the second virtual processor of the target physical processor. The method according to claim 6.

9. the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number written to the register by the host machine and an identifier of the virtual machine, the target interrupt number being an identifier of an interrupt that is triggered when the host machine simulates a hardware device; the virtual machine identifier and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is sent by the sending device to a first virtual processor of the target physical processor. The method according to claim 6.

10. the intermediate device includes an address register configured to store a second corresponding address in memory and an identifier of the virtual machine; The method further comprises: finding, by the intermediate device, the address register based on an identifier of the virtual machine; and obtaining, by the intermediate device, the second correspondence from the memory based on the address in the address register.

10. The method of claim 9.

11. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method according to any one of claims 6 to 10.

12. A computing device, said computing device comprising a chip system according to any one of claims 1 to 5.

Images