Imaging apparatus

Abstract

To provide an imaging apparatus that has a configuration of sharing a transistor among a plurality of pixels and capable of imaging in a global shutter system.SOLUTION: An imaging apparatus has a configuration that shares: a transistor that resets a potential of a charge detection unit in a plurality of pixels; a transistor that outputs a signal corresponding to the potential of the charge detection unit; and a transistor that selects a pixel. The imaging apparatus has a node AN (a first charge holding unit), a node FD (a second charge holding unit) and a node FDX (a charge detection unit). The imaging apparatus performs operation in which image data acquired in the node AN is transferred to the node FD, the image data is sequentially transferred to the node FDX and read out.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device and an operating method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Oxide semiconductors have been attracting attention as a semiconductor material that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor. Techniques for producing such a capacitor have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, an imaging device in which a transistor including an oxide semiconductor is used as part of a pixel circuit is It is disclosed in patent document 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0007] CMOS image sensors are being installed in a variety of devices, and are used for capturing high-resolution images. To obtain high-resolution images, highly integrated pixels are necessary. Therefore, the area per pixel must be reduced.

[0008] When reducing the area of ​​a pixel, not only is the design rule reduced, but also the size of devices such as transistors. It is also effective to reduce the number of transistors in the pixel circuit. There is a method of sharing the same among multiple pixels.

[0009] In addition, the imaging device is a grommet that can capture images without distortion even when the subject is moving at high speed. However, the global shutter method is not suitable for this purpose. The image data is simultaneously acquired from all pixels and read out sequentially, so the charge storage section can store data for a long time. In addition, a charge storage section must be provided for each pixel, so When operating in a dual shutter system, a circuit that shares charge storage areas among multiple pixels is used. It is difficult to use the configuration.

[0010] Therefore, in one embodiment of the present invention, an imaging device in which a transistor can be shared among a plurality of pixels is provided. One of the objects of the present invention is to provide an image device that can share wiring among a plurality of pixels. It is an object of the present invention to provide an imaging device in which a plurality of pixels can be used. and a global shutter type imaging device that can capture images using the global shutter method. One of the purposes is to read out the data of the previous frame during the exposure period. Another object of the present invention is to provide an imaging device that can capture an image with less noise. Another object of the present invention is to provide an imaging device suitable for high-speed operation. One of the objects of the present invention is to provide an imaging device having a high resolution. Another object of the present invention is to provide an imaging device with a high degree of integration. Another object of the present invention is to provide an imaging device capable of imaging under low illuminance. Another object of the present invention is to provide an imaging device that can be used in a wide temperature range. Another object of the present invention is to provide an imaging device with a high aperture ratio. One of the objects of the present invention is to provide a high quality imaging device. Another object of the present invention is to provide a novel imaging device. Another object of the present invention is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to an imaging device in which a transistor or the like can be shared among a plurality of pixels. do.

[0013] One embodiment of the present invention is a semiconductor device including first to sixth transistors, a photoelectric conversion element, and a An imaging device having a first capacitance element and a second capacitance element, The electrode is electrically connected to one of the source and drain of the first transistor. One of the source or drain of the transistor is connected to the source or drain of the second transistor. The other of the source and drain of the first transistor is electrically connected to a third The first transistor is electrically connected to the source or drain of the second transistor. The other of the source and the drain is electrically connected to one electrode of the first capacitor element. The other of the source or drain of the transistor is connected to the source or drain of a fourth transistor. The other of the source and drain of the third transistor is electrically connected to the fifth transistor. a gate of the first transistor and a source or drain of a third transistor; The other electrode of the fifth transistor is electrically connected to one electrode of the second capacitor. Either the source or the drain of the sixth transistor is electrically connected to either the source or the drain of the sixth transistor. A first transistor, a second transistor, a third transistor and a fourth transistor are connected to each other. The transistor has an oxide semiconductor in a channel region. It is an imaging device.

[0014] Another embodiment of the present invention is an imaging device having a first pixel and a second pixel, The first pixel includes a first transistor, a second transistor, and a third transistor. , a fourth transistor, a fifth transistor, a sixth transistor, and a first photoelectric conversion The second pixel includes a first capacitance element, a first capacitance element, and a second capacitance element. The seventh transistor, the eighth transistor, the ninth transistor, and the fourth transistor a fifth transistor, a sixth transistor, a second photoelectric conversion element, and a third capacitor. The first photoelectric conversion element is configured to include a first capacitance element and a second capacitance element. a first transistor connected to the source or drain of the second transistor; The source or drain of the first transistor is connected to the source or drain of the second transistor. The other of the source and drain of the first transistor is electrically connected to the third transistor. the source or drain of the first transistor, The other of the drain and the drain is electrically connected to one electrode of the first capacitance element, and the third transistor The other of the source or drain of the first transistor is connected to the source or drain of the fourth transistor. The other of the source and drain of the third transistor is electrically connected to the fifth transistor. the other of the source or drain of the third transistor is electrically connected to the gate of the third transistor is electrically connected to one electrode of the second capacitor element, and One of the drains is electrically connected to one of the source and drain of the sixth transistor. One electrode of the second photoelectric conversion element is connected to one of the source and drain of the seventh transistor. and one of the source and drain of the seventh transistor is electrically connected to the eighth transistor. a source of the seventh transistor; Or the other of the drains is electrically connected to one of the source or drain of the ninth transistor. The other of the source and drain of the seventh transistor is connected to one of the electrodes of the third capacitance element. The other of the source or drain of the ninth transistor is electrically connected to the fourth transistor. the source or drain of the ninth transistor; The other of the drain and the gate of the fifth transistor is electrically connected to the gate of the ninth transistor. The other of the source and drain of the transistor is electrically connected to one electrode of the second capacitance element. The first transistor, the second transistor, the third transistor, and the fourth transistor The seventh transistor, the eighth transistor and the ninth transistor have a channel The imaging device includes an oxide semiconductor in a region where a light-emitting diode is formed.

[0015] The gate of the first transistor and the gate of the seventh transistor can be electrically connected. The gate of the second transistor and the gate of the eighth transistor are electrically connected to each other. It can be connected.

[0016] The other electrode of the first photoelectric conversion element and the other electrode of the second photoelectric conversion element are electrically connected. It is possible.

[0017] The oxide semiconductor is In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, In addition, the fifth transistor and The sixth transistor may also include an oxide semiconductor in a region in which a channel is formed.

[0018] The photoelectric conversion element may use selenium or a compound containing selenium in the photoelectric conversion layer. For example, the selenium may be amorphous or crystalline.

[0019] In another embodiment of the present invention, a first photoelectric conversion element is provided for a first charge accumulation portion of a first pixel. Accumulation of charge by the element and a second photoelectric conversion element to a first charge accumulation portion of a second pixel. a first step of storing electric charges by the first pixel at the same timing; The charge in the first charge storage unit is transferred to a second charge storage unit of the first pixel, and the second pixel is a transfer of charges in a first charge storage unit of the second pixel to a second charge storage unit of the second pixel; A second step is performed at the same timing, and a charge in a second charge storage portion of the first pixel is discharged. a third step of transferring the charge to a charge detector and reading out a signal corresponding to the potential of the charge detector; A fourth step of resetting the potential of the detection unit and A fifth step of transferring the charge to a charge detector and reading out a signal corresponding to the potential of the charge detector. and a sixth step of resetting the potential of the charge detection unit in the above order. The imaging device is operated in the same manner as in the first embodiment.

[0020] In the above operation method, the first step and the second step are performed in the n-th frame (n is 1 or more). The third to sixth steps are performed in the n+1th frame. good. Effect of the Invention

[0021] By using one embodiment of the present invention, a transistor can be shared among a plurality of pixels. Alternatively, it is possible to provide an imaging device in which wiring can be shared among a plurality of pixels. Alternatively, a transistor may be shared among a plurality of pixels, It is possible to provide an imaging device capable of imaging using a global shutter system. It is possible to provide an imaging device that reads out data of the previous frame during the exposure period. Alternatively, it is possible to provide an imaging device capable of capturing an image with less noise. Alternatively, it is possible to provide an imaging device suitable for high speed operation. Alternatively, a highly integrated imaging device can be provided. Alternatively, it is possible to provide an imaging device capable of imaging under low illuminance. It is possible to provide an imaging device that can be used in a wide temperature range. It is possible to provide an imaging device. Alternatively, it is possible to provide an imaging device with high reliability. Alternatively, a novel imaging device or the like can be provided. Alternatively, a novel semiconductor device or the like can be provided.

[0022] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0023] [Figure 1] FIG. 2 is a circuit diagram illustrating a pixel. [Diagram 2] FIG. 2 is a circuit diagram illustrating a pixel. [Diagram 3] 1A to 1C are a top view illustrating an imaging device, a circuit diagram of a CDS circuit, and a block diagram of an A / D conversion circuit. [Figure 4] FIG. 2 is a circuit diagram illustrating a pixel block. [Diagram 5] FIG. 2 is a circuit diagram illustrating a pixel block. [Figure 6] FIG. 2 is a circuit diagram illustrating a pixel block. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel block. [Figure 8] 4 is a flowchart illustrating the operation of the imaging apparatus. [Figure 9] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 10] 3A to 3C are diagrams illustrating the operation of the imaging apparatus. [Figure 11] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 12] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 13] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 14] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 15] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 16] FIG. 2 is a circuit diagram illustrating a pixel block. [Figure 17] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 18] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 19] 1A and 1B are a top view and a perspective view illustrating a configuration of an imaging apparatus. [Figure 20] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 21] FIG. 2 is a cross-sectional view illustrating a structure of a photoelectric conversion element. [Figure 22] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Diagram 23] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 24] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 25] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 26] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 27]FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 28] 1A and 1B are a cross-sectional view and a circuit diagram illustrating an imaging device. [Figure 29] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 30] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 31] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 32] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 33] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 34] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 35] 1A and 1B are diagrams illustrating a curved imaging device. [Diagram 36] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 37] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 38] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 39] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 40] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Diagram 41] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 42] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 43] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 44] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 45] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 46] FIG. 1 is a top view illustrating a transistor. [Figure 47] 1A and 1B are diagrams illustrating the range of atomic ratios of oxide semiconductors. [Figure 48] A diagram explaining the InMZnO4 crystal. [Figure 49] FIG. [Figure 50] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 51] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 52] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 53] Cross-sectional TEM image of a-like OS. [Figure 54] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 55] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 56] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 57] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0025] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0026] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0027] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0028] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0029] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0030] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.) voltage sources, current sources, switching circuits, amplifier circuits (which output large signal amplitudes or current amounts, etc.) (common circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal One or more circuits (generator, memory, control circuit, etc.) can be connected between X and Y. For example, even if there is another circuit between X and Y, the output from X is If a signal is transmitted to Y, then X and Y are said to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected, and cases where X and Y are functionally connected. and Y are electrically connected.

[0031] In addition, if it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., there is another element or circuit between X and Y), When X and Y are functionally connected (i.e., when X and Y are (X and Y are connected functionally with another circuit between them) and (X and Y are connected directly (That is, when X and Y are connected without any other element or circuit between them.) ) is considered to be disclosed in the present specification. If it is explicitly stated, it is simply stated as connected. The same contents as those in the above case are deemed to be disclosed in the present specification and the like.

[0032] For example, if the source (or the first terminal, etc.) of the transistor is connected to the ), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or the transistor The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and another part of Z1. is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z1 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0033] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., of the transistor are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. "The source of the transistor is electrically connected to the (or the first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor, The transistor's drain (or second terminal, etc.), and Y are electrically connected in that order. "X is connected to the source ( or the first terminal, etc.) and the drain (or the second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, and The second terminal (or terminal 2, etc.), Y, is provided in this connection order. Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0034] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor" ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second The first connection path is a path via Z1, and the second connection path is a path between the The drain (or second terminal, etc.) of the transistor is connected to the Y, the third connection path does not have the second connection path, and The third connection path is a path via Z2." or " The source (or first terminal, etc.) of the transistor is connected to the , electrically connected to X via Z1, and the first connection path has a second connection path the second connection path has a connection path passing through a transistor, The drain (or second terminal, etc.) of and the third connection path does not include the second connection path. "The source (or first terminal) of the transistor is etc.) is electrically connected to X through Z1 by at least a first electrical path; The first electrical path does not have a second electrical path, and the second electrical path is The source (or first terminal, etc.) of a transistor is connected to the drain (or third terminal, etc.) of a transistor. 2) and the drain (or second terminal, etc.) of the transistor. ) is electrically connected to Y through Z2 by at least a third electrical path, The third electrical path does not have a fourth electrical path, and the fourth electrical path is a The drain (or second terminal, etc.) of a transistor is connected to the source (or first terminal, etc.) of a transistor. The electrical path to the terminal of the By using the current method, the connection paths in the circuit configuration are defined, and the transistor Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of The technical scope can be determined based on the above.

[0035] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0036] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0037] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0038] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0039] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0040] One embodiment of the present invention is a transistor that resets a potential of a charge detection unit in a plurality of pixels; A transistor that outputs a signal corresponding to the potential of the charge detection section, and a transistor that selects a pixel A circuit for an image pickup device capable of sharing a common transistor and performing image pickup using a global shutter method. The configuration and operation method of the path. Also, in the nth frame (n is a natural number of 1 or more), Then, the imaging data can be read out in the (n+1)th frame.

[0041] This allows the number of transistors per pixel to be reduced, making the pixel area smaller. That is, the pixels can be highly integrated. Since the image data is read out in a single scan, the image capture time for the nth frame can be extended. This allows for a wide dynamic range with less noise and maintaining gradation even under low illumination. It is possible to obtain an image of the image.

[0042] In some or all of the transistors used in the pixels of the imaging device, an oxide is formed in a channel formation region. A transistor having a nitride semiconductor can be used. It is possible to easily configure a small memory for holding data within a pixel.

[0043] 1 is a circuit diagram of a pixel 20 included in an imaging device according to one embodiment of the present invention. In the following description, an example in which the transistor is an n-ch transistor is shown; however, one embodiment of the present invention is not limited to this. However, some of the transistors may be replaced with p-ch transistors.

[0044] In the pixel 20, one electrode of the photoelectric conversion element PD is connected to the source of the transistor 41 or One of the source and drain of the transistor 41 is electrically connected to the other of the drain. is electrically connected to one of the source and drain of the transistor 42. The other of the source or drain of the transistor 41 is connected to one of the source or drain of the transistor 43. The other of the source and the drain of the transistor 41 is electrically connected to a capacitance element C1. The source or drain of the transistor 43 is electrically connected to one of the electrodes of the transistor C1. The other end is electrically connected to one of the source and drain of the transistor 44. The other of the source and drain of the transistor 43 is electrically connected to the gate of the transistor 45. The other of the source and the drain of the transistor 43 is connected to one electrode of the capacitor C2. One of the source and drain of the transistor 45 is electrically connected to the transistor 46. ​​The transistor 46 is electrically connected to either the source or drain of the transistor 46.

[0045] Here, one electrode of the photoelectric conversion element PD and one of the source or drain of the transistor 41 A node AN to which the source or drain of the transistor 42 is connected is referred to as a first The other of the source and drain of the transistor 41 is a charge storage portion of the transistor A node to which one of the source or drain of the transistor 43 and one of the electrodes of the capacitance element C1 are connected. The node FD is a second charge storage section. On the other hand, one of the source or drain of the transistor 44, the gate and A node FDX to which one electrode of the capacitance element C2 is connected is used as a charge detection unit.

[0046] In FIG. 1, the other electrode of the photoelectric conversion element PD is electrically connected to a wiring 71 (VPD). The other of the source or drain of transistor 42 and the other of the source or drain of transistor 44 The other of the drain and the drain of the capacitance element C1 is electrically connected to the wiring 72 (VRS). The first electrode and the other electrode of the capacitive element C2 are electrically connected to a wiring 73 (VSS). The other of the source and the drain of the transistor 45 is electrically connected to the wiring 74 (VPI). The other of the source and drain of the transistor 46 is connected to a wiring 91 (OUT1). are electrically connected.

[0047] In FIG. 1, wiring to which a plurality of transistors or a plurality of capacitors are electrically connected is Although an example in which they are shared is shown, they may be electrically connected to different wirings.

[0048] For example, as shown in FIG. 2A, the other of the source and drain of the transistor 42 is The other electrode of the capacitance element C2 is electrically connected to the wiring 78 (VSS2 ) may be electrically connected to the transistor as shown in FIG. The other of the source and drain of the capacitor 44 is electrically connected to the wiring 74 (VPI). As shown in FIG. 2C, the other potential of the capacitance element C1 and the capacitance element C2 may be The electrode may be electrically connected to the wiring 73 (VPD). In this way, the other of the source or drain of the transistor 42 and the transistor 44 is connected to a wiring 74 (VPI) may be electrically connected. The other of the source and drain of the transistor 42 is connected to the wiring 74 (VPI) of the adjacent pixel. As shown in FIG. 2F, the transistor 42 and the transistor The other of the source and drain of the transistor 44 is connected to the wiring 74 (VPI) of the adjacent pixel. Electrical connection may also be made.

[0049] Wiring 71 (VPD), wiring 72 (VRS), wiring 73 (VSS), wiring 74 (VPI), The wiring 77 (VRS2) and the wiring 78 (VSS2) function as power supply lines. For example, the wiring 71 (VPD), the wiring 73 (VSS), and the wiring 78 (VSS 2) can function as a low-potential power supply line. VPI) and the wiring 77 (VRS2) can function as a high-potential power supply line. .

[0050] A gate of the transistor 41 is electrically connected to a wiring 61 (GTX). The gate of the transistor 42 is electrically connected to the wiring 62 (RS1). The gate of the transistor 44 is electrically connected to the wiring 64 ( The gate of the transistor 46 is electrically connected to the wiring 65 (SE). are connected to the network.

[0051] Wiring 61 (GTX), wiring 62 (RS1), wiring 63 (TX), wiring 64 (RS2) and The wiring 65 (SE) serves as a signal line for controlling the conduction of the transistor to which it is connected. The wiring 63 (TX) can be controlled for each row.

[0052] The transistor 41 serves as a transistor for transferring the potential of the node AN to the node FD. The transistor 42 resets the potential of the node AN. The transistor 43 can function as a transistor having a potential of the node FD. The transistor can function as a transistor to transfer the signal to node FDX. The transistor 44 functions as a transistor for resetting the potential of the node FDX. The transistor 45 outputs a signal corresponding to the potential of the node FDX. The transistor 46 can function as a transistor for selecting the pixel 20. It can function as a transistor for

[0053] The above-described configuration of the pixel 20 is merely an example. In some cases, the capacitance element or some of the wirings may not be included. In some cases, the circuit may include a transistor, a capacitor, a wiring, etc. The topology may differ from the above configuration.

[0054] FIG. 3A is a diagram illustrating an imaging device according to one embodiment of the present invention. A pixel array 26 has pixel blocks 21 arranged in a square shape, and a driving circuit for driving the pixel blocks 21. A circuit 22 (row driver) having a function of operating the pixel block 21 and a circuit 23 (row driver) having a function of operating the pixel block 21 Circuit for performing CDS (Correlated Double Sampling) operation A circuit 23 (CDS circuit) converts analog data output from the circuit 23 into digital data. A circuit 24 (such as an A / D converter circuit) having a function of converting the data into a digital signal, and a circuit 25 for selecting the data converted by the circuit 24. and a circuit 25 (column driver) having a function of selecting and reading out the data. It is also possible to adopt a configuration in which no.

[0055] The pixel block 21 is made up of a plurality of pixels 20 (pixels 20a, 20b, 20c, 20d, 20e, 20f, 20f) as shown in FIG. The details will be described later, but the pixel block The pixel 21 has a configuration in which some of the transistors are shared by the plurality of pixels 20.

[0056] FIG. 3C shows a circuit diagram of a circuit 23 and a circuit 24 connected to one column of the pixel block 21. The circuit 23 includes a transistor 51, a transistor 52, a capacitance element C3, and a capacitance element C4. The circuit 24 may also include a comparator circuit. The configuration may include a circuit 27 and a counter circuit 29.

[0057] The transistor 53 functions as a current source circuit. A wiring 91 (OUT1) is electrically connected to one of the drains, and the other of the source or drain A power supply line is connected to the other side. The power supply line can be, for example, a low potential power supply line. In addition, a bias voltage is constantly applied to the gate of the transistor 53 .

[0058] In the circuit 23, one of the source and drain of the transistor 51 is connected to the transistor 52. The source or drain of the transistor 51 is electrically connected to the One of the drains is electrically connected to one of the electrodes of the capacitance element C3. The other of the source and drain is electrically connected to one electrode of the capacitance element C4. The other of the source and drain of the transistor 52 is electrically connected to the wiring 92 (OUT2). The other of the source and drain of the transistor 51 is connected to a high potential to which a reference potential is supplied, for example. The other electrode of the capacitance element C4 is electrically connected to the potential power supply line (CDSVDD). For example, it is electrically connected to the low potential power supply line (CDSVSS).

[0059] An example of the operation of the circuit 23 when connected to the pixel 20 shown in FIG. Next, the pixel 20 is connected to the wiring 91 (OUT 1) outputs the potential of the image data, and the reference potential (CDSVDD) is output to wiring 92 (OUT2). Thereafter, the transistor 51 is turned off to disconnect the pixel 20 from the wiring 91 (OUT1). to a reset potential (here, a potential higher than the potential of the image data, for example, the VDD potential) At this time, the wiring 92 (OUT2) outputs the difference between the potential of the image data and the reset potential. The absolute value of the voltage is added to the reference voltage (CDSVDD). The potential signal with less noise, which is obtained by adding the potential of the net image data to CDSVDD, is output to circuit 2. Can be supplied in 4.

[0060] The reset potential is a potential (such as a GND potential) lower than the potential of the image data. In this case, the wiring 92 (OUT2) is connected to the reference potential, which is the absolute value of the difference between the potential of the image data and the reset potential. The potential is subtracted from the CDSVDD potential.

[0061] In the circuit 24, the signal potential input from the circuit 23 to the comparator circuit 27 and the swept The potential is compared with the reference potential (RAMP). The counter circuit 29 operates and a digital signal is output to the wiring 93 (OUT3).

[0062] The pixel block 21a shown in FIG. 4 is an example of a specific configuration of the pixel block 21. The block 21a is made up of four wirings arranged in the direction in which the wiring 91 (OUT1) extends (hereinafter, the vertical direction). In the pixels (pixels 20a, 20b, 20c, and 20d), transistors 44, 45, and In addition, in FIG. 4, the pixel block 21a has four pixels. However, the present invention may be applied to a configuration having two pixels, three pixels, or five or more pixels. good.

[0063] In the pixel block 21a, the wiring 72 (VRS), the wiring 74 (VPI), the wiring 62 (R S1), wiring 63 (RS2) and wiring 65 (GTX) can be shared by four pixels. In addition, these wirings are shared with other pixel blocks 21a arranged in the vertical direction. can be done.

[0064] In the pixel block 21a, the wiring 71 (VPD) is arranged to be symmetrical with respect to the wiring 71 (VPD). By arranging the circuit in the vertical direction, it is possible to minimize wiring and In addition, the wiring 71 (VPD) can be easily shared. ) indicates other pixel blocks provided in the direction in which the wiring 64 (SE) extends (hereinafter, the horizontal direction). Can be shared with 21a.

[0065] In addition, the wiring 61a (TX1), the wiring 61b (TX2), the wiring 61c (TX3), and the wiring 61d (TX4) can be shared with other pixel blocks 21a arranged in the horizontal direction. Cut.

[0066] FIG. 5 shows pixel block 21a[m,n] and horizontally adjacent pixel block 21a[ m, n+1]. Note that m and n are arbitrary natural numbers, and are rows and In the operating condition of the pixel 20, the wiring 72 (VRS) and the wiring 74 (VP I) are at the same potential, one of the wires is omitted and the other wire is connected to the pixel block as shown in FIG. The pixel block 21a[m,n] and the pixel block 21a[m,n+1] can share the do.

[0067] The pixel block 21 may have the configuration of a pixel block 21b shown in FIG. Block 21b is made up of a total of four pixels (pixels 20a, 20b, 20c, and 20d) in the horizontal and vertical directions. The transistors 44, 45 and 46 are shared. In the elementary block 21b, various wirings are provided vertically or horizontally to correspond to other pixels. It may be shared with block 21b.

[0068] FIG. 7 shows pixel block 21b[m,n] and horizontally adjacent pixel block 21b[ m, n+1]. In the pixel block shown in FIG. 6, wiring 72 (VRS) are located at both ends in the horizontal direction, one of the wirings 72 (VRS) is omitted as shown in FIG. The other wiring 72 (VRS) is connected to pixel block 21b[m,n] and pixel block 21b[ m, n+1].

[0069] Next, using the flowchart shown in FIG. 8 and the timing chart shown in FIG. 9, The operation of the pixel block 21a shown in FIG. It operates using a single shutter system to obtain image data for the current frame and image data for the previous frame. The data can be read out in parallel.

[0070] Here, the operation method of the imaging device will be explained with reference to Figs. 10(A), (B), and (C). In 0(A), (B), and (C), "E" is the period during which exposure can be performed, and "R" is the period during which readout can be performed. The period during which the action can be performed. Also, n is the nth frame (n is a natural number of 2 or more). In addition, n-1 means the frame immediately before the nth frame, and n+1 means the frame immediately before the nth frame. This means the frame immediately following the nth frame. Note that, in this example, pixels are arranged in a matrix. Line[1] is the pixel in the first row, Li ne[M] means the pixel in the Mth row (last row).

[0071] FIG. 10(A) is a schematic diagram of the operation method of the rolling shutter method. The shutter method is a method of operation in which exposure and data readout are performed sequentially for each row. Therefore, there is no synchronism in the imaging, and therefore distortion occurs in the image when imaging a moving object.

[0072] FIG. 10B is a schematic diagram of the operation method of the normal global shutter method. The single shutter method is a method in which all pixels are exposed at the same time and then the data is read out row by row. Therefore, even when capturing a moving object, it is possible to obtain an image without distortion. However, as the number of pixels increases, the readout time also increases, which limits the exposure time.

[0073] FIG. 10C is a schematic diagram illustrating an operation method applied to an imaging device according to one embodiment of the present invention. The operation method is a global shutter method, and all pixels are exposed simultaneously in the nth frame. In the (n+1)th frame, the data acquired in the (n)th frame is read out. Since exposure and readout of the same frame are not performed within the same frame period, the conventional global shutter method The exposure time is not limited by the increase in readout time as shown in the formula. Therefore, , the exposure time can be increased.

[0074] 8 and 9, the description will be given with reference to an arbitrary n-th frame. D) is at low potential ("L"), and the wiring 72 (VRS) and wiring 74 (VPI) are at high potential ("H ").

[0075] In FIG. 9, RS1 is the potential of the wiring 62 (RS1), and RS2 is the potential of the wiring 63 (RS2). GTX is the potential of the wiring 65 (GTX), TX1 is the potential of the wiring 61a (TX1), T X4 is the potential of the wiring 61d (TX4), AN1 is the potential of the node AN1 in the pixel 20a, AN4 is the potential of node AN4 in pixel 20d, FD1 is the potential of node F in pixel 20a D1 potential, FD4 potential of node FD4 in pixel 20d, FDX potential of node FDX potential, SE[1] is the potential of the wiring 64 (SE) connected to the pixel block 21a in the first row, SE[M] is the potential of the wiring 64 (SE) connected to the pixel block 21a in the last row.

[0076] First, acquisition of imaging data will be described.

[0077] At time T1, when RS1 is set to “H”, AN[1:4] is reset to “H” ( The potential of the wiring 72 (VRS) is then (S1).

[0078] At time T2, when RS1 is set to “L”, AN[1:4] starts to decrease according to the illuminance. (S2).

[0079] At time T8, when GTX is set to “H”, the potentials of the nodes AN1 to AN4 are The packets are then transferred to nodes FD1 through FD4, respectively (S10).

[0080] At time T9, when GTX is set to “L”, FD[1:4] is held. This is the operation to acquire image data. At this time, the image data stored in FD[1:4] is It will be read out in the next frame.

[0081] Next, the image data acquired in the previous frame is acquired in parallel with the image data acquisition operation. The reading will now be described.

[0082] At time T1, when RS2 is set to “H”, FDX is reset to “H” (wire 72 (V R S ) (S3).

[0083] At time T2, if SE[1] is set to “H”, RS1 is set to “L”, and TX1 is set to “H”, then The pixel block 21a in the th row is selected (S4). DX, and the signals corresponding to FD1 and FDX are read out by the circuit 23 (S5, S6).

[0084] At time T3, when SE[1] is set to “H”, RS2 is set to “H”, and TX1 is set to “H”, D1 and FDX are reset, and a signal corresponding to the reset potential is read by the circuit 23. As described above, the circuit 23 outputs a signal corresponding to the image data and a link. The difference between the signal corresponding to the set potential can be detected, and image data with little noise can be obtained. can be obtained.

[0085] At times T3 to T7, the node FD2 of the pixel block 21a in the first row is The potentials of the nodes FD1 to FD4 are sequentially transferred to the node FDX, and the respective image data are read out. Do (S5-S8).

[0086] Then, during the period from time T7 to T8, the pixel blocks 21a from the second row to the last row are selected in sequence. Then, the image data of each pixel block 21a is read out (S4-S9). This is an operation for reading out the imaging data acquired in the previous frame.

[0087] In this manner, in the imaging device according to one aspect of the present invention, the node AN (first charge holding unit), It has a node FD (second charge storage unit) and a node FDX (charge detection unit), and is acquired at node AN. The captured image data is transferred to node FD, and then transferred from node FD to node FDX. The pixel blocks are sequentially transferred and read out. Even in a shared configuration, operation in the global shutter system is possible.

[0088] In addition, in the imaging device according to one embodiment of the present invention, the imaging data acquisition operation and the imaging data of the previous frame are By reading out the image data in the next frame, Even when using the global shutter method, the time allocated to exposure etc. within one frame period Therefore, it is possible to achieve a wide dynamic range and low noise even under low illumination. It is possible to obtain an image of the size.

[0089] In the timing chart shown in Figure 9, the read operation is performed while the nodes FD and FDX are conductive. However, the operation of the node FDX and the transistors connected to it is not possible to suppress noise. To reduce the number of reads, reading may be performed with both of them non-conductive.

[0090] The timing chart shown in Figure 11 is a readout state in which nodes FD and FDX are non-conductive. This shows the operation of reading out the data, and only TX1 and TX4 are different from the timing chart in Figure 9. The following describes the operation of TX1 as a representative example.

[0091] At time T1, when RS2 is set to “H”, FDX is reset to “H” (wire 72 (VRS)).

[0092] At time T2, when RS2 is set to “L” and TX1 is set to “H”, the potential of node FD1 becomes The data is forwarded to FDX.

[0093] At time T3, when TX1 is set to “L”, nodes FD1 and FDX are not connected. At this time, the circuit 23 is operated to obtain a signal corresponding to the FDX (image data). The signal to be read is

[0094] At time T4, when RS2 is set to “H” and TX1 is set to “H”, FD1 and FDX are reset. It is set.

[0095] At time T5, when TX1 is set to “L”, nodes FD1 and FDX are not connected. At this time, the circuit 23 is operated to set the potential FDX (reset potential) to 0V. The signal corresponding to the node FD and the node FDX is read out. Readout can be performed.

[0096] In addition, the imaging device according to one embodiment of the present invention is capable of acquiring imaging data within one frame and storing the imaging data. The operation is explained using the timing chart shown in FIG. Reveal.

[0097] At time T1, when RS1 is set to “H” and GTX is set to “H”, AN[1:4] and F D[1:4] is reset to "H" (the potential of the wiring 72 (VRS)).

[0098] At time T2, when RS1 is set to “L” and GTX is set to “L”, AN[1: 4] begins to decline.

[0099] At time T3, when RS2 is set to “H” and GTX is set to “H”, FDX is reset. The potential of the wiring 72 (VRS) is set to “H”. The position is transferred to nodes FD1 to FD4, respectively.

[0100] At time T4, SE[1] is set to “H”, RS2 is set to “L”, GTX is set to “L”, and TX1 is set to “ When the potential of the node FD1 is H”, the pixel block 21a in the first row is selected. The signal is transferred to node FDX, and the signals corresponding to FD1 and FDX are read out by circuit 23. .

[0101] At time T5, when SE[1] is set to “H”, RS2 is set to “H”, and TX1 is set to “H”, D1 and FDX are reset, and a signal corresponding to the reset potential is read by the circuit 23. From this point on, the timing chart of FIG. 9 is explained in the same manner as for each pixel and each pixel block. The imaging data can be read out from the memory.

[0102] The timing chart shown in FIG. 12 is in a state where nodes FD and FDX are conductive. This shows the operation of reading data when the nodes FD and FDX are not connected. To carry out this, the operation should be performed according to the timing chart of FIG.

[0103] The pixel 20 may have a configuration as shown in FIG. 14(A). The pixel 20 shown in FIG. The direction in which the photoelectric conversion element PD is connected is different from that of the pixel 20 shown in FIG. N, node FD, and node FDX are set to low potential at the time of reset, and are In this configuration, the wiring 71 (VPD) and the wiring 74 (VPI) are High potential ("H"), wiring 72 (VRS) and wiring 73 (VSS) are set to low potential ("L"). Good.

[0104] Also, as shown in FIG. 14B, the capacitance element C2 may be omitted. As shown in FIG. 15A, one of the source and drain of the transistor 45 is connected to the wiring 91. It may be configured to be connected to (OUT1).

[0105] In addition, as shown in FIG. 15B, the pixel 20 does not include the transistor 42. FIG. 16 shows an example in which a pixel block 21c is formed by the pixel 20 shown in FIG. 15(B). In the pixel block 21c, the line 71 (VPD) is set to a high potential during the reset period. The potential of the node AN is reset by applying a forward bias to the photoelectric conversion element PD. This operation can be performed according to the timing charts shown in Figs. 9, 11, 12 and 13. This can be done when RS1 of the

[0106] In addition, in the operation of the pixel block 21c, when imaging and reading are performed within one frame, In this case, as shown in the period from time T1 to time T2 in the timing chart of FIG. S2, GTX, TX1, and TX4 are set to "H" at the same time, and node AN and node FD are set to "H". and may reset node FDX.

[0107] The transistor used in the pixel 20 is, as shown in FIGS. A back gate may be provided for the transistors 41 to 46. ) is a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. In FIG. 18A, as an example, the back gate is connected to a wiring 71 (VPD) that supplies a low potential. Although an example of connecting to the wiring 73 (VSS) or the wiring 75 (VSS2) is shown, either It may be connected to one wiring. Also, FIG. 18(B) shows the same structure as the front gate. A potential is applied to the back gate, increasing the on-current and decreasing the off-current. In addition, the desired transistors can be formed in a manner similar to that shown in FIG. A combination of the configurations of FIG. 8(A) and FIG. 18(B) may also be used. There may be a transistor that does not have a gate. The configurations in Figs. 14(A),(B), 15(A),(B), and 18(A),(B) are They can be combined as needed.

[0108] The imaging device according to one embodiment of the present invention includes a pixel array 26 and circuits 22 to 25. It is possible to form a laminated structure with the substrate 35. For example, FIG. 19(B) is a top view of the substrate 35, as shown in the perspective view of FIG. 19(C). The pixel array 26 and the substrate 35 can be laminated together. It is possible to use transistors suitable for each element and to reduce the area of ​​the image pickup device. Note that the layout of the circuit in FIG. 19B is an example, and other layouts may be used. It could be out.

[0109] The circuits 22 to 25 are silicon-based in order to achieve both high speed operation and a CMOS circuit configuration. It is preferable to use a transistor using a silicon (hereinafter, a silicon transistor) for the fabrication of the transistor. For example, the substrate 35 may be a silicon substrate, and the above-mentioned circuit may be formed on the silicon substrate. The pixel array 26 includes a transistor using an oxide semiconductor (hereinafter, referred to as an OS transistor). It is preferable to use a quartz crystal for forming a part of the circuits 22 to 25. The transistors may be provided on the same surface as the pixel array 26 .

[0110] A specific configuration example of the imaging device of one embodiment of the present invention will be described with reference to the drawings. The cross-sectional view shown in (A) illustrates the photoelectric conversion element PD and the transistor 4 in the pixel 20 shown in FIG. 1 shows an example of a specific connection form of the transistor 43 and the capacitance element C1. In FIG. 20A, a transistor 42, a transistor 44, a transistor 45, The transistor 41 to the transistor 46 and the capacitance element C2 are not shown. 6 and the capacitance elements C1 and C2 are provided on the layer 1100, and the photoelectric conversion element PD is provided on the layer 1200. can be done.

[0111] In the cross-sectional views described in this embodiment, wiring, electrodes and contact plugs (conductors 8 1) are illustrated as separate elements, but when they are electrically connected In some cases, the wiring and the electrodes are connected via a conductor 81. The above embodiment is merely an example, and the electrodes may be directly connected to the wiring.

[0112] On each element, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film, and An insulating layer 83 and the like are provided. For example, the insulating layer 82 and the insulating layer 83 and the like are made of a silicon oxide film. Alternatively, an inorganic insulating film such as an acrylic resin film or a silicon oxynitride film can be used. An organic insulating film such as polyimide resin may be used. The top surface is polished by CMP (Chemical Mechanical Polish) if necessary. It is preferable to perform a planarization process by a planarization method or the like.

[0113] In addition, some of the wiring etc. shown in the drawing may not be provided, or wiring or traces not shown in the drawing may not be provided. In some cases, layers not shown in the drawings may be included. Also, some layers shown in the drawings may not be included.

[0114] The transistors 41 to 46, which are components of the pixel 20, are OS transistors. Since the OS transistor has an extremely low off-state current, The dynamic range of the image can be expanded. When the intensity of light incident on the photoelectric conversion element PD is large, the nodes AN, FD, and The potential of the node FDX becomes smaller. Since the OS transistor has an extremely low off-state current, Even when the gate potential is extremely small, the current according to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range, It can spread the word.

[0115] In addition, the transistors 41, 42, 43 and 44 The low off-state current of the MOSFET allows charge to be retained at nodes AN, FD, and FDX. Therefore, the circuit configuration and operation method can be made complex. It is possible to apply the global shutter method, which accumulates charge simultaneously in all pixels, without Note that the imaging device of one embodiment of the present invention can be operated by a rolling shutter system. It is also possible.

[0116] OS transistors have a higher electrical conductivity than transistors that use silicon as the active region or layer. The temperature dependency of the characteristic fluctuation is small, so it can be used in an extremely wide temperature range. Therefore, imaging devices and semiconductor devices having OS transistors are becoming more and more widely used in automobiles, aircraft, spacecraft, and other fields. It is also suitable for mounting on aircraft.

[0117] In addition, the OS transistor has a higher drain withstand voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, avalanche multiplication is utilized. It is preferable to operate the device by applying a relatively high voltage (for example, 10 V or more). By combining an OS transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer, This makes it possible to provide a highly reliable imaging device.

[0118] In FIG. 20A, each transistor has a back gate. As shown in FIG. 20(B), a configuration without a back gate is also possible. As shown in (C), only some of the transistors, for example, the transistor 41, are provided with a back gate. The back gate may be provided on the opposite side of the transistor. In some cases, the back gate may be electrically connected to the front gate of the In some cases, a fixed potential different from that of the back gate may be supplied. This embodiment can also be applied to other pixel configurations described in this embodiment.

[0119] The photoelectric conversion element PD provided in the layer 1200 can be an element of various types. FIG. 20A illustrates a mode in which a selenium-based material is used for the photoelectric conversion layer 561. Photoelectric conversion elements (PDs) made of silicon-based materials have the characteristic of having high external quantum efficiency for visible light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage that the photoelectric conversion layer 561 can be easily made thin. In photoelectric conversion elements (PDs) that use selenium-based materials, amplification is large due to avalanche multiplication. In other words, if a selenium-based material is used for the photoelectric conversion layer 561, a high-sensitivity sensor can be obtained. By using this, it is possible to obtain sufficient photocurrent even if the pixel area is reduced. Photoelectric conversion elements PD using silicon-based materials are also suitable for imaging in low-light environments. .

[0120] The selenium-based material may be amorphous or crystalline selenium. Crystalline selenium can be obtained, for example, by forming an amorphous selenium film and then heat treating it. By making the crystal grain size smaller than the pixel pitch, the characteristic variation between pixels can be reduced. Crystalline selenium also has higher spectral sensitivity and light absorption for visible light than amorphous selenium. It has high coefficient characteristics.

[0121] In FIG. 20A, the photoelectric conversion layer 561 is illustrated as a single layer. In this way, a hole injection blocking layer 568 made of gallium oxide, cerium oxide or In- Alternatively, an electrode 566 such as Ga-Zn oxide may be provided. Nickel oxide or antimony sulfide may be provided on the side as an electron injection blocking layer 569. Alternatively, as shown in FIG. 21C, a hole injection blocking layer 568 and an electron injection blocking layer 56 9 may be provided. As shown in FIG. 1 and FIG. 14(A), The photoelectric conversion element PD can be connected in a different direction. The hole injection blocking layer 568 and the electron injection blocking layer 569 shown in FIG. 21(A) to FIG. 21(C) are inserted. The configuration may be such that the number of the electrodes is changed.

[0122] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, the layer may include a compound of copper, indium, gallium, and selenium (CIGS). CIS and CIGS utilize avalanche multiplication in the same way as a single layer of selenium. A photoelectric conversion element can be formed.

[0123] The photoelectric conversion element PD using a selenium-based material has an electrode 56 formed of, for example, a metal material. A photoelectric conversion layer 561 may be provided between the insulating layer 6 and the light-transmitting conductive layer 562. In addition, CIS and CIGS are p-type semiconductors and require sulfurization of n-type semiconductors to form a junction. Cadmium, zinc sulfide, or the like may be provided in contact with the metal.

[0124] In FIG. 20A, the light-transmitting conductive layer 562 and the wiring 71 are in direct contact with each other. As shown in FIG. 20(A), the two may be connected via a wiring 88. In the example shown in FIG. 1, the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are not separated between the pixel circuits. However, as shown in FIG. 22(B), the structure may be such that the circuits are separated from each other. In the case of the photoelectric conversion layer 561, a partition wall 567 made of an insulator is provided in a region not having an electrode 566, and It is preferable to prevent cracks from occurring in the transparent conductive layer 562. Alternatively, as shown in (D), a configuration without the partition wall 567 may be used.

[0125] In addition, the electrodes 566 and the wirings 71 may be multi-layered. For example, as shown in FIG. As shown in FIG. 1, the electrode 566 is formed of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 71 is formed of the conductive layer 566a. In the configuration of FIG. 23(A), For example, the conductive layer 566a and the conductive layer 71a are formed by selecting a low-resistance metal or the like, and the conductive layer 566a and the conductive layer 71a are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals may be electrolytically corroded by contacting the transparent conductive layer 562. Even if such a metal is used for the conductive layer 71a, the conductive layer 71b may cause a This can prevent electrolytic corrosion.

[0126] The conductive layer 566b and the conductive layer 71b are made of, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 71a may be made of, for example, aluminum. , titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0127] As shown in FIG. 23B, the transparent conductive layer 562 and the wiring 71 are connected to the conductor 81 and the wiring Alternatively, the insulating layer 82 may be made of multiple layers. For example, as shown in FIG. 23(B), the insulating layer 82 has an insulating layer 82a and an insulating layer 82b. In addition, when the etching rates of the insulating layers 82a and 82b are different, the conductor 81 The insulating layer used for the interlayer insulating film and the planarizing film is multi-layered. In this case, the insulating layer 82 is a two-layer structure. However, the insulating layer 82 and other insulating layers may each have a structure of three or more layers.

[0128] The partition 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. The wall 567 is used for blocking light from transistors and the like and / or for reducing the area of ​​the light receiving portion per pixel. The mark may be colored black or the like to confirm the mark.

[0129] In addition, the photoelectric conversion element PD is a pin A diode element or the like may also be used.

[0130] For example, FIG. 24 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode includes an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type The i-type semiconductor layer 564 has an amorphous structure. It is preferable to use silicon. In addition, the p-type semiconductor layer 563 and the n-type semiconductor layer 5 65 is made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. A photodiode with amorphous silicon as the photoelectric conversion layer can be used. has high sensitivity in the visible light wavelength range and is easy to detect weak visible light.

[0131] In the photoelectric conversion element PD shown in FIG. 24, an n-type semiconductor layer 565 acting as a cathode is The transistor 41 is electrically connected to the electrode 566. The p-type semiconductor layer 563 acting as a node is electrically connected to the wiring 71 via the wiring 88. has.

[0132] The anode and cathode of the photoelectric conversion element PD, the electrode layer and the wiring, If the connection configuration is reversed, a configuration according to the circuit diagram shown in FIG. 14(A) can be obtained.

[0133] In either case, the photoelectric conversion element PD By using the p-type semiconductor layer 563 as a light receiving surface, a photoelectric conversion element The output current of the PD can be increased.

[0134] Also, the configuration of a photoelectric conversion element PD having a pin-type thin-film photodiode, and The photoelectric conversion element PD and the wiring connection are shown in the examples in Fig. 25(A), (B), and (C). The configuration of the photoelectric conversion element PD and the connection between the photoelectric conversion element PD and the wiring may be the same as above. The present invention is not limited to these, and other forms may be used.

[0135] FIG. 25(A) shows a light-transmitting conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The transparent conductive layer 562 acts as an electrode and outputs the photoelectric conversion element PD. The current can be increased.

[0136] The transparent conductive layer 562 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, graphene or In addition, the light-transmitting conductive layer 562 is not limited to a single layer. It may also be a laminate of different films.

[0137] In FIG. 25B, the transparent conductive layer 562 and the wiring 71 are connected via the conductor 81 and the wiring 88. The p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 71 are electrically connected. Alternatively, the connection may be made via the body 81 and the wiring 88. In this case, the light-transmitting conductive layer 562 may not be provided.

[0138] FIG. 25C shows an opening in the insulating layer covering the photoelectric conversion element PD, through which the p-type semiconductor layer 563 is exposed. A light-transmitting conductive layer 562 covering the opening is electrically connected to the wiring 71. It is a composition.

[0139] As shown in FIG. 26, the photoelectric conversion element PD has a silicon substrate 600 as a photoelectric conversion layer. A photodiode having a capacitance of 100 .mu.m may also be used.

[0140] The photoelectric conversion element PD formed using the above-mentioned selenium-based material and amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, selenium-based materials have high resistance, and as shown in Figure 20(A), The switching layer 561 may be configured not to separate the circuits. The imaging device can be manufactured at a high yield and low cost. When forming a photodiode with 600 as the photoelectric conversion layer, the polishing process and bonding process are This requires highly difficult processes such as

[0141] In addition, the imaging device according to one embodiment of the present invention includes a silicon substrate 600 on which a circuit is formed. For example, as shown in FIG. 27A, a silicon substrate 600 may have an active region. A layer 1400 having a transistor 610 and a transistor 620 is formed as a pixel circuit. FIG. 27B is a cross-sectional view of a transistor in a channel width direction. is equivalent to.

[0142] Here, in FIG. 27(A) and (B), the Si transistor is shown as an example of a fin type structure. However, it may be a planar type as shown in FIG. 28(A). As shown in FIG. 6, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulator). r) single crystal silicon.

[0143] The circuit formed on the silicon substrate 600 has a function of reading out the signal output by the pixel circuit and a function of detecting the corresponding It can have a function of performing a process of converting a signal, for example, as shown in the circuit diagram of FIG. The transistor 610 (nc The gates of the transistors 610 (p-ch type) and 620 (p-ch type) are electrically connected to each other. Either the source or drain of one transistor is connected to the source or drain of the other transistor. The source or drain of both transistors is electrically connected to one of the drains. The other of the inputs is electrically connected to a different wiring.

[0144] The circuit formed on the silicon substrate 600 is, for example, the circuit shown in FIG. This corresponds to circuit 22, circuit 23, circuit 24, circuit 25, etc.

[0145] In addition, the silicon substrate 600 is not limited to a bulk silicon substrate, but may be a germanium or silicon germanium substrate. Rumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide Substrates made of gallium nitride or organic semiconductors may also be used.

[0146] Here, as shown in FIG. 26 and FIGS. 27(A) and 27(B), a transistor having an oxide semiconductor is The area where the diode is formed and the area where the Si device (Si transistor or Si photodiode) is formed are An insulating layer 80 is provided between the region where the gate electrode is to be formed.

[0147] Water in the insulating layer provided near the active regions of transistor 610 and transistor 620 The hydrogen terminates the dangling bonds of silicon. Therefore, the hydrogen This has the effect of improving the reliability of transistor 10 and transistor 620. Hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, such as the oxide semiconductor This hydrogen is one of the factors that generate carriers in the layer. Therefore, it is recommended to use silicon-based semiconductor materials. In the case where one layer having a semiconductor transistor and the other layer having an OS transistor are stacked, It is preferable to provide an insulating layer 80 between them, which has the function of preventing the diffusion of hydrogen. The insulating layer 80 allows the transistor 610 and the transistor 620 to be isolated by trapping hydrogen in one layer. The reliability of the resistor 620 can be improved. Suppressing the diffusion can improve the reliability of the transistor 41 and the like.

[0148] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0149] In the configuration shown in FIGS. 27(A) and 27(B), a circuit (e.g. For example, a driving circuit, a transistor 41, etc., and a photoelectric conversion element PD are formed so as to overlap each other. This allows for a higher pixel density. For example, the number of pixels can be increased to 4K2K, 8K4K, or 16K8K. The pixel 20 is suitable for use in a device. The transistor 46 is formed of a Si transistor, and the transistors 41, 42, The photoelectric conversion element PD and the like are overlapped with each other. It is also possible.

[0150] An imaging device according to one embodiment of the present invention can have a structure as shown in FIG. The imaging device is a modification of the imaging device shown in FIG. 27(A), and uses an OS transistor and a Si An example of constructing a CMOS inverter using transistors is shown.

[0151] Here, the transistor 620, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 610 provided in the layer 1100 is an n-channel transistor. By providing only p-ch type transistors on the silicon substrate 600, well formation and n-type Steps such as forming an impurity layer can be omitted.

[0152] The imaging device shown in FIG. 29 uses selenium or the like for the photoelectric conversion element PD. Similarly, a pin type thin film photodiode may be used.

[0153] In the imaging device shown in FIG. 29, the transistor 610 is a transistor formed in the layer 1100. The transistor 41 and the transistor 43 can be fabricated in the same process. The manufacturing process of the imaging device can be simplified.

[0154] As shown in FIG. 30, the imaging device according to one embodiment of the present invention is formed on a silicon substrate 660. The pixel is composed of a photoelectric conversion element PD and an OS transistor formed on the element. Alternatively, the semiconductor device may have a structure in which the semiconductor device is laminated to a silicon substrate 600 on which a circuit is formed. With this configuration, the photoelectric conversion element PD formed on the silicon substrate 660 can be effectively In addition, the circuit formed on the silicon substrate 600 can be finely divided. By using highly integrated silicon transistors, it is possible to provide high-performance semiconductor devices. do.

[0155] As a modification of FIG. 30, an OS transistor and a Si transistor may be used as shown in FIG. The circuit may be formed of a silicon-based resistor. This makes it easy to increase the effective area of ​​the photoelectric conversion element PD formed on the plate 660. The circuit formed on the silicon substrate 600 is highly integrated with miniaturized Si transistors. Therefore, a high-performance semiconductor device can be provided.

[0156] In the case of the configuration of FIG. 31, a Si transistor is formed on a silicon substrate 600 and The formed OS transistor can be used to configure a CMOS circuit. Since the off-state current is extremely low, it is possible to construct a CMOS circuit with extremely low static leakage current. It is possible.

[0157] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. Thus, for example, one or more of the transistors 41 to 46 may be It may also be configured as a transistor having silicon or the like in the active region or active layer. In the present embodiment, the transistor 610 and / or the transistor 620 are formed of an oxide semiconductor in the active layer. The transistor may also be constructed with a semiconductor layer.

[0158] FIG. 32(A) is a cross-sectional view of an example of an embodiment in which a color filter or the like is added to an imaging device. The cross-sectional view shows a part of an area having pixel circuits for three pixels. On the layer 1200 to be formed, an insulating layer 2500 is formed. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A configuration in which a dielectric film such as fluorine is laminated may also be used.

[0159] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may include an upper The light shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. A metal layer such as tungsten or aluminum, or a dielectric layer that functions as an anti-reflective coating The film may be laminated.

[0160] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. In addition, a color filter 2530 (color filter 25 30a, color filter 2530b, and color filter 2530c) are formed. For example, , color filter 2530a, color filter 2530b, and color filter 2530 c: R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0161] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0162] Also, as shown in FIG. 32(B), an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. With this configuration, images in various wavelength regions can be obtained. It is possible to provide an imaging device having such a configuration.

[0163] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0164] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then converted into Image data is obtained by detecting the radiation. A position may also be used.

[0165] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and These include substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. Cut.

[0166] In photoelectric conversion elements (PDs) made of selenium-based materials, radiation such as X-rays is directly converted into electric charges. Therefore, a configuration that does not require a scintillator can be provided.

[0167] As shown in FIG. 32C, the color filter 2530a and the color filter 2530 A microlens array 2540 may be provided on color filter 2530b and color filter 2530c. The light passing through each lens of the microlens array 2540 hits the color filter directly below. As shown in FIG. 32(D), the light A microlens array 2540 may be provided on the optical conversion layer 2550. 1200 , the area other than the layer 1200 shown in (A), (B), (C), and (D) is referred to as a layer 1600 .

[0168] FIG. 33 illustrates a pixel 20 according to one embodiment of the present invention and the microlens array 2 shown in FIG. FIG. 33 is a diagram illustrating a specific laminated structure of the pixel shown in FIG. 34 is an example using the pixel configuration shown in FIG.

[0169] In this way, the photoelectric conversion element PD, the circuit of the pixel 20, and the drive circuit are mutually Since the imaging device can be configured to have an overlapping area, the imaging device can be made smaller. can.

[0170] Also, as shown in Figs. 33 and 34, a diffraction grating 1500 may be provided. The image of the object (diffraction image) through the diffraction grating 1500 is captured by a pixel, and the image of the pixel is The input image (image of the subject) can be reconstructed by arithmetic processing from the image. Using a diffraction grating 1500 instead can reduce the cost of the imaging device.

[0171] The diffraction grating 1500 can be made of a material having optical transparency. For example, silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. It may be laminated with an organic insulating film.

[0172] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0173] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. X can be 1 mm or less, preferably 100 μm or less. Alternatively, a light-transmitting material may be provided as a sealing layer or an adhesive layer. An inert gas such as a rare gas can be sealed in the gap. Alternatively, acrylic resin, Epoxy resin or polyimide resin may be provided in the gap. In addition, when the microlens array 2540 is not provided, In this case, a distance X may be provided between the color filter 2530 and the diffraction grating 1500 .

[0174] The imaging device may also be curved as shown in FIG. 35(A1) and FIG. 35(B1). FIG. 35(A1) shows the imaging device bent along the two-dot chain line Y1-Y2 in the figure. FIG. 35(A2) shows the portion indicated by the two-dot chain line X1-X2 in FIG. 35(A1). FIG. 35(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0175] FIG. 35(B1) shows a case where the imaging device is bent along the two-dot chain line X3-X4 in the same figure, and FIG. 35(B2) shows a state where the bent portion is bent along the two-dot chain line Y3-Y4 in the figure. FIG. 35(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 35(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG.

[0176] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, enabling miniaturization of semiconductor devices using imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0177] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The semiconductor may have at least one of gallium nitride and organic semiconductors. For example, in some cases or circumstances, various transistors in one aspect of the present invention may be A transistor channel forming region, a transistor source drain region, etc. The layer 100 may not include an oxide semiconductor.

[0178] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0179] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0180] 36A and 36B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 36(A) is a top view, and FIG. 36(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 36(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 38(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0181] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0182] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0183] In addition, a region 231 shown in FIG. 36(B) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0184] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0185] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0186] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0187] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0188] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 36C is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 36(D). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 38(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0189] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is small.

[0190] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0191] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 36E is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 36(F). Also, the dashed line D3 shown in FIG. The cross section in the -D4 direction corresponds to FIG. 38(A). The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0192] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0193] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0194] In addition, a region 231 shown in FIG. 36(F) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0195] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0196] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 37(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 38(A). The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0197] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0198] In addition, the regions 331 and 334 shown in FIG. 37(B) are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0199] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0200] Regions 334 and 335 correspond to regions 231 and 232 in the transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. and if the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. In some cases, the resistance reduction step 5 is not performed.

[0201] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0202] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37C is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 37(D). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 38(A). The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0203] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0204] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0205] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0206] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37E is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 37(F). Also, the dashed line G3 shown in FIG. The cross section in the -G4 direction corresponds to FIG. 38(A). The direction of the dashed dotted line G3-G4 is called the channel width direction.

[0207] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0208] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0209] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0210] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0211] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0212] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0213] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0214] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0215] In addition, the transistor of one embodiment of the present invention is 38(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer 173 may be used as a second gate electrode layer (back gate). By this, it is possible to increase the on-current and control the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. may be shorter than the width of

[0216] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0217] In addition, in the transistors 101 to 106 in FIG. 36 and FIG. 37, Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 may be formed as shown in FIG. 40(B), (C), or 40(D), (E) may be replaced with the oxide semiconductor layer 130 shown in FIG. This can be done.

[0218] FIG. 40A is a top view of the oxide semiconductor layer 130, and FIGS. 40B and 40C are top views of the two-layer structure. 40(D) ​​and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0219] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0220] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 41A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 41(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 43(A). The direction of the dashed line H1-H2 is the channel The longitudinal direction, the direction of the dashed dotted line H3-H4, is referred to as the channel width direction.

[0221] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0222] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0223] The transistor of one embodiment of the present invention may have a structure shown in FIGS. FIG. 41C is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 41(D). Also, the dashed line I3 shown in FIG. The cross section in the -I4 direction corresponds to FIG. 43(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, is referred to as the channel width direction.

[0224] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0225] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 41E is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 41(F). Also, the dashed line J3 shown in FIG. The cross section in the -J4 direction corresponds to FIG. 43(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, is referred to as the channel width direction.

[0226] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide semiconductor layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0227] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0228] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 42A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 42(B). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 43(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, is referred to as the channel width direction.

[0229] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0230] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 42C is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 42(D). Also, the dashed line L3 shown in FIG. The cross section in the -L4 direction corresponds to FIG. 43(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, is referred to as the channel width direction.

[0231] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0232] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0233] Further, the transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 42E is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 42(F). Also, the dashed line M3 shown in FIG. The cross section in the direction of -M4 corresponds to FIG. 43(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, is referred to as the channel width direction.

[0234] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0235] In addition, the transistor of one embodiment of the present invention is shown in FIG. 43(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0236] Further, the transistor of one embodiment of the present invention has the structure shown in FIG. FIG. 45(A) is a top view, and FIG. 45(B) is a top view of the 45 is a cross-sectional view corresponding to the dashed line N1-N2 and the dashed line N3-N4. In the top view of (A), some elements are omitted for clarity.

[0237] The transistor 113 shown in FIG. 45(A) and FIG. 45(B) is a transistor including a substrate 115 and a substrate 11 5, and the oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130 a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) and a The conductive layer 140 and the conductive layer 150 are spaced apart from each other, and the oxide semiconductor layer 130 is c, and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 form an insulating layer on the transistor 113. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the insulating layer 12 provided in the It is provided at an opening that reaches 0.

[0238] The configuration of the transistor 113 is different from the configurations of the other transistors described above in that the source Or, since the overlapping area between the drain conductor and the gate conductor is small, parasitic Therefore, the transistor 113 is required to operate at high speed. The transistor 113 is suitable as an element of a circuit for implementing the above-mentioned method. Chemical Mechanical Polishing (CMP) method is used. It is preferable to flatten the surface of the substrate by the flattening process, but it is also possible to adopt a structure in which the flattening process is not performed.

[0239] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. As shown in FIG. 30, only the conductive layer 140 and the conductive layer 150 are shown, (W OS ) of the conductive layer 140 and the conductive layer 150. SD ) is formed long It may be formed short. OS ≧W SD (W SD W OS (hereinafter) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor In addition, as shown in FIG. 46(C), the conductive layer 140 and The conductive layer 150 may be formed only in a region overlapping with the oxide semiconductor layer 130 .

[0240] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0241] In addition, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. Therefore, the on-current can be improved by making the oxide semiconductor layer 130b thicker. This may be the case.

[0242] With the above structure, the electrical characteristics of the transistor can be improved.

[0243] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0244] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0245] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0246] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom equivalent measured by a TDS method. The calculated amount of oxygen released is 1.0 x 10 19 atoms / cm 3 More preferably, it is equal to or greater than this. The surface temperature of the film during the TDS analysis was 100°C to 700°C or 10 The temperature range is from 0° C. to 500° C. In addition, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform planarization treatment by CMP or the like so that the surface becomes flat.

[0247] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0248] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The organic semiconductor layer 130c can be stacked in order from the insulating layer 120 side to form a three-layer structure.

[0249] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0250] In addition, when the oxide semiconductor layer 130 has two layers, a layer corresponding to the oxide semiconductor layer 130a and In this case, a layer corresponding to the oxide semiconductor layer 130b is stacked in this order from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are interchanged. It is also possible.

[0251] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). A compound semiconductor is used.

[0252] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that the nucleus has a region that functions in a specific manner.

[0253] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0254] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0255] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0256] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A stack of an alloy such as n and the above material may be used. 06, transistor 111, and transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. There can be.

[0257] The above material has a property of extracting oxygen from the oxide semiconductor film. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0258] In addition, when W is used for the conductive layer 140 and the conductive layer 150, it is possible to dope the W with nitrogen. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding to the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0259] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0260] An example of a layered structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0261] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0262] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0263] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 cm -3 5×10 or more 19 cm -3 The amount of ammonia released is as follows: The surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount of release is the amount of

[0264] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0265] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0266] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0267] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0268] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0269] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0270] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. When the gate electrode shrinks, the on-current decreases.

[0271] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0272] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from a direction perpendicular to the channel formation layer. Since the gate electric field is applied to the MOSFET, the effective channel width is enlarged, and the on-current is further increased. Can be enhanced.

[0273] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0274] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0275] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0276] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0277] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0278] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0279] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0280] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0281] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0282] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0283] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition). It can also be called deposition SP).

[0284] An oxide semiconductor layer is formed using a facing target sputtering apparatus, It is possible to reduce plasma damage during the formation of the oxide semiconductor layer. In addition, the oxygen deficiency in the film can be reduced by using a facing target sputtering device. Since this enables deposition at low pressure, the impurity concentration (e.g. For example, hydrogen, rare gases (such as argon), water, etc.) can be reduced.

[0285] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0286] (Embodiment 4) In this embodiment, a material for an oxide semiconductor layer that can be used in one embodiment of the present invention will be described. explain.

[0287] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0288] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Tantalum However, the element M may be a combination of multiple of the above elements. There are cases where it is acceptable to combine them.

[0289] First, with reference to Figs. 47(A), 47(B), and 47(C), the oxide according to the present invention A preferred range of the atomic ratio of indium, element M, and zinc contained in the semiconductor will be explained. The atomic ratio of oxygen is not described. The terms for the atomic ratio of element m, element M, and zinc are [In], [M], and [Zn], respectively. Let us assume that.

[0290] In Figures 47(A), 47(B), and 47(C), the dashed lines indicate [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2, [I n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ This line represents the atomic ratio of In:M:Zn=(1+α):(1-α):5. .

[0291] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β Represents in.

[0292] In FIG. 47A and FIG. 47B, indium oxide included in the oxide semiconductor of one embodiment of the present invention is 1 shows an example of a preferred range of the atomic ratio of element M, element M, and zinc.

[0293] As an example, FIG. 48 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. 4. Also, Fig. 48 shows the crystal structure of InMZn The crystal structure of the layer having M, Zn, and oxygen shown in FIG. The metal element in layer n) represents element M or zinc. In this case, element M and zinc The ratio of elements M and zinc is equal. The elements M and zinc can be substituted, and the arrangement is random. .

[0294] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 48. The layer containing indium and oxygen (hereinafter referred to as the In layer) is 1, while the element M, zinc, and The (M,Zn) layer containing oxygen is called 2.

[0295] Indium and the element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, the In layer It has a layered structure with one layer and two (In,M,Zn) layers.

[0296] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is For [In] and [M], the (M,Zn) layer is three. When [Zn] is large, when the oxide semiconductor crystallizes, the (M,Zn ) layer increases.

[0297] However, in the oxide semiconductor, the number of (M, Zn) layers for one In layer is a non-integer. In this case, multiple types of layered structures are used, each with an In layer and an integer number of (M, Zn) layers. For example, when [In]:[M]:[Zn]=1:1:1.5, A layered structure with 1 In layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, the resulting structure may be a layered structure in which a crystalline structure and a crystalline structure are mixed.

[0298] For example, when forming an oxide semiconductor film using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the ratio of the number of atoms in the target may change. [Zn] of the film may be smaller than [Zn].

[0299] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In this case, two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, In oxide semiconductors, two phases, a cubic crystal structure and a layered crystal structure, tend to coexist. When they coexist, grain boundaries form between the different crystal structures. It may be formed.

[0300] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor is improved. This is because the oxide semiconductor having indium, element M and zinc can be In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the area where the s orbitals overlap becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because

[0301] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios of 0.1 to 0.5 and their neighboring values ​​(for example, region C shown in FIG. 47(C)), the insulating properties are high. do.

[0302] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio is as shown in region A in FIG. 47(A), which tends to form a layer structure having no atomic number. I wish.

[0303] Also, in region B shown in FIG. 47(B), [In]:[M]:[Zn]=4:2:3 to 4. 1 and its neighboring values. For example, the atomic ratio [In]:[M] :[Zn]=5:3:4. The oxide semiconductor having the atomic ratio shown in region B is In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0304] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. Therefore, the illustrated region is a region showing an atomic ratio in which the oxide semiconductor has a layered structure, The boundaries between areas A and C are not strict.

[0305] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0306] By using the oxide semiconductor in a transistor, carrier scattering at grain boundaries can be prevented. This allows the realization of transistors with high field effect mobility. In addition, a highly reliable transistor can be realized.

[0307] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3That should be enough.

[0308] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. Since the carrier density can be reduced, the high purity intrinsic or substantially high purity Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0309] In addition, it takes a long time for the charges trapped in the trap states of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0310] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0311] Here, the influence of each impurity in an oxide semiconductor will be described.

[0312] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, it becomes an oxide. Defect levels are formed in the semiconductor. This causes the silicon and carbon in the oxide semiconductor to The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( By SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm3 Less than or equal to 2 x 10 17 at oms / cm 3 The control is performed so as to have a region where:

[0313] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form a carrier. Transistors using oxide semiconductors containing metals tend to be normally-on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable that the alkali metal in the oxide semiconductor obtained by SIMS analysis is Or the concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Below, preferably 2 ×10 16 atoms / cm 3 The control is performed so as to have a region where:

[0314] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using this oxide semiconductor is likely to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is preferable that the nitrogen content is reduced as much as possible by SIMS analysis. The nitrogen concentration in the resulting oxide semiconductor is 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3The following areas are considered: to control.

[0315] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, the hydrogen-containing oxide semiconductor The transistor using this type of transistor is likely to be normally on. It is preferable that the amount of oxygen is reduced as much as possible. The hydrogen concentration in the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Controlled to have an area less than do.

[0316] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor As described above, the highly purified oxide can provide stable electrical properties. The off-state current of a transistor using a semiconductor as a channel formation region is extremely small. For example, When the voltage between the source and drain is set to about 0.1V, 5V, or 10V, The off-current per channel width of the transistor is reduced to several yA / μm to several zA / μm. It becomes possible to do so.

[0317] Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A barrier layer made of an insulator is in contact with the stacked structure of the semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3. The band diagram of the insulator in contact with the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3. The oxide semiconductor S1 is an oxide semiconductor layer 1. 30a, the oxide semiconductor S2 is the oxide semiconductor layer 130b, and the oxide semiconductor S3 is the oxide semiconductor This corresponds to layer 130c.

[0318] FIG. 49(A) shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3. FIG. 49 is an example of a band diagram in the thickness direction of a laminated structure having an insulator I1 and an insulator I2. (B) is a semiconductor having an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the thickness direction of a laminated structure. Therefore, the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator The energy level (Ec) at the bottom of the conduction band of I2 is shown.

[0319] The oxide semiconductors S1 and S3 have a lower energy of the conduction band than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level at the bottom of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is 0. 15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less In other words, the oxide semiconductor S1 has a higher electron affinity than the oxide semiconductor S3. The electron affinity of the semiconductor S2 is large, and the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 are , the difference between the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more, It is also preferable that the electron transport potential is 2 eV or less, or 1 eV or less.

[0320] As shown in FIG. 49(A) and FIG. 49(B), an oxide semiconductor S1, an oxide semiconductor S2 In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. Then, it can be said that the band changes continuously or that the junction is continuous. In order to have such a property, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor S The defect level density of the mixed layer formed at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is reduced. stomach.

[0321] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S 3) A mixture with a low defect level density due to the common element (main component) other than oxygen. For example, the oxide semiconductor S2 may be an In-Ga-Zn oxide semiconductor. In this case, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors, It is preferable to use a Ga-Zn oxide semiconductor, gallium oxide, or the like.

[0322] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the semiconductor S2 and at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0323] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level can be moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor is shifted in the positive direction. This can prevent the above from happening.

[0324] The oxide semiconductors S1 and S3 have sufficiently high electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S1 are used. The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the interface between the oxide semiconductor S3 and the channel region are mainly For example, in FIG. 47(C), the atomic ratio shown in region C where the insulating property becomes high is An oxide semiconductor such as

[0325] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having the above atomic ratio. Therefore, the ratio [M] / ([Zn]+[In]) is 1 or more, which is sufficient to obtain high insulation. It is preferable to use an oxide semiconductor having such an atomic ratio.

[0326] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0327] (Embodiment 5) A structure of an oxide semiconductor that can be used in one embodiment of the present invention will be described below.

[0328] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0329] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0330] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0331] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0332] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0333] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0334] From the other perspective, a stable oxide semiconductor can be considered as completely amorphous. In addition, it is not isotropic (for example, in a small area) and cannot be called an oxide semiconductor. An oxide semiconductor having a periodic structure in a crystal structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has voids (also called voids) and is unstable. In terms of instability, a-like OS is physically an amorphous oxide. Close to semiconductors.

[0335] <caac-os> First, let me explain about CAAC-OS.

[0336] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0337] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 50(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the center are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not show such a peak.

[0338] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the measurement is performed, no clear peak appears, as shown in FIG. When φ is scanned with 2θ fixed at around 56° for nO4, as shown in Figure 50(C). As shown in Fig. 1, six peaks are observed that are attributable to crystal planes equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0339] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. This is also called the limited-area electron diffraction pattern.) may appear. This diffraction pattern includes In The spots are due to the (009) plane of the GaZnO4 crystal. In some cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the material is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident vertically is shown in Figure 50(E). As shown in Figure 50(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and b-axis of the slit have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is considered that the second ring in Figure 50(E) is due to the (110) plane, etc. It is possible.

[0340] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0341] Figure 51(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that.

[0342] From Figure 51(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned nan The pellets are also called oxide semiconductors with CAAC -OS surface or top surface unevenness, and CAAC-OS surface or top surface unevenness is parallel to the surface.

[0343] In addition, Fig. 51(B) and Fig. 51(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 51(D) and 51(E) show Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images of Figures 51(B) and 51(C), respectively. First, the method of performing the fast Fourier transform (FFT) on FIG. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT: Inverse Fast Fourier Transform (IFFT) processing is used to The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0344] In FIG. 51(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the dashed line is the connection between the pellets. The broken line indicates a hexagonal shape, so it can be seen that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0345] In FIG. 51(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different lattice arrangement. Even in the vicinity of the dotted line, no clear grain boundaries can be confirmed. When you connect the neighboring lattice points, you can get a distorted hexagon, pentagon, or / and heptagon. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the bond distance between atoms in the CAAC-OS is The reason is that the bond distance between atoms changes due to the substitution of metal elements. Therefore, it is believed that distortion can be tolerated.

[0346] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0347] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. In other words, the CAAC-OS can be regarded as an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0348] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor and rearrange the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0349] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0350] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 cm -3 Less than 1 x 10 11 cm -3 Less than More preferably, 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0351] <nc-os> Next, we will explain nc-OS.

[0352] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0353] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed in the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nm) when an electron beam with a probe diameter of 1 nm was incident on the same sample was The electron diffraction pattern (BEM pattern) is shown in FIG. 52(B). From FIG. 52(B), a ring-shaped region Therefore, nc-OS has a probe diameter of 50 nm. Although no order was observed by irradiating the electron beam, the order was observed by irradiating the electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0354] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 52(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals have highly crystalline regions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0355] FIG. 52(D) shows the Cs-corrected high resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. As shown in Fig. 1, there are areas where crystals can be confirmed, and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor having a diameter of more than 0 nm and less than 100 nm is called a microcrystalline oxide semiconductor. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be called a pellet.

[0356] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0357] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0358] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0359] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0360] Figure 53 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 Electrons (e - ) High a-like OS after irradiation 53(A) and 53(B) show that the a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0361] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0362] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0363] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0364] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0365] Figure 54 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 54, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was a nucleus (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the nc The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was The results show that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. Electron beam irradiation conditions The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0366] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0367] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of the oxide semiconductor is 78.6% or more and less than 92.3%. The density of the CAAC-OS is 92.3% or more that of single-crystal oxide semiconductors with the same composition. The density of an oxide semiconductor having a density of less than 78% of that of a single crystal oxide semiconductor can be obtained by deposition. It is difficult to do so.

[0368] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0369] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0370] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0371] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0372] (Embodiment 6) In this embodiment, a package containing an image sensor chip and a camera module An example will be described. The image sensor chip has a structure of an imaging device according to one embodiment of the present invention. The composition can be used.

[0373] FIG. 55(A) is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing an image sensor chip 850, a cover It has a bar glass 820 and an adhesive 830 for bonding the two together.

[0374] FIG. 55(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) with solder balls as bumps 840 is used. In addition to BGA, LGA (Land grid array) and PGA (P in Grid Array) etc.

[0375] FIG. 55(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 55(D) is a cross-sectional view of the package. Package substrate An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are The electrode pad 860 is electrically connected to the electrode pad 860 via a hole 880 and a land 885. is electrically connected to the electrodes of the image sensor chip 850 by wires 870. is.

[0376] FIG. 56(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. FIG. 1 is a perspective view of the appearance of the upper surface side of a camera module. A package substrate 811 that fixes the cap 851, a lens cover 821, and a lens 835 In addition, between the package substrate 811 and the image sensor chip 851, An IC chip 890 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0377] FIG. 56B is a perspective view showing the appearance of the lower surface side of the camera module. The bottom surface and four side surfaces of the package 11 are provided with lands 841 for mounting. The structure is a lat no-lead package. Note that this structure is just an example. It can be QFP (Quad flat package) or the BGA mentioned above. stomach.

[0378] FIG. 56(C) shows a module with the lens cover 821 and a portion of the lens 835 omitted. FIG. 56(D) is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. is.

[0379] By housing the image sensor chip in the above-mentioned package, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0380] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0381] (Embodiment 7) An imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device can be used. Examples of electronic devices that can be used include display devices, personal computers, and image storage devices equipped with recording media. image reproduction devices, mobile phones, portable game consoles, portable data terminals, e-book terminals Cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted displays), navigation systems, audio playback devices (car audio, digital digital audio players, copiers, fax machines, printers, printer-combined machines, These include automated teller machines (ATMs) and vending machines. An example is shown in Figure 57.

[0382] FIG. 57(A) shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. As one of the components for acquiring images in the surveillance camera, an imaging device according to one aspect of the present invention is used. The term "surveillance camera" is a common name and does not limit its use. For example, a device that has the function of a surveillance camera is a camera or a video camera. Also called La.

[0383] FIG. 57B shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring an image in the video camera, one aspect of the present invention is The imaging device may include:

[0384] FIG. 57C shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 63, a light emitting unit 967, a lens 965, etc. Acquire an image with the digital camera The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0385] FIG. 57D shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 has a time signal, ... A part for acquiring an image in the information terminal. The imaging device according to one embodiment of the present invention can be provided as an imaging device.

[0386] FIG. 57E shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. 57(E) has two display units 903 and a display unit 904, the number of display units that the portable game machine has is not limited to this. The present invention is not limited to the above. The imaging device may include an imaging device according to the present invention.

[0387] FIG. 57(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display portion 912 has a touch panel function through which data can be input and output. As one of the components for acquiring images in the portable data terminal, the imaging device according to one aspect of the present invention is The imaging device may be provided.

[0388] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0389] 20 pixels 20a pixels 20b pixels 20c pixels 20d pixels 21 pixel blocks 21a Pixel block 21b Pixel block 21c Pixel Block 22 Circuit 23 Circuit 24 circuits 25 Circuit 26 pixel array 27 Comparator Circuit 29 Counter Circuit 35 Substrate 41 Transistor 42 Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 51 Transistor 52 Transistor 53 Transistor 61 Wiring 61a Wiring 61b Wiring 61c Wiring 61d Wiring 62 Wiring 63 Wiring 64 Wiring 65 Wiring 71 Wiring 71a Conductive layer 71b Conductive layer 72 Wiring 73 Wiring 74 Wiring 75 Wiring 77 Wiring 78 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating Layer 88 Wiring 91 Wiring 92 Wiring 93 Wiring 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor Layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blocking layer 569 Electron injection blocking layer 600 Silicon substrate 610 Transistor 620 Transistor 650 active layer 660 Silicon Substrate 810 Package Substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 Image Sensor Chip 851 Image sensor chip 860 Electrode Pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1400 layers 1500 Diffraction Grating 1600 layers 2500 Insulation Layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation layer

Claims

[Claim 1] An imaging device including first to sixth transistors, a photoelectric conversion element, a first capacitor, and a second capacitor, one electrode of the photoelectric conversion element is electrically connected to one of the source and drain of the first transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitance element; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fifth transistor; the other of the source and the drain of the third transistor is electrically connected to one electrode of the second capacitance element; the fifth transistor has a source or a drain electrically connected to a source or a drain of the sixth transistor;

Images