Semiconductor device

Abstract

To provide a semiconductor device having an arithmetic processing function.SOLUTION: A semiconductor device is configured such that an imaging unit and an arithmetic unit are electrically connected through an analog processing circuit 24. The imaging unit has a pixel array 21 in which imaging pixels 20 and reference pixels 22 for image processing are arrayed in a matrix and a row decoder 25. The arithmetic unit has a storage element array 31 in which storage elements 30 and reference storage elements 32 are arrayed in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an imaging device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductors are widely used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, in Patent Document 3, a transistor having an oxide semiconductor and an extremely low off-state current is used as a pixel Used as part of the circuit, CMOS (Complementary Metal Oxide A transistor with silicon on which circuits can be fabricated. An imaging device configured for road use is disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0008] When transmitting data captured by an imaging device, the data is compressed to In still image compression, data is compressed using discrete cosine transform. There are also video compression formats such as the JPEG format, which compresses the amount of data. The captured image is subjected to a discrete cosine transform for each frame, and the difference data is subjected to a discrete cosine transform for the intermediate frames. Well-known formats include the MPEG format.

[0009] On the other hand, compressing the data captured by the imaging device reduces the load of data transmission, The digital image processing required to compress the data consumes a huge amount of power.

[0010] Therefore, one aspect of the present invention is to provide an imaging device with an image processing function. One of the objectives is to provide an imaging device capable of outputting data after image processing. One of the purposes is to convert image data into digital data. One object of the present invention is to provide an imaging device capable of performing discrete cosine transform without performing conversion processing. Another object of the present invention is to provide an imaging device with low power consumption. One of the objects of the present invention is to provide an imaging device suitable for high speed operation. One of the objects of the present invention is to provide an imaging device having a high integration density. Another object of the present invention is to provide an imaging device capable of imaging under low illuminance. Another object of the present invention is to provide an imaging device with a wide dynamic range. Alternatively, the present invention aims to provide an imaging device that can be used in a wide temperature range. Another object of the present invention is to provide an imaging device with a high aperture ratio. It is an object of the present invention to provide a highly reliable imaging device. Another object of the present invention is to provide a novel semiconductor device. One of the objectives is to:

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention relates to an imaging device with an image processing function.

[0013] One aspect of the present invention is an imaging device having a pixel array and a memory element array, The array is made up of first pixels arranged in a matrix and second pixels arranged in a line at the edge and shielded from light. and a second pixel, the first pixel being electrically connected to a first row decoder via a first wiring. The first pixel is electrically connected to the first analog processing circuit via the second wiring. The second pixel is electrically connected to the first row decoder through a first wiring. The second pixel is electrically connected to the first analog processing circuit via a third wiring. The memory element array includes a first memory element arranged in a matrix and a second memory element arranged in a row at an end. The first memory element is connected to the first analog input through a fourth wiring. The first memory element is electrically connected to the processing circuit, and the first memory element is connected to the column decoder via a fifth wiring. The first memory element is electrically connected to the second row decoder through a sixth wiring. The first memory element is electrically connected to the second analog processing circuit via a seventh wiring. The second memory element is electrically connected to the first analog processing circuit through a fourth wiring. The second memory element is electrically connected to the column decoder through a fifth wiring. The second memory element is electrically connected to the second row decoder through the eighth wiring. The second memory element is electrically connected to the second analog processing circuit via a ninth wiring. and electrically connected to the imaging device.

[0014] The first pixel and the second pixel include first to third transistors, a first capacitor, and a photodiode. One electrode of the photoelectric conversion element is connected to a source electrode of the first transistor or is electrically connected to one of the drain electrodes of the first transistor and is The other of the input electrodes is electrically connected to one of the source electrode or the drain electrode of the second transistor. The other of the source electrode or the drain electrode of the first transistor is connected to a third transistor. the source electrode or drain electrode of the first transistor; The other of the input electrodes is electrically connected to one of the electrodes of the first capacitance element. This can be done.

[0015] In addition, the first memory element and the second memory element include a fourth transistor, a fifth transistor, a second capacitor and a second capacitor element, and a source electrode or a drain electrode of the fourth transistor One of the terminals is electrically connected to the gate electrode of the fifth transistor. The gate electrode may be electrically connected to one electrode of the second capacitance element. Cut.

[0016] In addition, the first pixel and the first memory element may have an overlapping region. Cut.

[0017] In addition, the first to fourth transistors each have an oxide semiconductor in an active layer. The oxide semiconductor can be a transistor containing In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) and is preferred.

[0018] In addition, the photoelectric conversion element may use selenium or a compound containing selenium in the photoelectric conversion layer. For example, the selenium may be amorphous or crystalline. do. Effect of the Invention

[0019] By using one embodiment of the present invention, an imaging device with an image processing function can be provided. Alternatively, it is possible to provide an imaging device capable of outputting data after image processing. Alternatively, the image data can be converted to discrete data without A / D conversion. It is possible to provide an imaging device capable of performing sign conversion. Alternatively, an imaging device suitable for high speed operation can be provided. Alternatively, it is possible to provide an imaging device with high resolution. Alternatively, an imaging device capable of imaging under low illumination can be provided. Alternatively, an imaging device with a wide dynamic range can be provided. Alternatively, it is possible to provide an imaging device that can be used in a wide temperature range. In this way, it is possible to provide an imaging device with a high aperture ratio. Alternatively, a novel imaging device or the like can be provided. A semiconductor device or the like can be provided.

[0020] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram illustrating an imaging apparatus. [Diagram 2] FIG. 2 is a circuit diagram illustrating a pixel and a reference pixel. [Diagram 3] FIG. 2 is a diagram for explaining an analog processing circuit. [Figure 4] FIG. 2 is a circuit diagram illustrating a memory element and a reference memory element. [Diagram 5] FIG. 2 is a diagram for explaining an analog processing circuit. [Figure 6] 4 is a timing chart illustrating the operations of imaging and image processing. [Figure 7] 4 is a timing chart illustrating the operations of imaging and image processing. [Figure 8] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 9] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 10] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 11] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 12] 4A and 4B are diagrams for explaining the operations of the rolling shutter system and the global shutter system. [Figure 13] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 14] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 15] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 16] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 17] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 18] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 19] 1A and 1B are a cross-sectional view and a circuit diagram illustrating an imaging device. [Figure 20] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 21] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 22] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 23]FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 24] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 25] FIG. 1 is a block diagram illustrating an imaging apparatus. [Figure 26] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 27] FIG. 1 is a circuit diagram illustrating a memory element. [Figure 28] FIG. 1 is a cross-sectional view illustrating a structure of a memory element. [Figure 29] FIG. 1 is a cross-sectional view illustrating a structure of a memory element. [Diagram 30] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 31] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 32] 1A and 1B are diagrams illustrating a curved imaging device. [Diagram 33] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 34] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 35] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 36] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 37] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 40] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 41] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 42] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 43] FIG. 1 is a top view illustrating a transistor. [Diagram 44] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 45] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0023] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0024] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0025] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0026] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0027] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0028] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0029] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0031] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a transistor The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the transistor The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not include the second connection path, and the third connection path The connection path is the path through Z2. The source (or the first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, the first connection path does not have a second connection path, The second connection path includes a connection path through a transistor, and the second connection path includes a drain of the transistor. (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or the first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1, and the first electrical path is The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , the fourth electrical path is not included, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguish between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0032] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0034] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0035] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0036] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0037] FIG. 1 is a block diagram illustrating an imaging device according to an embodiment of the present invention. The image pickup unit 10 performs image pickup operations, and a calculation unit 11 mainly performs data conversion operations.

[0038] The imaging unit 10 has pixels 20 for imaging and reference pixels 22 for image processing arranged in a matrix. The pixel array 21 includes a row decoder 25 and an A / D converter 26. The unit 11 is a memory element array in which memory elements 30 and reference memory elements 32 are arranged in a matrix. The input / output terminal 31 has an analog processing circuit 34, a row decoder 35, and a column decoder 36. The imaging unit 10 and the calculation unit 11 are electrically connected via an analog processing circuit 24. Therefore, the analog processing circuit 24 is a component of the image pickup unit 10 and the calculation unit 11. It can be said that.

[0039] It is preferable that the imaging unit 10 and the calculation unit 11 have an overlapping area. For example, the imaging unit is provided on a first layer, the calculation unit is provided on a second layer, and the first layer and the second layer are Alternatively, a part of the pixel array 21 or the like may have an overlapping area. The elements of the imaging unit are provided on the first layer, and the other elements of the imaging unit and the calculation unit are provided on the second layer. Alternatively, the above elements may be arranged in three or more layers. By configuring the imaging device in this way, it is possible to reduce the size of the imaging device. A device configuration can be applied.

[0040] The row decoder 25 can output a signal WP, which is connected via a line 76 to the pixels 20 and the reference The row decoder 35 is connected to the pixel 22. The row decoder 35 can output a signal WW. The row decoder 35 is connected to the memory element 30 via a line 272. The row decoder 35 also outputs a signal WWR. The signal can be outputted from the reference memory element 32 via a wiring 276. The decoder 36 can output a signal RW, which is connected to the memory elements 30 and 31 via a line 271. It is connected to the reference memory element 32 .

[0041] In addition, the imaging device according to one embodiment of the present invention outputs imaging data from the pixel 20. The A / D converter 26 can be configured to have a function of converting the signal into digital form. However, the A / D converter 26 may be omitted.

[0042] The circuits constituting the pixels 20 and the reference pixels 22 are of the same configuration, and are arranged in a matrix. In a pixel array 21 having a plurality of formed pixels, a row at the end is set as a reference pixel 22. The reference pixel 22 is a pixel having a light-shielding layer. 15 is a light-shielded form.

[0043] In the imaging device according to one embodiment of the present invention shown in FIG. 1, the pixel 20 has a function of storing imaging data. By applying selection signals of different potentials to the pixels 20 in a plurality of rows, each pixel A current flows from 20 depending on the product of the potential of the image data and the potential of the selection signal. A first output data corresponding to the sum of these currents is obtained.

[0044] The memory element 30 has a function of holding the first output data. 0, a selection signal having a different potential is applied to each of the storage elements 30 to select the first output data. A current flows that depends on the product of the potential of the data and the potential of the selection signal. Then, second output data corresponding to the

[0045] The first output data corresponds to the data obtained by one-dimensional discrete cosine transform of the imaging data in the X-axis direction. The second output data is generated by performing a one-dimensional discrete cosine transformation on the first output data in the Y-axis direction. The converted data is the data obtained by performing a two-dimensional discrete cosine transform on the image data in the X and Y directions. This corresponds to .

[0046] FIG. 2 is a circuit diagram showing a specific configuration of the pixel array 21. The circuit in FIG. 2 includes a photoelectric conversion element PD, a transistor 41, a transistor 42, and a transistor The capacitor 43 and the capacitive element C1.

[0047] One electrode of the photoelectric conversion element PD (photodiode) is connected to the source electrode of the transistor 41. or drain electrode of the transistor 41. The other of the drain electrodes is electrically connected to one of the source electrode or drain electrode of the transistor 42. The other of the source electrode and the drain electrode of the transistor 41 is connected to a transistor 43 and the source or drain electrode of the transistor 41. The other pole is electrically connected to one electrode of the capacitive element C1.

[0048] Here, the other electrode of the photoelectric conversion element PD is electrically connected to the wiring 71 (VPD). The other of the source electrode and the drain electrode of the transistor 42 is electrically connected to the wiring 72 (VPR). One of the source electrode and the drain electrode of the transistor 43 is connected to the wiring 73 (VO ). The wiring 71 (VPD), the wiring 72 (VPR) and the wiring 73 (V O) can function as a power supply line, for example, wiring 71 (VPD) and wiring The line 73 (VO) functions as a low-potential power supply line, and the line 72 (VPR) functions as a high-potential power supply line. The wiring 74 (TX) and the wiring 75 (PR) are connected to each other to turn on and off the transistor. It can function as a signal line for controlling the

[0049] The other electrode of the capacitor C1 is electrically connected to the wiring 76. The other of the source electrode and the drain electrode is connected to a wiring 77 (a wiring 78 in the reference pixel 22). The wiring 76 is a signal line for supplying a desired potential to the charge storage unit (FD). The wiring 77 and the wiring 78 can function as a charge storage unit (F D) serves as a signal line for transistor 43 to pass a signal current according to the potential of This can be done.

[0050] Here, the transistor 41 controls the charge accumulation section (FD) in response to the output of the photoelectric conversion element PD. It can function as a transfer transistor to control the position of the transistor. The transistor 42 functions as a reset transistor that initializes the potential of the charge storage unit (FD). Also, the transistor 43 outputs an output according to the potential of the charge storage section (FD). The transistor can function as an amplifying transistor.

[0051] In FIG. 2, the pixel array 21 includes pixels 20[i,j], 20[i,j+1], 20[i+1,j], pixel 20[i+1,j+1], reference pixel 22[i], reference pixel 22 Although the example shows 2 rows and 3 columns of [i+1], it can be made up of n rows and m columns (n ​​and m are natural numbers greater than or equal to 2). The reference pixels 22 are arranged in a row at an end of the pixel array 21. That's good.

[0052] Here, potentials are supplied from a wiring 71 (VPD), a wiring 72 (VPR), and a wiring 73 (VO). The signal is fed to the wiring 74 (TX), the wiring 75 (PR), the wiring 76[i] and the wiring 76[i+1 ], the pixel is connected to the wiring 77[j], the wiring 77[j+1], and the wiring 78. The image data of the pixel 20 or the reference pixel 22 is output.

[0053] In addition, the charge storage unit (FD)[i,j], the charge storage unit (FD)[i,j+1], and the charge storage unit (FD)[i+1,j], charge storage section (FD)[i+1,j+1], charge storage section (FDR The charge storage unit (FDREF)[i] and the charge storage unit (FDREF)[i+1] store charge corresponding to the image data. As described above, the reference pixels 22[i] and 22[i+1] are occluded. The photoelectric conversion element PD is configured so that light does not reach the photoelectric conversion element PD.

[0054] FIG. 3 is a diagram showing an example of the configuration of the analog processing circuit 24 shown in FIG. The pixel includes a plurality of column output circuits (COUT) 27 and a reference current circuit (PCR) 28. In FIG. 3, column output circuits (COUT) 2 are provided in accordance with the number of columns of the pixels 20 illustrated in FIG. 7[j] and column output circuit (COUT) 27[j+1] are illustrated.

[0055] The column output circuit (COUT) 27 includes transistors 44 to 52, a capacitance element C2 , resistor R1, resistor R2, and operational amplifier 29. The source electrode of transistor 44 or One of the drain electrodes is electrically connected to one of the source electrode or drain electrode of the transistor 45. The other of the source electrode or the drain electrode of the transistor 44 is connected to a capacitance element C 2, and the source electrode or drain electrode of the transistor 44 The other end is electrically connected to a wiring 91 and serves as a source electrode or a drain electrode of the transistor 45. The other electrode is electrically connected to the gate electrode of the transistor 44 and the other electrode is electrically connected to the gate electrode of the transistor 45. The other of the source electrode and the drain electrode is electrically connected to the other electrode of the capacitance element C2. The gate electrode of the transistor 45 is electrically connected to the wiring 93 (PCSC). The wiring 91 can function as a power supply line, for example, a low power supply potential (VSS). The wiring 93 (PCSC) is connected to the transistor 45 and the transistor 52, and a signal line for controlling the on / off of a transistor 55 described later. It is possible.

[0056] In addition, the gate electrodes of the transistors 46 and 47 are transistors. The source electrode or the drain electrode of the capacitor 46 is electrically connected to the Here, the transistor 46 is an input side transistor, and the transistor 47 is an output side transistor. It can be called the input transistor.

[0057] One of the source electrode and the drain electrode of the transistor 46 is connected to the transistor 49 via One of the source electrode or drain electrode of the transistor 44 and the wiring 77 (BP) are electrically connected In addition, one of the source electrode and the drain electrode of the transistor 47 is connected to the transistor It is electrically connected to one input terminal (−) of the operational amplifier 29 via a transistor 50 . In addition, one of the input terminals of the operational amplifier 29 is connected to the output terminal of the operational amplifier 29 via a resistor R1. And it is electrically connected to the wiring 273 (WD).

[0058] The other of the source electrode or the drain electrode of the transistor 46 and the transistor 47 The other of the source electrode and the drain electrode is electrically connected to the wiring 92. The gate electrodes of the transistors 49 and 50 are electrically connected to the wiring 94 (PCOC). Here, the wiring 92 can function as a power supply line, for example, The power supply potential (VDD) can be supplied to the line 94 (PCOC). 49, transistor 50, transistor 51, and transistor 54 (to be described later) It can also function as a signal line for controlling the

[0059] In addition, one of the source electrode and the drain electrode of the transistor 48 is electrically connected to the wiring 92. The other of the source electrode and the drain electrode is connected to the op amp via a transistor 51. The other input terminal of the operational amplifier 29 is electrically connected to the other input terminal of the operational amplifier 29. is electrically connected to the wiring 91 via a resistor R2. The other of the electrodes or drain electrodes is connected to the source and drain electrodes of transistor 44 via transistor 52. The drain electrode and the wiring 77 (BP) can be electrically connected to one of the drain electrodes. do.

[0060] The reference current circuit (PCR) 28 includes transistors 53 to 55. One of the source electrode and the drain electrode of the transistor 53 is electrically connected to the wiring 92. The other of the source electrode and the drain electrode is connected to a wiring 78 (BPR) via a transistor 55. In addition, one of the source electrode and the drain electrode of the transistor 55 is electrically connected to is electrically connected to one of the source electrode and the drain electrode of the transistor 54. The other of the source electrode or drain electrode of the transistor 55 is connected to the source electrode of the transistor 54. Alternatively, the transistor 53 and the transistor 54 are electrically connected to each other of the drain electrodes. The transistor 48 constitutes a current mirror circuit. The transistor, transistor 48, can be referred to as the output transistor.

[0061] In the above configuration, the transistors 46, 47, and 48 and transistor 53 may be a p-ch transistor.

[0062] Here, a potential is supplied from the wiring 92, and a potential is applied to the wiring 93 (PCSC) or the wiring 94 (PCOC When a control signal is supplied from the wiring 78 (BPR), a current flows from the wiring 78 (BPR) to the reference pixel 22, and On line 96 a current source bias voltage (VPCR) is available.

[0063] A potential is supplied from the wiring 91 to the wiring 93 (PCSC) or the wiring 94 (PCOC). When a control signal is supplied from the A current flows from the input terminal of each column of pixels 20 to the output terminal of the operational amplifier 29 via a wiring 2 An output signal is output to wiring 73(WD)[j] and wiring 273(WD)[j+1].

[0064] The pixel array 21 and the analog processing circuit 24 are connected to each other via wiring 77 (BP) and wiring 78 ( The NI 8111 is electrically connected to the NI 8111 via the BPR.

[0065] FIG. 4 is a circuit diagram showing a specific configuration of the memory element array 31. The circuit of the reference memory element 32 includes a transistor 56, a transistor 57, and a capacitance element C Has 3.

[0066] One of the source and drain electrodes of transistor 56 is connected to the gate of transistor 57. The gate electrode of the transistor 57 is electrically connected to one of the electrodes of the capacitance element C3. and electrically connected to the

[0067] The other electrode of the capacitance element C3 is electrically connected to the wiring 271 (RW). The gate electrode of the transistor 56 is electrically connected to the wiring 272 (WW) or the wiring 276 (WWR). The other of the source electrode and the drain electrode of the transistor 56 is connected to a wiring 2 73 (WD) or wiring 278 (VDM). One of the source electrode and the drain electrode of the transistor 7 is electrically connected to the wiring 274 (VR). The other of the source electrode and the drain electrode of the transistor 57 is connected to a wiring 275 (BM ) or wiring 277 (BMR).

[0068] The wiring 271 (RW), the wiring 272 (WW) and the wiring 276 (WWR) are, for example, The wiring 273 (WD) can function as a signal line for controlling the on / off of the transistor. ) can function as a signal line for supplying a potential of data to be written to the memory element 30. Also, the wiring 274 (VR) and the wiring 278 (VDM) can function as power supply lines. In addition, the wiring 275 (BM) and the wiring 277 (BMR) can be, for example, The signal line serves as a signal line for outputting data from the memory element 30 or the reference memory element 32. It is possible.

[0069] Here, the transistor 56 is a write transistor for writing data to the charge storage unit (SN). The transistor 57 can function as a charge storage section (S N) can function as a readout transistor that outputs according to the potential of the

[0070] In FIG. 4, the memory element array 31 includes memory elements 30[k,j], 30[k,j +1], memory element 30[k+1,j], memory element 30[k+1,j+1], reference memory element In the example shown, the reference memory element 32[j] has 3 rows and 2 columns, and the reference memory element 32[j+1] has n rows and m columns (n ​​and The reference memory element 32 can be configured by a memory element. It is sufficient that they are provided in one row at the end of child array 31.

[0071] Here, a potential is supplied from the wiring 274 (VR) and the wiring 278 (VDM). 1(RW)[j], wiring 271(RW)[j+1], wiring 272(WW)[k], wiring 2 72(WW)[k+1], a control signal is supplied from the wiring 276(WWR), and the wiring 273( When data is input from the wire 275(WD)[j] and the wire 273(WD)[j+1], BM)[k], wiring 275 (BM)[k+1], wiring 277 (BMR), and the memory element 30 Alternatively, the data in the reference memory element 32 is output.

[0072] In addition, the charge storage unit (SN)[k,j], the charge storage unit (SN)[k,j+1], and the charge storage unit (SN)[k+1,j], the charge storage unit (SN)[k+1,j+1] is connected to the wiring 273 (W D) accumulates a charge corresponding to the potential of the charge storage unit (SNREF)[j] and the potential The charge storage unit (SNREF)[j+1] stores a charge corresponding to the potential of the wiring 278 (VDM). Accumulate.

[0073] The analog processing circuit 24 and the memory element array 31 are electrically connected via a wiring 273 (WD). are electrically connected.

[0074] FIG. 5 is a diagram showing an example of the configuration of the analog processing circuit 34 shown in FIG. The pixel includes a plurality of column output circuits (OUT) 227 and a reference current circuit (MCR) 228. In FIG. 5, a column output circuit (OUT ) 227[j] and column output circuit (OUT) 227[j+1].

[0075] The column output circuit (COUT) 27 includes transistors 58 to 66, a capacitance element C4 , resistor R3, resistor R4, and operational amplifier 229. One of the drain electrodes is electrically connected to one of the source electrode or drain electrode of the transistor 59. The other of the source electrode and the drain electrode of the transistor 58 is electrically connected to a capacitance element C4 and the source or drain electrode of transistor 58. The other electrode is electrically connected to the wiring 91 and serves as the source electrode or drain electrode of the transistor 59. The other of the electrodes is electrically connected to the gate electrode of the transistor 58. The other of the source electrode or the drain electrode is electrically connected to the other electrode of the capacitance element C4. The gate electrode of the transistor 59 is electrically connected to the wiring 293 (MCSC). Here, the wiring 293 (MCSC) is connected to the transistor 59, the transistor 66, and The input terminal 64 can function as a signal line for controlling the on / off of a transistor 69 connected to the input terminal 64 .

[0076] In addition, the gate electrodes of the transistors 60 and 61 are transistors. The source electrode or the drain electrode of the capacitor 60 is electrically connected to the Here, the transistor 60 is an input side transistor, and the transistor 61 is an output side transistor. It can be called the input transistor.

[0077] One of the source electrode and the drain electrode of the transistor 60 is connected to the transistor 63 via One of the source electrode or drain electrode of the transistor 58 and the wiring 275 (BM) are connected to the In addition, one of the source electrode and the drain electrode of the transistor 61 is electrically connected to It is electrically connected to one input terminal (-) of the operational amplifier 229 via the transistor 64. One input terminal of the operational amplifier 229 is connected to the The output terminal is electrically connected to the wiring 295 (OUT).

[0078] The other of the source electrode or the drain electrode of the transistor 60 and the transistor 61 The other of the source electrode and the drain electrode is electrically connected to the wiring 92. The gate electrodes of the transistors 63 and 64 are electrically connected to the wiring 294 (MCOC). Here, the wiring 294 (MCOC) is connected to the transistors 63 and 64. , and a signal line for controlling the on / off of a transistor 65 and a transistor 68 described later. It can have all the functions.

[0079] In addition, one of the source electrode and the drain electrode of the transistor 62 is electrically connected to the wiring 92. The other of the source electrode and the drain electrode is connected to the op amp via a transistor 65. The other input terminal of the operational amplifier 229 is electrically connected to the other input terminal of the operational amplifier 229. The terminal is electrically connected to the wiring 91 via a resistor R4. The other of the source and drain electrodes is connected to the source and drain electrodes of transistor 58 through transistor 66. The source electrode or the drain electrode and the wiring 275 (BM) are electrically connected to the can be done.

[0080] The reference current circuit (MCR) 228 includes transistors 67 to 69. One of the source electrode and the drain electrode of the transistor 67 is electrically connected to the wiring 92. The other of the source electrode and the drain electrode is connected to a wiring 277 (BM R) is electrically connected to the source electrode or drain electrode of the transistor 69. One of the terminals is electrically connected to one of the source electrode or the drain electrode of the transistor 68. The other of the source electrode or the drain electrode of the transistor 69 is connected to the source The transistor 67 and the transistor 68 are electrically connected to the other of the drain electrode and the drain electrode. The transistor 62 constitutes a current mirror circuit. The input transistor, transistor 62, can be referred to as the output transistor.

[0081] In the above configuration, the transistors 60, 61, 62, and and transistor 67 may be a p-ch transistor.

[0082] Here, a potential is supplied from the wiring 92, and a potential is applied to the wiring 293 (MCSC) or the wiring 294 (MC When a control signal is supplied from the line 277 (BMR), a current flows from the line 277 (BMR) to the reference memory element 32. flows, providing a current source bias voltage (VMCR) at line 296.

[0083] A potential is supplied from the wiring 91, and a potential is applied to the wiring 293 (MCSC) or the wiring 294 (MCO When a control signal is supplied from the line 275(BM)[j], the line 275(BM)[j +1] to the memory element 30 of each column, and is electrically connected to the output terminal of the operational amplifier 229. The output signal is sent to the wire 295(OUT)[j] and the wire 295(OUT)[j+1]. will be output.

[0084] The memory element array 31 and the analog processing circuit 34 are electrically connected via a wiring 275 (BM). are electrically connected.

[0085] The above-mentioned pixel 20, reference pixel 22, memory element 30, reference memory element 32, analog processing element The configurations of the control circuit 24 and the analog processing circuit 34 are merely examples. In some cases, the above-mentioned resistors, some of the capacitance elements, or some of the wirings may not be included. In some cases, circuits, transistors, capacitors, wiring, etc. that are not included in the configuration may be included. However, the connection form of some of the wiring may differ from the above-mentioned configuration.

[0086] Next, the timing charts shown in FIG. 6 and FIG. 7 will be used to explain the operation of the imaging device according to one embodiment of the present invention. An example of the operation will be described. Note that IP[j] shown in FIG. 6 flows through the wiring 77(BP)[j]. current signal, IP[j+1] is the current signal flowing through wiring 77(BP)[j+1], and IPR is the 7 is a current signal flowing through the line 78 (BPR). Also, IM[k] shown in FIG. The current signal IM[k+1] flows through the wiring 275(BM)[k+1]. The current signal IMR is a current signal flowing through the wiring 277 (BMR). VPD) is at low potential, wiring 72 (VPR) is at high potential, wiring 73 (VO) is at low potential, wiring 91 is at low potential, the wiring 92 is at high potential, the wiring 274 (VR) is at low potential, and the wiring 278 (VDM) is at random. The potential is the desired electric potential.

[0087] In FIG. 6, from time T01 to time T03, the image data is captured by each pixel 20 and each reference pixel 22. The period from time T04 to time T05 corresponds to an operation of acquiring data from the column output circuit (CO The period from time T06 to time T09 corresponds to an operation of setting a correction voltage to the output of the power supply 10 (UT) 27. This corresponds to an operation of obtaining first output data by performing arithmetic processing on the imaging data of each pixel.

[0088] In FIG. 7, the first output data is stored in each storage element 30 from time T06 to time T11. The period from time T12 to time T13 corresponds to an operation of storing data in the column output circuit 227 (OUT). The period from time T14 to time T17 corresponds to an operation for setting the correction voltage. This corresponds to an operation of obtaining second output data by performing arithmetic processing on the output data.

[0089] The transistors 43, 44, 46 to 48, Transistor 52, transistor 57, transistor 58, transistor 60 to transistor The resistor 62 and the transistor 67 are assumed to operate in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor are in the saturation region. The voltage is set to a range in which the transistor operates in the Even if the operation deviates from the ideal saturation region, the accuracy of the output data can be obtained within the desired range. If the transistor is connected to the power supply, the gate voltage, source voltage, and drain voltage of the transistor are appropriately set. The other transistors can be controlled to be on and off. It is sufficient that the switch has a switching function.

[0090] Between time T01 and time T02, the potential of the wiring 75 (PR) is set to “H” and the potential of the wiring 74 (TX ) is set to "H". At this time, the electric potential of the charge storage unit (FD) and the charge storage unit (FDREF ) is set to the potential of the wiring 72 (VPR).

[0091] Between time T02 and time T03, the potential of the wiring 75 (PR) is set to “L” and the potential of the wiring 74 (TX ) is set to "H". At this time, the charge accumulation The potential of the wiring 72 (VPR) is VPR, and the potential of the charge storage section (FD) is decreased. If the potential drop of (FD) is VP, the potential of the charge storage section (FD) is VPR-VP. The stronger the light irradiating the photoelectric conversion element PD, the lower the potential of the charge storage section (FD). do.

[0092] In the reference pixel 22, the photoelectric conversion element PD is shielded from light, so ideally, the charge The potential of the storage section (FDREF) is held at VPR. Since dark current flows in the PD, the potential of the charge storage section (FDREF) is slightly lower than VPR. However, the potential of the charge storage unit (FD) in the pixel 20 also decreases due to the dark current. Also, the charge storage unit (FD) in the pixel 20 and the reference pixel 22 The potential difference with the charge storage section (FDREF) contributes to the output data, so the dark current Therefore, the potential drop of the charge storage section (FDREF) due to the dark current is It does not need to be explicitly considered.

[0093] Now, when the potential of the wiring 76(WP)[i] is VWP[i], the pixel 20[i,j] has The drain current of the transistor 43 in +VPR-VP[i,j]) 2 In addition, the transistor in the reference pixel 22[i] The drain current of 43 is IPR[i]=α(VWP[i]-Vth+VPR) 2 It becomes.

[0094] Here, α is a coefficient, and Vth is the threshold voltage of the transistor 43. The potential of WP)[i] is superimposed on the gate potential of the transistor 43 via the capacitance element C1. Therefore, the change in the potential of the wiring 76(WP)[i] directly increases the gate potential of the transistor 43. More specifically, the capacitance of the capacitive element C1 and the gate capacitance of the transistor 43 are not the same. The capacitance coupling coefficient, which can be calculated from the parasitic capacitance, is multiplied by the potential change of the wiring 76 (WP) [i]. The change in potential is the increment in the gate potential of the transistor 43. The potential multiplied by the capacitance coupling coefficient is VWP[i], but is actually supplied to the wiring 76(WP)[i]. The potential to be measured may be appropriately converted using the capacitive coupling coefficient.

[0095] Here, the current flowing through the wire 77(BP)[j] is IP[j]=Σ i IP[i,j], wiring Current flowing through 78(BPR) IPR=Σ i IPR[i], the difference is ΔIP[j ]=IPR-IP[j]=Σ i IPR[i]-Σ i IP[i,j]=Σ i (α(VWP[ i]-Vth+VPR) 2 -α(VWP[i]-Vth+VPR-VP[i,j]) 2 ) =2αΣ i (VWP[i] VP[i,j])-2αΣ i (Vth-VPR) VP[i ,j]-αΣ i VP[i,j] 2 It is.

[0096] 1st term 2αΣ i (VWP[i] VP[i,j]) is the wiring 76 (WP) in the jth column. [i] potential VWP[i] and charge storage section (FD)[i,j] in pixel 20[i,j] This corresponds to the sum of the products of the potential changes VP[i,j] and the sum of the second and third terms -2αΣ i (V th-VPR)·VP[i,j]-αΣ i VP[i,j] 2 =IPoffset[j] Current IP[j] flowing through wire 77 (BP)[j] and current IP flowing through wire 78 (BPR) It can be calculated by subtracting it from the difference ΔIP[j] with R.

[0097] IPoffset[j] is VWP[i] set to 0, that is, wiring 76(WP)[i ] is set to 0, the current IP[j] flowing through the wire 77(BP)[j] and the current IP[j] flowing through the wire 78( BPR) and the potential of the wiring 76 (WP) [i]. 0 corresponds to an arbitrary reference potential, and the difference from that reference potential is the potential of the wire 76 (WP) [i]. It shall represent the rank.

[0098] Between time T04 and time T05, the potential of the wiring 93 (PCSC) is set to “H” and the potential of the wiring 76 ( The potential of the wiring 76(WP)[i] is set to 0, and the potential of the wiring 76(WP)[i+1] is set to 0. Current IP[j] flows through wire 77(BP)[j], and current IP[j+1] flows through wire 77(BP)[j+ 1], a current IPR flows through the wiring 78 (BPR), and the column output circuit (COUT) 27[j] A current IPC[j] flows through the transistor 44 in the column output circuit (COUT) 27[j+ A current IPC[j+1] flows through transistor 44 in node 1].

[0099] Now, the current mirror circuit consisting of transistors 48 and 53 The current flowing through transistor 48 and transistor 52 is and the current flowing through transistor 55, i.e., IPR. Therefore, The current IPR is equal to the sum of the current IP[j] and the current IPC[j] (IPR=I P[j]+IPC[j]).

[0100] In addition, the capacitance element C2 is charged with a potential capable of supplying a current IPC[j]=IPR-IP[j]. Here, as mentioned above, IPoffset[j]=IPR-IP[ j], and the current IPC[j] is equal to IPoffset[j]. Therefore, after the potential of the wiring 93 (PCSC) is set to "L", the column output circuit (COUT) 27 j], the transistor 44 is turned on by the potential held in the capacitor C2. It functions as a current source supplying et[j].

[0101] Similarly, in the column output circuit (COUT) 27[j+1], the transistor 44 is a capacitance element The potential held in C2 acts as a current source to supply IPoffset[j+1] do.

[0102] Between time T06 and time T07, the potential of the wiring 76(WP)[i] is VWP[i,k] , the potential of the wiring 76 (WP) [i+1] is VWP [i+1, k], the potential of the wiring 94 (PCOC) The potential is set to “H”. At this time, in the column output circuit (COUT) 27[j], a current IP A current equal to the sum of current IPC[j]=IPoffset[j] flows through transistor 4. Flows through 9.

[0103] In addition, a current mirror circuit formed by transistors 46 and 47 A current equal to the current flowing through transistor 49 flows through transistors 47 and 50. On the other hand, the current IPR flows through the transistor 54 to the wiring 78 (B In addition, the current mirror consisting of transistor 48 and transistor 53 By this circuit, a current equal to the current IPR flows through transistor 48 and transistor 51. and flows into resistor R2.

[0104] Here, the resistance values ​​of resistors R1 and R2 are equal to R, and the potential of wiring 278 (VDM) is V If DM, the output of the operational amplifier (AMP) 29 is the potential V of the wire 273 (WD) [j]. WD[j]=VDM+R·(IPR-(IP[j]+IPoffset[j])) From the above discussion, VDM+R·2αΣ i (VWP[i,k] VP[i,j]) = VD MF j [k].

[0105] Similarly, the output of the operational amplifier (AMP) 29 in the column output circuit (COUT) 27[j+1] The force is the potential of wire 273 (WD) [j+1] VWD [j+1] = VDM + R 2αΣ i ( VWP[i,k] VP[i,j+1]) = VDM-F j+1 [k].

[0106] At times T08 and T09, the potential of the wiring 76(WP)[i] is VWP[i,k+1] , the potential of the wiring 76 (WP) [i+1] is VWP [i+1, k+1], and the potential of the wiring 94 (PCOC ) is set to "H". At this time, as in the case of time T06 to time T07, the potential of the column output circuit ( The output of the operational amplifier (AMP) 29 in the COUT 27[j] is connected to the wiring 273 (WD) [j]'s potential VWD[j]=VDM+R·2αΣ i (VWP[i,k+1] VP[i, j])=VDM-F j [k+1]. Also, the column output circuit (COUT) 27[j+1] The output of the operational amplifier (AMP) 29 in D[j+1]=VDM+R·2αΣ i (VWP[i,k+1] VP[i,j+1]) = VDM-F j+1 The result is [k+1].

[0107] In addition, between time T06 and time T07, the potential of the wiring 272(WW)[k] is If the potential of the wiring 272 (WW) [k+1] is set to “L”, then the potential of the wiring 273 (WD) [j ] potential VWD[j]=VDM-F j [k], potential VW of wiring 273(WD)[j+1] D[j+1]=VDM-F j+1 [k] are the storage elements 30[k,j] and 30[ At this time, the potential of the charge storage unit (SN)[k,j] is VDM -F j [k], the potential of the charge storage section (SN) [k, j+1] is VDM-F j+1 Set to [k] It is determined.

[0108] In addition, between time T08 and time T09, the potential of the wiring 272(WW)[k] is If the potential of the wiring 272 (WW) [k+1] is “H”, then the potential of the wiring 273 (WD) [j ] potential VWD[j]=VDM-F j [k+1], potential of wiring 273 (WD) [j+1] VWD[j+1]=VDM-F j+1 [k+1] are the storage elements 30[k+1,j], At this time, the charge storage unit (SN) [k+1 ,j] is VDM-F j [k+1], potential of charge storage section (SN) [k+1,j+1] is VDM-F j+1 It is set to [k+1].

[0109] From time T10 to time T11, when the potential of the wiring 276 (WWR) is set to “H”, The potential of the charge storage unit (SNREF)[j] of the reference memory element 32[j] is VDM, The potential of the charge storage unit (SNREF)[j+1] of 32[j+1] is set to VDM.

[0110] Now, when the potential of the wiring 271(RW)[j] is VWM[j], The drain current of transistor 57 at k,j] is expressed as IM[k,j]=β(VWM[j]- Vth+VDM-F j [k]) 2 In addition, the transaction in the reference memory element 32[j] The drain current of transistor 57 is IMR[i]=β(VWM[j]-Vth+VDM). 2 and where β is a coefficient and Vth is the threshold voltage of the transistor 57.

[0111] The potential of the wiring 271(RW)[j] is connected to the gate of the transistor 57 through the capacitor C3. Since the potential of the wiring 271(RW)[j] is superimposed on the potential of the transistor, the potential change of the wiring 271(RW)[j] is directly More specifically, the capacitance of the capacitance element C3 and the The capacitance coupling coefficient, which can be calculated from the gate capacitance and parasitic capacitance of the transistor 57, is The potential change multiplied by the potential change of the transistor 57 is the increment of the gate potential of the transistor 57. For simplicity, let VWM[j] be the potential multiplied by the capacitive coupling coefficient. The potential supplied to 271(RW)[j] can be appropriately converted using the capacitive coupling coefficient. Good.

[0112] Here, the current IM[k] flowing through the wiring 275(BM)[k] is equal to Σ i IM[k,j], wiring Current flowing through 277(BMR) IMR=Σ i Considering IMR[j], the difference is ΔIM [k] = IMR - IM[k] = Σ i IMR[j]-Σ iIM[k,j]=Σ i (β(VW M[j]-Vth+VDM) 2 -β(VWM[j]-Vth+VDM-F j [k]) 2 ) =2βΣ i (VWM[j] F j [k])-2βΣ i (Vth-VDM)·F j [k] - βΣ i F j [k] 2 It is.

[0113] First term 2βΣ i (VWM[j] F j [k]) is the wiring 271 (RW) [ potential VWM[j] of the storage element 30[k,j] and the charge storage unit (SN)[k, j] and VDM, F j [k] and the sum of the products of . That is, the second term and the sum of the third term -2βΣ i (Vth-VDM)·F j [k]-βΣ i F j [k] 2 =IM offset[k] is the current IM[k] flowing through the wiring 275(BM)[k] and the wiring 277( It can be calculated by subtracting the difference ΔIM[k] between the current IMR flowing through the Note that IMoffset[k] is set to 0 for VWM[j], i.e., The current IM flowing through wiring 275 (BM) [k] when the potential of 271 (RW) [j] is set to 0 It corresponds to the difference between [k] and the current IMR flowing through the wiring 277 (BMR). The potential 0 of 1(RW)[j] corresponds to an arbitrary reference potential, and the difference from that reference potential is the wiring Let 271(RW)[j] represent the potential of

[0114] Between time T12 and time T13, the potential of the wiring 293 (MCSC) is set to “H” and the potential of the wiring 27 The potential of the wiring 271(RW)[j+1] is set to 0. , a current IM[k] flows through the wiring 275 (BM)[k], and a current IM R flows, and a current IMC In addition, a current IM[j+1] flows through the wiring 275(BM)[k+1], and A current IMR flows through the line 277 (BMR), and a current IMR flows through the column output circuit (OUT) 227[k+1]. A current IMC[k+1] flows through the transistor 54 .

[0115] Now, in the column output circuit (OUT) 227[k], the transistor 62 and the transistor 6 A current mirror circuit formed by 7 drives transistors 62 and 66. The current (IM[k]+IMC[k]) flowing through transistor 67 and transistor The current flowing through the capacitor 69, i.e., the current IMR, is equal to the current flowing through the capacitor C4. The potential that can supply the current IMC[k] is stored in the By theory, we can see that the current IMC[k] is equal to IMoffset[k]. Then, after the potential of the wiring 293 (MCSC) is set to "L", the column output circuit (OUT) 227 [ k], the transistor 58 is turned on by the potential held in the capacitor C4. Similarly, the column output circuit (OUT) 22 functions as a current source that supplies et[k]. The transistor 58 at 7[k+1] is connected to the IM Functions as a current source that supplies offset[k+1].

[0116] Between time T14 and time T15, the potential of the wiring 271(RW)[j] is VWM[j,l ], the potential of the wiring 271 (RW) [j+1] is VWM [j+1, l], the potential of the wiring 294 (MCO At this time, the potential of the column output circuit (OUT) 227[k] is set to “H”. A current equal to the sum of current IM[k] and current IMC[k] = IMoffset[k] flows through the transistor. It flows through Sta. 63.

[0117] In addition, a current mirror circuit formed by transistors 60 and 61 A current equal to the current flowing through transistor 63 flows through transistors 61 and 64. On the other hand, the current IMR flows through the wiring 277( Also, a current flows through the current mirror formed by transistors 62 and 67. The resistor circuit causes a current equal to the current IMR to flow through transistors 62 and 65. It flows through resistor R4.

[0118] Here, if the resistance values ​​of resistors R3 and R4 are equal, R, then wiring 295 (OUT) [k] The output potential of the operational amplifier (AMP) 229 is the potential VOUT[k]=R (I MR-(IM[k]+IMoffset[k])), and from the above discussion, R 2βΣ i (VWM[j,l] F j [k]) = F[k,l].

[0119] Similarly, in the column output circuit (OUT) 227[k+1], the wiring 295(OUT)[k+ The output potential of the operational amplifier (AMP) 229 output to the input terminal 1 is the potential VOUT[k+1]= R 2βΣ i (VWM[j,l] F j [k+1]) = F[k+1,l].

[0120] At time T16 to time T17, the potential of the wiring 271(RW)[j] is set to VWM[j,l +1], and the potential of the wiring 271(RW)[j+1] is VWM[j+1,l+1], and the potential of the wiring 294 The potential of (MCOC) is set to "H". At this time, as in the time T14 to the time T15, In the output circuit (OUT) 227[k], an output signal is output to the wiring 295(OUT)[k]. The output potential of the amplifier (AMP) 229 is the potential VOUT[k]=R·2βΣ i (VWM[ j,l+1]·F j [k]) = F[k,l+1]. Also, the column output circuit (OUT) 2 In 27[k+1], the operational amplifier (A The output potential of MP)229 is the potential VOUT[k+1]=R·2βΣ i (VWM[j,l+ 1]·F j [k+1]) = F[k+1,l+1].

[0121] Here, F j [k]=-R 2αΣ i (VWP[i,k] VP[i,j]) = C[k] / 2 Σ i VP[i,j]·cos((2i+1)kπ / 2(imax-1)), F[k ,l]=R·2βΣ i (VWM[j,l] F j [k])=C[l] / 2 Σ i F j [k ]·cos((2j+1)lπ / 2(jmax-1)), C[n]=1 / √2(n=0) , 1 (n ≠ 0), set VWP[i,k] and VWM[j,l], then F[k , l] corresponds to a transform coefficient obtained by performing a two-dimensional discrete cosine transform on VP[i, j].

[0122] Therefore, by applying the potential to the wiring 76 (WP) and the wiring 271 (RW) in this order, In one embodiment of the present invention, the imaging There is no need to perform a two-dimensional discrete cosine transform after A / D conversion and output of the data. In addition, since there is no need to input or output data to the digital memory during the two-dimensional discrete cosine transform process, power consumption is reduced. This can reduce power consumption. It is also possible to perform a two-dimensional discrete sine transform in a similar manner. It is possible.

[0123] It is also possible to perform the two-dimensional discrete cosine transform in any matrix unit. For example, If you want to do this in 8-row, 8-column units, use imax=8 and jmax=8 in the formula in the previous paragraph, and wiring 76 ( After applying a desired potential to the wiring 271 (WP) in units of eight rows, the desired potential is applied to the wiring 271 (RW) in units of eight columns. In this case, the memory element 30 in FIG. In a few minutes, two-dimensional discrete cosine transform is possible.

[0124] In addition, in the pixel 20 of FIG. 2, data is repeatedly output from a plurality of pixels 20 at the same time. Therefore, it is preferable to obtain the image data in a lump. It is preferable to capture the image using a single shutter system.

[0125] To enable such a configuration, the transistors 41 and 42 are turned off. It is preferable to use a transistor including an oxide semiconductor, which has an extremely low current. In order to maintain the set current, transistor 45 and transistor 46 in analog processing circuit 24 are connected to each other. The transistor 59 in the analog processing circuit 34 is made of an oxide semiconductor having an extremely low off-state current. It is preferable to use a transistor having a capacitance of 100 nm.

[0126] With the above configuration, the image data is converted into digital data through A / D conversion processing. It is now possible to perform discrete cosine transform processing on analog data without performing any conversion. Therefore, it is possible to provide an imaging device capable of performing data compression processing with low power consumption.

[0127] The circuits of the pixel 20 and the reference pixel 22 are not limited to the configuration shown in FIG. 2, but may be any of the configurations shown in FIGS. The pixel circuit may have a structure shown in FIG. As shown in FIG. 8(E) or FIG. 8(F), the transistor 41, the transistor 42, and the transistor The transistor 43 may have a back gate. This is a configuration in which a constant potential is applied, and the threshold voltage can be controlled. In this case, the same potential as that applied to the front gate is applied to the back gate, which increases the on-current. In FIG. 8E, the back gate is electrically connected to the wiring 73. However, it may be electrically connected to another wiring to which a constant potential is supplied. 8E and 8F show the pixel circuit shown in FIG. 2 in which a back gate is provided to the transistor. The same configuration can be realized by using the circuits shown in Figs. 8(A), (B), (C), and (D). It can also be applied to a transistor included in one pixel circuit. A constant potential is applied to the back gate. A circuit configuration that can be arbitrarily combined with a configuration with or without a back gate as needed. It is also possible to use the following.

[0128] As shown in FIG. 9A, the transistor 40 is provided between the transistor 43 and the wiring 77. The transistor 401 is controlled by the potential of the wiring 701. As shown in FIG. 9(B), A transistor 402 may be provided between the transistor 43 and the wiring 73. The transistor 402 is a switching transistor controlled by the potential of the wiring 702. It has the following functions.

[0129] The circuits of the pixel 20 and the reference pixel 22 are also shown in FIG. The transistor 43 may be shared by multiple pixels. In the example shown, the transistor 42 and the transistor 43 are shared in the pixel. The transistors 42 and 43 are shared by multiple pixels in the horizontal or vertical direction. By using such a configuration, the number of transistors per pixel can be reduced. In FIG. 10, the transistors 42 and 43 are four. Although a configuration in which the light source is shared by a pixel is illustrated, the light source may be shared by two pixels, three pixels, five pixels or more. In addition, the configuration shown in FIG. 8(A) to FIG. 8(D) and the configuration shown in FIG. 9(A) and (B) The configurations shown can be combined in any way.

[0130] Next, a specific configuration example of the imaging device of one embodiment of the present invention will be described with reference to the drawings. FIG. 11A shows the photoelectric conversion element PD, the transistor 41, and the transistor 1 shows an example of a specific connection state of the transistor 42 and the capacitance element C1. The transistor 43 is not shown in FIG. 1(A). The pixel 20 includes the transistors 41 to A layer 1100 in which the transistor 43 and the capacitance element C1 are provided, and a photoelectric conversion element PD The semiconductor device has a layer 1200 on which the

[0131] In the cross-sectional views described in this embodiment, each wiring, each electrode, and each conductor is shown as an individual Although illustrated as elements, they are the same element when they are electrically connected. In addition, the gate electrode, source electrode, or drain electrode of a transistor may be provided as a gate electrode. The form in which the drain electrode is connected to each wiring via a conductor is one example. In some cases, the source electrode, drain electrode, or the insulator electrode functions as wiring. be.

[0132] In addition, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film is formed on each element. For example, the insulating layer 82 and the insulating layer 83 are made of silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. The top surface of the 3rd class may be polished by CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a flattening process by a flattening method or the like.

[0133] In addition, in some cases, wiring, etc., not shown in the drawings may not be provided, or wiring, etc., not shown in the drawings may not be provided. In some cases, each layer may contain transistors, etc. Also, layers not shown in the drawings may be included in the laminate structure. In some cases, some layers shown in the drawings may not be included.

[0134] The transistors 41 to 43 are transistors including an oxide semiconductor (hereinafter It is particularly preferable to use an OS transistor.

[0135] OS transistors have extremely low off-state current characteristics, expanding the dynamic range of imaging. In the circuit configuration of the pixel 20 shown in FIG. When the intensity of the light is high, the potential of the charge storage section (FD) becomes small. Since the transistor has an extremely low off-state current, Therefore, it is possible to accurately output a current according to the gate potential. This can widen the range of illuminance that can be used, i.e., the dynamic range.

[0136] In addition, the low off-current characteristics of the transistors 41 and 42 reduce the charge storage capacity. (FD) can hold a charge for an extremely long period of time. Global shutter allows charge accumulation in all pixels simultaneously without complicating the operation method. The data method can be applied.

[0137] Generally, in an imaging device in which pixels are arranged in a matrix, the following is performed for each row as shown in FIG. A rolling driving method for performing an imaging operation 12, a data holding operation 13, and a read operation 14. When using the rolling shutter method, the simultaneity of imaging is Since this is lost, if the subject moves, the image will be distorted.

[0138] Therefore, one embodiment of the present invention is to perform imaging operation 12 and data simultaneously on all rows shown in FIG. A global shutter method in which a hold operation 13 is performed and a read operation 14 is performed row by row. By using the global shutter method, each pixel of the image pickup device This ensures simultaneous imaging of the object, and reduces distortion even when the object moves. In addition, the global shutter method allows the exposure time (charge Since the period during which the accumulation operation is performed can be extended, it is also suitable for imaging in low-light environments. Suitable.

[0139] An OS transistor is a transistor that uses silicon in the active region or active layer (hereafter referred to as Because the temperature dependency of the electrical characteristics is smaller than that of silicon transistors, the Therefore, imaging devices and semiconductor devices having OS transistors can be used in a wide range of applications. The conductor device is also suitable for installation in automobiles, aircraft, spacecraft, and the like.

[0140] In addition, the OS transistor has a higher drain withstand voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, the avalanche phenomenon is likely to occur. It is preferable to apply a relatively high voltage (e.g., 10 V or more) so that Combining an S transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer This makes it possible to provide a highly reliable imaging device.

[0141] Note that in FIG. 11A, each transistor has a back gate. However, as shown in FIG. 11(B), a configuration without a back gate is also possible. As shown in FIG. 11C, only some of the transistors, for example the transistor 41, have a backgain. The back gate may have a structure in which the transistors are arranged opposite to each other. In some cases, the back gate of the transistor may be electrically connected to the front gate of the transistor. A fixed potential different from that of the front gate may be supplied to the back gate. The form regarding the presence or absence can be applied to other pixel configurations described in this embodiment mode. .

[0142] The photoelectric conversion element PD provided in the layer 1200 can be an element of various types. FIG. 11A illustrates a mode in which a selenium-based material is used for the photoelectric conversion layer 561. Photoelectric conversion elements (PDs) made of silicon-based materials have the characteristic of having high external quantum efficiency for visible light. In this photoelectric conversion element, the avalanche phenomenon causes the amplification of electrons relative to the amount of light incident on the device. In addition, selenium-based materials have a high light absorption coefficient, This has the advantage that the photoelectric conversion layer 561 can be easily made thin.

[0143] The selenium-based material may be amorphous or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then performing a heat treatment. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0144] Although the photoelectric conversion layer 561 is illustrated as a single layer, the selenium-based material is a material having a hole injection layer on the light receiving surface side. Gallium oxide or cerium oxide is provided as an electron injection blocking layer on the electrode 566 side. The stop layer may be made of nickel oxide or antimony sulfide.

[0145] The photoelectric conversion layer 561 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon can be utilized in the same way as in the case of elemental selenium. It is possible to form a photoelectric conversion element that can be used.

[0146] The photoelectric conversion element PD using a selenium-based material has an electrode 56 formed of, for example, a metal material. A photoelectric conversion layer 561 may be provided between the insulating layer 6 and the light-transmitting conductive layer 562. In addition, CIS and CIGS are p-type semiconductors and require sulfurization of n-type semiconductors to form a junction. Cadmium, zinc sulfide, or the like may be provided in contact with the metal.

[0147] In order to generate the avalanche phenomenon, a relatively high voltage (e.g., 10 It is preferable to apply a voltage of 100 V or more to the OS transistor. Because it has high withstand voltage characteristics, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with high drain withstand voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be obtained. It is possible.

[0148] In FIG. 11A, the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are divided between pixel circuits. However, as shown in FIG. 13(A), the circuits may be separated from each other. In addition, a partition wall 567 made of an insulator is provided between pixels in a region not having an electrode 566. It is preferable to prevent cracks from occurring in the photoelectric conversion layer 561 and the light-transmitting conductive layer 562. However, as shown in FIG. 13B, a configuration without the partition wall 567 may be used. In (A), a wiring 88 and a conductor 81 are provided between the transparent conductive layer 562 and the wiring 87. 13(C) and (D), the transparent conductive layer 562 and the wiring 8 7 may be in direct contact with each other.

[0149] The electrode 566 and the wiring 87 may be multi-layered. For example, as shown in FIG. As shown in FIG. 1, the electrode 566 is formed of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 87 is formed of the conductive layer In the structure shown in FIG. 14(A), For example, the conductive layer 566a and the conductive layer 87a are formed by selecting a low-resistance metal or the like, and the conductive layer 566b and the conductive layer 87b are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals may be electrolytically corroded by contacting the transparent conductive layer 562. Even if such a metal is used for the conductive layer 87a, the conductive layer 87b may cause a This can prevent electrolytic corrosion.

[0150] The conductive layer 566b and the conductive layer 87b are made of, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 87a may be made of, for example, aluminum. , titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0151] Also, the insulating layer 82 may have a multi-layer structure. For example, as shown in FIG. The insulating layer 82 has an insulating layer 82a and an insulating layer 82b, and the insulating layer 82a and the insulating layer 8 If the etching rate of the conductor 81 is different from that of the layer 2b, the conductor 81 will have a step. In the case where other insulating layers used for the interlayer insulating film or the planarizing film are multi-layered, the conductor 81 is also In this embodiment, the insulating layer 82 has two layers. The insulating layers 82 and other layers may be made up of three or more layers.

[0152] The partition wall 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. In addition, the partition 567 is provided for blocking light from a transistor or the like and / or for preventing the number of pixels per pixel from increasing. The light receiving portion may be colored black or the like to define the area of ​​the light receiving portion.

[0153] In addition, the photoelectric conversion element PD is a pin A diode element or the like may also be used.

[0154] For example, FIG. 15 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode includes an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type The i-type semiconductor layer 564 has an amorphous structure. It is preferable to use silicon. In addition, the p-type semiconductor layer 563 and the n-type semiconductor layer 5 65 is made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. A photodiode with amorphous silicon as the photoelectric conversion layer can be used. has high sensitivity in the visible light wavelength range and is easy to detect weak visible light.

[0155] In the photoelectric conversion element PD shown in FIG. 15, an n-type semiconductor layer 565 acting as a cathode is It has an electrical connection to an electrode 566 which has an electrical connection to a transistor 41. The p-type semiconductor layer 563 acting as a gate is electrically connected to the wiring 87 via the conductor 81. has.

[0156] In the circuit diagram for explaining the pixel 20 shown in FIG. 2, the photoelectric conversion element PD is connected in the manner shown in FIG. The photoelectric conversion element P in FIG. The connection form between the anode and cathode of D and the electrode layer and wiring may be reversed.

[0157] In either case, the photoelectric conversion element is arranged so that the p-type semiconductor layer 563 serves as a light receiving surface. It is preferable to form a photodiode PD on the p-type semiconductor layer 563. The output current of the converter PD can be increased.

[0158] Also, the configuration of a photoelectric conversion element PD having a pin-type thin-film photodiode, and The photoelectric conversion element PD and the wiring connection form are shown in Fig. 16(A), (B), (C), (D), The examples shown in (E) and (F) may also be used. The connection form between the PD and the wiring is not limited to these, and other forms may be used.

[0159] FIG. 16A shows a light-transmitting conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The transparent conductive layer 562 acts as an electrode and outputs the photoelectric conversion element PD. The current can be increased.

[0160] The transparent conductive layer 562 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, or graphite The light-transmitting conductive layer 562 is not limited to a single layer, but may be a stack of different films. It may be.

[0161] FIG. 16B shows that the p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 88 are electrically connected. It is a configuration in which it is directly included.

[0162] FIG. 16C shows a transparent conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The wiring 87 and the light-transmitting conductive layer 562 are electrically connected to each other.

[0163] FIG. 16D shows an opening in the insulating layer covering the photoelectric conversion element PD, through which the p-type semiconductor layer 563 is exposed. A light-transmitting conductive layer 562 covering the opening is electrically connected to the wiring 88. It is a composition.

[0164] FIG. 16E shows a configuration in which a conductor 81 is provided to penetrate the photoelectric conversion element PD. In this configuration, the wiring 87 is electrically connected to the p-type semiconductor layer 563 via the conductor 81 . In the drawing, the wiring 87 and the electrode 566 are apparently connected via the n-type semiconductor layer 565. However, the lateral resistance of the n-type semiconductor layer 565 is Therefore, if an appropriate distance is provided between the wiring 87 and the electrode 566, the resistance between them is extremely high. Therefore, the photoelectric conversion element PD does not short-circuit the anode and cathode, It can have diode characteristics. There may be a plurality of conductors 81 .

[0165] FIG. 16F shows a photoelectric conversion element PD of FIG. 16E connected to a p-type semiconductor layer 563. In this embodiment, a light-transmitting conductive layer 562 is provided.

[0166] In the photoelectric conversion element PD shown in FIG. 16(D), FIG. 16(E), and FIG. 16(F), Since the light receiving region does not overlap with wiring, etc., this has the advantage that a wide light receiving area can be secured.

[0167] As shown in FIG. 17, the photoelectric conversion element PD has a silicon substrate 600 as a photoelectric conversion layer. A photodiode having a capacitance of 100 .mu.m may also be used.

[0168] The photoelectric conversion element PD formed using the above-mentioned selenium-based material and amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, selenium-based materials have high resistance, and as shown in Figure 11(A), The switching layer 561 may be configured not to separate the circuits. The imaging device can be manufactured at a high yield and low cost. When forming a photodiode with 600 as the photoelectric conversion layer, the polishing process and bonding process are This requires highly difficult processes such as

[0169] In addition, the imaging device according to one embodiment of the present invention includes a silicon substrate 600 on which a circuit is formed. For example, as shown in FIG. 18(A), an active region may be formed on a silicon substrate 600. A layer 1400 having a transistor 610 and a transistor 620 overlaps the pixel circuit. Note that FIG. 18B is a cross-sectional view in the channel width direction of a transistor. This corresponds to a surface view.

[0170] Here, in FIG. 18(A) and (B), the Si transistor is illustrated as having a fin-type structure. However, it may be a planar type as shown in FIG. 19(A). As shown in FIG. 6, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulator). r) single crystal silicon.

[0171] The circuit formed on the silicon substrate 600 has a function of reading out the signal output by the pixel circuit and a function of detecting the corresponding It can have a function of performing a process of converting a signal, for example, the circuit shown in FIG. The transistor 610 ( The gates of transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. In addition, either the source or drain of one transistor is connected to the source of the other transistor. The source or drain of both transistors is electrically connected to the The other of the drains is electrically connected to a different wiring.

[0172] The circuit formed on the silicon substrate 600 is, for example, the analog processing circuit 2 shown in FIG. 4, row decoder 25, A / D converter 26, memory element array 31, analog processing circuit 3 4, row decoder 35 and column decoder 36, etc.

[0173] In addition, the silicon substrate 600 is not limited to a bulk silicon substrate, but may be a germanium or silicon germanium substrate. Rumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide Substrates made of gallium nitride or organic semiconductors may also be used.

[0174] Here, as shown in FIG. 17 and FIG. 18A, a transistor including an oxide semiconductor The area where a Si device (Si transistor or Si photodiode) is formed. An insulating layer 80 is provided between the regions where the electrodes are to be formed.

[0175] Water in the insulating layer provided near the active regions of transistor 610 and transistor 620 The hydrogen terminates the dangling bonds of silicon. Therefore, the hydrogen This has the effect of improving the reliability of transistor 10 and transistor 620. Hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, such as the oxide semiconductor This hydrogen is one of the factors that generate carriers in the layer. Therefore, it is recommended to use silicon-based semiconductor materials. One layer has a transistor using an oxide semiconductor, and the other layer has a transistor using an oxide semiconductor. When layers are stacked, an insulating layer 80 having a function of preventing hydrogen diffusion is provided between the layers. It is preferable that the insulating layer 80 confines hydrogen to one layer, thereby preventing the transistor 6 from being damaged. The reliability of the transistor 620 and the semiconductor device 10 can be improved. The diffusion of hydrogen into the other layer is suppressed, thereby improving the reliability of the transistor 41, etc. can be done.

[0176] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0177] In the configuration shown in FIG. 11(A), a circuit (for example, For example, a driving circuit, a transistor 41, etc., and a photoelectric conversion element PD are formed so as to overlap each other. This allows for a higher pixel density. For example, the number of pixels can be increased to 4k2k, 8k4k, or 16k8k. The transistor 43 of the pixel 20 is preferably a Si transistor. The transistor 41, the transistor 42, the photoelectric conversion element PD, etc. are overlapped with each other. It is also possible to have a configuration having a region.

[0178] An imaging device according to one embodiment of the present invention can have a structure shown in FIG.

[0179] The imaging device shown in FIG. 20 is a modified example of the imaging device shown in FIG. 18(A), and includes an OS transistor. The figure shows an example of constructing a CMOS inverter using a silicon transistor and a silicon transistor.

[0180] Here, the transistor 620, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 610 provided in the layer 1100 is an n-channel transistor. By providing only p-ch type transistors on the silicon substrate 600, well formation and n-type Steps such as forming an impurity layer can be omitted.

[0181] In the imaging device shown in FIG. 20, an example is shown in which selenium or the like is used for the photoelectric conversion element PD. Similar to 15, a pin type thin film photodiode may be used.

[0182] In the imaging device shown in FIG. 20, the transistor 610 is a transistor formed in the layer 1100. The transistor 41 and the transistor 42 can be fabricated in the same process. The manufacturing process of the imaging device can be simplified.

[0183] As shown in FIG. 21, the imaging device according to one embodiment of the present invention is formed on a silicon substrate 660. The device has a pixel that is made up of a photodiode and an OS transistor formed on top of it. Alternatively, the semiconductor device may have a structure in which the semiconductor device is laminated to a silicon substrate 600 on which a circuit is formed. With this configuration, the effective photodiode formed on the silicon substrate 660 In addition, it is easy to miniaturize the circuits formed on the silicon substrate 600. By increasing the integration density of these Si transistors, it is possible to provide high-performance semiconductor devices. .

[0184] As a modification of FIG. 21, as shown in FIGS. 22 and 23, an OS transistor and The circuit may be configured with a silicon transistor and a silicon transistor. Therefore, it is easy to increase the effective area of ​​the photodiode formed on the silicon substrate 660. In addition, the circuits formed on the silicon substrate 600 are highly integrated using miniaturized Si transistors. By integrating the semiconductor device, a high performance semiconductor device can be provided.

[0185] The configuration of FIG. 22 is an OS transistor and a Si transistor on a silicon substrate 600. This allows the formation of a non-volatile memory that is effective in forming image processing circuits, etc. In the case of the configuration of FIG. 22, the OS transistor and CMOS circuits can be constructed using Si transistors. Since the leakage current is low, it is possible to construct a CMOS circuit with extremely low static leakage current. do.

[0186] The structure of FIG. 23 includes an OS transistor on a silicon substrate 660 and a silicon substrate 600. It is possible to form a non-volatile memory composed of Si transistors on the image processing circuit. In the case of the configuration of FIG. 23, the upper surface of the silicon substrate 660 is CMOS circuits are implemented using OS transistors and Si transistors on a silicon substrate 600. It can be configured.

[0187] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. For example, any one of the transistors 41 to 43 Alternatively, one or more of the transistors may be configured with silicon or the like in the active region or active layer. Alternatively, both or either of the transistors 610 and 620 may be activated. The transistor may also have an oxide semiconductor layer.

[0188] FIG. 24(A) is a cross-sectional view of an example of an imaging device to which a color filter or the like is added. The cross-sectional view shows a part of an area having pixel circuits for three pixels. On the layer 1200 to be formed, an insulating layer 2500 is formed. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A configuration in which a dielectric film such as fluorine is laminated may also be used.

[0189] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may include an upper The light shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. A metal layer such as tungsten or aluminum, or a dielectric layer that functions as an anti-reflective coating The film may be laminated.

[0190] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. In addition, a color filter 2530 (color filter 25 30a, color filter 2530b, and color filter 2530c) are formed. For example, , color filter 2530a, color filter 2530b, and color filter 2530 c: R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0191] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0192] Also, as shown in FIG. 24B, an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. With this configuration, images in various wavelength regions can be obtained. The imaging device can be configured as follows.

[0193] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0194] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then converted into Image data is obtained by detecting the radiation. A position may also be used.

[0195] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and It is made of a substance that emits visible or ultraviolet light or a material that contains such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and their The material may be dispersed in a resin or ceramic.

[0196] In addition, in photoelectric conversion elements PD that use selenium-based materials, radiation such as X-rays is directly converted into electric charges. Since the light can be converted, a configuration can be made in which a scintillator is not required.

[0197] As shown in FIG. 24C, the color filter 2530a and the color filter 2530 A microlens array 2540 may be provided on color filter 2530b and color filter 2530c. The light passing through each lens of the microlens array 2540 hits the color filter directly below. As shown in Figs. 24(A), (B), and (C), The area other than the layer 1200 shown in FIG.

[0198] In FIG. 1, the reference pixel 22 is shielded from light by the light shielding layer 15. As shown in FIG. 5, there are reference pixels 22, an analog processing circuit 24, a row decoder 25 and an A / D converter. The inverter 26 may be covered with a light-shielding layer 15. It is possible to suppress the deterioration of the electrical characteristics of the transistor due to the above. 1 is a cross-sectional view showing the positional relationship between a pixel 20, a reference pixel 22, and a light-shielding layer 15. For example, it may be provided above the microlens array 2540, but as shown in the figure, It may be provided by expanding the light blocking layer 2510 of the pixel 22 .

[0199] The circuits of the memory element 30 and the reference memory element 32 of the calculation unit 11 are configured as shown in FIG. As shown in FIGS. 27(A) and 27(B), FIG. 27A shows a front end of the transistor 56. The gate and back gate are at the same potential, and a constant voltage is applied to the back gate of transistor 57. FIG. 27B shows a configuration in which transistors 56 and 5 Both of these devices have a structure in which a constant potential is supplied to the back gate. In the case where the voltage is applied to the back gate, the on-current can be increased. In the case of applying a constant potential to the gate, the threshold voltage can be controlled. For transistors included in memory elements, the same potential as the front gate is applied to the back gate. a constant potential is applied to the back gate, or a back gate is not provided. The above may be arbitrarily combined as required to form a circuit configuration.

[0200] As shown in FIG. 27C, a switching element is formed between the transistor 57 and the wiring 275. A transistor 403 having the function may be provided. In this way, a transistor having a switching function is provided between the transistor 57 and the wiring 272. 404 may be provided.

[0201] FIG. 28A shows an example of a cross section of a region in which a memory element 30 is formed. The memory element 32 may have a similar configuration.

[0202] The memory element 30 includes a transistor 56 including an oxide semiconductor and a capacitor C3. A layer 2200 and a layer 2300 having a transistor 57 provided on a silicon substrate 670 are The configuration may include:

[0203] Note that in FIG. 28A, the transistor 56 has a back gate. However, as shown in FIG. 28(B), a configuration without a back gate is also possible. The back gate is electrically connected to the front gate of the transistor provided opposite to it. Or, the back gate may be supplied with a fixed potential different from that of the front gate. The presence or absence of the back gate may be the same as that described in this embodiment. The present invention can also be applied to the circuit configuration.

[0204] As the silicon substrate 670, a single crystal silicon substrate can be typically used. However, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum The substrates are made of gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors. It is also possible.

[0205] As shown in FIG. 28C, the transistor 57 has an active layer 678 made of a silicon thin film. The active layer 678 may be a transistor having a polysilicon or SOI ( The silicon on insulator (Silicon on Insulator) single crystal silicon can be used. In this configuration, the substrate 671 may be a substrate having an insulating surface such as a glass substrate. In addition, in FIG. 28(A), the Si transistor has a fin-type structure. However, it may be of a planar type similar to the imaging section (see FIG. 19(A)).

[0206] Since the OS transistor has an extremely low off-state current characteristic, for example, When an OS transistor is used for the transistor 56, the charge storage section (FD) can hold the charge. This allows the period during which the information can be written to be extremely long. The degree of the noise can be reduced, and the power consumption of the semiconductor device can be reduced. The semiconductor device can also be used as a substantially non-volatile memory device.

[0207] In addition, OS transistors have a higher drain withstand voltage than Si transistors. Therefore, a highly reliable semiconductor device can be obtained.

[0208] FIG. 29 shows a configuration in which, in addition to the configuration shown in FIG. 28(A), an analog processing circuit is provided on a silicon substrate 670. The current mirror circuit of the logic circuit 34 is provided. The current mirror circuit 34 includes a transistor 69 and a transistor 61. However, other transistors and capacitors included in the imaging device of one embodiment of the present invention can be used. The elements and the like may be provided on a silicon substrate 670 .

[0209] The memory element 30 has a configuration in which an OS transistor and a Si transistor overlap each other. This allows the device to be miniaturized.

[0210] The circuitry of the memory element 30 shown in FIG. 4 is capable of retaining memory contents even when power is not supplied. This is an example of a circuit that is possible and has no limit on the number of times it can be written to.

[0211] A transistor using an oxide semiconductor has electrical characteristics such as extremely low off-state current; For example, when the voltage between the source and drain is set to 0.1 V or 5 V, , or about 10 V, the off-state current normalized by the channel width of the transistor is The current density can be reduced from a few yA / μm to a few zA / μm. Transistors made of materials such as crystalline silicon are easy to operate at high speeds. By combining these two, a storage device with high data retention and high speed operation can be created. can be constructed.

[0212] In the circuit of the memory element 30, the potential of the gate electrode of the transistor 57 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0213] The writing and holding of information will be described. First, the potential of the wiring 272 (WW) is The potential is set to a level at which the transistor 56 is turned on, thereby turning the transistor 56 on.

[0214] By the above operation, the potential of the wiring 273 (WD) is That is, a predetermined charge is applied to the charge storage unit (SN). Here, the charges that give two different potential levels (hereafter referred to as low-level charges) are Either a low level charge or a high level charge shall be applied.

[0215] After that, the potential of the wiring 272 (WW) is set to a potential at which the transistor 56 is turned off. By turning off the transistor 56, the charge given to the charge storage section (SN) is stored. Since the off-state current of the transistor 56 is extremely small, the charge storage portion (SN ) charge is retained for a long time.

[0216] Next, the reading of information will be described. A predetermined potential (constant potential) is applied to the wiring 274 (VR). When an appropriate potential (read potential) is applied to the wiring 271 (RW) in this state, Depending on the amount of charge held in (SN), the wiring 275 (BM) takes on different potentials.

[0217] In general, if the transistor 57 is an n-channel type, the gate electrode ( The apparent threshold voltage when a high-level charge is applied to the charge storage section (SN) V th_H A low-level voltage is applied to the gate electrode (charge storage section (SN)) of the transistor 57. Apparent threshold voltage V under load th_L Lower.

[0218] Here, the apparent threshold voltage is the voltage required to turn on transistor 57. Therefore, the potential of the wiring 271(RW) V th_H and V th_L By setting the potential V0 between It is possible to distinguish the charge applied to the electrode (charge storage unit (SN)).

[0219] For example, in the case where a high level charge is applied in a write operation, the wiring 271 (RW) potential is V0 (> V th_H ), transistor 57 is in the "on state." When a low-level charge is applied, the potential of the wiring 271 (RW) becomes V0 (< V th_L ), transistor 57 remains in the "off state." By determining the potential of the line 275 (BM), the stored information can be read out. .

[0220] In the memory element 30 shown in FIG. 4, an oxide semiconductor is used in the channel formation region, and the off-state current is extremely small. By using extremely small transistors, memory contents can be retained for an extremely long period of time. That is, refresh operations are not necessary or the frequency of refresh operations is reduced. Since it is possible to reduce the power consumption to an extremely low level, the power consumption can be reduced sufficiently. In addition, even if there is no power supply (however, it is preferable that the potential is fixed), It is possible to retain the stored contents for a long period of time. An operation of supplying power may be performed.

[0221] In addition, in the above-mentioned driving method, a high voltage is applied to write information to the charge storage section (SN). There is no need for a transistor 57, and there is no problem of deterioration of the transistor 57. The injection of electrons into the floating gate by applying such a high voltage, and the floating gate Since there is no operation of drawing out electrons from the gate insulating film of the transistor 57, deterioration of the gate insulating film That is, the semiconductor device according to the present invention does not have the problems described above. There is no limit to the number of times it can be rewritten, which is an issue with memory, and reliability is improved dramatically. Furthermore, since information is written depending on the on / off state of the transistor, Fast operation can also be easily achieved.

[0222] FIG. 30 illustrates a pixel 20, a memory element 30, and the microcomputer shown in FIG. 24(C) according to one embodiment of the present invention. FIG. 30 is a diagram illustrating a specific laminated structure of the lens array 2540 and the like. 1(A) and the memory element 30 shown in FIG. 28(A). When the pixel 20 shown in FIG. 7 is used, the configuration is as shown in FIG.

[0223] In this manner, the photoelectric conversion element PD, the transistor or the capacitor constituting the circuit of the pixel 20 Each of the transistors or capacitance elements constituting the circuit of the memory element 30 is Since the imaging device can be configured to have overlapping regions, the imaging device can be made smaller. can be done.

[0224] As shown in FIG. 30 and FIG. 31, a diffraction grating is provided above the microlens array 2540. The image of the subject through the diffraction grating 1500 (diffraction image) may be The input image (image of the subject) is calculated from the captured image at the pixel. In addition, by using a diffraction grating 1500 instead of a lens, the imaging device can be This can reduce the cost of installation.

[0225] The diffraction grating 1500 can be made of a material having optical transparency. For example, silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. It may be laminated with an organic insulating film.

[0226] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0227] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be set to 1 mm or less, preferably 100 μm or less. The partition may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a rare gas can be sealed in the gap. Alternatively, a resin such as acrylic resin, epoxy resin, or polyimide resin may be provided in the space. A liquid such as silicone oil may be used. Even when the color filter 2530 and the diffraction grating 1500 are not arranged in the same manner, the distance X is set between the color filter 2530 and the diffraction grating 1500. It is okay.

[0228] The imaging device may also be curved as shown in FIG. 32(A1) and FIG. 32(B1). FIG. 32(A1) shows the imaging device bent in the direction of the two-dot chain line X1-X2 in the figure. FIG. 32(A2) shows the area indicated by the two-dot chain line X1-X2 in FIG. 32(A1). FIG. 32(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0229] FIG. 32(B1) shows a case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 32(B2) shows a state where the lens is bent in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 32(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 32(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG.

[0230] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, enabling miniaturization of semiconductor devices using imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0231] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The semiconductor may have at least one of gallium nitride and organic semiconductors. For example, in some cases or circumstances, various transistors in one aspect of the present invention may be A transistor channel forming region, a transistor source drain region, etc. The layer 100 may not include an oxide semiconductor.

[0232] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0233] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0234] 33A and 33B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 33(A) is a top view, and FIG. 33(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 33(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 35(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0235] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0236] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0237] In addition, a region 231 shown in FIG. 33(B) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0238] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0239] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0240] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0241] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0242] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 33C is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 33(D). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 35(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0243] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0244] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0245] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 33E is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 33(F). Also, the dashed line D3 shown in FIG. The cross section in the -D4 direction corresponds to FIG. 35(A). The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0246] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0247] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0248] In addition, a region 231 shown in FIG. 33(F) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0249] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0250] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 34A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 34(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 35(A). The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0251] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0252] In addition, the regions 331 and 334 shown in FIG. 34(B) are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0253] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0254] Regions 334 and 335 correspond to regions 231 and 232 in the transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. and if the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. In some cases, the resistance reduction step 5 is not performed.

[0255] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0256] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 34C is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 34(D). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 35(A). The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0257] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0258] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0259] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0260] The transistor of one embodiment of the present invention may have a structure shown in FIGS. FIG. 34E is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 34(F). Also, the dashed line G3 shown in FIG. 34(E) The cross section in the -G4 direction corresponds to FIG. 35(A). The direction of the dashed dotted line G3-G4 is called the channel width direction.

[0261] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0262] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0263] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0264] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0265] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0266] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0267] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0268] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0269] In addition, the transistor of one embodiment of the present invention is shown in FIG. 35(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0270] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0271] In addition, in the transistors 101 to 106 in FIG. Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 may be formed as shown in FIG. 37(B), (C), or 37(D), (E) may be replaced with the oxide semiconductor layer 130 shown in FIG. This can be done.

[0272] FIG. 37A is a top view of the oxide semiconductor layer 130, and FIGS. 37B and 37C are top views of the oxide semiconductor layer 130 having a two-layer structure. 37(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0273] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0274] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 38A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 38(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 40(A). The direction of the dashed line H1-H2 is the channel The longitudinal direction, the direction of the dashed dotted line H3-H4, is referred to as the channel width direction.

[0275] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0276] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0277] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 38C is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 38(D). Also, the dashed line I3 shown in FIG. The cross section in the -I4 direction corresponds to FIG. 40(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, is referred to as the channel width direction.

[0278] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0279] Further, the transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 38E is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 38(F). Also, the dashed line J3 shown in FIG. 38(E) The cross section in the -J4 direction corresponds to FIG. 40(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, is referred to as the channel width direction.

[0280] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0281] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0282] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 39A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 39(B). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 40(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, is referred to as the channel width direction.

[0283] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0284] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 39C is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 39(D). Also, the dashed line L3 shown in FIG. The cross section in the -L4 direction corresponds to FIG. 40(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, is referred to as the channel width direction.

[0285] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0286] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0287] Further, the transistor of one embodiment of the present invention may have the structure illustrated in FIGS. FIG. 39E is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 39(F). Also, the dashed line M3 shown in FIG. The cross section in the -M4 direction corresponds to FIG. 40(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, is referred to as the channel width direction.

[0288] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0289] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 40(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0290] Further, the transistor of one embodiment of the present invention has the structure shown in FIG. FIG. 42(A) is a top view, and FIG. 42(B) is a top view of the 42 is a cross-sectional view corresponding to the dashed line N1-N2 and the dashed line N3-N4. In the top view of (A), some elements are omitted for clarity of the drawing.

[0291] The transistor 113 shown in FIG. 42(A) and FIG. 42(B) is a transistor including a substrate 115 and a substrate 11 5, and the oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130 a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) and a The conductive layer 140 and the conductive layer 150 are spaced apart from each other, and the oxide semiconductor layer 130 is c, and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 form an insulating layer on the transistor 113. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b and the insulating layer 12 provided in the It is provided at an opening that reaches 0.

[0292] The configuration of the transistor 113 is different from the configurations of the other transistors described above in that the source Since the overlapping area between the conductor that will become the electrode or drain electrode and the conductor that will become the gate electrode is small, Therefore, the parasitic capacitance can be reduced. The upper surface of the transistor 113 is shown in FIG. As shown in (B), CMP (Chemical Mechanical Polishing) It is preferable to flatten the surface by using a method such as ng), but it is also possible to adopt a structure in which flattening is not performed. .

[0293] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. As shown in FIG. 30, only the conductive layer 140 and the conductive layer 150 are shown, (W OS ) of the conductive layer 140 and the conductive layer 150. SD) is formed long It may be formed short. OS ≧W SD (W SD W OS (hereinafter) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor In addition, as shown in FIG. 43(C), the conductive layer 140 and The conductive layer 150 may be formed only in a region overlapping with the oxide semiconductor layer 130 .

[0294] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0295] In addition, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. Therefore, the on-current can be improved by making the oxide semiconductor layer 130b thicker. This may be the case.

[0296] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0297] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0298] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0299] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0300] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom equivalent measured by a TDS method. The calculated amount of oxygen released is 1.0 x 10 19 atoms / cm 3 More preferably, it is equal to or greater than this. The surface temperature of the film during the TDS analysis was 100°C to 700°C or 10 The temperature range is from 0° C. to 500° C. In addition, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform planarization treatment by CMP or the like so that the surface becomes flat.

[0301] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0302] In this embodiment, the oxide semiconductor layer 130 of the transistor is a) The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The details will be mainly explained for the three-layer structure.

[0303] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0304] In addition, when the oxide semiconductor layer 130 has two layers, the oxide semiconductor layer 13 shown in this embodiment is A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be interchanged with 130b.

[0305] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0306] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0307] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0308] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0309] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0310] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0311] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0312] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0313] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0314] Here, for example, In-Ga-Zn oxide is a material having In, Ga, and Zn as main components. It means oxide. Metal elements other than In, Ga, and Zn may also be included. In this specification, a film made of In-Ga-Zn oxide is also called an IGZO film. .

[0315] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0316] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the mobility of the oxide semiconductor layer 130b is higher than that of the oxide semiconductor layer 130b. By using oxides with a high content of sodium, a transistor with high field effect mobility can be realized. It is possible.

[0317] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, more preferably More preferably, the thickness of the oxide semiconductor layer 130c is 10 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. Thicker than 0c is preferred.

[0318] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or substantially Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is Degree is 1 x 10 19 / cm 3 Less than 1 × 10 15 / cm 3 Less than 1 ×10 13 / cm 3 Less than or equal to 1 × 10 8 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than this.

[0319] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0320] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) The hydrogen concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 2 ×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 below, More preferably, 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 a toms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 It has an area where The nitrogen concentration is controlled to be 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 Less than or equal to 5×10 16 atoms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0321] In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer is decreased. In order not to deteriorate the crystallinity of the oxide semiconductor layer, the silicon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1× 10 18 atoms / cm 3 The carbon concentration is controlled to have a region where the carbon concentration is equal to or higher than the range. 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Less than 6 × 10 17 ato ms / cm 3 The control is performed so as to have a region where the above is satisfied.

[0322] In addition, a transistor using the purified oxide semiconductor layer as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0323] Since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is In this way, it is preferable that the gate insulating film does not contact the semiconductor layer. When a channel is formed at the interface between the oxide semiconductor layer and the silicon oxide semiconductor layer, carrier scattering occurs at the interface. From this viewpoint, the field effect mobility of the transistor may be reduced. It is preferable to separate the region of the semiconductor layer that becomes the channel from the gate insulating film.

[0324] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0325] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0326] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0327] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The atomic ratios of c each include a variation of ±40% of the above atomic ratios as an error. nothing.

[0328] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130 has an energy level at the bottom of the conduction band. Since the temperature changes continuously, it can also be called a U-shaped well. The channel formed in this configuration may also be referred to as a buried channel.

[0329] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0330] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0331] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0332] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A stack of an alloy such as n and the above material may be used. 06, transistor 111, and transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. There can be.

[0333] The above material has a property of extracting oxygen from the oxide semiconductor layer. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0334] In addition, when W is used for the conductive layer 140 and the conductive layer 150, it is possible to dope the W with nitrogen. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding to the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0335] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0336] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0337] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0338] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0339] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less. The amount of release is considered to be the amount of release by

[0340] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0341] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0342] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0343] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0344] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0345] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0346] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. When the gate electrode shrinks, the on-current decreases.

[0347] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0348] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from a direction perpendicular to the channel formation layer. Since the gate electric field is applied to the MOSFET, the effective channel width is enlarged, and the on-current is further increased. Can be enhanced.

[0349] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. This allows the gate to be more stable and the S value (subthreshold value) to be reduced. The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. In addition, the electrical characteristics of the transistor according to one embodiment of the present invention can be improved with miniaturization. Since deterioration of the semiconductor device can be suppressed, the present invention is suitable for forming a highly integrated semiconductor device.

[0350] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0351] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0352] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time. By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0353] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0354] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0355] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0356] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0357] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0358] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0359] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0360] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition). It can also be called deposition SP).

[0361] An oxide semiconductor layer is formed using a facing target sputtering apparatus, It is possible to reduce plasma damage during the formation of the oxide semiconductor layer. In addition, the oxygen deficiency in the film can be reduced by using a facing target sputtering device. Since this enables deposition at low pressure, the impurity concentration (e.g. For example, hydrogen, rare gases (such as argon), water, etc.) can be reduced.

[0362] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0363] (Embodiment 4) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0364] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0365] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0366] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0367] First, we will explain the CAAC-OS film.

[0368] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0369] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0370] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0371] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0372] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0373] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0374] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0375] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0376] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0377] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0378] Next, a microcrystalline oxide semiconductor film will be described.

[0379] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0380] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. If you do this, you may see a circular (ring-shaped) area of ​​high brightness. When nanobeam electron diffraction was performed on the nc-OS film, multiple spots were observed within the ring-shaped region. It may be observed.

[0381] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0382] Next, the amorphous oxide semiconductor film will be described.

[0383] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0384] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0385] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0386] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0387] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0388] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. Unit cell of the InGaZnO4 crystal The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0389] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0390] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0391] (Embodiment 5) In this embodiment, an example of a package that houses an imaging device according to one embodiment of the present invention will be described. do.

[0392] FIG. 44A is an external perspective view of a package that houses an imaging device of one embodiment of the present invention. The package includes an interposer 810 for fixing the imaging device, a cover glass 820, and and an adhesive 830 that bonds the two together.

[0393] FIG. 44(B) is a perspective view of the package from the rear side. The structure is called BGA (Ball grid array), with solder balls as bumps 840. This is not limited to BGA, but also applies to LGA (Land grid array) and PG A (Pin Grid Array), etc.

[0394] FIG. 44(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 44(D) is a cross-sectional view of the package taken at an arbitrary position parallel to the side of the package. An electrode pad 860 is formed on the interposer 810. 0 and bump 840 are connected to each other via through holes 880 formed in the interposer 810. The electrode pad 860 is electrically connected to the electrode of the imaging device 850 and the wire 87. Electrically connected by 0.

[0395] By forming the imaging device of the present invention into a package of the above-mentioned type, mounting becomes easy, and various It can be incorporated into various electronic devices.

[0396] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0397] (Embodiment 6) The imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are and image reproducing devices equipped with recording media (typically DVD: Digital A disc that can play recording media such as Versatile Discs and display the images. In addition, the imaging device according to one embodiment of the present invention can be used in a display device. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) , vending machines, etc. Specific examples of these electronic devices are shown in Figure 45.

[0398] FIG. 45A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0399] FIG. 45B shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display portion 912 has a touch panel function through which data can be input and output. The imaging device of one embodiment of the present invention can be used as the camera 919 .

[0400] FIG. 45C shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 33, operation buttons 935, a crown 936, a camera 939, etc. The camera 939 may be a touch panel. It is possible.

[0401] FIG. 45D shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. An imaging device according to one embodiment of the present invention can be provided at the focal position of the lens 952.

[0402] FIG. 45(E) shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 The lens 965 has a focal point of the present invention. The imaging device according to the present invention may include an imaging device according to the present invention.

[0403] FIG. 45(F) shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. The first housing 971 and the second housing 972 are connected by a connection portion 976. The angle between the first housing 971 and the second housing 972 can be changed by the connection part 976. The image on the display unit 973 is transmitted between the first housing 971 and the second housing 97 at the connection unit 976. 2. The focal point of the lens 975 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0404] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0405] 10. Imaging unit 11 Arithmetic section 12 Imaging operation 13 Data retention operation 14 Operation 15 Light blocking layer 20 pixels 21 Pixel Array 22 Reference Pixels 24 Analog Processing Circuit 25 Line Decoder 26 A / D Converter 29 Operational Amplifiers 30 Memory element 31 Memory Element Array 32 Reference memory element 34 Analog Processing Circuit 35 Line Decoder 36 Column Decoder 41 Transistor 42 Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 47 Transistor 48 Transistors 49 Transistor 50 Transistors 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Transistor 59 Transistor 60 Transistor 61 Transistor 62 Transistor 63 Transistor 64 Transistor 65 Transistor 66 Transistor 67 Transistor 68 Transistors 69 Transistor 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating Layer 87 Wiring 87a Conductive layer 87b Conductive layer 88 Wiring 91 Wiring 92 Wiring 93 Wiring 94 Wiring 96 Wiring 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 227 column output circuit 229 Operational Amplifiers 231 areas 232 areas 233 areas 271 Wiring 272 Wiring 273 Wiring 274 Wiring 275 Wiring 276 Wiring 277 Wiring 278 Wiring 293 Wiring 294 Wiring 295 Wiring 296 Wiring 331 areas 332 areas 333 areas 334 areas 335 areas 401 Transistor 402 Transistor 403 Transistor 404 Transistor 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor Layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 600 Silicon substrate 610 Transistor 620 Transistor 650 active layer 660 Silicon Substrate 670 Silicon Substrate 671 Substrate 678 Active layer 701 Wiring 702 Wiring 810 Interposer 820 Cover Glass 830 Adhesive 840 Bump 850 Imaging Device 860 Electrode Pads 870 Wire 880 through hole 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1400 layers 1500 Diffraction Grating 1600 layers 2200 layers 2300 layers 2500 Insulation Layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation layer

Claims

1. A semiconductor device having a pixel array, the pixel array having a first layer and a second layer overlying the first layer; the first layer has a photoelectric conversion element, A first conductive layer and a second conductive layer, the second layer includes a first transistor, a second transistor, a third transistor, and a capacitance element; the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor; the other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the third transistor; the other of the source electrode and the drain electrode of the first transistor is electrically connected to one electrode of the capacitance element; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a first wiring; one of a source electrode and a drain electrode of the third transistor is electrically connected to a second wiring; The other electrode of the capacitance element is electrically connected to a third wiring, one of a source electrode and a drain electrode of the third transistor is electrically connected to a fourth wiring; the first to third transistors each include a semiconductor film containing an oxide semiconductor, the photoelectric conversion element includes a first conductive layer, a photoelectric conversion layer in contact with an upper surface of the first conductive layer, and a second conductive layer in contact with an upper surface of the photoelectric conversion layer; the second conductive layer has a light-transmitting property, the first conductive layer is electrically connected to one of a source electrode or a drain electrode of the first transistor through a first contact hole; the second conductive layer is electrically connected to a third conductive layer provided in the same layer as the first conductive layer through a second contact hole; The first conductive layer and the third conductive layer comprise molybdenum.

2. In claim 1, The oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Images