Logical circuit

Abstract

To prevent an error from occurring in a logical circuit, and prevent resources for logical operations from being compressed.SOLUTION: A logical circuit (100, 100A) comprises: a plurality of logical elements 30; storages 10, 11, 12, 13 storing a plurality of pieces of configuration data CF0, CF1, CF2, CF3; a circuit reconfiguration unit 23; and a comparison circuit 32. A plurality of first logical elements and a plurality of second logical elements forming a first arithmetic circuit and a second arithmetic circuit on the basis of the pieces of configuration data, and a plurality of first logical elements and a plurality of second logical elements forming a first arithmetic circuit and a second arithmetic circuit on the basis of the other configuration data, are partially different from each other and partially common to each other. When notified that an error occurs, the circuit reconfiguration unit selects another configuration data different from selected configuration data, and executes reconfiguration of at least one of the first arithmetic circuit and the second arithmetic circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to logic circuits. [Background technology]

[0002] There is known an FPGA (Field Programmable Gate Array) that can configure various logic circuits by defining the connection relationship of multiple logic elements and execute logic operations. Patent Document 1 discloses a logic circuit that recovers from an error state by switching to a backup circuit prepared in advance and executing logic operations when a hard error occurs in the FPGA. Patent Document 2 discloses a logic circuit that recovers from an error state by executing logic operations using an area in the FPGA where logic operations are not executed when an error occurs in the FPGA. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-119359 A [Patent Document 2] JP 2016-9339 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the logic circuits described in Patent Documents 1 and 2, in order to configure a backup circuit when an error occurs, it is necessary to prepare an area separate from the arithmetic circuits used under normal circumstances, which creates a problem in that it puts strain on resources for logical operations in the FPGA. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one embodiment of the present disclosure, a logic circuit (100) is provided. The logic circuit includes a memory device (10, 11, 12, 13) that stores a plurality of logic elements (30), a plurality of configuration data (CF0, CF1, CF2, CF3) that defines a connection relationship of at least a portion of the plurality of logic elements so as to realize a predetermined function, a circuit reconfiguration unit (23) that selects one of the plurality of configuration data to configure a circuit that realizes the function, a first arithmetic circuit (311) that is configured with a plurality of first logic elements and executes a logical operation that realizes the function based on the configuration data selected by the circuit reconfiguration unit, a second arithmetic circuit (312) that is configured with a plurality of second logic elements different from the plurality of first logic elements and executes the logical operation based on the configuration data selected by the circuit reconfiguration unit, a first arithmetic result that is a result of the logical operation in the first arithmetic circuit, and a second arithmetic circuit (313) that is configured with a plurality of second logic elements different from the plurality of first logic elements and executes the logical operation in the second arithmetic circuit. and a comparison circuit (32) which compares the first and second operation results, which are the results of the first and second operation results, with each other and notifies that an error has occurred in at least one of the first operation circuit and the second operation circuit when the first operation result and the second operation result do not match each other, wherein the plurality of first logic elements and the plurality of second logic elements which constitute the first operation circuit and the second operation circuit based on each of the configuration data are compared with the plurality of first logic elements and the plurality of second logic elements which constitute the first operation circuit and the second operation circuit based on other configuration data to have some differences and some commonalities, and when notified by the comparison circuit that the error has occurred, the circuit reconfiguration unit selects the other configuration data which is different from the selected configuration data and executes reconfiguration of at least one of the first operation circuit and the second operation circuit.

[0007] According to this logic circuit, a storage device is provided that stores a plurality of configuration data that defines at least some of the connection relationships of the plurality of logic elements so as to realize a predetermined function, and the plurality of first logic elements and the plurality of second logic elements that configure the first arithmetic circuit and the second arithmetic circuit based on each configuration data are partially different from each other compared to the plurality of first logic elements and the plurality of second logic elements that configure the first arithmetic circuit and the second arithmetic circuit based on other configuration data. Therefore, when the comparison circuit notifies that an error has occurred, the same function can be realized using the plurality of logic elements that are partially different, and the occurrence of an error after the reconfiguration can be suppressed by selecting the other configuration data and executing reconfiguration of at least one of the first arithmetic circuit and the second arithmetic circuit. Also, the plurality of first logic elements and the plurality of second logic elements that configure the first arithmetic circuit and the second arithmetic circuit based on each configuration data are partially common to each other compared to the plurality of first logic elements and the plurality of second logic elements that configure the first arithmetic circuit and the second arithmetic circuit based on other configuration data. Therefore, compared to a configuration in which an area separate from the arithmetic circuits used under normal circumstances is prepared to configure a backup circuit in the event of an error, it is possible to reduce the strain on resources for logical operations that realize predetermined functions. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a logic circuit according to a first embodiment; [Diagram 2] 4 is a flowchart showing a procedure of a process executed in the logic circuit of the first embodiment. [Diagram 3] 5 is a flowchart showing the procedure of an error location detection process according to the first embodiment. [Figure 4] FIG. 11 is a block diagram showing a schematic configuration of a logic circuit according to a second embodiment. [Diagram 5] 10 is a flowchart showing the procedure of an error location detection process according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A. First embodiment: A-1.Circuit configuration: As shown in FIG. 1, a logic circuit 100 of this embodiment includes a ROM 10, a ROM 11, a ROM 12, a ROM 13, a control circuit 20, and an FPGA (Field Programmable Gate Array) 30.

[0010] ROM10 to ROM13 store configuration data, respectively. "Configuration data" refers to information that specifies the connection relationship of logic elements that configure FPGA 30 so as to realize a predetermined function in FPGA 30. In this embodiment, ROM10 stores configuration data CF0, ROM11 stores configuration data CF1, ROM12 stores configuration data CF2, and ROM13 stores configuration data CF3. In FIG. 1, hatching on configuration data CF0 to CF3 typically indicates the usage area of ​​a calculation circuit, which will be described later. Configuration data CF0 to CF3 may be stored in different storage areas of the same storage device. ROM10 to ROM13 correspond to the "storage device" in this disclosure.

[0011] The FPGA 30 is configured with a plurality of logic elements such as AND elements, OR elements, NAND elements, NOR elements, and look-up tables, a plurality of wiring elements, a plurality of switch elements, and the like, similar to the configuration of a known FPGA. The FPGA 30 receives any one of configuration data CF0 to CF3 written by the control circuit 20 as described below, and configures a circuit according to the connection relationship defined by the written configuration data. In this embodiment, the FPGA 30 configures a first arithmetic circuit 311, a second arithmetic circuit 312, a comparison circuit 32, and a test circuit 33.

[0012] The first arithmetic circuit 311 and the second arithmetic circuit 312 are configured by logic elements located in different regions of the FPGA 30. The first arithmetic circuit 311 and the second arithmetic circuit 312 receive the same data and execute the same logical operation. That is, when no error occurs in either the first arithmetic circuit 311 or the second arithmetic circuit 312, they output the same operation result. In the following description, the first arithmetic circuit 311 and the second arithmetic circuit 312 are also referred to as "arithmetic circuits" without distinction. The first arithmetic circuit 311 and the second arithmetic circuit 312 are configured such that some of the logic elements used for logical operations are different from each other and some are common to each other, depending on the written configuration data, compared to when the first arithmetic circuit 311 and the second arithmetic circuit 312 are configured according to the written configuration data.

[0013] In FPGA30, areas that can be used when configuring the first arithmetic circuit 311 are referred to as usage areas AR11, AR12, AR13, and AR14, and areas that can be used when configuring the second arithmetic circuit 312 are referred to as usage areas AR21, AR22, AR23, and AR24, and the differences in the usage areas for each configuration data will be described in more detail. In the following description, the logic elements that configure the first arithmetic circuit 311 based on each configuration data will also be referred to as the "first logic elements," and the logic elements that configure the second arithmetic circuit 312 based on each configuration data will also be referred to as the "second logic elements."

[0014] When configuration data CF0 is written, first arithmetic circuit 311 is configured with a plurality of logic elements located in use areas AR12, AR13, and AR14 as a plurality of first logic elements, and second arithmetic circuit 312 is configured with a plurality of logic elements located in use areas AR22, AR23, and AR24 as a plurality of second logic elements. Also, when configuration data CF1 is written, first arithmetic circuit 311 is configured with a plurality of logic elements located in use areas AR11, AR13, and AR14 as a plurality of first logic elements, and second arithmetic circuit 312 is configured with a plurality of logic elements located in use areas AR21, AR23, and AR24 as a plurality of second logic elements. Moreover, when configuration data CF2 is written, first arithmetic circuit 311 is configured with a plurality of logic elements located in use areas AR11, AR12, and AR14 as a plurality of first logic elements, and second arithmetic circuit 312 is configured with a plurality of logic elements located in use areas AR21, AR22, and AR24 as a plurality of second logic elements. Moreover, when configuration data CF3 is written, first arithmetic circuit 311 is configured with a plurality of logic elements located in use areas AR11, AR12, and AR13 as a plurality of first logic elements, and second arithmetic circuit 312 is configured with a plurality of logic elements located in use areas AR21, AR22, and AR23 as a plurality of second logic elements. Note that first arithmetic circuit 311 and second arithmetic circuit 312 may be configured with the same configuration data or different configuration data.

[0015] The comparison circuit 32 compares the result of the logical operation in the first arithmetic circuit 311 (hereinafter also referred to as the “first operation result”) with the result of the logical operation in the second arithmetic circuit 312 (hereinafter also referred to as the “second operation result”), and outputs an error signal to the control circuit 20 if the first operation result and the second operation result do not match each other.

[0016] When it is considered that a hard error occurs in the first arithmetic circuit 311 and the second arithmetic circuit 312, the test circuit 33 executes an error location diagnosis for the first arithmetic circuit 311 and the second arithmetic circuit 312, and outputs the error location to the control circuit 20. For example, as the error location diagnosis, the test circuit 33 transmits a signal to each of the above-mentioned multiple first logic elements when the first arithmetic circuit 311 is the target, and transmits a signal to each of the above-mentioned multiple second logic elements when the second arithmetic circuit 312 is the target. The test circuit 33 judges whether or not a reply from each logic element to the signal matches a predetermined normal value, and if they do not match, detects that an error has occurred in the logic element. The test circuit 33 may execute the error location diagnosis using any method known as a method for detecting an error in a logic element, not limited to the above method. The test circuit 33 notifies the control circuit 20 of information indicating the logic element detected as having an error.

[0017] The control circuit 20 executes the judgment of the error type and the reconfiguration of the arithmetic circuit according to the error signal output from the comparison circuit 32. The control circuit 20 functions as an error judgment unit 21, a flag register 22, and a circuit reconfiguration unit 23. The flag register 22 generates and stores an error flag when an error signal is received, and erases the error flag when the error signal is eliminated. The error judgment unit 21 judges whether the type of the error occurring in at least one of the first arithmetic circuit 311 and the second arithmetic circuit 312 is a soft error or a hard error according to the error signal output from the comparison circuit 32 and the storage state of the error flag. The circuit reconfiguration unit 23 selects configuration data according to the judgment result by the error judgment unit 21, and writes the selected configuration data into the FPGA 30 to configure the circuit. Specific processing in the error judgment unit 21 and the circuit reconfiguration unit 23 will be described later.

[0018] A-2. Processing in logic circuit 100: 2 is repeatedly executed in the operating state of the logic circuit 100. In step S10, the error determination unit 21 determines whether an error signal is received from the comparison circuit 32 or not.

[0019] If it is determined that an error signal has been received (step S10: Yes), in step S20, the error determination unit 21 determines whether an error flag is stored in the flag register 22 or not.

[0020] If it is determined that the error flag is not stored (step S20: No), in step S42, the circuit reconfiguration unit 23 reconfigures the first arithmetic circuit 311 and the second arithmetic circuit 312 using the same configuration data as the previously written configuration data. In step S52, the flag register 22 stores the error flag. After that, the error determination unit 21 executes step S10 again.

[0021] When an error notification is received in a state where an error flag is not stored, the error may be a temporary soft error that occurred at that time. On the other hand, when an error notification is received in a state where an error flag is stored, the error may be a hard error, since it is considered that the error was not resolved by the measures taken after the error occurred, which will be described later. If it is a soft error, the error state can be easily resolved by rewriting the same configuration data and reconfiguring the arithmetic circuit as a post-error measure, so the circuit reconfiguration unit 23 executes step S42.

[0022] On the other hand, if it is determined that an error flag is stored (step S20: Yes), in step S30, the test circuit 33 executes the error location detection process shown in Fig. 3. If an error notification is received while an error flag is stored, as described above, the error is likely to be a hard error that has not been resolved even by reconfiguring the arithmetic circuit, and it is necessary to identify the logic element in which the hard error has occurred in order to resolve the error state. Therefore, the test circuit 33 executes the error location detection process to detect the location in the arithmetic circuit where the hard error has occurred.

[0023] In step S102, the test circuit 33 executes an error location diagnosis on the first arithmetic circuit 311. In step S104, the test circuit 33 determines whether or not an error has been detected in the first arithmetic circuit 311. If it is determined that an error has been detected (step S104: Yes), the test circuit 33 notifies the control circuit 20 of the location of the detected error in the first arithmetic circuit 311. In this embodiment, the "error location" refers to the logic element detected by the test circuit 33.

[0024] On the other hand, if it is determined that no error is detected in the first arithmetic circuit 311 (step S104: No), in step S108, the test circuit 33 executes an error location diagnosis on the second arithmetic circuit 312. In step S106, the test circuit 33 notifies the control circuit 20 of the location of the detected error in the second arithmetic circuit 312.

[0025] 2, the circuit reconfiguration unit 23 reconfigures the arithmetic circuit with configuration data that does not use the error location notified by the test circuit 33. For example, when the test circuit 33 notifies that a logic element located in the use area AR12 of the first arithmetic circuit 311 is an error location, the circuit reconfiguration unit 23 reconfigures the first arithmetic circuit 311 with configuration data CF1 that does not use the use area AR12. This makes it possible to reconfigure the arithmetic circuit while avoiding the area where a hard error is thought to have occurred.

[0026] In step S50, the flag register 22 erases the stored error flag. This is because it is considered that the error state has been resolved by reconfiguring the arithmetic circuit while avoiding the area where the hard error is thought to have occurred. After that, the error determination unit 21 executes step S10 again.

[0027] If it is determined in step S10 that an error signal has not been received (step S10: No), then in step S24, the error determination unit 21 determines whether or not an error flag is stored in the flag register 22. If it is determined that an error flag is stored (step S24: Yes), then in step S54, the flag register 22 erases the stored error flag. This is because it is considered that the error state that has occurred has been resolved. Thereafter, the error determination unit 21 executes step S10 again. On the other hand, if it is determined that an error flag is not stored (step S24: No), the error determination unit 21 executes step S10 again without executing step S54.

[0028] The logic circuit 100 of the first embodiment described above includes ROMs 10-13 for storing configuration data CF0-CF3, and the first logic elements and the second logic elements constituting the first arithmetic circuit 311 and the second arithmetic circuit 312 based on each configuration data are partially different from the first logic elements and the second logic elements constituting the first arithmetic circuit 311 and the second arithmetic circuit 312 based on other configuration data. Therefore, when the comparison circuit 32 notifies the occurrence of an error, the other configuration data is selected to reconfigure at least one of the first arithmetic circuit 311 and the second arithmetic circuit 312, thereby making it possible to realize the same function using some different logic elements among the plurality of logic elements and to suppress the occurrence of an error after the reconfiguration. Furthermore, the multiple first logic elements and multiple second logic elements constituting the first arithmetic circuit 311 and the second arithmetic circuit 312 based on each configuration data have a portion in common with each other, compared to the multiple first logic elements and multiple second logic elements constituting the first arithmetic circuit 311 and the second arithmetic circuit 312 based on other configuration data. Therefore, compared to a configuration in which an area different from the arithmetic circuits used under normal circumstances is prepared to configure a backup circuit when an error occurs, it is possible to suppress pressure on resources for logical operations that realize predetermined functions.

[0029] The circuit reconfiguration unit 23 also includes a test circuit 33 that detects a logic element in which a hard error has occurred, and selects, from the configuration data CF0 to CF3, configuration data that specifies a connection relationship that does not use a logic element in which a hard error has been detected by the test circuit 33, and performs reconfiguration, thereby further suppressing the occurrence of errors after reconfiguration.

[0030] B. Second embodiment: The logic circuit 100A of the second embodiment differs from the logic circuit 100 of the first embodiment in that the control circuit 20A further includes an error location register 24 as shown in Fig. 4, the FPGA 30 does not include a test circuit 33, and the logic circuit 100A executes the process shown in Fig. 5 instead of the process shown in Fig. 3. The other circuit configurations of the logic circuit 100A of the second embodiment and other steps of the process in the logic circuit 100A are the same as those of the logic circuit 100 of the first embodiment, so the same configurations and steps are denoted by the same reference numerals and detailed descriptions thereof will be omitted.

[0031] The error location register 24 shown in FIG. 4 stores error information indicating the location of an error where a hard error has been detected by the comparison circuit 32 as described later.

[0032] Hereinafter, a process will be described taking as an example a case where a hard error occurs in either the first arithmetic circuit 311 or the second arithmetic circuit 312 configured by the configuration data CF0. In step S202 shown in Fig. 5, the circuit reconfiguration unit 23 reconfigures the first arithmetic circuit 311 by the configuration data CF1.

[0033] In step S204, the comparison circuit 32 judges whether the first calculation result and the second calculation result match each other. If it is judged that the first calculation result and the second calculation result match each other (step S204: Yes), in step S206, the comparison circuit 32 notifies the control circuit 20 of the error location, assuming that a hard error has occurred in the use area AR12 that is an area that was used in the first calculation circuit 311 configured by the configuration data CF0 but is not used in the first calculation circuit 311 configured by the configuration data CF1. In this embodiment, the "error location" refers to information indicating the use area that is detected as the location of the logic element in which the error has occurred.

[0034] If it is determined in step S204 that the first and second calculation results do not match each other (step S204: No), in step S208, the circuit reconfiguration unit 23 reconfigures the first calculation circuit 311 using the configuration data CF2.

[0035] In step S210, the comparison circuit 32 judges whether the first calculation result and the second calculation result match each other. If it is judged that the first calculation result and the second calculation result match each other (step S210: Yes), in step S206, the comparison circuit 32 notifies the control circuit 20 of the error location, assuming that a hard error has occurred in the used area AR13, which is an area that was used in the first calculation circuit 311 configured by the configuration data CF0 and CF1 but is not used in the first calculation circuit 311 configured by the configuration data CF2.

[0036] If it is determined in step S210 that the first calculation result and the second calculation result do not match each other (step S210: No), in step S212, the circuit reconfiguration unit 23 reconfigures the first calculation circuit 311 using the configuration data CF3.

[0037] In step S214, the comparison circuit 32 judges whether the first calculation result and the second calculation result match each other. If it is judged that the first calculation result and the second calculation result match each other (step S214: Yes), in step S206, the comparison circuit 32 notifies the control circuit 20 of the error location, assuming that a hard error has occurred in the used area AR14, which is an area that was used in the first calculation circuit 311 configured by the configuration data CF0, the configuration data CF1, and the configuration data CF2, but is not used in the first calculation circuit 311 configured by the configuration data CF3.

[0038] If it is determined in step S214 that the first calculation result and the second calculation result do not match each other (step S214: No), in step S216, the circuit reconfiguration unit 23 reconfigures the first calculation circuit 311 using the configuration data CF0 and reconfigures the second calculation circuit 312 using the configuration data CF1.

[0039] In step S218, the comparison circuit 32 judges whether the first calculation result and the second calculation result match each other. If it is judged that the first calculation result and the second calculation result match each other (step S218: Yes), in step S206, the comparison circuit 32 notifies the control circuit 20 of the error location, assuming that a hard error has occurred in the used area AR22 that is an area that was used in the second calculation circuit 312 configured by the configuration data CF0 but is not used in the second calculation circuit 312 configured by the configuration data CF1.

[0040] If it is determined in step S218 that the first calculation result and the second calculation result do not match each other (step S218: No), in step S220, the circuit reconfiguration unit 23 reconfigures the second calculation circuit 312 using the configuration data CF2.

[0041] In step S222, the comparator circuit 32 compares the first and second calculation results with each other. If it is determined that the first and second calculation results match each other (step S222: Yes), in step S206, the comparator circuit 32 notifies the control circuit 20 of the error location, determining that a hard error has occurred in the used area AR23, which is an area that was used in the second calculation circuit 312 configured by the configuration data CF0 and the configuration data CF1 but is not used in the second calculation circuit 312 configured by the configuration data CF2.

[0042] If it is determined in step S222 that the outputs do not match each other (step S222: No), in step S224, the circuit reconfiguration unit 23 reconfigures the second arithmetic circuit 312 with the configuration data CF3. In step S206, the comparison circuit 32 notifies the control circuit 20 of the error location, determining that a hard error has occurred in the used area AR24 that is an area that was used in the second arithmetic circuit 312 configured with the configuration data CF0, the configuration data CF1, and the configuration data CF2 but is not used in the second arithmetic circuit 312 configured with the configuration data CF3.

[0043] In this manner, in this embodiment, the first arithmetic circuit 311 and the second arithmetic circuit 312 are reconfigured in order using the configuration data CF0 to CF3, and the first arithmetic result and the second arithmetic result are compared to detect the location of an error.

[0044] In step S226, the error location register 24 stores error information indicating the logic element in which a hard error has been detected by the comparison circuit 32. This makes it possible to prioritize the execution of error location detection processing on the logic element indicated by the stored error information when an error occurs again, thereby shortening the time required to detect the error location.

[0045] In this embodiment, since the reconfiguration is performed so that the first calculation result and the second calculation result match in the error location detection process, the circuit reconfiguration unit 23 does not need to execute step S40 shown in FIG.

[0046] The logic circuit 100A of the second embodiment described above provides the same effect as the logic circuit 100 of the first embodiment. In addition, when the first operation result and the second operation result match each other as a result of reconfiguration by the circuit reconfiguration unit 23, the comparison circuit 32 detects that an error has occurred in a logic element that is not used as the first logic elements and the second logic elements that configure the first operation circuit 311 and the second operation circuit 312 based on the configuration data used after the reconfiguration, among the first logic elements and the second logic elements that configure the first operation circuit 311 and the second operation circuit 312 based on the configuration data used before the reconfiguration. Therefore, the error location can be detected using the judgment result by the comparison circuit 32 without using the test circuit 33, and compared to a configuration including the test circuit 33, the pressure on resources for logical operations can be further suppressed.

[0047] The circuit further includes an error location register 24 that stores error information indicating a logic element in which a hard error has been detected by the comparison circuit 32, and the circuit reconfiguration unit 23 selects configuration data that specifies a connection relationship that does not use the logic element indicated by the error information and executes the reconfiguration. Therefore, if an error occurs again, the logic element indicated by the stored error information can be given priority in the execution of error location detection processing, thereby shortening the time required to detect the error location.

[0048] C. Other embodiments: (C1) In the above embodiment, in step S40, the circuit reconfiguration unit 23 reconfigures the arithmetic circuit using configuration data that does not use the error location detected by the error location detection process, but the present disclosure is not limited to this. The circuit reconfiguration unit 23 may not execute the error location detection process and may reconfigure the arithmetic circuit using any configuration data that is different from the configuration data in which it is determined that a hard error has occurred. In this case, the FPGA 30 does not need to include the test circuit 33. According to this embodiment, since it is not necessary to execute the error location detection process, it is possible to prevent the processing in the logic circuit 100 from becoming complicated. In addition, since it is not necessary to include the test circuit 33, it is possible to further prevent the pressure on resources for logical operations.

[0049] (C2) In the above embodiment, the logic circuit 100 includes four pieces of configuration data CF0 to CF3, but the present disclosure is not limited to this. The logic circuit 100 may include five or more pieces of configuration data. By preparing more pieces of configuration data in which some of the usage areas are different from each other and some are in common with each other, and comparing the results of each operation in the operation circuits configured with each configuration data, the location of an error can be detected more accurately.

[0050] Alternatively, any two or three of the four pieces of configuration data CF0 to CF3 may be provided. This configuration also makes it possible to prevent errors from occurring after reconfiguration, compared to a configuration having only one piece of configuration data. In addition, it is possible to prevent the storage capacity of the storage device that stores the configuration data from being overloaded.

[0051] (C3) In the above embodiment, the control circuit 20 includes the error determination unit 21 and the flag register 22, and determines whether the error occurring in the first arithmetic circuit 311 and the second arithmetic circuit 312 is a soft error or a hard error, but the present disclosure is not limited thereto. The control circuit 20 may not include the error determination unit 21 and the flag register 22. In this case, when it is determined that an error signal has been received in the process shown in FIG. 2 (step S10: Yes), steps S30 and S40 are executed, and the other steps shown in FIG. 2 may not be executed. Even in this configuration, the arithmetic circuit is reconfigured using configuration data that does not use the error location detected in the error location detection process, so that the error state can be eliminated. Note that, when an error location is not detected as a result of executing the error location detection process, the error may be regarded as a soft error, and the arithmetic circuit may be reconfigured using the same configuration data. According to this embodiment, since it is not necessary to execute a determination as to whether the error type is a soft error or a hard error, it is possible to prevent the processing in the logic circuit 100 from becoming complicated.

[0052] (C4) In the above embodiment, the FPGA 30 constitutes the comparison circuit 32 and the test circuit 33, but the present disclosure is not limited to this. The FPGA 30 constitutes the first arithmetic circuit 311 and the second arithmetic circuit 312, and the comparison circuit 32 and the test circuit 33 may be provided in advance as circuits different from the FPGA 30. Furthermore, the logic circuit 100 may include a CPU in addition to the FPGA 30, and execute logic operations using both the FPGA 30 and the CPU. This form also provides the same effects as the above embodiment.

[0053] (C5) In the second embodiment described above, the logic circuit 100A includes the error location register 24, and when an error occurs again, the logic element indicated by the error information stored in the error location register 24 is prioritized as the target for error location detection processing, but the present disclosure is not limited to this. The logic circuit 100A may not include the error location register 24, and when an error occurs again, the logic element to be detected may be changed in a predetermined order to execute the error location detection processing. Even with this configuration, the error location can be detected using the determination result by the comparison circuit 32 without using the test circuit 33, and compared to a configuration including the test circuit 33, the strain on resources for logical operations can be further suppressed.

[0054] The present disclosure is not limited to the above-mentioned embodiment, and can be realized in various configurations without departing from the spirit of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention column can be appropriately replaced or combined in order to solve some or all of the above-mentioned problems or to achieve some or all of the above-mentioned effects. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

[0055] The control circuit 20 and the techniques described herein may be implemented by a special purpose computer provided by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control circuit 20 and the techniques described herein may be implemented by a special purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control circuit 20 and the techniques described herein may be implemented by one or more special purpose computers provided by a combination of a processor and memory programmed to perform one or more functions and a processor configured with one or more hardware logic circuits. The computer program may also be stored on a computer-readable non-transitory tangible storage medium as instructions executed by the computer. [Explanation of symbols]

[0056] 10, 11, 12, 13...ROM, 23...circuit reconfiguration unit, 30...FPGA, 32...comparison circuit, 100, 100A...logic circuit, 311...first arithmetic circuit, 312...second arithmetic circuit, CF0, CF1, CF2, CF3...configuration data

Claims

1. A logic circuit (100, 100A), A plurality of logic elements (30); a storage device (10, 11, 12, 13) for storing a plurality of configuration data (CF0, CF1, CF2, CF3) that defines at least a part of the connection relationship of the plurality of logic elements so as to realize a predetermined function; a circuit reconfiguration unit (23) that selects one of the plurality of configuration data and configures a circuit that realizes the function; a first arithmetic circuit (311) configured with a plurality of first logic elements and executing a logical operation to realize the function based on the configuration data selected by the circuit reconfiguration unit; a second operation circuit (312) configured with a plurality of second logic elements different from the plurality of first logic elements based on the configuration data selected by the circuit reconfiguration unit, and performing the logical operation; a comparison circuit (32) which compares a first operation result, which is a result of the logical operation in the first operation circuit, with a second operation result, which is a result of the logical operation in the second operation circuit, and notifies that an error has occurred in at least one of the first operation circuit and the second operation circuit when the first operation result and the second operation result do not match each other; Equipped with The plurality of first logic elements and the plurality of second logic elements constituting the first arithmetic circuit and the second arithmetic circuit based on each of the configuration data are partially different from each other and partially in common with each other as compared with the plurality of first logic elements and the plurality of second logic elements constituting the first arithmetic circuit and the second arithmetic circuit based on other of the configuration data; when the circuit reconfiguration unit is notified by the comparison circuit that the error has occurred, the circuit reconfiguration unit selects another configuration data different from the selected configuration data, and executes reconfiguration of at least one of the first arithmetic circuit and the second arithmetic circuit. Logic circuit.

2. 2. The logic circuit of claim 1, A test circuit (33) is further provided to detect a logic element in which a hard error occurs among the plurality of logic elements, the circuit reconfiguration unit selects, from among the plurality of configuration data, configuration data that specifies the connection relationship that does not use the logic element in which the test circuit has detected that a hard error has occurred, and executes the reconfiguration. Logic circuit.

3. 2. The logic circuit of claim 1, When the first operation result and the second operation result match each other as a result of the reconfiguration performed by the circuit reconfiguration unit, the comparison circuit detects that the error has occurred in a logic element that is not used as the multiple first logic elements and the multiple second logic elements that configure the first operation circuit and the second operation circuit based on the configuration data used after the reconfiguration, among the multiple first logic elements and the multiple second logic elements that configure the first operation circuit and the second operation circuit based on the configuration data used before the reconfiguration. Logic circuit.

4. 4. The logic circuit of claim 3, an error location register that stores error information indicating the logic element in which a hard error has occurred, the error location register being configured to store ... the circuit reconfiguration unit selects configuration data that specifies the connection relationship that does not use the logic element indicated by the error information, and executes the reconfiguration. Logic circuit.

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