Infrared LED element

Abstract

To provide an infrared LED element in which an uneven shape can be efficiently formed on a light exit surface and luminous efficiency does not easily decrease even in a case of being driven with a large current.SOLUTION: An infrared LED element includes: a support substrate having conductivity; and a semiconductor laminate disposed on an upper layer of the support substrate and comprising a material that can be lattice-matched with InP. The semiconductor laminate includes: a first semiconductor layer disposed on a side closest to the support substrate and indicating a first conductivity type; an active layer disposed on an upper layer of the first semiconductor layer; a second semiconductor layer disposed on an upper layer of the active layer and indicating a second conductivity type different from the first conductivity type; and a third semiconductor layer disposed on an upper layer of the second semiconductor layer and comprising AlaGabIncAs indicating the second conductivity type. The third semiconductor layer has an uneven part on a surface opposite to a side on which the second semiconductor layer is positioned, and the third semiconductor layer has band gap energy lower than band gap energy of the second semiconductor layer and higher than band gap energy of the active layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an infrared LED element, and in particular to an infrared LED element with an emission wavelength of 1,000 nm or more. [Background technology]

[0002] In recent years, semiconductor light-emitting elements that emit light in the infrared region with wavelengths of 1,000 nm or more have been widely used in a variety of applications, including security and surveillance cameras, gas detectors, medical sensors, and industrial equipment.

[0003] Semiconductor light-emitting devices with an emission wavelength of 1,000 nm or more are generally manufactured by the following procedure. A first conductivity type semiconductor layer, an active layer (sometimes called an "emitting layer"), and a second conductivity type semiconductor layer are epitaxially grown in this order on an InP substrate used as a growth substrate, and then electrodes for current injection are formed on the semiconductor wafer. The resulting product is then cut into chips.

[0004] In the past, semiconductor laser elements have been the leading semiconductor light-emitting element with an emission wavelength of 1,000 nm or more, but LED elements have not seen as much development as laser elements, due in part to the lack of applications for these elements.

[0005] However, in recent years, with the expansion of applications, there is an increasing demand for high efficiency infrared LED elements. As a configuration that meets this demand, for example, Patent Document 1 discloses an infrared LED element in which electrodes are formed on the top and bottom surfaces of a wafer in which an LED structure is crystal-grown on an InP substrate, and a voltage is applied between the two electrodes to inject a current into the active layer, causing it to emit light.

[0006] Furthermore, as the applications of the relevant wavelength band become more widespread, there is a demand for LEDs with higher light emission efficiency and smaller size and height.As a configuration that meets this demand, Patent Document 2 discloses a structure in which a light-emitting diode wafer in which an epitaxial semiconductor film of an LED structure is crystal-grown on a growth substrate is bonded to a support substrate with a metal layer via a highly reflective film, and then the growth substrate is thinned or completely removed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 4-282875 [Patent Document 2] JP 2012-129357 A [Patent Document 3] JP 2023-018332 A [Patent Document 4] JP 2012-074489 A Summary of the Invention [Problem to be solved by the invention]

[0008] The growth substrate and semiconductor layer of an infrared LED element with an emission wavelength of 1,000 nm or more are made of a material consisting of a combination of multiple elements selected from Al, Ga, In, As, and P. Many of these materials are known to have a high refractive index. For example, InP has a refractive index of about 3.1 to 3.3 for light with a wavelength of 1,000 nm or more and 2,000 nm or less. For this reason, when extracting light from the InP substrate side, if no treatment is applied to the InP substrate, most of the light generated in the semiconductor layer is totally reflected at the boundary between the InP substrate and air. It is expected that the light reflected at the interface with the InP substrate and returned to the active layer side is extracted to the outside after repeated reflections, but part of the light is absorbed during the process of traveling through the InP substrate and the semiconductor layer, resulting in a decrease in extraction efficiency.

[0009] In addition, in infrared LED elements, etching is performed with a chemical solution to form an uneven shape on the light extraction surface in order to extract more light. However, as mentioned in the above Patent Document 3, a method has not been established for forming an uneven shape on the surface of an InP substrate that exhibits the same degree of randomness as GaN-based or GaAs-based LED elements by a simple chemical etching process. For this reason, infrared LED elements that use the main surface of an InP substrate as the light extraction surface have a problem in that when an uneven shape is formed on the light extraction surface by etching with a chemical solution, the randomness becomes insufficient, and multiple peaks (multi-peaks) appear in the spectrum of the emitted light.

[0010] In infrared LED elements that use InP as a growth substrate, InP is generally used as a semiconductor layer that is lattice-matched to the substrate, and InP is also used for the light extraction surface that forms a rough surface. As a method for forming a rough shape, a method (wet etching) in which the light extraction surface is dipped in an acid-based etching solution without using a patterning mask, as shown in Patent Document 4, is known, but it could not solve the problem of multiple peaks as described above.

[0011] Here, the phenomenon of the emission spectrum becoming multi-peaked occurs when light propagates in a thin region sandwiched between a pair of interfaces exhibiting reflectivity. In view of this, it is considered that the occurrence of multi-peaking can be suppressed by reducing the reflectance of the light extraction surface. In the above-mentioned GaN-based and GaAs-based LED elements, the main surface of the semiconductor layer constituting the light extraction surface is etched to randomly roughen the surface. This suppresses the occurrence of multi-peaking in the emission spectrum of the GaN-based and GaAs-based LED elements.

[0012] The above method can be used in GaN and GaAs LED elements because a method has been established that can perform highly reproducible etching on the main surface of the semiconductor layer. In the case of GaN, the nitrogen polarity surface ([000-1] surface) has relatively low chemical stability and high defect density, so a rough surface can be formed relatively easily by etching with a chemical solution such as KOH. In the case of GaAs, As is an element that is relatively easily oxidized, so a rough surface can be easily formed by etching while forming a micromask on the surface using an etchant with an added oxidizing agent.

[0013] However, at the time of the present invention, a method for randomly roughening the surface of an InP-based LED element with good reproducibility has not been established. The reason for this is that InP is more stable and has a lower defect density than the nitrogen polarity surface of GaN, and it is difficult to form an oxide micromask suitably. Furthermore, as mentioned above, there has been little demand for InP-based LED elements compared to GaN-based and GaAs-based LED elements, and there is also a situation in which the development of an etchant that can randomly roughen the surface has not progressed. Even if such an etchant were developed, it is expected that the cost would be extremely high in light of the above circumstances.

[0014] Furthermore, in a vertical infrared LED element, an electrode is placed on the upper surface of the light extraction surface. When roughening the light extraction surface, it is necessary to intentionally avoid the area where this electrode is formed. For these reasons, high reproducibility is required when roughening the surface.

[0015] For the reasons described above, there is currently no practical method for randomly roughening the surface of an InP-based infrared LED element with good reproducibility.

[0016] Therefore, we focused on As-containing materials, for which a dip treatment method is generally used as a method for forming unevenness. It is known that GaAs and AlGaAs, which are generally used in red LED elements, can be dipped into an etching solution containing nitric acid to form a relatively random uneven shape without forming a patterning mask. However, when GaAs or AlGaAs is used in an infrared LED element using an InP substrate as a growth substrate, crystal defects are introduced due to lattice mismatch. In particular, in a structure in which the growth substrate is peeled off and bonded to a support substrate as described in Patent Document 2, a layer that forms unevenness is grown at the beginning of crystal growth, so that crystal defects introduced by lattice mismatch pass through the active layer, causing a decrease in light emission efficiency and reliability. Therefore, based on the correlation diagram of the band gap energy of semiconductor materials shown in Figure 1, the inventors focused on AlGaInAs, which is an As-containing material that is thought to be easy to form unevenness, but is lattice-matched with InP.

[0017] By changing the n-InP layer that serves as the light extraction surface to n-AlGaInAs, it was confirmed that it was possible to easily form an uneven shape. It was also confirmed that this was effective in suppressing multiple peaks, which is one of the purposes of forming an uneven shape on the light extraction surface.

[0018] However, the inventors realized that when the entire n-type layer is changed from InP to AlGaInAs, the light-emitting efficiency of the infrared LED element decreases compared to an element with the structure before the change, especially when driven with a large current.

[0019] In view of the above problems, an object of the present invention is to provide an infrared LED element in which an uneven shape can be efficiently formed on the light emitting surface and in which the light emitting efficiency is not likely to decrease even when driven with a large current. [Means for solving the problem]

[0020] The semiconductor light-emitting element of the present invention comprises: An infrared LED element capable of emitting infrared light with a peak wavelength of 1,000 nm to 2,000 nm, a conductive support substrate, and a semiconductor laminate disposed on the upper layer of the support substrate and made of a material lattice-matched to InP, the semiconductor laminate includes a first semiconductor layer showing a first conductivity type disposed on the side closest to the support substrate, an active layer disposed on the upper layer of the first semiconductor layer, a second semiconductor layer showing a second conductivity type different from the first conductivity type disposed on the upper layer of the active layer, Al a Ga b In c As(0 ≦ a < 1, 0 < b < 1, 0 < c < 1, a + b + c = 1) disposed on the upper layer of the second semiconductor layer, the third semiconductor layer has uneven portions on the surface opposite to the side where the second semiconductor layer is located, the band gap energy of the third semiconductor layer is lower than the band gap energy of the second semiconductor layer and higher than the band gap energy of the active layer.

[0021] The inventors of the present invention have intensively studied and speculated that in a conventional infrared LED element, when the entire n-type layer is changed from InP to AlGaInAs, the reduction in luminous efficiency is caused by the decrease in the band gap energy difference between the active layer and the n-type layer. Generally, the active layer adopts a structure sandwiched between P-type and N-type semiconductors with a large band gap energy. This is to confine electrons and holes contributing to light emission within the active layer and efficiently recombine them. However, if the band gap energy difference between the active layer and the n-type layer, or between the active layer and the p-type layer, is small, electrons and holes are likely to leak out of the active layer before recombination. That is, the above-described reduction in luminous efficiency is considered to be due to the reduction in the band gap energy difference between the active layer and the n-type layer.

[0022] ​Based on the above speculation, the inventors conceived of forming, in the semiconductor laminate, a roughened layer that is lattice-matched with InP while being made of an As-containing material that is thought to be easy to form into an uneven shape, and a cladding layer (second semiconductor layer) that has a large band gap energy and is unlikely to cause a decrease in luminous efficiency.

[0023] In the infrared LED element having the above configuration, the second semiconductor layer is formed on the active layer in the same manner as in the conventional configuration, so that the band gap energy difference between the active layer and the second semiconductor layer is maintained at the same level as in the conventional configuration. Furthermore, the third semiconductor layer constituting the light emitting surface is easier to form unevenness for improving the light extraction efficiency than InP.

[0024] Therefore, the infrared LED element having the above structure can efficiently form an uneven shape on the light emitting surface, and the light emission efficiency is unlikely to decrease even when driven with a large current.

[0025] The infrared LED element is The second semiconductor layer may be InP.

[0026] InP has the largest band gap energy among materials that are lattice-matched to an InP substrate, making it suitable as a material for the second semiconductor layer (cladding layer).

[0027] The above LED elements are The third semiconductor layer may have a thickness of 1 μm to 5 μm.

[0028] If the third semiconductor layer is too thin, it becomes extremely difficult to form a rough surface, and if it is too thick, the electrical resistance value becomes large. For this reason, the third semiconductor layer is preferably designed to have a thickness that allows the formation of a rough surface and does not cause an electrical resistance value problem, specifically, within the range of 1 μm to 5 μm.

[0029] The infrared LED element is a first electrode disposed in contact with a portion of an upper surface of the third semiconductor layer; The dopant concentration of the third semiconductor layer is higher than the dopant concentration of the second semiconductor layer and is 5×10 17 / cm 3 It may be more than that.

[0030] Furthermore, the infrared LED element has The dopant concentration of the second semiconductor layer is 5×10 17 / cm 3 That's all. The dopant concentration of the third semiconductor layer is 1×10 18 / cm 3 It may be more than that.

[0031] In a configuration in which the first electrode is formed on a part of the upper surface of the third semiconductor layer, the third semiconductor layer functions as a contact layer that electrically connects the first electrode and the second semiconductor layer. For this reason, it is more important that the third semiconductor layer has a lower electrical resistance value than the second semiconductor layer. In addition, the dopant concentration of the third semiconductor layer is 5×10 17 / cm 3 If it is less than this, the electrical resistance will be large, which may lead to problems such as a rise in temperature during operation.

[0032] In the above configuration, by adjusting the dopant concentrations of the second and third semiconductor layers as described above, the third semiconductor layer functions as a contact layer having a sufficiently small electrical resistance between the first electrode and the second semiconductor layer. In addition, considering that the second semiconductor layer functions as a cladding layer, the dopant concentration of the second semiconductor layer is 5×10 17 / cm 3 or more, and the dopant concentration of the third semiconductor layer is 1×10 18 / cm 3 More preferably, it is equal to or greater than this.

[0033] In addition, the infrared LED element is a second electrode disposed on a surface of the support substrate opposite to a surface on which the semiconductor laminate is disposed; The semiconductor device may further include a reflective layer made of a conductive material and disposed between the support substrate and the semiconductor laminate.

[0034] According to the above configuration, the reflective layer reflects light generated in the active layer and traveling toward the first conductor layer side, i.e., the side opposite to the light emitting surface formed on the main surface of the third semiconductor layer, toward the light emitting surface side. Therefore, the infrared LED element having the above configuration can extract more light generated in the active layer from the light emitting surface.

[0035] The infrared LED element is The band gap energy of the second semiconductor layer may be 1.1 times or more the band gap energy of the active layer.

[0036] When the band gap energy of the second semiconductor layer and the band gap energy of the active layer satisfy the above-mentioned relationship, the decrease in efficiency is further suppressed.

[0037] The infrared LED element is The unevenness formed on the surface of the third semiconductor layer may have a surface roughness (Ra) of 0.25 to 1.00. Effect of the Invention

[0038] According to the present invention, an infrared LED element can be realized in which a concave-convex shape can be efficiently formed on the light emitting surface and in which the light emitting efficiency is not easily reduced even when driven with a large current. [Brief description of the drawings]

[0039] [Figure 1] FIG. 1 is a correlation diagram of band gap energy of semiconductor materials. [Diagram 2] 1 is a cross-sectional view showing a schematic structure of an infrared LED element according to one embodiment. [Figure 3A] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3B]3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3C] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3D] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3E] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3F] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3G] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3H] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3I] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3J] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3K] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. [Figure 3L] 3 is a cross-sectional view illustrating a process for producing the infrared LED element shown in FIG. 2. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] The infrared LED element of the present invention will be described below with reference to the drawings. Note that the following drawings of the infrared LED element are all schematic illustrations, and the dimensional ratios and numbers in the drawings do not necessarily match the actual dimensional ratios and numbers.

[0041] In this specification, the expression "layer B is formed on layer A" is intended to include not only the case where layer B is formed directly on the surface of layer A, but also the case where layer B is formed on the surface of layer A via a thin film. Note that the "thin film" referred to here refers to a layer having a thickness of 50 nm or less, and preferably refers to a layer having a thickness of 10 nm or less.

[0042] Fig. 2 is a cross-sectional view showing a schematic structure of the infrared LED element of this embodiment. The infrared LED element 1 shown in Fig. 2 includes a semiconductor laminate 20 arranged on the upper layer (+Y side) of a support substrate 11. The infrared LED element 1 shown in Fig. 2 corresponds to a schematic cross-sectional view when cut along the XY plane at a predetermined position. In the following description, the XYZ coordinate system shown in Fig. 2 will be referred to as appropriate.

[0043] In the following description, when a positive or negative direction is to be distinguished when expressing a direction, the direction is described with a positive or negative sign, such as "+X direction" and "-X direction". When a direction is to be expressed without distinguishing between positive and negative directions, the direction is simply described as "X direction". That is, in this specification, when the direction is simply described as "X direction", both the "+X direction" and the "-X direction" are included. The same applies to the Y direction and the Z direction.

[0044] In the infrared LED element 1, infrared light L is generated in the semiconductor laminate 20 (more specifically, in the active layer 25 described below). More specifically, as shown in Fig. 2, the infrared light L (L1, L2) is extracted in the +Y direction with respect to the active layer 25. The infrared light L has a peak wavelength of 1,000 nm to 2,000 nm.

[0045] [Element structure] The structure of the infrared LED element 1 will be described in detail below.

[0046] (Support substrate 11) The support substrate 11 is made of a semiconductor such as Si or Ge, or a metal material such as Cu or CuW. When the support substrate 11 is made of a semiconductor, it may be doped with a high concentration of a dopant so as to exhibit electrical conductivity. As an example, the support substrate 11 is doped with 1×10 19 / cm 3 The support substrate 11 is a Si substrate doped with a dopant concentration of 1000 or more and having a resistivity of 10 mΩ cm or less. As the dopant, for example, phosphorus (P), arsenic (As), antimony (Sb), etc. can be used other than boron (B). From the viewpoint of achieving both high heat dissipation and low manufacturing costs, the support substrate 11 is preferably a Si substrate.

[0047] The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 μm to 500 μm, and preferably 100 μm to 300 μm.

[0048] (Metal bonding layer 13) The infrared LED element 1 includes a metal bonding layer 13 disposed on the upper layer of a support substrate 11. The metal bonding layer 13 is made of a solder material with a low melting point, such as Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, or Sn. As described later with reference to FIG. 3G, the metal bonding layer 13 is used to bond the growth substrate 3 having the semiconductor laminate 20 formed on the upper surface thereof to the support substrate 11. The thickness of the metal bonding layer 13 is not particularly limited, but is, for example, 0.5 μm to 5.0 μm, and preferably 1.0 μm to 3.0 μm.

[0049] Barrier layers may be formed on the upper and lower layers of the metal bonding layer 13. The barrier layers may be provided for the purpose of suppressing diffusion of the solder material constituting the metal bonding layer 13. The material is not limited as long as it achieves this function, but the barrier layer can be realized by a material containing, for example, Ti, Pt, W, Mo, or Ni. A more specific example is a laminate of Ti / Pt / Au.

[0050] (Reflection layer 15) The infrared LED element 1 of this embodiment includes a reflective layer 15 disposed on the metal bonding layer 13 .

[0051] The reflective layer 15 has a function of reflecting infrared light L2 traveling toward the support substrate 11 (-Y direction) out of the infrared light L generated in the active layer 25, and guiding it to the +Y direction. The reflective layer 15 is made of a conductive material that exhibits high reflectance to the infrared light L. The reflectance of the reflective layer 15 to the infrared light L is 50% or more, preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0052] When the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, Ag, an Ag alloy, Au, Al, Cu, etc. can be used as the material of the reflective layer 15. This material can be appropriately selected depending on the wavelength of the infrared light L.

[0053] The thickness of the reflective layer 15 is not particularly limited, but is, for example, from 0.1 μm to 2.0 μm or less, and preferably from 0.3 μm to 1.0 μm or less.

[0054] In addition, when a barrier layer as described above is formed between the reflective layer 15 and the metal bonding layer 13, it is possible to prevent the material constituting the metal bonding layer 13 from diffusing toward the reflective layer 15 side, thereby preventing the reflectance of the reflective layer 15 from decreasing.

[0055] From the viewpoint of improving the light extraction efficiency, it is preferable that the infrared LED element 1 has a reflective layer 15 as shown in FIG. 2. However, in the present invention, it is optional whether or not the infrared LED element 1 has the reflective layer 15.

[0056] Although not shown, from the viewpoint of improving the light extraction efficiency, the infrared LED element 1 preferably includes an anti-reflection film covering the upper surface, side surface, or both of the semiconductor laminate 23. However, whether or not the infrared LED element 1 includes an anti-reflection film is optional. The anti-reflection film is formed on the upper surface, side surface, or both of the semiconductor laminate 23 by the plasma CVD method, using a material such as SiO2 or SiN, and has an appropriate film thickness determined so as to provide an optical film thickness that reduces the reflectance based on the refractive index and emission wavelength.

[0057] (insulating layer 17) The infrared LED element 1 shown in Fig. 2 includes an insulating layer 17 disposed on the reflective layer 15. The insulating layer 17 is made of a material that exhibits electrical insulation and is highly transparent to infrared light L. The transmittance of the insulating layer 17 to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0058] When the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, SiO2, SiN, Al2O3, ZrO, HfO, MgO, or the like can be used as the material of the insulating layer 17. This material can be appropriately selected depending on the wavelength of the light generated in the active layer 25.

[0059] (Semiconductor laminate 20) The infrared LED element 1 shown in Fig. 2 has a semiconductor laminate 20 disposed on an insulating layer 17. The semiconductor laminate 20 is a laminate of multiple semiconductor layers, and includes, for example, a first contact layer 21, a first cladding layer 23, an active layer 25, and a second cladding layer 27. Each of the semiconductor layers (21, 23, 25, 27) constituting the semiconductor laminate 20 is made of a material that is lattice-matched with a growth substrate 3 described below and can grow epitaxially.

[0060] The total thickness of the semiconductor laminate 20 is 30 μm (30,000 nm) or less, and preferably 5 μm to 20 μm.

[0061] First contact layer 21, first cladding layer 23 In this embodiment, the first contact layer 21 is made of, for example, p-type GaInAsP. The thickness of the first contact layer 21 is not limited, but is, for example, 10 nm to 1000 nm, and preferably 50 nm to 500 nm. The p-type dopant concentration of the first contact layer 21 is preferably 5×10 17 / cm 3 ~3×10 19 / cm 3 and more preferably 1×10 18 / cm 3 ~2×10 19 / cm 3 It is.

[0062] In this embodiment, the first cladding layer 23 is disposed on the first contact layer 21 and is made of, for example, p-type InP. The thickness of the first cladding layer 23 is not limited, but is, for example, 1,000 nm to 10,000 nm, and preferably 2,000 nm to 5,000 nm. The p-type dopant concentration of the first cladding layer 23 at a position away from the active layer 25 is preferably 1×10 17 / cm 3 ~3×10 18 / cm 3 More preferably, it is 5×10 or less. 17 / cm 3 ~3×10 18 / cm 3 The following is the result.

[0063] The p-type dopant contained in the first contact layer 21 and the first cladding layer 23 may be Zn, Mg, Be, or the like, with Zn or Mg being preferred, and Zn being particularly preferred. In this embodiment, the first contact layer 21 and the first cladding layer 23 correspond to the "first semiconductor layer."

[0064] 《Active layer 25》 In this embodiment, the active layer 25 is disposed on the first cladding layer 23. The material of the active layer 25 is appropriately selected from materials that can generate light of a target wavelength and can be epitaxially grown in a lattice-matched manner with the growth substrate 3, as described later with reference to FIG.

[0065] In manufacturing the infrared LED element 1 that emits infrared light L with a peak wavelength of 1,000 nm to 2,000 nm, the active layer 25 may have a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or may have an MQW (Multiple Quantum Well) structure including a well layer made of GaInAsP, AlGaInAs, or InGaAs, and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP having a larger band gap energy than the well layer.

[0066] The thickness of the active layer 25 is 50 nm to 2,000 nm, and preferably 100 nm to 300 nm, when the active layer 25 has a single layer structure, and is configured by stacking well layers and barrier layers, each having a thickness of 5 nm to 20 nm, in the range of 2 periods to 50 periods.

[0067] The active layer 25 may be doped to n-type or p-type, or may be undoped. When doped to n-type, for example, Si can be used as a dopant.

[0068] Second Clad Layer 27 In this embodiment, the second cladding layer 27 is disposed on the active layer 25, and is made of, for example, n-type InP. The second cladding layer 27 is required to have a certain degree of film thickness and impurity concentration in order to spread current. The thickness of the second cladding layer 27 is not limited, but is, for example, 2,000 nm to 15,000 nm, and preferably 5,000 nm to 10,000 nm. The n-type dopant concentration of the second cladding layer 27 is preferably 5×10 17 / cm 3 More preferably, it is 1×10 18 / cm 3 In addition, when current dispersion and the like are also taken into consideration, the range of the n-type dopant concentration of the second cladding layer 27 is preferably, for example, 5×10 17 / cm 3 ~1×10 19 / cm 3 and more preferably, 1 × 10 18 / cm 3 ~5 × 10 18 / cm 3 .

[0069] The materials of the first cladding layer 23 and the second cladding layer 27 are materials that do not absorb the infrared light L generated in the active layer 25, and are appropriately selected from materials that can be epitaxially grown in lattice matching with the growth substrate 3 (see FIG. 3B). When an InP substrate is employed as the growth substrate 3, materials such as InP, GaInAsP, or AlGaInAs can be used as the materials of the first cladding layer 23 and the second cladding layer 27, but InP is preferred.

[0070] Optionally, from the viewpoint of suppressing a decrease in efficiency, the bandgap energy of the second cladding layer 27 is preferably 1.1 times or more the bandgap energy of the active layer 25.

[0071] 《Second contact layer 28》 In the present embodiment, the material of the second contact layer 28 is disposed on the upper layer of the second cladding layer 27 and is appropriately selected from materials satisfying Al a Ga b In c As (0 ≤ a < 1, 0 < b < 1, 0 < c < 1, a + b + c = 1). More specifically, for example, AlGaInAs, InGaAs, or the like can be used.

[0072] For the second contact layer 28, a material is selected whose bandgap energy is lower than that of the second cladding layer 27 and higher than that of the active layer 25.

[0073] In the present embodiment, the second contact layer 28 is composed of, for example, n-type AlGaInAs. The thickness of the second contact layer 28 is not limited, but is preferably 1 μm to 5 μm, and more preferably 2 μm to 4 μm. Also, the n-type dopant concentration of the second contact layer 28 is preferably 5 × 10 17 / cm 3More preferably, it is 1×10 18 / cm 3 That's all.

[0074] In addition, when current dispersion and the like are also taken into consideration, the range of the n-type dopant concentration of the second contact layer 28 is, for example, 5×10 17 / cm 3 ~3×10 19 / cm 3 and more preferably 1×10 18 / cm 3 ~2×10 19 / cm 3 In addition, although optional, from the viewpoint of relatively reducing the electrical resistance value, it is preferable that the dopant concentration of the second contact layer 28 is configured to be higher than the dopant concentration of the second cladding layer.

[0075] As the n-type impurity material doped into the second cladding layer 27 and the second contact layer 28, Sn, Si, S, Ge, Se, or the like can be used, with Si being particularly preferable. The second cladding layer 27 corresponds to the "second semiconductor layer", and the second contact layer 28 corresponds to the "third semiconductor layer".

[0076] As shown in Fig. 2, in the infrared LED element 1 of this embodiment, a concave-convex portion 40 is formed on the surface (hereinafter referred to as the "first surface 28a") on the +Y side of the second contact layer 28. Although the concave-convex portion 40 is shown in Fig. 2 as having a schematic periodic shape, in reality it has a random concave-convex shape formed by a dipping treatment using an etching solution. Here, although this is optional, from the viewpoints of increasing the light extraction efficiency and ease of formation, it is preferable that the surface roughness (Ra) of the concave-convex portion 40 is 0.25 to 1.00.

[0077] (Internal electrode 31) 2 has internal electrodes 31 formed in a plurality of locations within the insulating layer 17, penetrating the insulating layer 17 in the Y direction. The internal electrodes 31 electrically connect the first semiconductor layers (21, 23) to the supporting substrate 11. The internal electrodes 31 are preferably provided at a plurality of locations dispersed in a direction parallel to the XZ plane (i.e., a direction parallel to the main surface of the supporting substrate 11).

[0078] The internal electrode 31 is made of a material capable of forming an ohmic connection with the first contact layer 21. As an example, the internal electrode 31 is made of AuZn, AuBe, or a laminated structure containing at least Au and Zn (e.g., Au / Zn / Au, etc.). Note that these materials have a lower reflectance for infrared light L than the material constituting the reflective layer 15.

[0079] When viewed in the Y direction, the pattern shape of the internal electrodes 31 is arbitrary. However, from the viewpoint of passing a current over a wide area in the active layer 25 in a direction parallel to the main surface (XZ plane) of the support substrate 11 (hereinafter referred to as the "plane direction"), it is preferable that a plurality of internal electrodes 31 are disposed and distributed in the plane direction.

[0080] The total area of ​​all the internal electrodes 31 as viewed in the Y direction is preferably 30% or less, more preferably 20% or less, and particularly preferably 15% or less, of the area in the planar direction of the semiconductor laminate 20 (e.g., active layer 25). If the total area of ​​the internal electrodes 31 is relatively large, the amount of infrared light L2 traveling from the active layer 25 to the support substrate 11 side (-Y direction) that is absorbed by the internal electrodes 31 increases, resulting in a decrease in light extraction efficiency. On the other hand, if the total area of ​​the internal electrodes 31 is too small, the resistance value increases, resulting in an increase in forward voltage.

[0081] (Top electrode 32) The infrared LED element 1 shown in Fig. 2 has an upper electrode 32 disposed on the upper surface of the semiconductor laminate 20. The upper electrodes 32 are typically formed so that multiple electrodes extend in a predetermined direction. As an example, the upper electrodes 32 extend in the X and Z directions along the sides of the semiconductor laminate 20, forming a comb shape. However, the arrangement pattern of the upper electrodes 32 is arbitrary, and may be, for example, a lattice shape or a spiral shape.

[0082] The upper electrode 32 is formed over a wide range on the XZ plane while exposing (except for a part of the dielectric layer formed directly or on the same surface) the surface of the second contact layer 28 located below (-Y side). This allows the current flowing in the active layer 25 to be spread in a direction parallel to the XZ plane, and allows light to be emitted over a wide range in the active layer 25.

[0083] The upper electrode 32 is made of, for example, AuGe / Ni / Au, AuGe, or other materials, and may be made of a plurality of these materials. The upper electrode 32 corresponds to a "first electrode."

[0084] (Pad electrode 34) As shown in Fig. 2, the infrared LED element 1 has a pad electrode 34 disposed on the upper surface of a portion of the upper electrode 32. Note that in Fig. 2, the pad electrode 34 is shown as being formed on the entire surface of the upper electrode 32, but this is for convenience of illustration. In reality, the pad electrode 34 may be formed on a portion of the surface of the upper electrode 32 extending in the planar direction.

[0085] The pad electrode 34 is made of, for example, Ti / Au, Ti / Pt / Au, etc. The pad electrode 34 is provided for the purpose of securing an area for contacting a bonding wire for power supply, but in the present invention, it is optional whether or not to provide the pad electrode 34.

[0086] (Back electrode 33) The infrared LED element 1 shown in Fig. 2 includes a back electrode 33 disposed on the surface of the supporting substrate 11 opposite to the semiconductor laminate 20 (-Y side). The back electrode 33 is in ohmic contact with the supporting substrate 11. As an example, the back electrode 33 is made of a material such as Ti / Au or Ti / Pt / Au, and may include a plurality of these materials. The back electrode 33 corresponds to the "second electrode."

[0087] [Manufacturing method] An example of a method for manufacturing the above-mentioned infrared LED element 1 will be described with reference to Figures 3A to 3L. Figures 3A to 3L are all cross-sectional views of one step in the manufacturing process. Note that the order of the following steps may be changed as appropriate as long as it does not affect the manufacture of the infrared LED element 1.

[0088] (Step S1) As shown in Fig. 3A, a growth substrate 3 is prepared. In this embodiment, an InP substrate having one of its main surfaces as a (001) plane is preferably used as the growth substrate 3. An example of the thickness is 370 µm, and the diameter of the main surface is 2 inches. However, the thickness and size of the growth substrate 3 are set appropriately.

[0089] (Step S2) The growth substrate 3 is transferred into, for example, an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and a buffer layer 22, an etching stop layer (ES layer) 24, a second contact layer 28, a second cladding layer 27, an active layer 25, a first cladding layer 23, and a first contact layer 21 are epitaxially grown in this order on the growth substrate 3 to form a semiconductor laminate 20 (see FIG. 3B). In this step S2, the type and flow rate of the source gas, the processing time, the environmental temperature, and the like are appropriately adjusted according to the material or film thickness of the layer to be grown.

[0090] An example of forming the semiconductor laminate 20 is as follows. First, n-type InP doped with Si is laminated on the growth substrate 3 to a predetermined thickness (for example, about 500 nm) to obtain the buffer layer 22. Next, a layer of a material different from the buffer layer 22 (here, an InGaAs layer) is laminated to a predetermined thickness (for example, about 200 nm) to obtain the ES layer 24a. Next, a layer of a material different from the ES layer 24a (here, an InP layer) is laminated to a predetermined thickness (for example, about 300 nm) to obtain the ES layer 24b. Thereafter, the second contact layer 28, the second cladding layer 27, the active layer 25, the first cladding layer 23, and the first contact layer 21 are sequentially formed under the condition that the growth conditions are set so as to obtain the above-mentioned thickness and composition. Note that, if the second semiconductor layer has the function of the ES layer, the ES layer 24 may not be formed.

[0091] As a detailed example, AlGaInAs is laminated to a thickness of 5,000 nm to obtain the second contact layer 28. Next, n-type InP doped with Si is laminated to a thickness of 3,000 nm to obtain the second cladding layer 27. Next, InGaAsP is laminated to a thickness of 900 nm to obtain the active layer 25. Here, the conditions are set so that the peak wavelength of the infrared light L emitted from the infrared LED element 1 is 1,300 nm. However, as described above, the peak wavelength of the infrared light L can be adjusted within the range of 1,000 nm to 2,000 nm by adjusting the composition ratio of the materials constituting the active layer 25 or by adopting an MQW structure.

[0092] Then, p-type InP doped with Zn is deposited to a thickness of 3,000 nm to form the first cladding layer 23, and then p-type InGaAsP doped with Zn is deposited to a thickness of 200 nm to form the first contact layer 21.

[0093] (Step S3) After the wafer on which the semiconductor laminate 20 is formed on the growth substrate 3 is removed from the MOCVD apparatus, an insulating layer 17 made of, for example, SiO2 is formed by a plasma CVD method (see FIG. 3C). An example of the thickness is 200 nm. Next, a resist mask patterned by a photolithography method is formed on the surface of the insulating layer 17. The insulating layer 17 formed in the resist opening is removed by an etching method using a specific agent such as buffered hydrofluoric acid, and then a material film of the internal electrode 31 made of, for example, Au / Zn / Au is formed by using an EB deposition apparatus. An example of the thickness of the material film of the internal electrode 31 is Au / Zn / Au=25 nm / 25 nm / 150 nm.

[0094] Next, after the resist mask is removed, the material film formed in the unnecessary region is lifted off to form the internal electrode 31 (see FIG. 3C). After that, an annealing process is performed by heating at 450° C. for 10 minutes, for example, to realize ohmic contact between the first contact layer 21 and the internal electrode 31.

[0095] (Step S4) 3D, the reflective layer 15 and the metal bonding layer 13a are successively formed on the upper surface of the insulating layer 17. For example, the reflective layer 15 is formed by depositing Al / Au to a predetermined thickness using an EB deposition apparatus, and then the metal bonding layer 13a is formed by depositing Ti / Au to a predetermined thickness. The metal bonding layer 13a may be made of the same material as the metal bonding layer 13 described above.

[0096] An example of the material film of the reflective layer 15 is Al / Au=5nm / 200nm. An example of the film thickness of the metal bonding layer 13a is Ti / Au=150nm / 1500nm. As described above, a barrier layer may be formed between the reflective layer 15 and the metal bonding layer 13a. An example of the material film of the barrier layer is Ti / Pt / Au=150nm / 300nm / 200nm.

[0097] (Step S5) As shown in FIG. 3E, a support substrate 11 is prepared in addition to the growth substrate 3. In this embodiment, a conductive Si substrate having a (001) plane as one of its main surfaces and doped with a high concentration of boron (B) is used. The electrical resistivity of the support substrate 11 is preferably less than 10 mΩ·cm (=0.1 mΩ·m). As described above, a barrier layer may be formed between the support substrate 11 and the metal bonding layer 13b.

[0098] (Step S6) 3F, metal bonding layer 13b is formed on the main surface of support substrate 11. Metal bonding layer 13b can be formed in the same manner as metal bonding layer 13a described above in step S4.

[0099] (Step S7) As shown in FIG. 3G, the growth substrate 3 and the support substrate 11 are bonded together with the metal bonding layers 13 (13a, 13b) interposed therebetween while being pressed using, for example, a wafer bonding device. Preferably, the surfaces of the metal bonding layers 13 (13a, 13b) are cleaned before being laminated together. This bonding process is performed, for example, at 300° C. and 1 MPa. Through this process, the metal bonding layer 13a on the growth substrate 3 and the metal bonding layer 13b on the support substrate 11 are melted and integrated (metal bonding layer 13).

[0100] (Step S8) As shown in Fig. 3H, the growth substrate 3 is removed. For example, the bonded wafer is immersed in a hydrochloric acid-based etchant to remove the growth substrate 3. At this time, since the ES layer 24 formed of a material different from the growth substrate 3 and the buffer layer 22 is insoluble in the hydrochloric acid-based etchant, the etching process is stopped when the ES layer 24a is exposed.

[0101] (Step S9) As shown in FIG. 3I, the ES layer 24a and the ES layer 24b are removed to expose the second contact layer 28. For example, after washing with pure water as necessary, the ES layer 24a is removed by immersing in a predetermined chemical solution that is soluble in the ES layer 24a and insoluble in the ES layer 24b. As an example of the chemical solution for removing the ES layer 24a, a mixture of sulfuric acid and hydrogen peroxide (SPM) can be used. Thereafter, the ES layer 24b is removed by immersing in a predetermined chemical solution that is soluble in the ES layer 24b and insoluble in the second contact layer 28. As an example of the chemical solution for removing the ES layer 24b, a hydrochloric acid-based etchant can be used.

[0102] (Step S10) 3J, a top electrode 32 is formed on the exposed surface of the second contact layer 28. Specifically, the process is performed in the following procedure.

[0103] A resist mask patterned by photolithography is formed on the surface of the second contact layer 28. Next, a material (e.g., Au / Ge / Au) for forming the upper electrode 32 is deposited by an EB deposition apparatus, and then lifted off to form the upper electrode 32. An example of the thickness of the upper electrode 32 is Au / Ge / Au=10 nm / 30 nm / 150 nm.

[0104] Thereafter, in order to realize ohmic properties of the upper electrode 32, an annealing process is performed by heating at, for example, 450° C. for 10 minutes.

[0105] Next, a pad electrode 34 is formed on the upper surface of the upper electrode 32 at a predetermined position. This can also be achieved by a film formation process using an EB deposition apparatus and a lift-off process, similar to the upper electrode 32. The pad electrode 34 is formed, for example, of Ti / Pt / Au, with thicknesses of Ti / Pt / Au=150 nm / 300 nm / 1500 nm, for example.

[0106] (Step S11) As shown in FIG. 3K, the unevenness 40 is formed on the first surface 28a of the second contact layer 28.

[0107] As an example of a specific method, first, a resist patterned by photolithography is formed on the first surface 28a of the second contact layer 28. This resist is formed so as to cover the upper part of the region where the upper electrode 32 is formed.

[0108] Through this patterned resist, the first surface 28a of the second contact layer 28 is etched using an etchant such as a sulfuric acid-nitric acid mixture. In this manner, an uneven portion 40 having a random uneven shape is formed on the first surface 28a of the second contact layer 28. For example, a nitric acid-water mixture is used as the etchant.

[0109] Thereafter, the resist is removed with a cleaning liquid such as acetone, etc. As an etchant, for example, a resist stripping liquid sold by various resist manufacturers is used.

[0110] (Step S12) As shown in FIG. 3L, mesa etching is performed to separate each element. Specifically, wet etching is performed using a specific etchant while the non-etched area of ​​the surface of the second contact layer 28 is masked with a resist patterned by photolithography. This removes a part of the semiconductor laminate 20 located in the unmasked area.

[0111] As an example of a specific method, first, the second contact layer 28 and the second cladding layer 27 are removed by etching using a mixed solution of hydrochloric acid and phosphoric acid. This reaction is stopped when the active layer 25 is exposed. Next, the active layer 25 is removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide (SPM). This reaction is stopped at the first cladding layer 23. Next, the first cladding layer 23 is partially removed by etching using a mixed solution of hydrochloric acid and phosphoric acid. Thereafter, the resist is removed by a cleaning liquid such as acetone. It is also possible to remove the first cladding layer 23 and the first contact layer 21 to expose the insulating layer 17.

[0112] (Step S13) After the thickness of the back surface side of the support substrate 11 is adjusted, a back surface electrode 33 is formed on the back surface side of the support substrate 11 (see FIG. 2). As a specific method for forming the back surface electrode 33, similar to the upper surface electrode 32, the back surface electrode 33 can be formed by depositing a film of a material for forming the back surface electrode 33 (e.g., Ti / Pt / Au) using a vacuum deposition apparatus. An example of the film thickness of the back surface electrode 33 is Ti / Pt / Au=150 nm / 300 nm / 1500 nm.

[0113] The thickness of the support substrate 11 can be adjusted by any method, but as an example, the semiconductor laminate 20 side is attached to a back-grinding tape and then ground with a back-grinder. The thickness after grinding is adjusted to within a range of, for example, 50 μm to 250 μm, and is appropriately selected depending on the application of the infrared LED element 1 and the subsequent processes. As a specific example, the thickness of the support substrate 11 after grinding is 150 μm. After the grinding process is completed, the support substrate 11 is peeled off from the tape and washed.

[0114] The thickness of the back surface side of the support substrate 11 may be adjusted as necessary, and is not an essential step.

[0115] (Step S14) Next, the substrate 11 is diced together with the back electrode 33 to form chips. For example, with the back electrode 33 attached with dicing tape, the substrate 11 is diced together with the back electrode 33 from the top electrode 32 side using a diamond blade or the like along the dicing line formed by mesa etching in step S13.

[0116] Thereafter, the infrared LED element 1 formed into a chip is mounted on a stem or the like using a conductive adhesive such as Ag paste. The pad electrode 34 is connected to the post portion of the stem by wire bonding.

[0117] In the infrared LED element 1 having the above configuration, as in the conventional structure, the second cladding layer 27 corresponding to the second semiconductor layer is formed on the active layer 25, so that the band gap energy difference between the active layer and the second semiconductor layer is maintained at the same level as in the conventional structure. Furthermore, the second contact layer 28 constituting the light emitting surface (first surface 28a) is easier to form the uneven portion 40 for improving the light extraction efficiency than InP. Therefore, the infrared LED element 1 is an element in which an uneven shape can be efficiently formed on the light emitting surface (first surface 28a), and the light emission efficiency is unlikely to decrease even when driven with a large current.

[0118] In the above embodiment, the first semiconductor layer (first contact layer 21, first cladding layer 23) is a p-type semiconductor and the second semiconductor layer (second contact layer 28, second cladding layer 27) is an n-type semiconductor, but the conductivity types of the two may be reversed. [Explanation of symbols]

[0119] 1: Infrared LED element 3: Growth substrate 11: Support substrate 13,13a,13b: Metal bonding layer 15 : Reflective layer 17: Insulating layer 20: Semiconductor laminate 21: First contact layer 22: Buffer layer 23: First clad layer 24: ES layer 25: Active layer 27: Second cladding layer 28: Second contact layer 28a: Front page 31 : Internal electrode 32: Top electrode 33: Back electrode 34: Pad electrode 36: Dielectric layer 40: Uneven part L: Infrared light

Claims

1. An infrared LED element capable of emitting infrared light having a peak wavelength of 1,000 nm to 2,000 nm, A conductive supporting substrate; a semiconductor laminate disposed on the support substrate and made of a material that can lattice match InP; The semiconductor laminate is A first semiconductor layer exhibiting a first conductivity type, which is disposed closest to the support substrate; an active layer disposed on the first semiconductor layer; a second semiconductor layer that is disposed on the active layer and exhibits a second conductivity type different from the first conductivity type; The second conductive type Al is disposed on the second semiconductor layer. a G b In c and a third semiconductor layer made of As (0≦a<1, 0<b<1, 0<c<1, a+b+c=1), the third semiconductor layer has an uneven portion on a surface opposite to a surface on which the second semiconductor layer is located, An infrared LED element, wherein the band gap energy of the third semiconductor layer is lower than the band gap energy of the second semiconductor layer and higher than the band gap energy of the active layer.

2. 2. The infrared LED element according to claim 1, wherein the second semiconductor layer is made of InP.

3. 3. The infrared LED element according to claim 1, wherein the third semiconductor layer has a thickness of 1 μm to 5 μm.

4. a first electrode disposed in contact with a portion of an upper surface of the third semiconductor layer; The dopant concentration of the third semiconductor layer is higher than the dopant concentration of the second semiconductor layer and is 5×10 17 / cm 3 3. The infrared LED element according to claim 1, wherein:

5. The dopant concentration of the second semiconductor layer is 5×10 17 / cm 3 That's all. The dopant concentration of the third semiconductor layer is 1×10 18 / cm 3 5. The infrared LED element according to claim 4, wherein

6. a second electrode disposed on a surface of the support substrate opposite to a surface on which the semiconductor laminate is disposed; 5. The infrared LED element according to claim 4, further comprising a reflective layer made of a conductive material, disposed between the support substrate and the semiconductor laminate.

7. 3. The infrared LED element according to claim 1, wherein the band gap energy of the second semiconductor layer is 1.1 times or more as large as the band gap energy of the active layer.

8. 3. The infrared LED element according to claim 1, wherein the surface roughness (Ra) of the uneven portion formed on the surface of the third semiconductor layer is 0.25 to 1.00.

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