Semiconductor device

Abstract

To provide a semiconductor device capable of improving characteristics.SOLUTION: A semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first compound member and a first insulation member. The first semiconductor member contains Alx1Ga1-x1 N (0≤x1<1). The second semiconductor member contains Alx2Ga1-x2 N (0<x2≤1, x1<x2). The first compound member contains Alz1Ga1-z1 N (0<z1≤1, x2<z1). A third region of the first compound member contains crystals. At least a part of a first insulation portion of the first insulation member and at least a part of the first insulation member and a second insulation member are amorphous.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, in semiconductor devices such as transistors, improvements in characteristics are desired. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2011-529639 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of improving characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first compound member, and a first insulating member. The third electrode includes a first electrode portion. The position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction. The first semiconductor member is Al x1 Ga 1-x1It includes N(0≦x1<1). The first semiconductor member includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, a sixth partial region, and a seventh partial region. The direction from the first partial region to the first electrode is along a second direction that intersects the first direction. The direction from the second partial region to the second electrode is along the second direction. The direction from the third partial region to the first electrode portion is along the second direction. The position of the fourth partial region in the first direction is between the position of the first partial region in the first direction and the position of the third partial region in the first direction. The position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction. The position of the sixth partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction. The position of the seventh partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction. The second semiconductor member contains Al x2 Ga 1-x2 It includes N(0<x2≦1, x1<x2). The second semiconductor member includes a first semiconductor part and a second semiconductor part. The direction from the fourth partial region to the first semiconductor part is along the second direction. The direction from the fifth partial region to the second semiconductor part is along the second direction. The first compound member contains Al z1 Ga 1-z1It includes N(0 < z1 ≤ 1, x2 < z1). The first compound member includes a first region, a second region, a third region, a fourth region, and a fifth region. The first region is between the fourth partial region and the first electrode portion in the first direction. The second region is between the first electrode portion and the fifth partial region in the first direction. The third region is between the third partial region and the first electrode portion in the second direction. The fourth region is between the first region and the third region. The fifth region is between the third region and the second region. The third region contains crystals. The first insulating member includes a first insulating portion and a second insulating portion. The first insulating portion is between the fourth partial region and the third region in the first direction. The first insulating portion is between the sixth partial region and the fourth region in the second direction. The second insulating portion is between the third region and the fifth partial region in the first direction. The second insulating portion is between the seventh partial region and the fifth region in the second direction. At least a part of the first insulating portion and at least a part of the second insulating portion are amorphous.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same reference numerals are given to the same elements as those described above with respect to the previously shown figures, and detailed descriptions are appropriately omitted.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 1, a semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor member 10, a second semiconductor member 20, a first compound member 31, and a first insulating member 41. In this example, the semiconductor device 110 includes a substrate 10S and a nitride member 10B.

[0009] A first direction D1 from the first electrode 51 to the second electrode 52 is defined as the X-axis direction. A direction perpendicular to the X-axis direction is defined as the Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is defined as the Y-axis direction.

[0010] The third electrode 53 includes a first electrode portion 53a. The position of the third electrode 53 in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second electrode 52 in the first direction D1.

[0011] The first semiconductor member 10 is made of Al x1 Ga 1-x1 N (0≦x1<1). The composition ratio x1 may be, for example, 0 or more and 0.13 or less. The first semiconductor member 10 may be, for example, GaN. The first semiconductor member 10 does not need to contain impurities that impart electrical conductivity.

[0012] The first semiconductor member 10 includes a first partial region 11, a second partial region 12, a third partial region 13, a fourth partial region 14, a fifth partial region 15, a sixth partial region 16, and a seventh partial region 17. The direction from the first partial region 11 to the first electrode 51 is along a second direction D2 that intersects with the first direction D1. The second direction D2 may be the Z-axis direction.

[0013] The direction from the second partial region 12 to the second electrode 52 is along the second direction D2. The direction from the third partial region 13 to the first electrode portion 53a is along the second direction D2. The position of the fourth partial region 14 in the first direction D1 is between the position of the first partial region 11 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the fifth partial region 15 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the second partial region 12 in the first direction D1. The position of the sixth partial region 16 in the first direction D1 is between the position of the fourth partial region 14 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the seventh partial region 17 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the fifth partial region 15 in the first direction D1.

[0014] The second semiconductor member 20 contains Al x2 Ga 1-x2 N (0 < x2 ≤ 1, x1 < x2). The composition ratio x2 may be, for example, 0.15 or more and 0.35 or less. The second semiconductor member 20 is AlGaN. The second semiconductor member 20 may not contain impurities that impart conductivity.

[0015] The second semiconductor member 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. The direction from the fifth partial region 15 to the second semiconductor portion 22 is along the second direction D2.

[0016] The first compound member 31 contains Al z1 Ga 1-z1 N (0 < z1 ≤ 1, x2 < z1). The composition ratio z1 may be 0.9 or more and 1 or less. The first compound member 31 may be, for example, AlGaN or AlN.

[0017] The first compound member 31 includes a first region 31a, a second region 31b, a third region 31c, a fourth region 31d, and a fifth region 31e. The first region 31a is between the fourth partial region 14 and the first electrode portion 53a in the first direction D1. The second region 31b is between the first electrode portion 53a and the fifth partial region 15 in the first direction D1. The third region 31c is between the third partial region 13 and the first electrode portion 53a in the second direction D2. The fourth region 31d is between the first region 31a and the third region 31c. The fifth region 31e is between the third region 31c and the second region 31b. The third region 31c includes a crystal. At least a portion of the third region 31c includes a crystal. The third region 31c has, for example, polarization.

[0018] The first insulating member 41 includes a first insulating portion 41a and a second insulating portion 41b. The first insulating portion 41a is between the fourth partial region 14 and the third region 31c in the first direction D1. The first insulating portion 41a is between the sixth partial region 16 and the fourth region 31d in the second direction D2. The second insulating portion 41b is between the third region 31c and the fifth partial region 15 in the first direction D1. The second insulating portion 41b is between the seventh partial region 17 and the fifth region 31e in the second direction D2.

[0019] At least a part of the first insulating portion 41a and at least a part of the second insulating portion 41b are amorphous. These portions, for example, have no polarization.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as, for example, a drain electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0021] The first semiconductor member 10 includes a portion facing the second semiconductor member 20. A carrier region 10C is formed in this portion. The carrier region 10C is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0022] In the embodiment, the third region 31c is provided. For example, the third partial region 13 includes a portion facing the third region 31c. The carrier region 10C is formed in this portion. In the third region 31c, the Al composition ratio z1 is high. A high carrier density is obtained. For example, a low on-resistance is obtained.

[0023] In the embodiment, a first insulating portion 41a and a second insulating portion 41b are provided. In the sixth partial region 16 and the seventh partial region 17 corresponding to these regions, the carrier density is low. Or, carriers are not generated. For example, a high threshold voltage is stably obtained. For example, a normally-off operation is obtained. According to the embodiment, a stable high threshold voltage is obtained. According to the embodiment, a semiconductor device capable of improving characteristics can be provided.

[0024] Depending on the voltage applied to the third electrode 53 , carriers can flow through the sixth partial region 16 and the seventh partial region 17 .

[0025] In the semiconductor device 110, two amorphous insulating portions (the first insulating portion 41a and the second insulating portion 41b) are provided. This divides the carrier region 10C at two positions. The threshold voltage can be controlled more stably.

[0026] For example, the first region 31a and the second region 31b include crystals, making it easy to obtain a low on-resistance.

[0027] At least a part of the fourth region 31d and at least a part of the fifth region 31e may be amorphous. For example, crystal distortion is easily alleviated. For example, high crystallinity is easily obtained in the third region 31c, the first region 31a, and the second region 31b.

[0028] The distance (first distance) between the first electrode 51 and the third electrode 53 is shorter than the distance (second distance) between the third electrode 53 and the second electrode 52. Stable operation is easily obtained. The first electrode 51, the second electrode 52, and the third electrode 53 may extend, for example, along the third direction D3. The third direction D3 intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0029] In the embodiment, the first electrode portion 53a is located between the fourth partial region 14 and the fifth partial region 15 in the first direction D1. The third electrode 53 is, for example, a recessed gate electrode. A high threshold voltage can be stably obtained.

[0030] 1, the third electrode 53 may include a second electrode portion 53b. The second electrode portion 53b is connected to the first electrode portion 53a. A portion of the second electrode portion 53b overlaps with the fourth partial region 14 in the second direction D2. Another portion of the second electrode portion 53b overlaps with the fifth partial region 15 in the second direction D2.

[0031] As shown in FIG. 1, the third electrode 53 includes a first electrode region 53F and a second electrode region 53M. At least a portion of the first electrode region 53F is between the first semiconductor member 10 and the second electrode region 53M, and between the second semiconductor member 20 and the second electrode region 53M. The first electrode region 53F includes, for example, nitrogen and a metal element. In one example, the first electrode region 53F includes TiN. The first electrode region 53F is, for example, an intermediate layer. The second electrode region 53M includes, for example, a metal. In one example, the second electrode region 53M includes, for example, aluminum.

[0032] The semiconductor device 110 may further include a second insulating member 42. The second insulating member 42 includes a first insulating region 42a, a second insulating region 42b, and a third insulating region 42c. The first insulating region 42a is between the first region 31a and the first electrode portion 53a in the first direction D1. The second insulating region 42b is between the first electrode portion 53a and the second region 31b in the first direction D1. The third insulating region 42c is provided between the third region 31c and the first electrode portion 53a, between the fourth region 31d and the first electrode portion 53a, and between the fifth region 31e and the first electrode portion 53a. By providing the second insulating member 42, high insulation is obtained. Stable operation is obtained.

[0033] For example, the second insulating member 42 contains silicon and oxygen. The first insulating member 41 contains silicon and nitrogen. The first insulating member 41 does not contain oxygen. Or, the concentration of oxygen in the first insulating member 41 is lower than the concentration of oxygen in the second insulating member 42. The first insulating member 41 contains, for example, SiN. The second insulating member 42 contains silicon oxide. The first insulating member 41 contains, for example, SiO2.

[0034] 1, the first insulating member 41 may further include a third insulating portion 41c and a fourth insulating portion 41d. The first semiconductor portion 21 is between the fourth partial region 14 and the third insulating portion 41c in the second direction D2. The second semiconductor portion 22 is between the fifth partial region 15 and the fourth insulating portion 41d in the second direction D2.

[0035] 1, the second insulating member 42 may further include a fourth insulating region 42d and a fifth insulating region 42e. The third insulating portion 41c is between the first semiconductor portion 21 and the fourth insulating region 42d in the second direction D2. The fourth insulating portion 41d is between the second semiconductor portion 22 and the fifth insulating region 42e in the second direction D2.

[0036] For example, the third region 31c contacts the third partial region 13. The first insulating portion 41a contacts the sixth partial region 16. The second insulating portion 41b contacts the seventh partial region 17. The first insulating portion 41a contacts the fourth partial region 14. The second insulating portion 41b contacts the fifth partial region 15.

[0037] In the semiconductor device 110, a first semiconductor member 10 is provided between a substrate 10S and a second semiconductor member 20. A nitride member 10B is provided between the substrate 10S and the first semiconductor member 10. The substrate 10S may be, for example, a silicon substrate. The nitride member 10B may include, for example, a nitride semiconductor. The nitride member 10B may include, for example, Al, Ga, and nitrogen. The nitride member 10B is, for example, a buffer layer.

[0038] FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 2, the length of the first insulating portion 41a along the first direction D1 is defined as a first insulating portion length w41a. The length of the first insulating portion 41a along the second direction D2 is defined as a first insulating portion thickness t41a. The length of the second insulating portion 41b along the first direction D1 is defined as a second insulating portion length w41b. The length of the second insulating portion 41b along the second direction D2 is defined as a second insulating portion thickness t41b.

[0039] In the embodiment, a first ratio of the first insulating portion length w41a to the first insulating portion thickness t41a is preferably 0.5 to 1.5. A second ratio of the second insulating portion length w41b to the second insulating portion thickness t41b is preferably 0.5 to 1.5. The electric field is effectively controlled at the corner including the first insulating portion 41a or the second insulating portion 41b. For example, the electric field distribution is likely to be uniform at the edge of the bottom of the recess.

[0040] The sum of the first insulating portion length w41a and the first insulating portion thickness t41a is defined as a first sum. The sum of the second insulating portion length w41b and the second insulating portion thickness t41b is defined as a second sum. In the embodiment, the first sum may be different from the second sum. For example, the first sum may be shorter than the second sum. This allows, for example, a lower on-resistance on the side of the first electrode 51 (source electrode).

[0041] In one example, the first insulating portion length w41a is equal to or greater than 5 nm and equal to or less than 200 nm, and the second insulating portion length w41b is equal to or greater than 5 nm and equal to or less than 200 nm.

[0042] The length of the third region 31c along the first direction D1 is defined as the third region length w31c. For example, the third region length w31c may be longer than the first insulating portion length w41a. The third region length w31c may be longer than the second insulating portion length w41b. For example, the ratio of the first insulating portion length w41a to the third region length w31c may be 0.01 or more and less than 0.5. For example, the ratio of the first insulating portion length w41a to the third region length w31c may be 0.3 or less. The ratio of the second insulating portion length w41b to the third region length w31c may be 0.01 or more and less than 0.5. The ratio of the second insulating portion length w41b to the third region length w31c may be 0.3 or less.

[0043] The first insulating portion thickness t41a may be, for example, 5 nm to 700 nm, and the second insulating portion thickness t41b may be, for example, 5 nm to 700 nm.

[0044] As shown in FIG. 2, the length of the first region 31a along the second direction D2 is defined as a first region length L31a. The first region length L31a may be, for example, 150 nm or more. The first region length L31a may be, for example, 500 nm or less. The length of the second region 31b along the second direction D2 is defined as a second region length L31b. The second region length L31b may be, for example, 150 nm or more. The second region length L31b may be, for example, 500 nm or less. For example, a high threshold voltage is easily and stably obtained.

[0045] As shown in FIG. 1, the fourth partial region 14 includes a first portion 14a in contact with the first region 31a and a second portion 14b in contact with the first insulating portion 41a. The first crystallinity of the first portion 14a may be higher than the second crystallinity of the second portion 14b. The fourth partial region 14 further includes a third portion 14c in contact with the fourth region 31d. For example, the third crystallinity of the third portion 14c may be lower than the first crystallinity. Crystal distortion is easily alleviated. For example, high crystallinity is easily obtained in the first portion 14a and the first region 31a. Low on-resistance is easily obtained.

[0046] As shown in FIG. 1, the fifth partial region 15 includes a fourth portion 15d in contact with the second region 31b and a fifth portion 15e in contact with the second insulating portion 41b. The fourth crystallinity of the fourth portion 15d may be higher than the fifth crystallinity of the fifth portion 15e. The fifth partial region 15 further includes a sixth portion 15f in contact with the fifth region 31e. For example, the sixth crystallinity of the sixth portion 15f may be lower than the fourth crystallinity. Crystal distortion is easily alleviated. For example, high crystallinity is easily obtained in the fourth portion 15d and the second region 31b. A low on-resistance is easily obtained.

[0047] In the embodiment, when the gate is off, the resistance is high and the effect of increasing the threshold voltage due to the potential drop is large. When the gate is on, the resistance decreases at both ends of the bottom of the recess. A high threshold is obtained when the gate is off, and a low on-resistance is obtained when the gate is on.

[0048] The above configuration of the semiconductor device 110 can be formed, for example, by the following process. A trench is formed in a structure including a first semiconductor member 10 and a second semiconductor member 20. An insulating film is formed inside the trench. A first insulating portion 41a is obtained from a part of the insulating film. A second insulating portion 41b is obtained from another part of the insulating film. Then, a first compound member 31 and a second insulating member 42 are formed. A first electrode portion 53a of a third electrode 53 is formed in the remaining space of the trench.

[0049] In an embodiment, information regarding the length and thickness is obtained by observation using an electron microscope, etc. Information regarding the composition of the material is obtained by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX), etc.

[0050] The embodiments may include the following technical solutions. (Technical proposal 1) A first electrode; A second electrode; a third electrode including a first electrode portion, the third electrode being located between a position of the first electrode in the first direction from the first electrode to the second electrode and a position of the second electrode in the first direction; Al x1 Ga 1-x1 N (0≦x1<1), the first semiconductor member including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, a sixth partial region, and a seventh partial region, a direction from the first partial region to the first electrode is along a second direction intersecting with the first direction, a direction from the second partial region to the second electrode is along the second direction, a direction from the third partial region to the first electrode portion is along the second direction, and a position of the fourth partial region in the first direction is determined by a position of the first partial region in the first direction and a position of the third partial region in the first direction. the position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction, the position of the sixth partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction, and the position of the seventh partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction; Al x2 Ga 1-x2A second semiconductor member including N(0 < x2 ≤ 1, x1 < x2), wherein the second semiconductor member includes a first semiconductor portion and a second semiconductor portion, the direction from the fourth partial region to the first semiconductor portion is along the second direction, and the direction from the fifth partial region to the second semiconductor portion is along the second direction, the second semiconductor member, Al z1 Ga 1-z1 A first compound member including N(0 < z1 ≤ 1, x2 < z1), wherein the first compound member includes a first region, a second region, a third region, a fourth region, and a fifth region, the first region is between the fourth partial region and the first electrode portion in the first direction, the second region is between the first electrode portion and the fifth partial region in the first direction, the third region is between the third partial region and the first electrode portion in the second direction, the fourth region is between the first region and the third region, the fifth region is between the third region and the second region, and the third region includes a crystal, the first compound member, A first insulating member, wherein the first insulating member includes a first insulating portion and a second insulating portion, the first insulating portion is between the fourth partial region and the third region in the first direction, the first insulating portion is between the sixth partial region and the fourth region in the second direction, the second insulating portion is between the third region and the fifth partial region in the first direction, the second insulating portion is between the seventh partial region and the fifth region in the second direction, and at least a part of the first insulating portion and at least a part of the second insulating portion are amorphous, the first insulating member, A semiconductor device comprising the above.

[0051] (Technical Solution 2) The semiconductor device according to Technical Solution 1, wherein the first region and the second region include a crystal.

[0052] (Technical Solution 3) The semiconductor device according to Technical Solution 2, wherein at least a part of the fourth region and at least a part of the fifth region are amorphous.

[0053] (Technical proposal 4) Further comprising a second insulating member; the second insulating member includes a first insulating region, a second insulating region, and a third insulating region; the first insulating region is between the first region and the first electrode portion in the first direction; the second insulating region is between the first electrode portion and the second region in the first direction, The semiconductor device described in any one of Technical Proposals 1 to 3, wherein the third insulating region is provided between the third region and the first electrode portion, between the fourth region and the first electrode portion, and between the fifth region and the first electrode portion.

[0054] (Technical proposal 5) the second insulating member includes silicon and oxygen; the first insulating member includes silicon and nitrogen; The semiconductor device described in Technical Proposal 4, wherein the first insulating member does not contain oxygen, or the concentration of oxygen in the first insulating member is lower than the concentration of oxygen in the second insulating member.

[0055] (Technical proposal 6) The first insulating member further includes a third insulating portion and a fourth insulating portion, the first semiconductor portion is between the fourth portion region and the third insulating portion in the second direction; The semiconductor device according to Technical Proposal 4 or 5, wherein the second semiconductor portion is between the fifth portion region and the fourth insulating portion in the second direction.

[0056] (Technical proposal 7) The second insulating member further includes a fourth insulating region and a fifth insulating region, the third insulating portion is between the first semiconductor portion and the fourth insulating region in the second direction; A semiconductor device as described in Technical Proposal 6, wherein the fourth insulating portion is between the second semiconductor portion and the fifth insulating region in the second direction.

[0057] (Technical proposal 8) a first region length along the second direction of the first region is 150 nm or more; The semiconductor device according to any one of Technical Solutions 1 to 7, wherein a second region length of the second region along the second direction is 150 nm or more.

[0058] (Technical proposal 9) a first distance between the first electrode and the third electrode is shorter than a second distance between the third electrode and the second electrode; The first sum is shorter than the second sum, the first sum is a sum of a first insulating portion length of the first insulating portion along the first direction and a first insulating portion thickness of the first insulating portion along the second direction, The semiconductor device described in any one of Technical Proposals 1 to 8, wherein the second sum is the sum of a second insulating portion length of the second insulating portion along the first direction and a second insulating portion thickness of the second insulating portion along the second direction.

[0059] (Technical proposal 10) a first ratio of a first insulating portion length along the first direction of the first insulating portion to a first insulating portion thickness along the second direction of the first insulating portion is not less than 0.5 and not more than 1.5; A semiconductor device described in any one of Technical Proposals 1 to 8, wherein a second ratio of a second insulating portion length of the second insulating portion along the first direction to a second insulating portion thickness of the second insulating portion along the second direction is greater than or equal to 0.5 and less than or equal to 1.5.

[0060] (Technical proposal 11) a first insulating portion length along the first direction of the first insulating portion is not less than 5 nm and not more than 200 nm; The semiconductor device according to any one of Technical Solutions 1 to 8, wherein a second insulating portion length of the second insulating portion along the first direction is not less than 5 nm and not more than 200 nm.

[0061] (Technical proposal 12) a ratio of a first insulating portion length of the first insulating portion along the first direction to a third region length of the third region along the first direction is equal to or greater than 0.01 and less than 0.5; The semiconductor device according to any one of Technical Solutions 1 to 8, wherein a ratio of a second insulating portion length along the first direction of the second insulating portion to a third region length is greater than or equal to 0.01 and less than 0.5.

[0062] (Technical proposal 13) a first insulating portion thickness along the second direction of the first insulating portion is not less than 5 nm and not more than 700 nm; The semiconductor device according to any one of Technical Solutions 1 to 8, wherein a second insulating portion thickness of the second insulating portion along the second direction is not less than 5 nm and not more than 700 nm.

[0063] (Technical proposal 14) The semiconductor device according to any one of Technical Solutions 1 to 13, wherein the first electrode portion is located between the fourth partial region and the fifth partial region in the first direction.

[0064] (Technical proposal 15) The third region is in contact with the third partial region, the first insulating portion is in contact with the sixth portion region, The semiconductor device according to any one of Technical Solutions 1 to 14, wherein the second insulating portion is in contact with the seventh portion region.

[0065] (Technical proposal 16) The fourth partial region is a first portion in contact with the first region; a second portion in contact with the first insulating portion; Including, The semiconductor device according to any one of Technical Schemes 1 to 15, wherein the first crystallinity of the first portion is higher than the second crystallinity of the second portion.

[0066] (Technical proposal 17) the fourth region further includes a third portion in contact with the fourth region, The semiconductor device described in Technical Proposal 16, wherein the third crystallinity of the third portion is lower than the first crystallinity.

[0067] (Technical proposal 18) The fifth partial region is a fourth portion in contact with the second region; a fifth portion in contact with the second insulating portion; Including, The semiconductor device according to any one of Technical Schemes 1 to 17, wherein a fourth crystallinity of the fourth portion is higher than a fifth crystallinity of the fifth portion.

[0068] (Technical proposal 19) the fifth region further includes a sixth portion in contact with the fifth region, The semiconductor device described in Technical Proposal 18, wherein the sixth crystallinity of the sixth portion is lower than the fourth crystallinity.

[0069] (Technical proposal 20) 20. The semiconductor device according to any one of Technical Schemes 1 to 19, wherein z1 is 0.9 or more and 1 or less.

[0070] According to the embodiment, it is possible to provide a semiconductor device capable of improving characteristics.

[0071] In the embodiment, the "nitride semiconductor" is B x In y Al z Ga 1-x-y-z It includes all semiconductors with compositions in which the composition ratios x, y, and z in the chemical formula N (0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z≦1) are changed within their respective ranges. In the above chemical formula, the term "nitride semiconductor" also includes those that further contain Group V elements other than N (nitrogen), those that further contain various elements added to control various physical properties such as the conductivity type, and those that further contain various elements that are unintentionally included.

[0072] The above describes the embodiments of the present invention with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element, such as a semiconductor member, an electrode, and an insulating member, included in a semiconductor device are included in the scope of the present invention as long as a person skilled in the art can implement the present invention in the same manner and obtain the same effects by appropriately selecting them from the known range.

[0073] Furthermore, any combination of two or more elements of each of the specific examples, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0074] In addition, all semiconductor devices and manufacturing methods thereof that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor device and manufacturing method thereof described above as the embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0075] In addition, within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0076] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0077] 10, 20: first and second semiconductor members, 10B: nitride member, 10C: carrier region, 10S: substrate, 11-17: first to sixth partial regions, 14a-14c: first to third portions, 15d-15f: fourth to sixth portions, 21, 22: first and second semiconductor portions, 31: first compound member, 31a-31e: first to fifth regions, 41, 42: first and second insulating members, 41a-41d: first to fourth insulating portions, 42a-42e: first to fifth insulating regions, 51-53: first to third electrodes, 53F: first electrode region, 53M: second electrode region, 53a, 53b: first and second electrode portions, 110: semiconductor device, D1-D3: first to third directions, L31a, L31b: 1st and 2nd region length, t41a, t41b: 1st and 2nd insulation thickness, w31c: 3rd region length, w41a, w41b: 1st and 2nd insulation length

Claims

1. A first electrode; A second electrode; a third electrode including a first electrode portion, the third electrode being located between a position of the first electrode in a first direction from the first electrode to the second electrode and a position of the second electrode in the first direction; A ｘ１ G １－ｘ１ N (0≦x1<1), the first semiconductor member including a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, a sixth partial region, and a seventh partial region, a direction from the first partial region to the first electrode is along a second direction intersecting with the first direction, a direction from the second partial region to the second electrode is along the second direction, a direction from the third partial region to the first electrode portion is along the second direction, and a position of the fourth partial region in the first direction is a position of the first partial region in the first direction and a position of the third partial region in the first direction. a position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction, a position of the sixth partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction, and a position of the seventh partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction; A ｘ２ G １－ｘ２ A second semiconductor member including N (0<x2≦1, x1<x2), the second semiconductor member including a first semiconductor portion and a second semiconductor portion, a direction from the fourth partial region to the first semiconductor portion along the second direction, and a direction from the fifth partial region to the second semiconductor portion along the second direction; A ｚ１ G １－ｚ１ N (0<z1≦1, x2<z1), the first compound member including a first region, a second region, a third region, a fourth region, and a fifth region, the first region being between the fourth partial region and the first electrode portion in the first direction, the second region being between the first electrode portion and the fifth partial region in the first direction, the third region being between the third partial region and the first electrode portion in the second direction, the fourth region being between the first region and the third region, the fifth region being between the third region and the second region, and the third region including a crystal; a first insulating member, the first insulating member including a first insulating portion and a second insulating portion, the first insulating portion being between the fourth partial region and the third region in the first direction, the first insulating portion being between the sixth partial region and the fourth region in the second direction, the second insulating portion being between the third partial region and the fifth partial region in the first direction, and the second insulating portion being between the seventh partial region and the fifth region in the second direction, and at least a portion of the first insulating portion and at least a portion of the second insulating portion being amorphous; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first region and the second region include a crystal.

3. The semiconductor device according to claim 2 , wherein at least a part of said fourth region and at least a part of said fifth region are amorphous.

4. Further comprising a second insulating member; the second insulating member includes a first insulating region, a second insulating region, and a third insulating region; the first insulating region is between the first region and the first electrode portion in the first direction; the second insulating region is between the first electrode portion and the second region in the first direction, 2. The semiconductor device according to claim 1, wherein the third insulating region is provided between the third region and the first electrode portion, between the fourth region and the first electrode portion, and between the fifth region and the first electrode portion.

5. the second insulating member includes silicon and oxygen; the first insulating member includes silicon and nitrogen; 5. The semiconductor device according to claim 4, wherein the first insulating member does not contain oxygen, or the concentration of oxygen in the first insulating member is lower than the concentration of oxygen in the second insulating member.

6. The first insulating member further includes a third insulating portion and a fourth insulating portion, the first semiconductor portion is between the fourth portion region and the third insulating portion in the second direction; The semiconductor device according to claim 4 , wherein the second semiconductor portion is between the fifth portion region and the fourth insulating portion in the second direction.

7. The second insulating member further includes a fourth insulating region and a fifth insulating region, the third insulating portion is between the first semiconductor portion and the fourth insulating region in the second direction; The semiconductor device according to claim 6 , wherein the fourth insulating portion is between the second semiconductor portion and the fifth insulating region in the second direction.

8. a first region length along the second direction of the first region is 150 nm or more; The semiconductor device according to claim 1 , wherein a second region length in the second direction of the second region is 150 nm or more.

9. a first distance between the first electrode and the third electrode is less than a second distance between the third electrode and the second electrode; The first sum is shorter than the second sum, the first sum is a sum of a first insulating portion length of the first insulating portion along the first direction and a first insulating portion thickness of the first insulating portion along the second direction, The semiconductor device according to any one of claims 1 to 8, wherein the second sum is a sum of a second insulating portion length of the second insulating portion along the first direction and a second insulating portion thickness of the second insulating portion along the second direction.

10. a first ratio of a first insulating portion length along the first direction of the first insulating portion to a first insulating portion thickness along the second direction of the first insulating portion is greater than or equal to 0.5 and less than or equal to 1.5; The semiconductor device according to any one of claims 1 to 8, wherein a second ratio of a second insulating portion length along the first direction of the second insulating portion to a second insulating portion thickness along the second direction of the second insulating portion is greater than or equal to 0.5 and less than or equal to 1.

5.

11. 9. The semiconductor device according to claim 1, wherein the first electrode portion is located between the fourth partial region and the fifth partial region in the first direction.

12. The third region is in contact with the third partial region, the first insulating portion is in contact with the sixth portion region, 9. The semiconductor device according to claim 1, wherein the second insulating portion is in contact with the seventh region.

13. The fourth partial region is a first portion in contact with the first region; a second portion in contact with the first insulating portion; Including, 9. The semiconductor device according to claim 1, wherein the first crystallinity of the first portion is higher than the second crystallinity of the second portion.

14. the fourth region further includes a third portion in contact with the fourth region, The semiconductor device according to claim 13 , wherein the third crystallinity of the third portion is lower than the first crystallinity.

15. The fifth partial region is a fourth portion in contact with the second region; a fifth portion in contact with the second insulating portion; Including, 9. The semiconductor device according to claim 1, wherein a fourth crystallinity of the fourth portion is higher than a fifth crystallinity of the fifth portion.

16. The fifth region further includes a sixth portion in contact with the fifth region, The semiconductor device according to claim 15 , wherein a sixth crystallinity of the sixth portion is lower than the fourth crystallinity.

17. 9. The semiconductor device according to claim 1, wherein z1 is equal to or greater than 0.9 and equal to or less than 1.

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