Display device and wearable electronic device

Abstract

To provide a display device and a wearable electronic device.SOLUTION: A display device includes: a base layer having a trench formed therein; and a first sub-pixel and a second sub-pixel disposed on either side of the trench. Each of the first sub-pixel and the second sub-pixel includes: a first electrode disposed on the base layer; a first light-emitting structure disposed on the first electrode and emitting light; an intermediate layer disposed on the first light-emitting structure; a second light-emitting structure disposed on the intermediate layer and emitting light; and a second electrode disposed on the second light-emitting structure. The first light-emitting structure includes a first hole transport layer, a first light-emitting layer, and a first electron transport layer. The second light-emitting structure includes a second hole transport layer, a second light-emitting layer, and a second electron transport layer. A thickness of the first hole transport layer is smaller than a depth of the trench, and a thickness of the second hole transport layer is larger than a depth of the trench.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present invention relates to a display device and a wearable electronic device. [Background technology]

[0002] Organic light emitting diode (OLED) is an active light emitting display device that has the advantages of a wide viewing angle, excellent contrast, low voltage operation, lightweight and thin design, and fast response speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 2008-0001185

[0004] One pixel may have a structure in which a plurality of light-emitting layers are stacked, and the plurality of light-emitting layers may be provided commonly and continuously to sub-pixels within the pixel. Summary of the Invention [Problem to be solved by the invention]

[0005] In a super high resolution display device, since the interval between sub-pixels is narrow, leakage current (or lateral leakage phenomenon) may occur between adjacent sub-pixels through a commonly provided light emitting layer, and the sub-pixels may not emit light with a desired luminance, which may result in degradation of display quality.

[0006] An object of the present invention is to provide a display device and a wearable electronic device with improved display quality.

[0007] The object of the present invention is not limited to the above-mentioned object, and other technical objects not mentioned above will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to an embodiment of the present invention includes a base layer having a trench formed therein, and a first sub-pixel and a second sub-pixel disposed on either side of the trench. Each of the first sub-pixel and the second sub-pixel includes a first electrode disposed on the base layer, a first light-emitting structure disposed on the first electrode and emitting light, an intermediate layer disposed on the first light-emitting structure, a second light-emitting structure disposed on the intermediate layer and emitting light, and a second electrode disposed on the second light-emitting structure. The first light-emitting structure includes a first hole transport layer, a first light-emitting layer, and a first electron transport layer, and the second light-emitting structure includes a second hole transport layer, a second light-emitting layer, and a second electron transport layer. A thickness of the first hole transport layer is smaller than a depth of the trench, and a thickness of the second hole transport layer is larger than the depth of the trench.

[0009] The trenches may include a first trench surrounding the first sub-pixel in a plan view and a second trench surrounding the second sub-pixel in a plan view, and the first trench and the second trench may be separated from each other.

[0010] The depth of the trench may be between 2500 Å and 8500 Å, the width of the trench may be between 800 Å and 1700 Å, the thickness of the first hole transport layer may be in the range of between 1200 Å and 1650 Å, and the thickness of the second hole transport layer may be in the range of between 3600 Å and 4400 Å.

[0011] The first hole transport layer and the second hole transport layer may include different materials.

[0012] The glass transition temperature of the second hole transport layer may be 10% to 30% higher than the glass transition temperature of the first hole transport layer.

[0013] The glass transition temperature of the second hole transport layer may be 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

[0014] The second electrode may have a thickness in the range of 100 Å to 190 Å.

[0015] A step of the second electrode on the trench may be 500 Å or less.

[0016] The first light emitting structure may have a thickness less than the depth of the trench, and the second light emitting structure may have a thickness greater than the depth of the trench.

[0017] The thickness of the first light emitting structure may be less than or equal to 70% of the depth of the trench, and the thickness of the second light emitting structure may be more than or equal to 160% of the depth of the trench.

[0018] The depth of the trench may be greater than or equal to 2500 Å and less than or equal to 8500 Å, the width of the trench may be greater than or equal to 800 Å and less than or equal to 1700 Å, the thickness of the first light emitting structure may be in the range of greater than or equal to 1650 Å and less than or equal to 2050 Å, and the thickness of the second light emitting structure may be in the range of greater than or equal to 4500 Å and less than or equal to 5400 Å.

[0019] On the trench, the first light emitting structure and the intermediate layer of the first sub-pixel and the second sub-pixel may be disconnected, and at least a portion of the second light emitting structure of the first sub-pixel and the second sub-pixel may be connected.

[0020] Each of the first and second subpixels may further include a third light emitting structure disposed between the first electrode and the first light emitting structure and emitting light, and a first intermediate layer disposed between the third light emitting structure and the first light emitting structure, and each of the third light emitting structure and the first intermediate layer may be interrupted above the trench.

[0021] The first light emitting structure may emit light of a first color, and the second light emitting structure may emit light of a second color different from the first color.

[0022] The first light emitting structure and the second light emitting structure may emit light of the same color.

[0023] A display device according to an embodiment of the present invention includes a first electrode disposed on a base layer, a first light emitting structure disposed on the first electrode and emitting light, an intermediate layer disposed on the first light emitting structure, a second light emitting structure disposed on the intermediate layer and emitting light, and a second electrode disposed on the second light emitting structure. The first light emitting structure includes a first hole transport layer, a first light emitting layer, and a first electron transport layer, and the second light emitting structure includes a second hole transport layer, a second light emitting layer, and a second electron transport layer. The glass transition temperature of the second hole transport layer is 10% to 30% higher than the glass transition temperature of the first hole transport layer.

[0024] The glass transition temperature of the second hole transport layer may be 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

[0025] A wearable electronic device according to an embodiment of the present invention includes a display panel that emits light, and at least one lens disposed on the display panel. The display panel includes a base layer in which a trench is formed, and a first sub-pixel and a second sub-pixel disposed on either side of the trench. Each of the first sub-pixel and the second sub-pixel includes a first electrode disposed on the base layer, a first light-emitting structure disposed on the first electrode and emitting light, an intermediate layer disposed on the first light-emitting structure, a second light-emitting structure disposed on the intermediate layer and emitting light, and a second electrode disposed on the second light-emitting structure. The first light-emitting structure includes a first hole transport layer, a first light-emitting layer, and a first electron transport layer. The second light-emitting structure includes a second hole transport layer, a second light-emitting layer, and a second electron transport layer. A thickness of the first hole transport layer is smaller than a depth of the trench, and a thickness of the second hole transport layer is larger than the depth of the trench.

[0026] The glass transition temperature of the second hole transport layer may be 10% to 30% higher than the glass transition temperature of the first hole transport layer.

[0027] The glass transition temperature of the second hole transport layer may be 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

[0028] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0029] In the display device and wearable electronic device according to the embodiment of the present invention, each of the sub-pixels includes a first light emitting structure, an intermediate layer, and a second light emitting structure, which are sequentially stacked between a first electrode and a second electrode, and the first light emitting structure and the intermediate layer are disconnected in the boundary region of the sub-pixel, but the second light emitting structure and the cathode electrode may be continuous. Since the intermediate layer is disconnected in the boundary region, leakage current between the sub-pixels through the intermediate layer is reduced, and the sub-pixels can emit light with a desired brightness.

[0030] Moreover, in the boundary region, the second light emitting structure and the cathode electrode are continuous, so that the sub-pixel can be driven normally.

[0031] The effects of the embodiments are not limited to the above examples, and various other effects may be included in the present specification. [Brief description of the drawings]

[0032] [Figure 1] 1 is a block diagram showing a display device according to an embodiment. [Diagram 2] 2 is a block diagram showing an embodiment of a subpixel included in the display device of FIG. 1. [Diagram 3] FIG. 3 is a circuit diagram illustrating an embodiment of the subpixel of FIG. 2. [Figure 4] FIG. 2 is a plan view showing an embodiment of the display device of FIG. [Diagram 5] FIG. 5 is an exploded perspective view showing one embodiment of the display device of FIG. [Figure 6a]6 is a plan view illustrating an embodiment of a pixel included in the display device of FIG. 5. [Figure 6b] 6 is a plan view illustrating an embodiment of a pixel included in the display device of FIG. 5. [Figure 6c] 6 is a plan view illustrating an embodiment of a pixel included in the display device of FIG. 5. [Figure 7] FIG. 6b is a cross-sectional view showing an embodiment of the display device taken along line II' in FIG. 6a. [Figure 8] 8 is an enlarged cross-sectional view of a portion of the display device of FIG. 7. [Figure 9] 8 is a cross-sectional view illustrating an embodiment of a light-emitting layer included in the display device of FIG. 7. [Figure 10] 9 is an image showing one embodiment of the display device of FIG. 8. [Figure 11] FIG. 6b is a cross-sectional view showing another embodiment of the display device taken along line II' in FIG. 6a. [Figure 12] 12 is an enlarged cross-sectional view of a portion of the display device of FIG. 11. [Figure 13] 12 is a cross-sectional view illustrating an embodiment of a light-emitting layer included in the display device of FIG. [Figure 14] 6 is a plan view illustrating an embodiment of a pixel included in the display device of FIG. 5. [Figure 15] 15 is a cross-sectional view showing an embodiment of a display device taken along line II-II' in FIG. 14. [Figure 16] 15 is a cross-sectional view showing an embodiment of a display device taken along line II-II' in FIG. 14. [Figure 17] 17 is an enlarged cross-sectional view of a portion of the display device of FIG. 16. [Figure 18] FIG. 1 is a block diagram illustrating an embodiment of a display system. [Figure 19] FIG. 19 is a perspective view showing an application example of the display system of FIG. [Figure 20] FIG. 20 is a diagram showing a head-mounted display device worn by the user of FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Please note that in the following description, only parts necessary for understanding the operation of the present invention will be described, and descriptions of other parts will be omitted so as not to make the gist of the present invention unclear. In addition, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. However, the embodiments described herein are provided in detail to the extent that those skilled in the art to which the present invention pertains can easily implement the technical ideas of the present invention.

[0034] Throughout this specification, a part being "connected" to another part includes not only the case of being "directly connected" to another part, but also the case of being "indirectly connected" to another part through another element therebetween. The terms used herein are for describing a particular embodiment, and are not intended to limit the present invention. Throughout this specification, a part "comprises" a certain component, unless otherwise specified to the contrary, means that it can further include the other component, not excluding the other component. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the corresponding configurations.

[0035] Here, the terms "first", "second", etc. may be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another. Thus, the first component can refer to the second component within a range that does not deviate from the contents disclosed herein.

[0036] Spatially relative terms such as "below," "above," and the like may be used for purposes of description, thereby describing the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to include different orientations during use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if a device shown in the figures were turned upside down, an element depicted as being "below" another element or feature would be in an orientation "above" the other element or feature. Thus, in one embodiment, "below" can include both an orientation of above and below. Additionally, a device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted accordingly.

[0037] Some embodiments are described in the accompanying drawings with reference to functional blocks, units, and / or modules. Those skilled in the art will appreciate that such blocks, units, and / or modules may be physically embodied by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits, which may be formed using semiconductor-based fabrication techniques or other fabrication techniques. In the case of blocks, units, and / or modules embodied by microprocessors or other similar hardware, they may be programmed and controlled using software to perform various functions discussed in the present invention, and may be selectively driven by firmware and / or software. Also, each block, unit, and / or module may be embodied by dedicated hardware, or a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing different functions. Also, in some embodiments, the blocks, units, and / or modules may be physically separated into two or more separate blocks, units, and / or modules that interact with each other without departing from the concept of the present invention. Moreover, in some embodiments, the blocks, units and / or modules may be combined into more physically complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0038] Various embodiments are described with reference to drawings that illustrate idealized embodiments. As such, it is to be expected that the shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as limited to the particular shapes shown, but should be construed to include, for example, variations in shapes that result from manufacturing. As such, the drawings may not depict the actual shape of a region of a device, and the embodiments are not limited thereto.

[0039] FIG. 1 is a block diagram showing a display device according to an embodiment.

[0040] Referring to FIG. 1, a display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0041] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to a gate driver 120 via first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to a data driver 130 via first to n-th data lines DL1 to DLn.

[0042] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. For example, the light-emitting element may be an organic light-emitting diode in a tandem structure. This allows each of the sub-pixels SP to generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP may form one pixel PXL capable of expressing full colors. For example, three sub-pixels may form one pixel PXL as shown in FIG. 1.

[0043] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction via the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In the embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing at which a data signal is applied, and the like.

[0044] In one embodiment, the display panel 110 may further include first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction. In this case, the gate driver 120 can output emission control signals to the first to m-th emission control lines EL1 to ELm in the same manner as the gate signals. For example, the gate driver 120 may include a emission control driver that outputs emission control signals.

[0045] The gate driver 120 may be disposed on one side of the display panel 110, but the embodiment is not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically divided, and the drivers may be disposed on one side of the display panel 110 and the other side of the display panel 110 opposite to the one side. In this manner, the gate driver 120 may be disposed around the display panel 110 in various forms according to the embodiment.

[0046] The data driver 130 may be connected to the sub-pixels SP arranged in a column direction via the first to n-th data lines DL1 to DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0047] The data driver 130 can apply data signals having gray scale voltages corresponding to the video data DATA to the first to n-th data lines DL1 to DLn using the voltage from the voltage generator 140. When gate signals are applied to the first to m-th gate lines GL1 to GLm, respectively, the data signals corresponding to the video data DATA can be applied to the data lines DL1 to DLm. This allows the corresponding sub-pixels SP to generate light corresponding to the data signals. This allows an image to be displayed on the display panel 110.

[0048] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0049] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 may be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and generate a plurality of voltages by regulating the adjusted voltage.

[0050] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS may be provided to the sub-pixels SP. The second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0051] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the sub-pixel SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such a reference voltage.

[0052] The controller 150 can control various operations of the display device 100. The controller 150 can receive input image data IMG from the outside and a control signal CTRL for controlling the display of the input image data IMG. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0053] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, and output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG to be suitable for the row-based sub-pixels SP, and output the image data DATA.

[0054] Two or more of the data driver 130, the voltage generator 140, and the controller 150 may be implemented in one integrated circuit. As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a separate component from the driver integrated circuit DIC.

[0055] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature in its surroundings and generate temperature data TEP indicative of the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0056] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In one embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signals and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0057] Fig. 2 is a block diagram illustrating an embodiment of a sub-pixel included in the display device of Fig. 1. Fig. 2 exemplarily illustrates a sub-pixel SPij arranged in an i-th row (i is an integer of 1 or more and m or less) and a j-th column (j is an integer of 1 or more and n or less).

[0058] Referring to FIG. 2, the sub-pixel SPij may include a sub-pixel circuit SPC (or pixel circuit) and a light-emitting element LD.

[0059] The light emitting element LD may be connected between a first power supply voltage node VDDN (or a first power supply line) and a second power supply voltage node VSSN (or a second power supply line). In this case, the first power supply voltage node VDDN is a node that transmits the first power supply voltage VDD in FIG. 1, and the second power supply voltage node VSSN is a node that transmits the second power supply voltage VSS in FIG. 1.

[0060] The anode electrode AE ​​of the light emitting element LD may be connected to a first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to a second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0061] The subpixel circuit SPC is connected to the ith gate line GLi among the gate lines GL1 to GLm in FIG. 1, the ith light-emitting control line ELi among the light-emitting control lines EL1 to ELm in FIG. 1, and the jth data line DLj among the data lines DL1 to DLn in FIG. 1, and can control the light-emitting element LD to generate light in response to signals received via these signal lines.

[0062] The i-th gate line GLi may include one or more sub-gate lines (or scan lines). In an embodiment, as shown in FIG. 2, the i-th gate line GLi may include first and second sub-gate lines SGL1, SGL2. The sub-pixel circuit SPC may operate in response to a gate signal (or scan signal) received via the first and second sub-gate lines SGL1, SGL2 (or the first and second scan lines).

[0063] The sub-pixel circuit SPC may receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first and second sub-gate lines SGL1 and SGL2. Thus, the light emitting element LD may generate light having a brightness corresponding to the data signal.

[0064] In one embodiment, the sub-pixel SPij may be further connected to an i-th emission control line ELi. The sub-pixel circuit SPC may operate in response to an emission control signal received via the i-th emission control line ELi. For example, the sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN through the light emitting element LD to the second power supply voltage node VSSN according to the stored voltage in response to the emission control signal received via the i-th emission control line ELi.

[0065] According to an embodiment, the i-th light-emitting control line ELi may include one or more sub-light-emitting control lines. When the i-th light-emitting control line ELi includes two or more sub-light-emitting control lines, the sub-pixel circuit SPC can operate in response to a light-emitting control signal received through the corresponding sub-light-emitting control line.

[0066] FIG. 3 is a circuit diagram illustrating one embodiment of the subpixel of FIG.

[0067] Referring to FIG. 3, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0068] The sub-pixel circuit SPC may be connected to the ith gate line GLi', the ith light-emitting control line ELi', and the jth data line DLj. Compared with the ith gate line GLi of FIG. 2, the ith gate line GLi' may further include a third sub-gate line SGL3 (or a third scan line). Compared with the ith light-emitting control line ELi of FIG. 2, the ith light-emitting control line ELi' may include a first sub-light-emitting control line SEL1 and a second sub-light-emitting control line SEL2.

[0069] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6, and first and second capacitors C1 and C2.

[0070] The first transistor T1 may be connected between a first power supply voltage node VDDN and a first node N1. The gate (or gate electrode) of the first transistor T1 is connected to a second node N2, so that the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0071] The second transistor T2 may be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 is connected to the first sub-gate line SGL1, so that the second transistor T2 can be turned on in response to a gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0072] The third transistor T3 may be connected between the first node N1 and the second node N2. The gate of the third transistor T3 is connected to the second sub-gate line SGL2, so that the third transistor T3 can be turned on in response to a gate signal of the second sub-gate line SGL2.

[0073] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. The gate of the fourth transistor T4 is connected to the second sub-emission control line SEL2, so that the fourth transistor T4 can be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0074] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and an initialization voltage node VINTN (or initialization voltage line). The initialization voltage node VINTN may be configured to transmit an initialization voltage. In one embodiment, the initialization voltage may be provided by the voltage generator 140 of FIG. 1. In another embodiment, the initialization voltage may be provided by a device external to the display device 100. The gate of the fifth transistor T5 is connected to the third sub-gate line SGL3, such that the fifth transistor T5 may be turned on in response to a gate signal of the third sub-gate line SGL3.

[0075] The sixth transistor T6 may be connected between the first power supply voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 is connected to the first sub-emission control line SEL1, so that the sixth transistor T6 can be turned on in response to the emission control signal of the first sub-emission control line SEL1.

[0076] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power supply voltage node VDDN and the second node N2.

[0077] As described above, the sub-pixel circuit SPC may include the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2, but the embodiment is not limited thereto. The sub-pixel circuit SPC may be implemented as any one of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. The number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may vary depending on the embodiment of the sub-pixel circuit SPC.

[0078] The first to sixth transistors T1 to T6 may be P-type transistors. Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal Oxide Silicon Field Effect Transistor), but the embodiment is not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 may be replaced with an N-type transistor.

[0079] In the embodiment, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a polycrystalline silicon semiconductor, a single crystal silicon semiconductor, an oxide semiconductor, or the like.

[0080] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting layer. The light emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. The first transistor T1 is turned on in response to the voltage of the second node N2, and the fourth and sixth transistors T4 and T6 are turned on in response to a light emitting control signal (e.g., a turn-on voltage level, a low level) applied to the first and second sub light emitting control lines SEL1 and SEL2, so that a current can flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD can emit light in response to the amount of current flowing.

[0081] Fig. 4 is a plan view showing an embodiment of the display device of Fig. 1. Fig. 4 exemplarily shows a display panel DP constituting the display device.

[0082] 4, the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0083] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0084] When the display panel DP is used as a display screen for a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to a user's eyes. In this case, a relatively high integration density of sub-pixels SP may be required. In order to increase the integration density of the sub-pixels SP, a silicon substrate may be provided as the substrate SUB. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB, which is a silicon substrate. A display device 100 (see FIG. 1) including a display panel DP formed on the substrate SUB, which is a silicon substrate, may be referred to as an OLEDoS (OLED on Silicon) display device.

[0085] The sub-pixels SP may be disposed in a display area DA on a substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a PENTILETM shape. The first direction DR1 may be the row direction, and the second direction DR2 may be the column direction.

[0086] As described with reference to FIG. 1, two or more sub-pixels among the plurality of sub-pixels SP can form one pixel PXL.

[0087] Components for controlling the sub-pixels SP may be arranged in the non-display area NDA on the substrate SUB. For example, wirings connected to the sub-pixels SP, such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn in FIG. 1, may be arranged in the non-display area NDA.

[0088] 1 may be implemented in the display panel DP and disposed in the non-display area NDA, or in another embodiment, the gate driver 120 may be embodied as an integrated circuit separate from the display panel DP.

[0089] Pads PD may be disposed in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP via wiring. For example, the pads PD may be connected to the sub-pixels SP via the first to n-th data lines DL1 to DLn.

[0090] The pad PD can interface the display panel DP with other components of the display device 100 (see FIG. 1). In an embodiment, voltages and signals required for operation of the components included in the display panel DP may be provided from the driver integrated circuit DIC of FIG. 1 via the pad PD. For example, the first to n-th data lines DL1 to DLn may be connected to the driver integrated circuit DIC via the pad PD. For example, the first and second power supply voltages VDD and VSS may be received from the driver integrated circuit DIC via the pad PD. When the gate driver 120 is implemented in the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pad PD.

[0091] In an embodiment, the circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. Here, the circuit board may be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board and electrically connected to the pads PD.

[0092] In the embodiment, the display area DA can have various shapes. The display area DA may be a closed loop with straight and / or curved sides. For example, the display area DA may be a polygon, a circle, a semicircle, an ellipse, etc.

[0093] In an embodiment, the display panel DP may have a flat display surface. In another embodiment, the display panel DP may have an at least partially round display surface. In an embodiment, the display panel DP may be bendable, foldable or rollable. In this case, the display panel DP and / or the substrate SUB may comprise a material having flexible properties.

[0094] Figure 5 is an exploded perspective view showing one embodiment of the display device of Figure 4. For clarity and conciseness of explanation, Figure 5 shows only a schematic representation of the portions of the display panel DP corresponding to two pixels PXL1, PXL2 of the pixels PXL of Figure 4. The portions of the display panel DP corresponding to the remaining pixels may be similarly configured.

[0095] 4 and 5, each of the first and second pixels PXL1 and PXL2 may include first, second, and third sub-pixels SP1, SP2, and SP3, but the embodiment is not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0096] 5, the first to third sub-pixels SP1 to SP3 are shown to have a rectangular shape and the same size when viewed in a third direction DR3 intersecting the first and second directions DR1 and DR2, but the embodiment is not limited thereto. Each of the first to third sub-pixels SP1 to SP3 may be modified to have various shapes.

[0097] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a sealing layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0098] In an embodiment, the substrate SUB may comprise a silicon wafer substrate formed using a semiconductor process. The substrate SUB may comprise a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may comprise silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like. In another embodiment, the substrate SUB may comprise a glass substrate. In yet another embodiment, the substrate SUB may comprise a polyimide (PI) substrate.

[0099] A pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layer. For example, the conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, a wiring, etc. The conductive pattern may include copper, although the embodiment is not limited thereto.

[0100] The pixel circuit layer PCL may include sub-pixel circuits SPC (see FIG. 2) of the first to third sub-pixels SP1 to SP3. That is, the pixel circuit layer PCL may include a transistor and a capacitor as a circuit element. Each transistor may include a semiconductor pattern including a source and drain region and a channel region, a gate electrode superimposed on the semiconductor pattern, and a source and drain electrode connected to the source and drain region. In the embodiment, when a silicon substrate is provided as the substrate SUB, the semiconductor pattern may be provided in the substrate SUB, and the gate electrode and the source and drain electrodes may be provided in the pixel circuit layer PCL. In the embodiment, when a glass substrate or a PI substrate is provided as the substrate SUB, the semiconductor pattern, the gate electrode, and the source and drain electrodes may be provided in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes spaced apart from each other in the third direction DR3 with an insulating layer sandwiched therebetween.

[0101] The pixel circuit layer PCL may include signal lines connected to the first to third sub-pixels SP1 to SP3, respectively. For example, the pixel circuit layer PCL may include gate lines, light emission control lines, data lines, etc. as wirings. The wirings may further include a wiring connected to the first power supply voltage node VDDN in FIG. 2. The wirings may further include a wiring connected to the second power supply voltage node VSSN in FIG. 2.

[0102] The light emitting element layer LDL may include an anode electrode AE, a light emitting structure EU, a cathode electrode CE, and a pixel defining layer PDL.

[0103] The anode electrode AE ​​(or the first electrode) may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may contact a circuit element (e.g., the fourth transistor T4 in FIG. 3) of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material that can reflect light, but the embodiment is not limited thereto.

[0104] A pixel defining film PDL may be disposed on the anode electrode AE. The pixel defining film PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining film PDL may be understood as a light emitting region corresponding to each of the first to third sub-pixels SP1 to SP3.

[0105] In an embodiment, the pixel-defining membrane PDL may include an inorganic material. In this case, the pixel-defining membrane PDL may include a plurality of stacked inorganic layers. For example, the pixel-defining membrane PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x In other embodiments, the pixel defining membrane PDL may include an organic material, although the material of the pixel defining membrane PDL is not limited thereto.

[0106] The light emitting structure EU may be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel defining film PDL. The light emitting structure EU may include an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and a light emitting layer in which holes and electrons combine to form excitons and generate light.

[0107] In the embodiment, the light emitting structure EU fills the opening OP of the pixel defining film PDL, but may be entirely disposed on the upper part of the pixel defining film PDL. That is, the light emitting structure EU may extend across the first to third sub-pixels SP1 to SP3. In this case, a part of a layer in the light emitting structure EU may be cut or bent at the boundary between the first to third sub-pixels SP1 to SP3. However, the embodiment is not limited thereto. For example, the parts of the light emitting structure EU corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of them may be disposed within the opening OP of the pixel defining film PDL.

[0108] The cathode electrode CE may be disposed on the light emitting structure EU. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. In this manner, the cathode electrode CE may be provided as a common electrode for the first to third sub-pixels SP1 to SP3.

[0109] The cathode electrode CE may be a thin metal layer having a sufficient thickness to transmit light emitted from the light emitting structure EU. The cathode electrode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of a transparent conductive material. In an embodiment, the cathode electrode CE may include at least one of a variety of transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. However, the material of the cathode electrode CE is not limited thereto.

[0110] Any one of the anode electrodes AE, a portion of the light emitting structure EU overlapping therewith, and a portion of the cathode electrode CE overlapping therewith can be understood as constituting one light emitting element LD (see FIG. 2). That is, each of the light emitting elements of the first to third sub-pixels SP1 to SP3 can include one anode electrode, a portion of the light emitting structure EU overlapping therewith, and a portion of the cathode electrode CE overlapping therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported into the light emitting structure EU to form excitons, and when the excitons transition from an excited state to a ground state, light can be generated. The luminance of the light can be determined according to the amount of current flowing through the light emitting structure EU. The wavelength range of the generated light can be determined according to the configuration of the light emitting structure EU.

[0111] An encapsulation layer TFE may be disposed on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film may be silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y For example, the organic film may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimides resin, an unsaturated polyesters resin, a polyphenylenes resin, a polyphenylenesulfides resin, or benzocyclobutene (BCB). However, the materials of the organic film and the inorganic film of the sealing layer TFE are not limited thereto.

[0112] In order to improve the sealing efficiency of the sealing layer TFE, the sealing layer TFE is made of aluminum oxide (AlO x The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0113] The optical functional layer OFL is disposed on the encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA.

[0114] The color filter layer CFL may be disposed between the sealing layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EU to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL includes color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of the color filters CF can pass light of a wavelength range corresponding to the corresponding sub-pixel. For example, the color filter CF corresponding to the first sub-pixel SP1 can pass red light, the color filter CF corresponding to the second sub-pixel SP2 can pass green light, and the color filter CF corresponding to the third sub-pixel SP3 can pass blue light. At least a part of the color filters CF may be omitted in accordance with the light emitted from the light emitting structure EU in each sub-pixel.

[0115] The lens array LA may be disposed on the color filter layer CFL (or the encapsulation layer TFE). The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS can improve light output efficiency by outputting light emitted from the light emitting structure EU to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index of 1.5 or more and 1.7 or less. However, the refractive index of the lens array LA is not limited thereto, and the refractive index of the lens array LA may be changed depending on the design of a system to which the display device is applied. In an embodiment, the lens LS may include an organic material.

[0116] In the embodiment, at least a part of the color filters CF of the color filter layer CFL and at least a part of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first and second directions DR1 and DR2, compared with the apertures OP of the pixel definition film PDL. For example, in a central region of the display area DA, the apertures OP of the pixel definition film PDL may completely overlap with the color filters CF of the color filter layer CFL and the lenses LS of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, the apertures OP of the pixel definition film PDL may partially overlap with the color filters CF of the color filter layer CFL and the lenses LS of the lens array LA. As a result, in the center of the display area DA, the light emitted from the light emitting structure EU can be efficiently output in a normal direction to the display surface, and in the outer periphery of the display area DA, the light emitted from the light emitting structure EU can be efficiently output in a direction inclined by a predetermined angle with respect to the normal direction to the display surface.

[0117] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EU, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the layers below it from foreign substances such as dust and moisture. For example, the overcoat layer OC may include an organic insulating film. For example, the overcoat layer OC may include epoxy, but the embodiment is not limited thereto. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0118] A cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect the layers underneath. The cover window CW may have a higher refractive index than the overcoat layer OC. The cover window CW may include glass, although embodiments are not limited thereto. For example, the cover window CW may be an encapsulation glass configured to protect the components disposed underneath it. In other embodiments, the cover window CW may be omitted.

[0119] Figures 6a, 6b and 6c are plan views illustrating an embodiment of a pixel included in the display device of Figure 5. Figure 6a illustrates a schematic diagram of a first pixel PXL1 of Figure 5 for clarity and simplicity of explanation. The remaining pixels may be configured similarly to the first pixel PXL1.

[0120] First, referring to FIGS. 4, 5, and 6a, the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0121] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA around the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA around the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA around the third light-emitting region EMA3.

[0122] The first light-emitting region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EU (see FIG. 5) corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EU corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EU corresponding to the third sub-pixel SP3. As described with reference to FIG. 5, each light-emitting region can be understood as an opening OP in the pixel defining film PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0123] In the embodiment, trenches TRCH1 to TRCH3 may be disposed between adjacent subpixels among the first to third subpixels SP1 to SP3. The trenches TRCH1 to TRCH3 may be recessed or formed by penetrating a base layer (e.g., an upper surface of the pixel definition film PDL) for disposing the light emitting structure EU of FIG. 5. For example, in a plan view, the first trench TRCH1 may be disposed along an edge of the first subpixel SP1 so as to surround the first subpixel SP1, and may have a closed loop shape corresponding to the planar shape of the first subpixel SP1. As with the first trench TRCH1, in a plan view, the second trench TRCH2 may be disposed along an edge of the second subpixel SP2 so as to surround the second subpixel SP2, and the third trench TRCH3 may be disposed along an edge of the third subpixel SP3 so as to surround the third subpixel SP3. In this case, the first trench TRCH1 and the second trench TRCH2 may be arranged in the boundary region (or non-emitting area NEA) between the first subpixel SP1 and the second subpixel SP2, and the second trench TRCH2 and the third trench TRCH3 may be arranged in the boundary region between the second subpixel SP2 and the third subpixel SP3.

[0124] The trenches TRCH1 to TRCH3 may be separated and independent from each other. In this case, each of the trenches TRCH1 to TRCH3 has a uniform width along the extension direction, and as will be described later, the cathode electrodes on the upper parts of the trenches TRCH1 to TRCH3 remain connected without being cut, allowing the first to third sub-pixels SP1 to SP3 to operate or emit light normally.

[0125] Meanwhile, in FIG. 6a, the first to third sub-pixels SP1 to SP3 are arranged along the first direction DR1 and have a rectangular planar shape, but this is not limiting.

[0126] Referring to FIG. 6b, the first pixel PXL1' may include first, second, and third subpixels SP1', SP2', and SP3', where the first subpixel SP1' and the second subpixel SP2' are arranged in the second direction DR2, and the third subpixel SP3' may be disposed in the first direction DR1 relative to each of the first and second subpixels SP1', SP2'.

[0127] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Thus, the second light-emitting region EMA2' may have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' may have a larger area than the second light-emitting region EMA2'. However, the embodiment is not limited thereto. For example, the first and second sub-pixels SP1', SP2' may have substantially the same area, and the third sub-pixel SP3' may have a larger area than the first and second sub-pixels SP1', SP2'. As such, the areas of the first to third sub-pixels SP1' to SP3' may vary variously according to the embodiment.

[0128] Referring to FIG. 6c, the first pixel PXL1″ may include first, second, and third sub-pixels SP1″, SP2″, and SP3″. Each of the first to third sub-pixels SP1″ to SP3″ may have a polygonal shape when viewed from the third direction DR3. For example, as shown in FIG. 11, each of the first to third sub-pixels SP1″ to SP3″ may have a hexagonal shape.

[0129] The first to third light emitting regions EMA1'' to EMA3'' of the first to third sub-pixels SP1'' to SP3'' may be circular when viewed from the third direction DR3. However, the embodiment is not limited thereto. For example, each of the first to third light emitting regions EMA1'' to EMA3'' may be polygonal.

[0130] The first and third sub-pixels SP1'', SP3'' may be arranged in the first direction DR1. The second sub-pixel SP2'' may be arranged in a direction inclined at an acute angle (or diagonally) with respect to the first sub-pixel SP1'' with respect to the second direction DR2.

[0131] The arrangements of the sub-pixels shown in Figures 6a, 6b, and 6c are exemplary and are not limiting embodiments, each pixel includes two or more sub-pixels, the sub-pixels can be arranged in various ways, each of the sub-pixels can have various shapes, and each of its light-emitting areas can also have various shapes.

[0132] FIG. 7 is a cross-sectional view showing an embodiment of the display device taken along line II' in FIG. 6a.

[0133] Referring to FIG. 7, a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB may be provided.

[0134] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0135] A pixel circuit layer PCL may be disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be any one of the transistors included in the sub-pixel circuit SPC of the first sub-pixel SP1 (see FIG. 2), the transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In FIG. 7, for clarity and conciseness, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0136] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0137] The source region SRA and the drain region DRA may be disposed in a substrate SUB. A well WL formed through an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed in the well WL so as to be spaced apart from each other. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0138] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be disposed in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0139] The layers included in the pixel circuit layer PCL include conductive patterns disposed between insulating layers, and the conductive patterns may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection part DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection part SRC that penetrates one or more insulating layers.

[0140] The gate electrode GE and the first and second conductive patterns CP1, CP2 are connected to other circuit elements and / or wirings, so that the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of the transistors of the first sub-pixel SP1.

[0141] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may each be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0142] In this manner, the substrate SUB and the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3.

[0143] A via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and can have an overall flat surface. The via layer VIAL may be configured to flatten steps on the pixel circuit layer PCL. The via layer VIAL may be formed of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbon nitride (SiCN), but embodiments are not limited thereto.

[0144] The light emitting element layer LDL may be disposed on the via layer VIAL. The light emitting element layer LDL may include first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, first to third anode electrodes AE1 to AE3, a pixel defining film PDL, a light emitting structure EU, and a cathode electrode CE.

[0145] On the via layer VIAL, first to third reflective electrodes RE1 to RE3 may be disposed for the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 can be in contact with a circuit element of the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0146] The first to third reflective electrodes RE1 to RE3 can function as full mirrors that reflect light emitted from the light emitting structure EU toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom, but the embodiment is not limited thereto.

[0147] In an embodiment, a buffer electrode may be disposed under each of the first to third reflective electrodes RE1 to RE3. The buffer electrode may improve electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The buffer electrode may have a multi-layer structure. The multi-layer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, a corresponding reflective electrode may be located between multiple layers of the buffer electrodes.

[0148] A buffer pattern BFP may be disposed on at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. By disposing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0149] The first to third reflective electrodes RE1 to RE3 can function as full mirrors, and the cathode electrode CE can function as a half mirror. The light emitted from the light-emitting structure EU can be amplified by at least partially traveling back and forth between the corresponding reflective electrode and the cathode electrode CE, and the amplified light can be output via the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE can be understood as a resonance distance for the light emitted from the light-emitting structure EU.

[0150] The first sub-pixel SP1 may have a shorter resonance distance than the other sub-pixels due to the buffer pattern BFP. The adjusted resonance distance may effectively and efficiently amplify light in a specific wavelength range (e.g., red). Therefore, the first sub-pixel SP1 may effectively and efficiently output light in a corresponding wavelength range.

[0151] 7 shows that the buffer pattern BFP is provided in the first sub-pixel SP1, but not in the second and third sub-pixels SP2 and SP3, but the embodiment is not limited thereto. At least one of the second and third sub-pixels SP2 and SP3 may also be provided with a buffer pattern to adjust the resonance distance of at least one of the second and third sub-pixels SP2 and SP3. For example, the first to third sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0152] A planarization layer PLNL (or a base layer) may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may planarize steps between the first to third reflective electrodes RE1 to RE3 and provide a base surface for the light emitting structure EU. The planarization layer PLNL generally covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL, and may have a flat surface. The planarization layer PLNL may include an organic material. Depending on the embodiment, the planarization layer PLNL may be omitted.

[0153] On the planarization layer PLNL, the first to third anode electrodes AE1 to AE3 (or the first electrodes) may be arranged so as to overlap the first to third reflective electrodes RE1 to RE3, respectively. The first to third anode electrodes AE1 to AE3 may have shapes similar to the light-emitting regions EMA1 to EMA3 of the first to third sub-pixels SP1 to SP3 in FIG. 6a to FIG. 6c, as viewed from the third direction DR3. The first to third anode electrodes AE1 to AE3 may be in direct contact with the light-emitting structure EU (or a semiconductor layer thereof) and may form an energy barrier at the interface. The first to third anode electrodes AE1 to AE3 may be connected to the first to third reflective electrodes RE1 to RE3, respectively. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the planarizing layer PLNL.

[0154] In the embodiment, the first to third anode electrodes AE1 to AE3 are each made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x The first to third anode electrodes AE1 to AE3 may include at least one of transparent conductive materials such as titanium nitride, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0155] In the embodiment, an insulating layer for adjusting the height of one or more of the first to third anode electrodes AE1 to AE3 may be further provided. The insulating layer may be disposed between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding reflective electrode. In this case, the planarizing layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third sub-pixels SP1 to SP3 correspond to red, green, and blue, respectively, and the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0156] A pixel defining film PDL may be disposed on portions of the first to third anode electrodes AE1 to AE3 and the planarizing layer PLNL. The pixel defining film PDL may include openings OP exposing portions of the first to third anode electrodes AE1 to AE3. The openings OP of the pixel defining film PDL may define light emitting regions of the first to third sub-pixels SP1 to SP3, respectively. In this manner, the pixel defining film PDL is disposed in the non-light emitting region NEA of Fig. 6a and may define the first to third light emitting regions EMA1 to EMA3 of Fig. 6a.

[0157] A separator SPR may be provided in the boundary region BDA between adjacent sub-pixels.

[0158] The separator SPR can cause the formation of a discontinuity in the light emitting structure EU overlapping the boundary region BDA. For example, the separator SPR can cause the first light emitting structure EU1 of the light emitting structure EU to be cut off at the boundary region BDA. The separator SPR may be provided in the pixel defining film PDL and the planarizing layer PLNL or on the pixel defining film PDL.

[0159] In the embodiment, the pixel defining layer PDL may include one or more trenches TRCH1-TRCH3 as separators SPR in the boundary region BDA. For example, as shown in Fig. 7, first and second trenches TRCH1, TRCH2 may be provided as separators in the boundary region BDA between the first sub-pixel SP1 and the second sub-pixel SP2, and second and third trenches TRCH2, TRCH3 may be provided as separators in the boundary region BDA between the second sub-pixel SP2 and the third sub-pixel SP3.

[0160] In one embodiment, the trenches TRCH1 to TRCH3 may penetrate the pixel definition film PDL and partially penetrate the planarization layer PLNL. Depending on the embodiment, the trenches TRCH1 to TRCH3 may penetrate the pixel definition film PDL and the planarization layer PLNL and partially penetrate the via layer VIAL. In one embodiment, the pixel definition film PDL may not be disposed in the trenches TRCH1 to TRCH3, and most of the trenches TRCH1 to TRCH3 may be empty spaces (or voids). However, this is not limited thereto, and for example, a part of the pixel definition film PDL may be disposed in the trenches TRCH1 to TRCH3.

[0161] In FIG. 7, two trenches are shown to be provided in the boundary region BDA, but the embodiment is not limited thereto. For example, the pixel definition film PDL may include one trench in the boundary region BDA (see FIG. 15). Or, the pixel definition film PDL may include three or more trenches in the boundary region BDA.

[0162] Alternatively, the separator SPR may be modified in various ways so that the light emitting structure EU has a discontinuous portion in the boundary region BDA. Other embodiments of the separator SPR will be described later with reference to FIGS.

[0163] The light emitting structure EU may be disposed on the anode electrode AE ​​exposed through the opening OP of the pixel defining film PDL. The light emitting structure EU fills the opening OP of the pixel defining film PDL, but may be disposed over the entire first to third sub-pixels SP1 to SP3.

[0164] In the embodiment, the light emitting structure EU may include a first light emitting structure EU1 (or a first stack) and a second light emitting structure EU2 (or a second stack) which are stacked in sequence. That is, the light emitting structure EU may have a tandem structure in which the first and second light emitting structures EU1, EU2 are stacked. Each of the first and second light emitting structures EU1, EU2 may emit light. The first and second light emitting structures EU1, EU2 may emit light of different colors, but are not limited thereto. The first and second light emitting structures EU1, EU2 may also emit light of the same color.

[0165] In one embodiment, the first light emitting structure EU1 may be separated at the boundary region BDA by a separator SPR. For example, the first light emitting structure EU1 of the first sub-pixel SP1 and the first light emitting structure EU1 of the second sub-pixel SP2 may be disconnected or separated at the boundary region BDA. This reduces current flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through a layer included in the light emitting structure EU during operation of the display panel DP. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0166] On the other hand, the second light emitting structure EU2 may be continuous without being interrupted at the boundary region BDA. For example, the second light emitting structure EU2 of the first subpixel SP1 and the second light emitting structure EU2 of the second subpixel SP2 may be connected at the boundary region BDA. Depending on the embodiment, a part of the second light emitting structure EU2 (e.g., a part of the lower part) may be interrupted at the boundary region BDA, but the rest of the second light emitting structure EU2 may be continuous (see FIG. 8).

[0167] The cathode electrode CE (or the second electrode) may be disposed on the light emitting structure EU. The cathode electrode CE may be provided in common to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EU. In order to protect the cathode electrode CE, a capping layer containing an inorganic material may be further disposed on the cathode electrode CE (see CPL in FIG. 9).

[0168] When the second light emitting structure EU2 is continuous in the boundary region BDA, the cathode electrode CE disposed on the second light emitting structure EU2 can be continuous without being interrupted in the boundary region BDA, which allows the second power supply voltage to be stably supplied to the first to third sub-pixels SP1 to SP3, and allows the first to third light emitting elements LD1 to LD3 to operate normally.

[0169] The first anode electrode AE, a portion of the light emitting structure EU overlapping the first anode electrode AE, and a portion of the cathode electrode CE overlapping the first anode electrode AE ​​can form a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EU overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 can form a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EU overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 can form a third light emitting element LD3.

[0170] A sealing layer TFE may be disposed on the cathode electrode CE. The sealing layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0171] An optical functional layer OFL may be disposed on the encapsulation layer TFE. In an embodiment, the optical functional layer OFL may be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optical functional layer OFL may be manufactured separately and attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL may further function to protect the underlying layers including the encapsulation layer TFE.

[0172] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first, second, and third color filters CF1, CF2, and CF3 corresponding to the first, second, and third sub-pixels SP1, SP2, and SP3, respectively. The first, second, and third color filters CF1, CF2, and CF3 can transmit light of different wavelength ranges. For example, the first, second, and third color filters CF1, CF2, and CF3 can transmit red, green, and blue light, respectively.

[0173] In the embodiment, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In another embodiment, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0174] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first, second, and third lenses LS1, LS2, and LS3 corresponding to the first, second, and third sub-pixels SP1, SP2, and SP3, respectively. The first to third lenses LS1 to LS3 output the light emitted from the first to third light-emitting elements LD1 to LD3 to intended paths, thereby improving the light output efficiency.

[0175] FIG 8 is an enlarged cross-sectional view of a portion of the display device of FIG 7. FIG 8 shows a light emitting structure EU and a cathode electrode CE in a portion of the display device including the first and second trenches TRCH1 and TRCH2 (e.g., a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2). For clarity, a planarization layer PLNL, a pixel definition layer PDL, and an encapsulation layer TFE are also shown. FIG 9 is a cross-sectional view showing an embodiment of a light emitting layer included in the display device of FIG 7. A cathode electrode CE is also shown in FIG 9. FIG 10 is an image showing an embodiment of the display device of FIG 8.

[0176] 7 to 9, the pixel definition layer PDL may include first, second, and third inorganic layers PDL1, PDL2, and PDL3 sequentially stacked on the planarization layer PLNL. The first inorganic layer PDL1 and the third inorganic layer PDL3 are made of silicon nitride (SiN x ), and the second inorganic layer PDL2 includes silicon oxide (SiO x ), however, the embodiment is not limited thereto. The pixel definition film PDL including the first, second, and third inorganic layers PDL1, PDL2, and PDL3 may have a stepped cross section in a region adjacent to the opening OP (see FIG. 7).

[0177] Since the first and second trenches TRCH1, TRCH2 are substantially the same, the trench TRCH will be described collectively as the first and second trenches TRCH1, TRCH2.

[0178] Each trench TRCH may include or be defined by a through portion of the pixel definition layer PDL and a recessed portion of the planarization layer PLNL.

[0179] In the embodiment, the light emitting structure EU may include first and second light emitting structures EU1 and EU2. The light emitting structure EU may be configured substantially similarly in each of the first to third light emitting elements LD1 to LD3 in Fig. 7. The light emitting structure EU may be formed by a method such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0180] Each of the first and second light-emitting structures EU1 and EU2 may include a light-emitting layer that generates light in response to an applied current. The first light-emitting structure EU1 may include a first light-emitting layer EML1, a 1-2 functional layer ETR1 (or a first electron transport layer), and a 1-1 functional layer HTR1 (or a first hole transport layer). The first light-emitting layer EML1 may be disposed between the 1-2 functional layer ETR1 and the 1-1 functional layer HTR1. The second light-emitting structure EU2 may include a second light-emitting layer EML2, a 2-2 functional layer ETR2 (or a second electron transport layer), and a 2-1 functional layer HTR2 (or a second hole transport layer). The second light-emitting layer EML2 may be disposed between the 2-2 functional layer ETR2 and the 2-1 functional layer HTR2.

[0181] Each of the 1-1 and 2-1 functional layers HTR1 and HTR2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., as necessary. The 1-1 and 2-1 functional layers HTR1 and HTR2 may have different configurations.

[0182] Each of the 1-2 and 2-2 functional layers ETR1 and ETR2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc., as necessary. The 1-2 and 2-2 functional layers ETR1 and ETR2 may have the same or different configurations.

[0183] In the embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors. The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2 may be mixed and viewed as white light. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In the embodiment, the second light-emitting layer EML2 may include a structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red light and the green light may be mixed to provide yellow light. In this case, a layer configured to perform a function of transporting holes and / or a function of blocking electron transport may be further disposed between the first and second sub-light-emitting layers.

[0184] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color.

[0185] An intermediate layer CGL (or charge generation layer) may be disposed between the first light emitting structure EU1 and the second light emitting structure EU2. The intermediate layer CGL may generate charges and connect the first light emitting structure EU1 and the second light emitting structure EU2. In an embodiment, the intermediate layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, NDP-9, etc., and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof, but the embodiment is not limited thereto.

[0186] In the embodiment, the intermediate layer CGL can be cut at the top of the trench TRCH, similarly to the first light emitting structure EU1, as shown in Fig. 8. In this case, current is prevented from flowing out from the subpixel to another subpixel adjacent thereto via the intermediate layer CGL, and the subpixel can operate with high reliability.

[0187] In the embodiment, with respect to the third direction DR3, the thickness of the first light emitting structure EU1 may be smaller than the depth L_T of the trench TRCH, and the thickness of the second light emitting structure EU2 may be larger than the depth L_T of the trench TRCH.

[0188] In one embodiment, the thickness of the first light emitting structure EU1 may be less than or equal to 70% of the depth L_T of the trench TRCH, and the thickness of the second light emitting structure EU2 may be more than or equal to 160% of the depth L_T of the trench TRCH.

[0189] In one embodiment, the ratio of the width W_T of the trench TRCH to the depth L_T of the trench TRCH may be 1:1.45 to 1:11. More preferably, the ratio of the width W_T of the trench TRCH to the depth L_T of the trench TRCH may be 1:2.4 to 1:3.7. For example, the ratio of the width W_T of the trench TRCH to the depth L_T of the trench TRCH may be about 1:3. That is, the depth L_T of the trench TRCH may be 1.45 times or more and 11 times or less than the width W_T of the trench TRCH, and more preferably, the depth L_T of the trench TRCH may be 2.4 times or more and 3.7 times or less than the width W_T of the trench TRCH. In other words, the width W_T of the trench TRCH may be 9% or more and 70% or less of the depth L_T of the trench TRCH, and more preferably, the width W_T of the trench TRCH may be 25% or more and 40% or less of the depth L_T of the trench TRCH.

[0190] In one embodiment, the thickness of the first light emitting structure EU1 may be 19% to 82% of the depth L_T of the trench TRCH. More preferably, the thickness of the first light emitting structure EU1 may be 50% to 76% of the depth L_T of the trench TRCH. For example, the thickness of the first light emitting structure EU1 may be about 62% of the depth L_T of the trench TRCH.

[0191] In one embodiment, the thickness of the first light emitting structure EU1 may be 0.9 to 2.6 times the width W_T of the trench TRCH. More preferably, the thickness of the first light emitting structure EU1 may be 1.5 to 2.3 times the width W_T of the trench TRCH. For example, the thickness of the first light emitting structure EU1 may be about 1.85 times the width W_T of the trench TRCH.

[0192] In one embodiment, the thickness of the second light emitting structure EU2 may be 0.5 to 2.2 times the depth L_T of the trench TRCH. More preferably, the thickness of the second light emitting structure EU2 may be 1.3 to 2 times the depth L_T of the trench TRCH. For example, the thickness of the second light emitting structure EU2 may be about 1.63 times the depth L_T of the trench TRCH.

[0193] In one embodiment, the thickness of the second light emitting structure EU2 may be 2.6 times or more and 6.8 times or less than the width W_T of the trench TRCH. More preferably, the thickness of the second light emitting structure EU2 may be 4 times or more and 6 times or less than the width W_T of the trench TRCH. For example, the thickness of the second light emitting structure EU2 may be about 4.9 times the width W_T of the trench TRCH.

[0194] In one embodiment, the depth L_T of the trench TRCH may be 2500 Å to 8500 Å, and the width W_T of the trench TRCH may be 800 Å to 1700 Å. More preferably, the depth L_T of the trench TRCH may be 2700 Å to 3300 Å, and the width W_T of the trench TRCH may be 900 Å to 1100 Å. The thickness of the first light emitting structure EU1 may be in the range of 1650 Å to 2050 Å, and the thickness of the second light emitting structure EU2 may be in the range of 4500 Å to 5400 Å. For example, the depth L_T of the trench TRCH may be about 3000 Å, the width W_T of the trench TRCH may be about 1000 Å, the thickness of the first light emitting structure EU1 may be about 1840 Å, and the thickness of the second light emitting structure EU2 may be about 4920 Å.

[0195] In addition, the depth L_T and width W_T of the trench TRCH and the thicknesses of the first and second light emitting structures EU1 and EU2 may be set in consideration of the disconnection of the intermediate layer CGL and the connection (resonance distance) with the cathode electrode CE. For example, if the depth L_T of each trench TRCH is greater than 8500 Å or the width W_T of each trench TRCH is greater than 1700 Å, the cathode electrode CE may be disconnected at the top of the trench TRCH as shown in the first image IMAGE1 in Fig. 10, and the sub-pixel may not emit light. For example, if the depth L_T of each trench TRCH is less than 2500 Å or the width W_T of each trench TRCH is less than 800 Å, the intermediate layer CGL may be connected without being separated at the top of the trench TRCH, and side leakage may occur through the intermediate layer CGL. When the depth L_T of each trench TRCH is about 3000 Å and the width W_T of each trench TRCH is about 1000 Å, the cathode electrode CE is connected at the top of the trench TRCH as shown in the second image IMAGE2 of FIG. 10, but the intermediate layer CGL can be separated at the top of the trench TRCH.

[0196] In an embodiment, with respect to the third direction DR3, the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) may be smaller than the depth L_T of the trench TRCH, and the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be larger than the depth L_T of the trench TRCH.

[0197] In one embodiment, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be 0.4 times or more and 1.8 times or less the depth L_T of the trench TRCH. More preferably, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be 1 time or more and 1.7 times or less the depth L_T of the trench TRCH. For example, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be about 1.33 times the depth L_T of the trench TRCH.

[0198] In one embodiment, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be 2 times or more and 5.5 times or less than the width W_T of the trench TRCH. More preferably, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be 3.2 times or more and 4.8 times or less than the width W_T of the trench TRCH. For example, the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) may be about 4 times the width W_T of the trench TRCH.

[0199] In one embodiment, when the depth L_T of the trench TRCH is about 3000 Å and the width W_T of the trench TRCH is in the range of 800 Å to 1700 Å, the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) can be in the range of 1200 Å to 1650 Å, and the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) can be in the range of 3600 Å to 4400 Å. For example, the thickness TH1 of the 1-1 functional layer HTR1 (or the first hole transport layer) can be about 1350 Å, and the thickness TH2 of the 2-1 functional layer HTR2 (or the second hole transport layer) can be about 4000 Å.

[0200] For reference, the thickness of the first emitting layer EML1 may be 170 Å or more and 210 Å or less (e.g., about 190 Å), the thickness of the 1-2 functional layer ETR1 may be 90 Å or more and 110 Å or less (e.g., about 100 Å), the thickness of the intermediate layer CGL may be 160 Å or more and 195 Å or less (e.g., about 175 Å), the thickness of the second emitting layer EML2 may be 360 ​​Å or more and 440 Å or less (e.g., about 400 Å), and the thickness of the 2-2 functional layer ETR2 may be 230 Å or more and 290 Å or less (e.g., about 260 Å).

[0201] When the thickness TH1 of the 1-1 functional layer HTR1 is smaller than the depth L_T of the trench TRCH, the intermediate layer CGL (and the first light emitting structure EU1) can be stably disconnected at the top of the trench TRCH. When the thickness TH2 of the 2-1 functional layer HTR2 is larger than the depth L_T of the trench TRCH, the second light emitting structure EU2 (and the cathode electrode CE) can be stably connected at the top of the trench TRCH. In addition, when the thickness TH1 of the 1-1 functional layer HTR1 is 1200 Å or more and 1650 Å or less and the thickness TH1 of the 2-1 functional layer HTR2 is 3600 Å or more and 4400 Å or less (based on the first light emitting structure EU1 having a thickness of 1650 Å or more and 2050 Å or less and the second light emitting structure EU2 having a thickness of 4500 Å or more and 5400 Å or less), a balance of holes and electrons that combine in each of the first and second light emitting layers EML1, EML2 can be achieved, thereby maximizing the luminous efficiency of the first and second light emitting structures EU1, EU2. Furthermore, when the thickness TH1 of the 1-1 functional layer HTR1 is 1200 Å or more and 1650 Å or less, and the thickness TH1 of the 2-1 functional layer HTR2 is 3600 Å or more and 4400 Å or less, the resonance distance of the light emitted from the first and second light emitting layers EML1, EML2 (e.g., the distance emitted from each of the first and second light emitting layers EML1, EML2 and travels back and forth between the reflective electrodes RE1, RE2 and the cathode electrode CE) is optimized, so that the light generated in the first and second light emitting layers EML1, EML2 can be amplified and output via the cathode electrode CE.

[0202] In the embodiment, the 1-1 functional layer HTR1 and the 2-1 functional layer HTR2 may include different materials. For example, the 1-1 functional layer HTR1 and the 2-1 functional layer HTR2 each include a common material (e.g., an organic conductive material containing carbon and hydrogen) constituting a hole transport layer of an organic light emitting diode, but the 1-1 functional layer HTR1 and the 2-1 functional layer HTR2 may include materials having different structures.

[0203] In one embodiment, the 1-1 functional layer HTR1 (or the first hole transport layer) may include a plate-like material (or a material having a plate-like structure), and the 2-1 functional layer HTR2 (or the second hole transport layer) may include a material (hereinafter referred to as a "bulk material") (or a material having a bulk-like structure) that is bulkier than the plate-like material. Here, the plate-like may refer to a structure in which atoms are arranged two-dimensionally or with the thickness of an atomic layer, or a structure in which materials are stacked in a thin, flat plate shape. For example, a plate-like material may have a high specific surface area and a strong bonding force, but low compressive strength or tensile strength. The bulk-like may refer to a structure in which a material exists in a large, thick mass, or a structure in which atoms are arranged three-dimensionally, but the atomic arrangement of the surface coincides with the atomic arrangement of the bulk. In other words, the bulk-like may be a structure in which the displacement of a solid is minimized when forming a surface. That is, the bulk type has a feature that the spacing between atoms is constant and the spacing between each layer is the same. The bulk type has a low specific surface area and is strong and hard, but can have low flexibility and bonding strength.

[0204] The properties (or physical properties, for example, Tg, Td, HOMO, LUMO, and reflective index) of the plate-like and bulk-like materials are described below. In the following, "Tg" (hereinafter referred to as "thermal characteristic Tg") means glass transition temperature, which is the temperature at which a polymer transitions from a glass state to a polymeric solid. Thermal characteristic Tg can be measured by a thermal analyzer or DSC (Differential Scanning Calorimetry), and DSC is an analytical technique that measures the amount of heat released or absorbed when a sample is heated or cooled in a specific temperature range. "Td" means the temperature at which a substance (or sample) decomposes, "Td(1%)" (hereinafter referred to as thermal characteristic Td(1%)) is the temperature at which the weight is reduced by 1% from the initial weight, and "Td(5%)" (hereinafter referred to as thermal characteristic Td(5%)) is the temperature at which the weight is reduced by 5% from the initial weight. "Td" can be measured by a thermogravimetric analyzer or TGA (Thermogravimetric Analysis). HOMO (Highest Occupied Molecular Orbital) and LUMO (Lowest Unoccupied Molecular Orbital) are molecular orbitals that indicate the electronic structure of a molecule. HOMO refers to the molecular orbital in the highest energy region in which electrons can participate in bonds, and LUMO refers to the molecular orbital in the lowest energy region in which electrons can participate in antibonding.

[0205] The thermal characteristic Tg (or glass transition temperature) of the plate-shaped material may be 120° C. to 130° C., and the thermal characteristic Tg of the bulk material may be 145° C. to 155° C. That is, the thermal characteristic Tg of the bulk material may be 15° C. to 35° C., or 10% to 30% higher than the thermal characteristic Tg of the plate-shaped material. The lower the thermal characteristic Tg (or glass transition temperature), the easier it can be deformed.

[0206] The thermal characteristic Td(1%) of the plate-like material can be 320° C. or more and 335° C. or less, and the thermal characteristic Td(1%) of the bulk material can be 340° C. or more and 365° C. or less. That is, the thermal characteristic Td(1%) of the bulk material can be higher than the thermal characteristic Td(1%) of the plate-like material by 5° C. or more and 45° C. or less, or by 1.5% or more and 15% or less.

[0207] The thermal characteristic Td(5%) of the plate-like material can be 340° C. or more and 365° C. or less, and the thermal characteristic Td(5%) of the bulk material can be 385° C. or more and 405° C. or less. In other words, the thermal characteristic Td(5%) of the bulk material can be higher than the thermal characteristic Td(5%) of the plate-like material by 20° C. or more and 65° C. or less, or by 5% or more and 20% or less.

[0208] The HOMO molecular orbital energy of the plate-like material may be 5.3 eV to 5.7 eV, and the HOMO molecular orbital energy of the bulk material may be -5.4 eV to -4.6 eV, i.e., 9.9 eV to 11.1 eV, or 173% to 210% lower than the HOMO molecular orbital energy of the plate-like material.

[0209] The LUMO molecular orbital energy of the plate-like material may be 2.2 eV to 2.6 eV, and the LUMO molecular orbital energy of the bulk material may be -2.2 eV to -0.8 eV, i.e., the LUMO molecular orbital energy of the bulk material may be 3.0 eV to 4.8 eV, or 115% to 220% higher than the LUMO molecular orbital energy of the plate-like material.

[0210] The reflective index of the plate-like material may be 1.7 to 1.9 or 1.77 to 1.89, and the reflective index of the bulk material may be 1.6 to 1.8 or 1.7 to 1.76, i.e., the reflective index of the bulk material may be smaller than that of the plate-like material.

[0211] In one embodiment, the molecular form (or Geometry Optimization) of the plate-like material is flat, the Van Der Waals force (or bond force) of the plate-like material is 405 to 497, the angle of the plate-like material is 198 to 204, and the torsion (or torsion force) of the plate-like material is 446 to 546. Here, Van Der Waals means the force of attraction between molecules (unit: kJ / mol), the angle means the angle between two bonds of the molecule (unit: radian), and the torsion means the rotation within the molecule (unit: radian). In one embodiment, the molecular form of the bulk material is twisted, the Van Der Waals of the bulk material is 710 to 866, the angle of the bulk material is 1221 to 1491, and the torsion of the bulk material is 659 to 805. The van der Waals, angles, and twist of the bulk material can be greater than the van der Waals, angles, and twist of the platelet material, respectively.

[0212] Plate-like materials have a flat molecular shape and are deposited regularly, but because the van der Waals (or van der Waals forces) of the plate-like materials are small, the plate-like materials (or plate-like material layers) can be significantly affected by the underlying film (e.g., voids). Bulk-like materials have a large angle and twist, so they are deposited in a twisted shape and the bulk-like materials (or bulk-like material layers) can be significantly affected by the underlying film (e.g., voids). In addition, because the van der Waals forces of the bulk-like materials are large, even when deposited scatteredly, the bulk-like materials (or bulk-like material layers) can cover the underlying film like a net and maintain their shape, regardless of the shape of the underlying film (e.g., voids).

[0213] Since plate-like materials have a flat shape, they can have bonds concentrated in the center of the lattice. For example, plate-like materials can have a shape of stacked bricks. Since bulk-like materials are twisted, they can have a shape that spreads out like a net within the lattice. Since the van der Waals of bulk-like materials is large, the bulk-like materials can maintain a net shape. When examining the lattice density, the bulk-like materials spread out more widely compared to plate-like materials, and there is a higher probability that the bulk-like materials will cover a specific underlying film structure (e.g., voids).

[0214] Depending on the embodiment, the platelets may include p-dopants, in which case the van der Waals of the platelets may be 349 to 425, and the angle of the platelets may be 191 to 233. On the other hand, the bulk material may not include p-dopants.

[0215] When the 1-1 functional layer HTR1 including a plate-like material is formed on the upper part of the trench TRCH, the 1-1 functional layer HTR1 can be bent and cut at the trench TRCH. As a result, the first light emitting structure EU1 including the 1-1 functional layer HTR1 and the intermediate layer CGL having a relatively thin thickness can be cut at the trench TRCH. In contrast, when the 1-1 functional layer HTR1 includes a bulk-like material, the 1-1 functional layer HTR1 is not cut at the trench TRCH, and as a result, the intermediate layer CGL is connected at the trench TRCH, which may cause side leakage. On the other hand, when the 2-1 functional layer HTR2 including a bulk-like material is formed on the upper part of the trench TRCH, the 2-1 functional layer HTR2 can be connected without being bent at the trench TRCH. As a result, the second light emitting structure EU2 including the 2-1 functional layer HTR2 is not cut by the trench TRCH, and a large step is not formed on the upper surface of the second light emitting structure EU2 including the 2-1 functional layer HTR2, so that the cathode electrode CE is not cut. In contrast, when the 2-1 functional layer HTR2 includes a plate-shaped material, the 2-1 functional layer HTR2 is cut by the trench TRCH, and therefore the cathode electrode CE can also be cut by the trench TRCH.

[0216] In one embodiment, the thickness TH3 of the cathode electrode CE may be in the range of 100 Å to 190 Å, or in the range of 150 Å to 185 Å. Also, the step difference DIFF of the cathode electrode CE at the upper part of the trench TRCH may be 500 Å or less. As the thickness TH3 of the cathode electrode CE is thicker, the cathode electrode CE may be more stably connected at the trench TRCH, but the light transmission efficiency of the cathode electrode CE may be reduced. When the second light emitting structure EU2 (or the 2-1 functional layer HTR2) is connected without bending at the trench TRCH, the step difference of the bent part of the upper surface of the second light emitting structure EU2 is reduced to 500 Å or less, and the cathode electrode CE may be connected without being broken at the upper part of the trench TRCH even with a thickness of 150 Å to 185 Å (for example, about 170 Å).

[0217] As described above, the thickness of the first light-emitting transport region HTR1 (or the first light-emitting structure EU1) may be smaller than the depth L_T of the trench TRCH, and the thickness of the second light-emitting transport region HTR2 (or the second light-emitting structure EU2) may be larger than the depth L_T of the trench TRCH. In addition, the 1-1 functional layer HTR1 (or the first hole transport layer) may include a plate-like material, and the 2-1 functional layer HTR2 (or the second hole transport layer) may include a bulk-like material. In this case, the first light-emitting structure EU1 and the intermediate layer CGL are cut at the top of the trench TRCH to prevent side leakage, and the second light-emitting structure EU2 and the cathode electrode CE are connected to allow the sub-pixel to operate normally. That is, the sub-pixel accurately emits light with a desired luminance, and the display quality is improved.

[0218] Figure 11 is a cross-sectional view showing another embodiment of the display device taken along line I-I' in Figure 6a. Figure 12 is an enlarged cross-sectional view of a portion of the display device of Figure 11. Figure 12 shows a light emitting structure EU' and a cathode electrode CE in a portion of the display device (e.g., a boundary region between the first sub-pixel SP1 and the second sub-pixel SP2) including the first and second trenches TRCH1', TRCH2'. Figure 13 is a cross-sectional view showing an embodiment of a light emitting layer included in the display device of Figure 11.

[0219] 7 to 13, except for the light emitting layer EML', the display device of Fig. 11 may be substantially the same as or similar to the display devices of Fig. 7 and Fig. 8. Therefore, a duplicated description will be omitted.

[0220] The light emitting layer EML' may have a tandem structure in which the first, second, and third light emitting structures EU1', EU2', and EU3' are stacked. The light emitting layer EML' may be configured substantially the same in each of the first to third light emitting elements LD1 to LD3 in FIG.

[0221] 11, the first light emitting structure EU1' and the second light emitting structure EU2' may be separated in the boundary region BDA by a separator SPR (e.g., trenches TRCH1-TRCH3). For example, the first and second light emitting structures EU1', EU2' of the first sub-pixel SP1 and the first and second light emitting structures EU1', EU2' of the second sub-pixel SP2 may be disconnected or separated in the boundary region BDA. As a result, when the display panel DP is operated, the current flowing from each of the first to third sub-pixels SP1-SP3 to the adjacent sub-pixels through a layer included in the light emitting layer EML' may be reduced.

[0222] Meanwhile, the third light emitting structure EU3′ may be continuous without being interrupted at the boundary region BDA. For example, the third light emitting structure EU3′ of the first sub-pixel SP1 and the third light emitting structure EU3′ of the second sub-pixel SP2 may be connected at the boundary region BDA.

[0223] Each of the first to third light emitting structures EU1' to EU3' may include a light emitting layer that generates light in response to an applied current. The first light emitting structure EU1' may include a first light emitting layer EML1', a 1-2 functional layer ETR1', and a 1-1 functional layer HTR1'. The first light emitting layer EML1' may be disposed between the 1-2 functional layer ETR1' and the 1-1 functional layer HTR1'. The second light emitting structure EU2' may include a second light emitting layer EML2', a 2-2 functional layer ETR2', and a 2-1 functional layer HTR2'. The second light emitting layer EML2' may be disposed between the 2-2 functional layer ETR2' and the 2-1 functional layer HTR2'. The third light emitting structure EU3' may include a third light emitting layer EML3', a 3-2 functional layer ETR3', and a 3-1 functional layer HTR3'. The third light-emitting layer EML3' may be disposed between the 3-2 functional layer ETR3' and the 3-1 functional layer HTR3'.

[0224] Each of the 1-1, 2-1, and 3-1 functional layers HTR1', HTR2', and HTR3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. Parts of the 1-1, 2-1, and 3-1 functional layers HTR1', HTR2', and HTR3' may have different configurations from each other.

[0225] Each of the 1-2, 2-2, and 3-2 functional layers ETR1', ETR2', and ETR3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The 1-2, 2-2, and 3-2 functional layers ETR1', ETR2', and ETR3' may have the same configuration or different configurations.

[0226] In the embodiment, the first to third light emitting layers EML1' to EML3' may generate light of different colors. The light emitted from each of the first to third light emitting layers EML1' to EML3' may be mixed and viewed as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0227] In another embodiment, two or more of the first to third light emitting layers EML1' to EML3' can generate light of the same color.

[0228] The first intermediate layer CGL1' (or the first charge generation layer) may be disposed between the first light emitting structure EU1' and the second light emitting structure EU2'. The second intermediate layer CGL2' (or the second charge generation layer) may be disposed between the second light emitting structure EU2' and the third light emitting structure EU3'.

[0229] In the embodiment, the first and second intermediate layers CGL1', CGL2' may be cut at the tops of the trenches TRCH1-TRCH3, similar to the first and second light emitting structures EU1', EU2', as shown in Fig. 12. In this case, current is prevented from flowing from a subpixel to another adjacent subpixel via the first and second intermediate layers CGL1', CGL2', and the subpixels can operate with high reliability.

[0230] In an embodiment, the ratio of the width W_T' to the depth L_T' of the trench TRCH' may be 1:1.45 to 1:11. More preferably, the ratio of the width W_T' to the depth L_T' of the trench TRCH' may be 1:4.2 to 1:6.4. For example, the ratio of the width W_T' to the depth L_T' of the trench TRCH' may be about 1:5.2. That is, the width W_T' of the trench TRCH' may be 9% to 70% of the depth L_T' of the trench TRCH', and more preferably, the width W_T' of the trench TRCH' may be 15% to 24% of the depth L_T' of the trench TRCH'.

[0231] The total thickness of the first and second light emitting structures EU1', EU2' may be similar to the thickness of the first light emitting structure EU1 in FIG. 9, and the thickness of the third light emitting structure EU3' may be similar to the thickness of the second light emitting structure EU2 in FIG.

[0232] In one embodiment, the total thickness of the first and second light emitting structures EU1', EU2' may be 17% to 82% of the depth L_T' of the trench TRCH'. More preferably, the total thickness of the first and second light emitting structures EU1', EU2' may be 51% to 78% of the depth L_T' of the trench TRCH'. For example, the total thickness of the first and second light emitting structures EU1', EU2' may be about 63% of the depth L_T' of the trench TRCH'.

[0233] In one embodiment, the total thickness of the first and second light emitting structures EU1', EU2' may be 0.8 to 2.6 times the width W_T' of the trench TRCH'. More preferably, the total thickness of the first and second light emitting structures EU1', EU2' may be 1.2 to 1.8 times the width W_T' of the trench TRCH'. For example, the total thickness of the first and second light emitting structures EU1', EU2' may be about 1.53 times the width W_T' of the trench TRCH'.

[0234] In one embodiment, the thickness of the third light emitting structure EU3' may be 0.4 to 2.5 times the depth L_T' of the trench TRCH'. More preferably, the thickness of the third light emitting structure EU3' may be 0.6 to 1.0 times the depth L_T' of the trench TRCH'. For example, the thickness of the third light emitting structure EU3' may be about 0.78 times the depth L_T' of the trench TRCH'.

[0235] In one embodiment, the thickness of the third light emitting structure EU3' may be 2.4 to 6.5 times the width W_T' of the trench TRCH'. More preferably, the thickness of the third light emitting structure EU3' may be 3.3 to 5.0 times the width W_T' of the trench TRCH'. For example, the thickness of the third light emitting structure EU3' may be about 4.1 times the width W_T of the trench TRCH.

[0236] In one embodiment, the depth L_T' of the trench TRCH' may be 2500 Å to 8500 Å, and the width W_T' of the trench TRCH' may be 800 Å to 1700 Å. More preferably, the depth L_T' of the trench TRCH' may be 5400 Å to 6600 Å, and the width W_T' of the trench TRCH' may be 1035 Å to 1265 Å. The thickness of the first light emitting structure EU1' may be in the range of 900 Å to 1100 Å, the thickness of the second light emitting structure EU2' may be in the range of 531 Å to 649 Å, and the thickness of the third light emitting structure EU3' may be in the range of 4312 Å to 5148 Å. For example, the depth L_T' of the trench TRCH' may be about 6000 Å, the width W_T' of the trench TRCH' may be about 1150 Å, the thickness of the first light emitting structure EU1' may be about 1000 Å, the thickness of the second light emitting structure EU2' may be about 590 Å, and the thickness of the third light emitting structure EU3' may be about 4680 Å. The thickness of the 3-1 functional layer HTR3' may be similar to the thickness TH2 of the 2-1 functional layer HTR2 in FIG.

[0237] In one embodiment, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be 0.4 times or more and 1.8 times or less the depth L_T' of the trench TRCH'. More preferably, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be 0.5 times or more and 0.8 times or less the depth L_T' of the trench TRCH'. For example, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be about 0.63 times the depth L_T' of the trench TRCH'.

[0238] In one embodiment, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be 2 to 5.5 times the width W_T' of the trench TRCH'. More preferably, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be 2.7 to 4.1 times the width W_T' of the trench TRCH'. For example, the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be about 3.3 times the width W_T' of the trench TRCH'.

[0239] In one embodiment, when the depth L_T' of the trench TRCH' is about 6000 Å and the width W_T' of the trench TRCH' is in the range of 800 Å to 1700 Å, the thickness of the 1-1 functional layer HTR1' (or the first hole transport layer) may be in the range of 225 Å to 275 Å, the thickness of the 2-1 functional layer HTR2' (or the second hole transport layer) may be in the range of 180 Å to 220 Å, and the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be in the range of 3411 Å to 4169 Å. For example, the thickness of the 1-1 functional layer HTR1' (or the first hole transport layer) may be about 250 Å, the thickness of the 2-1 functional layer HTR2' (or the second hole transport layer) may be about 200 Å, and the thickness of the 3-1 functional layer HTR3' (or the third hole transport layer) may be about 3790 Å.

[0240] For reference, the thickness of the first emitting layer EML1' is 400 Å or more and 500 Å or less (e.g., about 450 Å), the thickness of the first-2 functional layer ETR1' is 130 Å or more and 170 Å or less (e.g., about 150 Å), the thickness of the first intermediate layer CGL1' is 160 Å or more and 195 Å or less (e.g., about 175 Å), and the thickness of the second emitting layer EML2' is 170 Å or more and 210 Å or less (e.g., about 190 Å). The thickness of the 2-2 functional layer ETR2' may be 130 Å or more and 170 Å or less (e.g., about 150 Å), the thickness of the second intermediate layer CGL2' may be 160 Å or more and 195 Å or less (e.g., about 175 Å), the thickness of the third light-emitting layer EML3' may be 290 Å or more and 370 Å or less (e.g., about 330 Å), and the thickness of the 3-2 functional layer ETR3' may be 280 Å or more and 360 Å or less (e.g., about 320 Å).

[0241] In the embodiment, the first and 2-1 functional layers HTR1', HTR2' (or the first and second hole transport layers) may include a plate-like material, and the 2-1 functional layer HTR3' (or the third hole transport layer) may include a bulk material. In this case, the first light emitting structure EU1', the first intermediate layer CGL1', the second light emitting structure EU2', and the second intermediate layer CGL2' may be separated by the trenches TRCH1 to TRCH3, and the third light emitting structure EU3' and the cathode electrode CE may not be separated by the trenches TRCH1 to TRCH3.

[0242] By disconnecting the first and second intermediate layers CGL1' and CGL2', side leakage is prevented, and by connecting the cathode electrode CE, the sub-pixel can be normally driven.

[0243] Fig. 14 is a plan view showing an embodiment of a pixel included in the display device of Fig. 5. Fig. 15 is a cross-sectional view showing an embodiment of a display device taken along line II-II' of Fig. 14.

[0244] 6a, 7, 14, and 15, except for the trench TRCH (or separator SPR), the display device of Fig. 14 and Fig. 15 may be substantially the same as or similar to the display device of Fig. 6a and Fig. 7. Therefore, a duplicated description will be omitted.

[0245] A separator SPR may be provided in the boundary region BDA between adjacent sub-pixels.

[0246] In the embodiment, the pixel definition layer PDL may include one trench TRCH as a separator SPR in the boundary region BDA. For example, as shown in Figures 14 and 15, one trench TRCH may be provided as a separator in the boundary region BDA between the first sub-pixel SP1 and the second sub-pixel SP2, or in the boundary region BDA between the second sub-pixel SP2 and the third sub-pixel SP3.

[0247] As shown in Fig. 6a, one trench TRCH may surround each of the first to third sub-pixels SP1 to SP3. The trench TRCH may have a lattice corresponding to the sub-pixels. That is, the trench TRCH may have a mesh structure.

[0248] In an embodiment, the trench TRCH may penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL, but is not limited thereto. In an embodiment, the pixel defining layer PDL may not be disposed in the trench TRCH, but is not limited thereto, for example, the pixel defining layer PDL may be disposed on the side and bottom surfaces of the trench TRCH, and the trench TRCH may be defined by the pixel defining layer PDL.

[0249] The specifications (eg, depth, width) of the trench TRCH have been described with reference to FIG. 8, so description of the specifications of the trench TRCH will be omitted.

[0250] The first light emitting structure EU1 can be separated at the boundary region BDA by the separator SPR, so that when the display panel DP is in operation, current flowing from each of the first to third sub-pixels SP1 to SP3 to the adjacent sub-pixels through a layer included in the light emitting structure EU can be reduced.

[0251] On the other hand, the second light emitting structure EU2 can be continuous without being interrupted at the boundary region BDA. In this case, the cathode electrode CE can be continuous without being interrupted at the boundary region BDA. This allows the second power supply voltage to be stably supplied to the first to third sub-pixels SP1 to SP3, and the first to third light emitting elements LD1 to LD3 to operate normally.

[0252] Fig. 16 is a cross-sectional view showing an embodiment of a display device taken along line II-II' in Fig. 14. Fig. 17 is an enlarged cross-sectional view of a part of the display device in Fig. 16.

[0253] 7, 8, 14, 16, and 17, the display devices of Fig. 16 and 17 may be substantially the same as or similar to the display devices of Fig. 7 and 8, except that the separator SPR is provided with a protrusion PRT instead of a trench. Therefore, a duplicated description will be omitted.

[0254] In the embodiment, the pixel defining film PDL may include a protrusion PRT protruding in the third direction DR3 in the boundary region BDA. The protrusion PRT may form a step in the base layer (i.e., the upper surface of the pixel defining film PDL) for disposing the first light emitting structure EU1 in the boundary region BDA, and may disconnect the first light emitting structure EU1 (and the intermediate layer CGL) in the boundary region BDA.

[0255] The protrusion PRT may include inorganic insulating patterns stacked in sequence. As described with reference to FIG. 8, the pixel defining layer PDL may include first, second, and third inorganic layers PDL1, PDL2, and PDL3 stacked in sequence. The protrusion PRT may include first, second, and third inorganic insulating patterns PRT_L1, PRT_L2, and PRT_L3 (or fourth, fifth, and sixth inorganic layers) stacked in sequence on the third inorganic layer PDL3. The first inorganic insulating pattern PRT_L1 and the third inorganic insulating pattern PRT_L3 may be made of silicon oxide (SiO x ), and the second inorganic insulating pattern PRT_L2 is made of silicon nitride (SiN x ).

[0256] In one embodiment, the width of the third inorganic insulating pattern PRT_L3 may be greater than the width of the second inorganic insulating pattern PRT_L2 based on the first direction DR1. Also, the width of the second inorganic insulating pattern PRT_L2 may be less than or equal to the width of the first inorganic insulating pattern PRT_L1. In this case, the protrusion PRT may have an inverted tapered, "T" or "I" shaped cross section.

[0257] Due to the shape of the protrusion PRT (or pixel defining layer PDL), the first light emitting structure EU1 and the intermediate layer CGL may be separated in the boundary area BDA, whereas the second light emitting structure EU2 and the cathode electrode CE may be connected without being separated in the boundary area BDA.

[0258] As shown in FIG. 17, the first light emitting structure EU1 and the intermediate layer CGL are not formed (or deposited) on the side surface of the protrusion PRT, and the first light emitting structure EU1 and the intermediate layer CGL may be cut off at the edge of the protrusion PRT.

[0259] In the embodiment, with respect to the third direction DR3, the thickness of the first light emitting structure EU1 may be smaller than the thickness of the protrusion PRT, and the thickness of the second light emitting structure EU2 may be larger than the thickness of the protrusion PRT. In this case, at the edge of the protrusion PRT, each of the first light emitting structure EU1 and the intermediate layer CGL may be cut or discontinuous, and each of the second light emitting structure EU2 and the cathode electrode CE may be connected or continuous.

[0260] As described with reference to FIG. 9, the first light-emitting structure EU1 may include a first light-emitting layer EML1, a 1-2 functional layer ETR1 (or a first electron transport layer), and a 1-1 functional layer HTR1 (or a first hole transport layer). The first light-emitting layer EML1 may be disposed between the 1-2 functional layer ETR1 and the 1-1 functional layer HTR1. The second light-emitting structure EU2 may include a second light-emitting layer EML2, a 2-2 functional layer ETR2 (or a second electron transport layer), and a 2-1 functional layer HTR2 (or a second hole transport layer). The second light-emitting layer EML2 may be disposed between the 2-2 functional layer ETR2 and the 2-1 functional layer HTR2.

[0261] In one embodiment, the 1-1 functional layer HTR1 (or the first hole transport layer) may include a plate-like material, and the 2-1 functional layer HTR2 (or the second hole transport layer) may include a bulk-like material. In this case, at the edge of the protrusion PRT, the 1-1 functional layer HTR1 may be bent and cut, and the 2-1 functional layer HTR2 may not be cut. Thereby, each of the first light emitting structure EU1 and the intermediate layer CGL may be cut or discontinuous, and each of the second light emitting structure EU2 and the cathode electrode CE may be connected or continuous.

[0262] By cutting the intermediate layer CGL, side leakage is prevented, and by connecting the cathode electrode CE, the sub-pixel can be normally driven.

[0263] FIG. 18 is a block diagram illustrating an embodiment of a display system.

[0264] Referring to FIG. 18, a display system 1000 may include a processor 1100 and one or more display devices 1210,1220.

[0265] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphic processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system and can control them.

[0266] 18 shows a display system 1000 including first and second display devices 1210, 1220. The processor 1100 may be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0267] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 via the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may be configured similarly to the display device 100 described with reference to FIG 1. In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as the input image data IMG and the control signal CTRL of FIG 1, respectively.

[0268] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 via the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be configured similarly to the display device 100 described with reference to FIG 1. In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL of FIG 1, respectively.

[0269] The display system 1000 may include a computing system providing a video display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 1000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0270] FIG. 19 is a perspective view showing an application example of the display system of FIG.

[0271] 19, the display system 1000 of FIG. 18 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be mounted on a user's head.

[0272] The head mounted display device 2000 may include a head mounted band 2100 and a display device housing case 2200. The head mounted band 2100 may be connected to the display device housing case 2200. The head mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head mounted display device 2000 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the top of the user's head. However, the embodiment is not limited thereto. For example, the head mounted band 2100 may be embodied in the shape of a glasses frame, a helmet, or the like.

[0273] The display device housing case 2200 can house the first and second display devices 1210 and 1220 of Fig. 18. The display device housing case 2200 can further house the processor 1100 of Fig. 18.

[0274] FIG. 20 is a diagram showing the head-mounted display device worn by the user of FIG.

[0275] 20, a head-mounted display device 2000 (or a wearable electronic device) may include a display panel that emits light and a lens unit disposed on the display panel (or on the light emission path). The display panel may include a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220. The lens unit may include one or more lenses LLNS, RLNS.

[0276] In the display device storage case 2200, the right-eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user. In the display device storage case 2200, the left-eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user.

[0277] An image output from the first display panel DP1 can be viewed by the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 so that it faces the user's right eye. The right-eye lens RLNS can perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0278] An image output from the second display panel DP2 can be viewed by the left eye of the user through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 so that it faces the left eye of the user. The left eye lens LLNS can perform an optical function for adjusting the viewing distance between the second display panel DP2 and the left eye of the user.

[0279] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel outputs an image corresponding to each sub-region of the multi-channel lens, and the output image can pass through the corresponding sub-region to be viewed by a user.

[0280] Although specific embodiments and application examples have been described above, other embodiments and modifications can be derived from the above description. Therefore, the spirit of the present invention is not limited to the embodiments, but extends to the appended claims, various obvious modifications, and equivalents. [Explanation of symbols]

[0281] 100 display device 110 Display Panel 120 Gate Driver 130 Data Driver 140 Voltage Generator 150 Controller 160 Temperature Sensor AE anode electrode CE cathode electrode CF Color Filter CGL middle tier CW Cover Window DP display panel EML Light Emitting Layer ETR1, ETR2 1-2 and 2-2 functional layers (or electron transport layers) EU Light Emitting Structure HTR1, HTR2 1-1st and 2-1st functional layers (or hole transport layers) LA Lens Array LD light emitting element LDL Light emitting device layer OC overcoat layer PCL Pixel circuit layer PDL Pixel Defined Membrane PLNL planarization layer PRT protrusion PXL Pixel SP subpixel SPR Separator TFE sealing layer TRCH Trench SUB board

Claims

1. a base layer having a trench formed therein; a first sub-pixel and a second sub-pixel disposed on either side of the trench; Each of the first sub-pixel and the second sub-pixel has a first electrode disposed on the base layer; a first light emitting structure disposed on the first electrode and configured to emit light; an intermediate layer disposed on the first light emitting structure; a second light emitting structure disposed on the intermediate layer and emitting light; a second electrode disposed on the second light emitting structure; the first light emitting structure includes a first hole transport layer, a first light emitting layer, and a first electron transport layer; the second light emitting structure includes a second hole transport layer, a second light emitting layer, and a second electron transport layer; the thickness of the first hole transport layer is less than the depth of the trench; The thickness of the second hole transport layer is greater than the depth of the trench.

2. The trench is a first trench surrounding the first sub-pixel in a plan view; a second trench surrounding the second sub-pixel in a plan view; The display device of claim 1 , wherein the first trench and the second trench are isolated from each other.

3. The depth of the trench is greater than or equal to 2500 Å and less than or equal to 8500 Å, and the width of the trench is greater than or equal to 800 Å and less than or equal to 1700 Å; the thickness of the first hole transport layer is in the range of 1200 Å to 1650 Å; 2. The display device of claim 1, wherein the thickness of the second hole transport layer is in the range of 3600 Å to 4400 Å.

4. The display device of claim 1 , wherein the first hole transport layer and the second hole transport layer include different materials.

5. 5. The display device according to claim 4, wherein the second hole transport layer has a glass transition temperature that is 10% to 30% higher than the glass transition temperature of the first hole transport layer.

6. The display device according to claim 5 , wherein the second hole transport layer has a glass transition temperature that is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

7. The display device according to claim 1 , wherein the second electrode has a thickness in the range of 100 Å to 190 Å.

8. The display device according to claim 7 , wherein a step of the second electrode on the trench is 500 Å or less.

9. a thickness of the first light emitting structure is less than the depth of the trench; The display device of claim 1 , wherein the thickness of the second light emitting structure is greater than the depth of the trench.

10. the thickness of the first light emitting structure is less than or equal to 70% of the depth of the trench; The display device of claim 9 , wherein the thickness of the second light emitting structure is greater than or equal to 160% of the depth of the trench.

11. The depth of the trench is greater than or equal to 2500 Å and less than or equal to 8500 Å, and the width of the trench is greater than or equal to 800 Å and less than or equal to 1700 Å; the thickness of the first light emitting structure is in the range of 1650 Å to 2050 Å; The display device of claim 9 , wherein the thickness of the second light emitting structure is in the range of 4500 Å to 5400 Å.

12. 2. The display device of claim 1, wherein the first light emitting structure and the intermediate layer of the first subpixel and the second subpixel are disconnected above the trench, and at least a portion of the second light emitting structure of the first subpixel and the second subpixel are connected.

13. Each of the first and second sub-pixels is a third light emitting structure disposed between the first electrode and the first light emitting structure and configured to emit light; a first intermediate layer disposed between the third light emitting structure and the first light emitting structure; The display device according to claim 12 , wherein the third light emitting structure and the first intermediate layer are each interrupted above the trench.

14. the first light emitting structure emits light of a first color; The display device according to claim 1 , wherein the second light emitting structure emits light of a second color different from the first color.

15. The display device according to claim 1 , wherein the first light emitting structure and the second light emitting structure emit light of the same color.

16. a first electrode disposed on the base layer; a first light emitting structure disposed on the first electrode and configured to emit light; an intermediate layer disposed on the first light emitting structure; a second light emitting structure disposed on the intermediate layer and emitting light; a second electrode disposed on the second light emitting structure; the first light emitting structure includes a first hole transport layer, a first light emitting layer, and a first electron transport layer; the second light emitting structure includes a second hole transport layer, a second light emitting layer, and a second electron transport layer; The glass transition temperature of the second hole transport layer is 10% to 30% higher than the glass transition temperature of the first hole transport layer.

17. The display device according to claim 16 , wherein the second hole transport layer has a glass transition temperature that is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

18. A display panel that emits light; at least one lens disposed on the display panel; The display panel includes: a base layer having a trench formed therein; a first sub-pixel and a second sub-pixel disposed on either side of the trench; Each of the first sub-pixel and the second sub-pixel has a first electrode disposed on the base layer; a first light emitting structure disposed on the first electrode and configured to emit light; an intermediate layer disposed on the first light emitting structure; a second light emitting structure disposed on the intermediate layer and emitting light; a second electrode disposed on the second light emitting structure; the first light emitting structure includes a first hole transport layer, a first light emitting layer, and a first electron transport layer; the second light emitting structure includes a second hole transport layer, a second light emitting layer, and a second electron transport layer; the thickness of the first hole transport layer is less than the depth of the trench; A wearable electronic device, wherein the thickness of the second hole transport layer is greater than the depth of the trench.

19. The wearable electronic device of claim 18 , wherein the glass transition temperature of the second hole transport layer is greater than or equal to 10% and less than or equal to 30% higher than the glass transition temperature of the first hole transport layer.

20. The wearable electronic device of claim 18 , wherein the second hole transport layer has a glass transition temperature that is 15° C. to 35° C. higher than the glass transition temperature of the first hole transport layer.

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