Game machine

Abstract

To aim for technical improvement in a game machine.SOLUTION: A game machine of the present invention includes: CPU means for generating first information specifying an image performance by a display device and second information specifying an audio performance; and transfer means for transferring the first information and the second information to a first circuit and a second circuit via a predetermined transmission path. The first information and / or the second information are / is configured to be stored in an address area of an internal RAM or an external RAM starting from a start address where predetermined bits or less are zero.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a technology relating to a gaming machine such as a pinball gaming machine. [Background technology]

[0002] A pinball game machine such as a pachinko machine is configured with a symbol start opening on the game board, a symbol display unit that displays a series of symbol changes based on multiple displayed symbols, and a jackpot opening with an opening / closing plate. When a detection switch on the symbol start opening detects the passage of a game ball, the machine enters a winning state. After the game ball is paid out as a prize ball, the displayed symbols on the symbol display unit change for a predetermined period of time. When the symbols then stop in a predetermined pattern, such as 7-7-7, the machine enters a jackpot state, and the jackpot opening is repeatedly opened, creating a game state advantageous to the player.

[0003] Whether or not such a game state occurs is determined by a jackpot lottery, which is executed on the condition that a gaming ball enters the symbol start slot, and the above-mentioned symbol variation action is based on the result of this lottery. For example, if the lottery result is a winning state, a presentation action called a reach action is executed for about 20 seconds, and then special symbols are aligned. On the other hand, a similar reach action may be executed even in a losing state, and in this case, the player will closely watch the progression of the presentation action while strongly hoping for a jackpot state. Then, if the predetermined symbol is aligned on the stop line at the end of the symbol variation action, the player is guaranteed a jackpot state.

[0004] The following patent documents can be cited as examples of related prior art. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-040883 [Patent Document 2] Japanese Patent Publication No. 2020-065707 [Patent Document 3] Japanese Patent Publication No. 2020-022673 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to provide a technical improvement to gaming machines. [Means for solving the problem]

[0007] The gaming machine of the present invention is provided with a CPU means for generating first information that specifies an image presentation by a display device and second information that specifies an audio presentation, and a transfer means for transferring the first information and second information to a first circuit and a second circuit via a predetermined transmission path, and the first information and / or second information is configured to be stored in an address area of ​​an internal RAM or an external RAM starting from a starting address where a predetermined number of bits or less are zero. [Effects of the Invention]

[0008] According to the present invention, it is possible to achieve technical improvements in gaming machines. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a gaming machine according to a first embodiment; [Figure 2] 2 is a front view showing the gaming area of ​​the gaming machine of FIG. 1. [Figure 3] FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] This diagram illustrates the internal configuration of the performance interface board, performance control board, and liquid crystal interface board. [Figure 5] FIG. 1 is a circuit block diagram illustrating a composite chip including its associated circuit elements. [Figure 6] 1 is a diagram illustrating an index space and a virtual drawing space. [Figure 7] 1 is a diagram illustrating a display circuit. [Figure 8] 1 is a diagram illustrating an internal configuration of a data transfer circuit. [Figure 9] 10 is a diagram for explaining the transfer operation of a display list and a voice command list. [Figure 10] 10 is a diagram illustrating a filter process based on a display list. [Figure 11] 1 is a diagram illustrating a procedure for playing back IPB streaming video. [Figure 12] 1 is a diagram illustrating the internal configuration and control procedure of an audio processing unit. [Figure 13] 10 is a diagram for explaining a drawing pipeline process of a drawing circuit. [Figure 14] FIG. 1 is a process diagram illustrating various rendering modes that utilize all or part of the rendering pipeline steps. [Figure 15] 10 is a flowchart illustrating the control operation of a performance control CPU that does not include a preload operation. [Figure 16] 16 is a flowchart illustrating a part of FIG. 15. [Figure 17] 10 is a flowchart illustrating the control operation of the performance control CPU, including the preload operation. [Figure 18] FIG. 10 is a block diagram for explaining the schematic circuit configuration of a gaming machine according to a second embodiment. [Figure 19] An explanatory diagram of an example of signals communicated between the payout control board and the ball dispensing machine in the second embodiment. [Figure 20] A diagram showing an example of the arrangement of various electronic components on a dispensing control board in the second embodiment. [Figure 21] FIG. 10 is a circuit diagram showing a connection between an external connector and each insulating transmission means in a second embodiment. [Figure 22] FIG. 10 is a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. [Figure 23]FIG. 10 is also a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. [Figure 24] FIG. 10 is also a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. [Figure 25] 10 is a diagram showing an example of a wiring pattern on the surface (component mounting surface) of a dispensing control board in the second embodiment. FIG. [Figure 26] A diagram showing an example of a wiring pattern on the back surface of a dispensing control board in the second embodiment. [Figure 27] FIG. 10 is an explanatory diagram illustrating an example of the arrangement of insulating transmission means in the second embodiment. [Figure 28] An explanatory diagram showing the positions of various connectors on the dispensing control board in the second embodiment. [Figure 29] A schematic cross-sectional view to explain an example of the formation pattern of separation sections and grounds in a dispensing control board as a second embodiment. [Figure 30] FIG. 10 is an explanatory diagram relating to the width of a separation portion in the second embodiment. [Figure 31] An explanatory diagram of a communication board provided in a gaming machine as a first modified example in the second embodiment. [Figure 32] FIG. 10 is an explanatory diagram of a communication board provided in a gaming machine as another example of the first modified example in the second embodiment. [Figure 33] An explanatory diagram of a communication board provided in a gaming machine as a second modified example in the second embodiment. [Figure 34] FIG. 10 is an explanatory diagram of a communication board provided in a gaming machine as another example of the second modified example in the second embodiment. [Figure 35] FIG. 10 is a perspective view showing the appearance of a gaming machine according to a third embodiment. [Figure 36] This is an oblique view of the gaming machine with the front frame open. [Figure 37] FIG. [Figure 38] FIG. [Figure 39] 10 is a diagram illustrating the main display and the fourth pattern display. FIG. [Figure 40] FIG. 2 is a block diagram showing the control configuration of the gaming machine. [Figure 41] FIG. 2 is a block diagram showing the control configuration of the gaming machine. [Figure 42] FIG. 10 is a diagram illustrating a screen displayed on the LCD unit. [Figure 43] 10 is a flowchart showing the main processing on the main control side. [Figure 44] 10 is a flowchart showing the main control side timer interrupt processing. [Figure 45] 10 is a flowchart showing a frame control side main process. [Figure 46] 10 is a flowchart showing a timer interrupt process on the frame control side. [Figure 47] 10 is a flowchart showing the main processing on the performance control side. [Figure 48] 10 is a flowchart showing the timer interrupt processing on the performance control side. [Figure 49] A diagram showing an example of a jackpot determination table and a pattern table. [Figure 50] FIG. 10 is a diagram showing an example of a fluctuation pattern table. [Figure 51] FIG. 10 is a diagram showing the presentation means used when executing the SP presentation. [Figure 52] This is a diagram explaining the flow of the SP performance. [Figure 53] FIG. 10 is a diagram showing an example of a special presentation. [Figure 54] FIG. 10 is a diagram showing an example of a special presentation. [Figure 55] FIG. 10 is a diagram showing an example of a special presentation. [Figure 56] FIG. 10 is a diagram showing an example of a special presentation. [Figure 57] This is a diagram showing a time chart of the presentation means for the notification presentation at the time of a jackpot. [Figure 58] FIG. 10 is a diagram showing an example of a special presentation. [Figure 59]FIG. 10 is a diagram showing an example of a special presentation. [Figure 60] FIG. 10 is a diagram showing an example of a special presentation. [Figure 61] FIG. 10 is a diagram showing an example of a special presentation. [Figure 62] A diagram showing the LED light emission pattern during notification performance. [Figure 63] 10A and 10B are diagrams showing modified examples of light emission patterns. [Figure 64] FIG. 2 is a diagram illustrating the configuration of a main display device. [Figure 65] FIG. 2 is a diagram illustrating the circuit configuration around the main control unit on the main control board. [Figure 66] FIG. 2 is a diagram illustrating a circuit configuration related to display control of a main display on a main control board. [Figure 67] FIG. 2 is a diagram illustrating the circuit configuration of a main display board. [Figure 68] FIG. 2 is a view of the gaming machine from the rear side. [Figure 69] 10A and 10B are diagrams illustrating the structure of a frame control board. [Figure 70] FIG. 10 is a diagram illustrating the configuration of a game ball number display. [Figure 71] 10 is a diagram illustrating the circuit configuration around the frame control unit on the frame control board. FIG. [Figure 72] 10 is a diagram illustrating a circuit configuration related to display control of a performance indicator on a frame control board. FIG. [Figure 73] 10 is a diagram illustrating the circuit configuration around a predetermined connector on the frame control board. FIG. [Figure 74] A diagram explaining the circuit configuration of the game ball number display board. [Figure 75] A diagram explaining the structure of the fourth pattern display device. [Figure 76] This is a diagram showing part of the circuit configuration of the decorative relay board that relays between the performance control board and the fourth pattern display board. [Figure 77] A diagram explaining the circuit configuration of the fourth pattern display board. [Figure 78] FIG. 10 is a diagram showing the circuit configuration of a main control board in Modification 1. [Figure 79] A diagram explaining the fourth pattern display device in variant example 2. [Figure 80] This is a diagram showing various values ​​related to the LEDs of the main display, performance display, number of game balls display, and fourth pattern display. [Figure 81] FIG. 10 is a diagram showing various values ​​related to the LEDs of the main display and performance display A of the first modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. <1. First embodiment> 2. Second Embodiment [2.1 Overview of communication functions with external devices and communication board configuration] [2.2 Example of substrate configuration as second embodiment] (2.2.1 Configuration example A) (2.2.2 Configuration example B) (2.2.3 Configuration example C) (2.2.4 Configuration example D) (2.2.5 Configuration examples E, F) [2.3 First Modification (Configuration Example G)] [2.4 Second Modification (Configuration Example H)] [2.5 Other Modifications] 3. Third Embodiment [3.1 Structure of the gaming machine in the third embodiment] [3.2 Control configuration of gaming machine in third embodiment] (3.2.1 Main control board) (3.2.2 Frame control board) (3.2.3 Power supply board) (3.2.4 Performance control board) [3.3 Overview of operation] (3.3.1 Game Status) (3.3.2 Special symbol variation display game) (3.3.3 Jackpot Games) (3.3.4 Regular symbol variation display game) (3.3.5 Screen displayed on LCD unit) [3.4 Processing the main control board] (3.4.1 Main control side main processing) (3.4.2 Main control side timer interrupt processing) [3.5. Processing of frame control board] (3.5.1 Main processing on the frame control side) (3.5.2 Timer interrupt processing on the frame control side) [3.6 Processing of the performance control board] (3.6.1 Main processing on the performance control side) (3.6.2 Performance control side timer interrupt processing) [3.7 Effects based on fluctuation patterns] (3.7.1 Lottery for Special Variable Display Game in Main Control Unit) (3.7.2 Production methods used in SP production) (3.7.3 SP Production) [3.8 Lighting patterns of LEDs for effects] [3.9 Configuration example of the third embodiment] 4. Fourth Embodiment [4.1 LEDs on the main control board] [4.2 LEDs on the frame control board] [4.3 LEDs on the performance control board] 4.4 Modification of the Fourth Embodiment (4.4.1 Variation 1) (4.4.2 Variation 2) [4.5 Configuration example of the fourth embodiment]

[0011] <1. First embodiment> FIG. 1 is a perspective view showing a gaming machine GM according to a first embodiment. This gaming machine GM is configured as a pachinko machine and includes a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached so as to be able to open and close via hinges 2 fixed to the outer frame 1. A gaming board 5 is detachably attached to the inner frame 3 from the front side, not from the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be able to open and close. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the "front door member." The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may also be referred to as the "game frame."

[0012] Illuminated lamps such as LED lamps are arranged in a roughly C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right sides and on the lower side of the glass door 6. The two upper speakers output audio for the left and right channels R and L, respectively, and the lower speaker is configured to output low-pitched sounds.

[0013] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0014] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is normally inactive, but when the game state is in the button chance state, a built-in lamp lights up and the button becomes operable. The button chance state is a game state that is set as needed.

[0015] In addition, a rotary switch-type volume switch VLSW is located below the chance button 11, and by operating the volume switch VLSW, the player can adjust the speaker volume in eight stages, from silent (=0) to the highest level (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial setting volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality alert sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume, regardless of the volume initially set by the attendant or the volume set by the player.

[0016] On the right side of the upper tray 8, there is provided an operation panel 12 for operating the ball lending operation for the card-type ball lending machine, which is provided with a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of game balls for a specified amount, and a return switch that commands the return of the card when the game ends.

[0017] As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in approximately the center of the guide rail 13. A movable effect body (not shown) is stored in a concealed state below the central opening HO, and during the movable preview effect, the movable effect body rises and becomes exposed, thereby realizing a preview effect with a predetermined reliability. Here, the preview effect is an effect that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the preview effect means the probability that the jackpot state will occur.

[0018] A display device DS consisting of a large (for example, 1280 horizontal x 1024 vertical pixels) liquid crystal color display is disposed in the central opening HO. The display device DS is composed of a main liquid crystal display section MONI and an LED backlight section BL, and is a device that variably displays specific symbols related to the jackpot state, as well as animated background images and various characters. This display device DS has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right corner. The special symbol display sections Da-Dc may execute reach effects that raise expectations for the arrival of a jackpot state, and appropriate preview effects are executed in and around the special symbol display sections Da-Dc.

[0019] The game area where the game balls fall and move is provided with a first symbol start opening 15a, a second symbol start opening 15b, a first big prize opening 16a, a second big prize opening 16b, a normal prize opening 17, and a gate 18. Each of these winning openings 15 to 18 has a detection switch inside, so that it can detect the passage of the game balls.

[0020] Above the first symbol start opening 15a, there is arranged a performance stage 14 configured so that the gaming ball that has entered from the introduction opening IN can move in a seesaw or roulette shape and then enter the first symbol start opening 15. When the gaming ball enters the first symbol start opening 15, the variable operation of the special symbol display sections Da to Dc is started.

[0021] The second pattern starting port 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0022] The normal symbol display unit 19 displays normal symbols, and when a gaming ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time and stops by displaying a stopping symbol determined by a random number value for lottery that is extracted at the time the gaming ball passes through the gate 18.

[0023] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first symbol starting opening 15a, and the second large prize opening 16b is configured to correspond to the first symbol starting opening 15b.

[0024] In other words, when a game ball enters the first pattern start port 15a, the special pattern display sections Da to Dc begin to change, and then when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the slide plate of the first jackpot entry port 16a opens forward, making it easier for the game ball to enter.

[0025] On the other hand, as a result of the varying operation initiated by the entry of a gaming ball into the second symbol start opening 15b, when a predetermined jackpot symbol is aligned in the special symbol display sections Da to Dc, a special game representing a second jackpot is initiated, and the opening and closing plate of the second large winning opening 16b is opened to facilitate the entry of the gaming ball. The gaming value of the special game (jackpot state) varies depending on the aligned jackpot symbols, etc., but which gaming value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the gaming ball.

[0026] In a typical jackpot state, after the opening / closing plate of the jackpot opening 16 is opened, the opening / closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered. This operation may continue up to, for example, 15 times, and is controlled to be advantageous to the player. If the stopped symbol after the change of the special symbol display sections Da to Dc is a specific symbol among the special symbols, a special benefit is given in which the game after the special game ends will be in a high probability state (probability variable state).

[0027] Fig. 3(a) is a block diagram showing the overall circuit configuration of the gaming machine GM that realizes the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT arranged on the payout control board 25. As shown in Figure 3(a), this gaming machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) together with AC 24V, a main control board 21 that is responsible for central and overall game control operations, a presentation interface board 22 that is equipped with a digital amplifier 29 for audio presentation, a presentation control board 23 that executes lamp presentations, audio presentations, and image presentations in a unified manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the presentation control board 23 and the display device DS, a payout control board 25 that controls the payout motor M to pay out game balls based on control commands CMD' received from the main control board 21, and a launch control board 26 that launches game balls in response to player operations.

[0028] Figure 4 is a slightly more detailed illustration of a portion of Figure 3(a), and shows the internal configuration of the performance interface board 22, performance control board 23, and LCD interface board 24. As shown in Figures 4 and 3(a), the performance interface board 22, performance control board 23, and LCD interface board 24 are directly connected via male and female connectors without using wiring cables. This makes it possible to minimize the storage space for the entire board even if the circuit configuration of each electronic circuit is made complex and advanced, and by shortening the connection lines, noise resistance can be improved.

[0029] As shown in Figure 3(a), the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel twice, each 8 bits long.

[0030] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 incorporating computer circuits such as an overall performance circuit 52 and an internal CPU circuit 51. Therefore, in this specification, the main control unit 21, the performance control unit 23, and the payout control unit 25 are sometimes referred to functionally as the control boards 21, 25, and 23, the circuits mounted on the performance interface board 22, and the LCD interface board 24, and the operations realized by these circuits. The performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0031] This gaming machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Figure 3(a) and a board side member GM2 fixed to the back of the gaming board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 outside of that, and is installed in a fixed position in the gaming hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All members except the frame side member GM1 are board side members GM2.

[0032] As shown in the dashed-line frame in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are each fixed in appropriate locations on the inner frame 3. Meanwhile, a main control board 21 and a performance control board 23 are fixed to the back of the gaming board 5, along with a display device DS and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3, which are centrally located in one place.

[0033] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0034] The DC 35V is used to drive the ball-feeding solenoid and launch solenoid involved in the launching of gaming balls, and to drive the electromagnetic solenoids that open and close the electric tulip (variable winning device) and the large winning slot 16. The DC 12V is used to drive the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier, while the DC 5V is used as the power supply voltage for the one-chip microcomputers on the payout control board 25 and main control board 21, and for the logic elements mounted on each control board. The DC 5V is stepped down by the DC / DC converters on the performance interface board 22 and performance control board 23, and the stepped down voltages at various levels are then used as the power supply voltage for various computer circuits (such as the composite chip 50).

[0035] The backup power supply BAK is a DC 5V power supply for maintaining the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0036] On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with an electric double layer capacitor that can retain the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0037] In this embodiment, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC voltage AC24V, is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that is powered by the DC voltage 5V received from the power supply board 20 and turns ON based on the light emitted by the photodiode D, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON state of the phototransistor TR. The photodiode D and phototransistor TR together form a photocoupler PH.

[0038] In the above configuration, after power is turned on, the photocoupler PH quickly switches to the ON state, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power subsequently drops abnormally for some reason (normally due to a power outage), the photocoupler PH switches to the OFF state, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer on the payout control board 25 and also to the one-chip microcomputer on the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal-level power supply abnormality signal ABN executes a backup process to store necessary information in its own internal RAM. As explained above, the information in the internal RAM is maintained by the backup power supply BAK, allowing game operation to resume as it was before the power was turned off after power is turned on.

[0039] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 that has built-in computer circuits such as a general performance circuit 52 and an internal CPU circuit 51, and the LCD interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) that stores performance data, and a power supply control circuit SPY.

[0040] In this embodiment, the integrated effect circuit 52 built into the composite chip 50 includes a video display processor (VDP), an audio processor (SND), a motor controller MT_CTL, and a lamp controller L_CTL. Based on control from the built-in CPU circuit 51, the integrated effect circuit 52 operates intermittently with an operating period δ (= 1 / 30 seconds) to execute image effects using the display device DS, audio effects that drive speakers via the digital amplifier 29, motor effects that rotate effect motors M1 to Mn to move props, and lamp effects that flash LED lamps, etc. In the following description, the built-in CPU circuit 51 may be abbreviated as the CPU circuit 51.

[0041] When power is turned on, the reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20, and resets the power supply to the internal circuits and other electronic elements of the composite chip 50. As explained above, the internal circuits of the composite chip 50 include a video display processor (VDP) and an audio processor (SND), and the power reset signal is nothing more than the system reset signal SYS of the composite chip 50, and synchronously resets the power supply to the CPU circuit 51 and the overall performance circuit 52.

[0042] In this embodiment, while the system reset signal SYS is asserted low, all internal circuits are uniformly initialized and default values ​​are set in the performance control register RGij of the composite chip 50. After that, when the system reset signal SYS transitions to high level, the boot program is started and the necessary initial setting operations are performed on the performance control register RGij. On the other hand, if the DC voltage drops to 5V (usually when the power is cut off), the system reset signal SYS drops to low level, and the CPU circuit 51 and the overall performance circuit 52 of the performance control board 23 are put into a stopped state.

[0043] As will be described later, this embodiment is configured so that the system reset signal SYS does not change even when the WDT (Watch Dog Timer) circuit 58 is activated, and so not all internal circuits are initialized uniformly even in the event of an abnormality that activates the WDT 58. In other words, this embodiment is configured so that predetermined internal circuits that are arbitrarily selected are initialized.

[0044] Next, the clock circuit 38 and effect data memory 39 mounted on the liquid crystal interface board 24 are driven by a secondary battery (not shown), and this secondary battery is charged appropriately during game operation by the power supply voltage from the power supply board 20. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 continues, and the game performance information stored in the effect data memory 39 is permanently stored and held (non-volatile).

[0045] The clock circuit 38 is configured to be able to output an interrupt signal (RTC interrupt) to the CPU circuit 51. This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed, but in this embodiment, an alarm interrupt IRQ_RTC is used that updates the daily gaming performance information at the end of business each day.

[0046] As shown in Figure 3(a), the payout control board 25 and the main control unit 21 are each equipped with reset circuits RST1 and RST2, and are configured so that when the power is turned on, a power reset signal is generated and the power to each computer circuit is reset. In this way, in this embodiment, the main control unit 21, the payout control unit 25, and the performance interface board 22 are each equipped with reset circuits RST1 to RST3, and for example, a system reset signal generated by the power supply board 20 is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0047] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the dispensing control unit 25 each incorporate a watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, the CPU is forcibly reset. The main control unit 21 is also provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire RAM area of ​​the one-chip microcomputer of each control unit 21, 25.

[0048] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball count signal indicating the payout operation of game balls, a status signal CON relating to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0049] The main control unit 21 also receives switch signals from the detection switches built into each winning slot 16-18 on the gaming board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Furthermore, each switch signal indicating the winning status of the symbol start slot 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and the power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0050] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connector C2 (see Figures 3(a) and 4). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as a drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the game frame and is used as a drive voltage for solenoids that move movable objects back and forth.

[0051] Meanwhile, the 5V DC voltage is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to the DC / DC converter DC to generate 3.3V (see Figure 4). The generated 3.3V DC voltage then becomes the base voltage for the power reset signal (system reset signal) SYS generated by the reset circuit RST3. The 5V DC voltage distributed to the performance interface board 22 is then distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as a power supply voltage to the composite chip 50 and external ROM 55.

[0052] 4, two DC / DC converters DC1 and DC2 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the VRAM 53 and the expansion RAM 54. Therefore, the DC voltage of 1.5V is also supplied to the VRAM 53 and the expansion RAM 54 as a power supply voltage.

[0053] As shown in Figure 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Figure 4, the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 57 acquires the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0054] 4, the input buffer 44 of the performance interface board 22 receives switch signals from the chance button 11 and the volume switch VLSW from the frame relay board 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW, and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0055] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, in FIG. 4, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives outputs SN0 to SNn from origin sensors that grasp the current positions of the movable performance objects (the rotational positions of the performance motors M1 to Mn), and transmits these to the motor control unit MT_CTL of the performance control board 23.

[0056] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers to each driver IC serial signals received from the lamp control unit L_CTL and motor control unit MT_CTL of the performance control board 23. Specifically, the serial signals are lamp (motor) drive signal SDATA and clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronization system, executing lamp performances using numerous LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn.

[0057] In this embodiment, the lamp effects are performed by three systems of lamp groups CH0 to CH2, and the driver IC of the lamp drive board 37 receives the lamp drive signal SDATA0 for CH0 output by the lamp control unit L_CTL in synchronization with the clock signal CK0 via the frame relay board 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO 62) changes to the active level, thereby updating the lighting status of the lamp group CH0 all at once.

[0058] The same applies to the lamp drive board 30, and the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for the lamp group CH1 output from the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually, PIO 62) changes to the active level, the lighting states of the lamp group CH1 are updated all at once.

[0059] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted in clock synchronization from the motor control unit MT_CTL to drive the lamp group CH2, and also receives a motor drive signal transmitted in clock synchronization to drive the performance motor group M1-Mn, which is made up of multiple stepping motors. Because the lamp drive signal and the motor drive signal are the same type of serial signal, a series of composite serial signals SDATA2 is output from the motor control unit MT_CTL in synchronization with the clock signal CK2, and the driver IC that receives this updates the drive status of the lamp group CH2 and the motor group M1-Mn when the operation control signal ENABLE2 changes to the active level.

[0060] In this embodiment, for convenience, the motor control unit MT_CTL is in charge of the motor and lamp effects for the motor lamp drive board 31, and therefore the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Note that the lamp drive signals SDATA0 and SDATA1 for the lamp drive board 37 and the lamp drive board 30 may also be configured to be output from the motor control unit MT_CTL.

[0061] 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is chip-selected by a chip select signal, the CPU circuit 51 can arbitrarily access the internal registers (which have 4-bit address values).

[0062] In addition, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus.When the chip is selected, the game performance information and other data stored in the SRAM (performance data memory) 39 can be accessed by the CPU circuit 51 via R / W as appropriate.

[0063] Furthermore, a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL is mounted on the liquid crystal interface board 24. Specifically, the power supply control circuit SPY controls the start timing of supplying power supply voltages of 12V and 5V to the display device DS and the backlight board BL using a control signal STBY, and controls the brightness of the backlight light and the start timing of light emission using a control signal PWM.

[0064] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 that incorporates a CPU circuit 51 and an overall performance circuit 52, a VRAM 53 that is accessed via R / W at high speed from the CPU circuit 51 and the overall performance circuit 52, an expansion RAM 54 that can store large amounts of data, and an external ROM 55 that stores CG data and other data in a non-volatile manner.

[0065] The VRAM 53 is capable of high-speed access with a theoretical transfer rate of approximately 102 GB / sec and has a storage capacity of approximately 48 MB. The VRAM 53 is primarily used (1) to store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see FIG. 5(a)). It can also (2) store copies of data from the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0066] The expansion RAM 54 can operate at a theoretical transfer rate of approximately 17.0 GB / sec, has a storage capacity of approximately 1 GB, and can be used in the same manner as the VRAM 53. That is, the expansion RAM 54 can (1) store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) store copies of data in the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0067] The external ROM 55 in this embodiment is a non-volatile storage device that stores a boot program that starts when the power is turned on, a control program for the CPU circuit 51 that realizes performance control, control data including lamp drive data, compressed CG data for image performance, and compressed audio data for audio performance. The storage capacity of the external ROM 55 is approximately 256 GB at maximum, but high-speed access is not possible. Therefore, in this embodiment, a portion of the data in the external ROM 55 is transferred to the expansion RAM 54 when the power is turned on. Specifically, the control program and control data that operate the CPU circuit 51 are transferred and copied from the external ROM 55 to the expansion RAM 54 by the boot program stored in the external ROM 55 when the power is turned on.

[0068] 5(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including its associated circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL and a voice command list VC, and an overall performance circuit 52 that executes image performances based on the display list DL, executes voice performances based on the voice command list VC, and executes lamp and motor performances. The CPU circuit 51 and the overall performance circuit 52 are connected via a CPU bus unit 56 that relays data sent and received between them.

[0069] First, we will explain the CPU bus unit 56 located between the CPU circuit 51 and the overall performance circuit 52. As shown in Figure 5(a), the CPU bus unit 56 is connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via the VRAM IF unit 53a, the extended RAM IF unit 54a, and the CG bus IF unit 55a. Therefore, in this embodiment, the VRAM 53, the extended RAM 54, and the external ROM 55 can be accessed not only by the overall performance circuit 52 but also by the CPU circuit 51.

[0070] The VRAMIF unit 53a, the extended RAMIF unit 54a, and the CG busIF unit 55a are connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via an arbitration circuit ICM (Inter Connect Module) not shown. The arbitration circuit ICM is located between each functional block of the overall performance circuit 52 and the VRAMI / F unit 53a, the extended RAMI / F unit 54a, and the CG bus I / F unit 55a, and arbitrates data requests issued by each functional block as appropriate to establish the required connection relationships.

[0071] In any case, the CPU circuit 51 of this embodiment can access the VRAM 53, the expansion RAM 54, and the external ROM 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external ROM 55 to the expansion RAM 54 when the power is turned on, it does not access the external ROM 55. In other words, after the copy operation, the CPU circuit 51 executes control operations based on the control program and control data copied to the expansion RAM 54.

[0072] The CPU circuit 51 can read / write access various performance control registers RGij to control the internal operation of the overall performance circuit 52. The data transfer circuit 70 can also transmit and receive data between the CPU circuit 51 and the overall performance circuit 52 via the CPU bus unit 56. Data transmission from the CPU circuit 51 to the overall performance circuit 52 includes issuing a display list DL and a voice command list VC.

[0073] As shown on the right side of Figure 5(a), the overall performance circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphics Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND, and the performance control register RGij is used to enable the CPU circuit 51 to appropriately control these internal circuits of the overall performance circuit 52.

[0074] Therefore, the performance control register RGij is broadly divided into (1) data transfer register, (2) display register, (3) preload register, (4) GDEC register, (5) drawing register, (6) image filter register, (7) index table register, (8) MT_CTL register, (9) L_CTL register, (10) sound register, etc., corresponding to each of the above circuits (1) to (10), and a system control register is provided for overall system control (see Figure 5(b)). Note that the system control register and each of the registers (1) to (10) for individual circuits are actually composed of multiple register groups that are further divided.

[0075] Based on the above, we will now explain the CPU circuit 51. The CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcomputer, and as shown on the left side of Figure 5(a), it is configured with a performance control CPU 57 that comprehensively controls image / audio / lamp / motor performances based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU if the program goes out of control, an internal RAM 59 with a storage capacity of about 2 MB that is used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without going through the performance control CPU 57, a serial input / output port (SIO) 61 having multiple input ports Si and output ports So, a parallel input / output port (PIO) 62 having multiple input ports Pi and output ports Po, and an operation control register REG in which setting values ​​are set to control the internal configuration of the CPU circuit 51.

[0076] For convenience, the term "input / output port" is used in this specification, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0077] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port 62 via the input / output circuit 64p.

[0078] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby activating the reception interrupt process. Based on the reception interrupt process, the performance control CPU 57 grasps the control command CMD and, through a performance lottery or the like, performs unified control of the audio performance, lamp performance, motor performance, and image performance corresponding to the control command CMD. The parallel input / output port 62 outputs operation control signals ENABLE0 to ENABLE1 for the lamp performance via the input / output circuit 64p.

[0079] Furthermore, the serial input / output port (SIO) 61 is configured to be able to transmit and receive serial signals via the input / output circuit 63s. Therefore, as shown by the dashed lines in Figure 5(a), a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA can also be output via the input / output circuit 63s internally connected to the serial input / output port SIO 61. However, in this embodiment, lamp / motor effects are realized using the lamp control unit L_CTL and motor control unit MT_CTL of the overall effect circuit 52 without using the serial input / output port 61.

[0080] Incidentally, a DL buffer BUF for sequentially updating and storing a display list DL in which a series of instruction commands specifying one frame of the display device DS are listed is secured in the built-in RAM 59 of the CPU circuit 51. Furthermore, this DL buffer BUF is configured by partitioning areas, and also sequentially updating and storing a voice command list VC specifying the performance contents of the voice performance.

[0081] In this embodiment, the instruction commands of the display list DL that define one frame of the display screen include (1) index table control commands related to the index table IDXTBL that manages the index space, (2) texture load commands such as the LOADTX command for reading and decoding (decompressing / expanding) image material (texture) from the external ROM 55, (3) filter execution commands that specify filter processing for the decompressed image data, (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space, (5) pipeline commands related to drawing pipeline operation, and (6) overall control commands that define the overall operation of the overall performance circuit 52. The display list DL is configured to list an appropriate number of instruction commands and then terminate with a predetermined end command EODL (32 bits long). In addition, the voice command list VC, which specifies the operation of the voice processing unit SND that executes the voice performance, lists an appropriate number of voice commands and then concludes with a predetermined termination command EOSC (32 bits long). Here, the voice commands are roughly divided into track-related commands that specify the operation of the pre-processing unit FT shown in Fig. 12(a), master effect-related commands that specify the operation of the post-processing unit BK shown in Fig. 12(a), and other system-related commands, and all voice commands are composed of an integer multiple (>0) of 32 bits.

[0082] As will be described later, the rendering pipeline operation of this embodiment is executed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer, and is configured to include an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The pipeline command (5) above functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0083] Incidentally, texture is generally a concept that refers to the feel and texture of an object's surface, but in this specification, the term texture is used to collectively refer to image data before and after decoding. For example, sprite image data that makes up a still image, frame image data that makes up one frame of video, and pasted image data that is pasted onto drawing primitives such as triangular polygons and quadrilateral polygons are also referred to as textures.

[0084] Then, (2) the texture is read from external ROM 55 and decoded by the LOADTX command, a texture load command. (5) The source image data is set to be a texture by the SETTXINDEX command, which is a texture sampler process TX command included in the pipeline commands. (4) The texture is then virtually drawn in the virtual drawing space shown in Figure 6(c) by the SPRITE command, a drawing command. The contents drawn in the virtual drawing space are output to the display device DS via the frame buffer FB, which will be described later.

[0085] The index space managed by the index table control command (1) above refers to a one-dimensional or two-dimensional memory work area (logical address space) used by the overall performance circuit 52 during drawing operations, etc. This index space is specified as a one-dimensional or two-dimensional logical address space by the index number written in the instruction command of the display list DL.

[0086] That is, in this embodiment, an index space is reserved in an appropriate location in memory (VRAM 53 and expansion RAM 54) that can be accessed as a memory work area, and this is specified by an index number. Also, the VRAM 53 and expansion RAM 54 are divided into virtual work areas (AAC area, page area, arbitrary area), and an index space can be reserved for each (see Figures 6(a) and 6(b)). Therefore, the index number becomes a unique value for each virtual work area, which simplifies texture load commands, filter execution commands, drawing commands, pipeline commands, etc.

[0087] It also allows for individual operation for each virtual work area (AAC area, page area, arbitrary area). For example, in the AAC area, index space is automatically reserved as an area for expanding decoded data, and then automatically released. Therefore, index numbers are not required in the ACC area.

[0088] Specifically, the virtual work area (AAC area, page area, arbitrary area) is defined during the initial processing after power-on, and the necessary index space is secured in the necessary virtual work area at the necessary timing thereafter. The secured index space is then linked to the index number and managed by the index table IDXTBL, thereby realizing subsequent operations based on the index number.

[0089] The relationship between the virtual work area and the actual work areas of VRAM 53 and expansion RAM 54 will be explained below. First, VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other optional areas. Specifically, in the initial processing after power-on, an appropriate starting address and area data size for VRAM 53 are set in the corresponding performance control register RGij, thereby securing the shared area of ​​VRAM 53. Then, areas other than the shared area secured in VRAM 53 automatically become optional areas of VRAM 53 (Figure 6(a)).

[0090] The shared area reserved in VRAM 53 can be used as both an ACC area, which does not require management of index numbers, and a page area, which requires management of index space using index numbers. Therefore, when using a shared area, you simply specify that index space is reserved in the AAC area with the SETTXINDEX command, and then specify the size and storage address of the texture (image material) with the LOADTX command, and the decompressed data of the read texture can be expanded in the index space automatically reserved in the ACC area.

[0091] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, for still images and I-stream moving images (S-stream moving images consisting only of I-pictures, which will be described later), decoded data is developed in the AAC area of ​​the VRAM 53. That is, in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as an AAC area.

[0092] Next, in the initial processing after power-on, the expansion RAM 54 secures a page area in the expansion RAM 54 by setting the starting address and area data size in the expansion RAM 54 in the corresponding performance control register RGij, and the remaining area becomes an arbitrary area in the expansion RAM 54 (FIG. 6(b)). Here, the "arbitrary area" refers to an area in the expansion RAM 54 and VRAM 53 that can be used arbitrarily, and can be used not only for securing index space but also for other purposes. Therefore, in this embodiment, a preload area for pre-transferring (preloading) CG data acquired from the external ROM 55 is secured in an arbitrary area in the expansion RAM 54 (see FIG. 6(b)), and a preload buffer for storing a rewrite list DL' obtained by the preloader 72 rewriting the display list DL is secured in an arbitrary area in the VRAM 53 (see FIG. 6(a)).

[0093] In this embodiment, the control program and control data stored in the external ROM 55 are transferred and copied to any area of ​​the extended RAM 54 when the power is turned on (see FIG. 6(b)). Of course, all or part of the control program and control data may be transferred and copied to the VRAM 53 instead of the extended RAM 54. Furthermore, the control program and control data are not limited to being transferred and copied, and all or part of CG compressed data and audio compressed CG data may also be transferred and copied to the RAMs 53 and 54.

[0094] In any case, the index space can be allocated appropriately in the extended RAM 54 and VRAM 53 in (1) the ACC area, (2) the VRAM page area, (3) the VRAM optional area, (4) the extended RAM page area, and (5) the extended RAM optional area, but in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as the AAC area. However, the area allocated as a shared area in the VRAM 53 can be used as both a page area and an AAC area, so the following explanation will be based on this point.

[0095] When reserving index space in the page area of ​​the VRAM 53, it is necessary to set an index number and space size in a predetermined performance control register RGij for the VRAM. Furthermore, the index space in the page area of ​​the expansion RAM 54 is reserved by setting an index number and space size in a predetermined performance control register RGij for the expansion RAM. In this embodiment, the page area of ​​the expansion RAM 54 is used to expand video frames. In addition, in the page area, the starting address of the index space is determined appropriately based on internal processing, which is convenient as it eliminates the need to manage the starting address. In other words, when reserving index space in the page area, there is no need to worry about overlap with existing index space.

[0096] On the other hand, when a two-dimensional index space is secured in any area of ​​the VRAM 53 or any area of ​​the extended RAM 54, it is necessary to set the index number, the starting address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. Note that in the case of a one-dimensional index space, the vertical size is not necessary.

[0097] In this way, when an index space is allocated in an arbitrary area, the starting address and size can be set precisely, which has the advantage of allowing for efficient memory use. Therefore, in this embodiment, image data for one frame of the display device DS is completed and the frame buffer FB is allocated as a two-dimensional index space in an arbitrary area of ​​the VRAM 53 (see FIG. 6(a)). Of course, the frame buffer FB may also be allocated in an arbitrary area of ​​the expansion RAM 54.

[0098] The frame buffer FB allocated in any area of ​​the VRAM 53 corresponds to the drawing area of ​​the virtual drawing space that is the drawing target for drawing commands such as the SPRITE command. Figure 6(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the frame buffer FB that stores image data to be output to the display device DS.

[0099] One frame of image data for the display screen is written into the frame buffer FB by the drawing circuit 74, while one frame of image data for the display screen is read out by the display circuit 71. The frame buffer FB has a double buffer structure consisting of a pair of index spaces, and is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0100] For the display circuit 71, the first buffer and the second buffer are read-out areas for image data, and the image data in the first buffer and the second buffer are read out in sequence for each operating cycle δ by toggling the index numbers N1 / N2 based on the information embedded in a predetermined display register RGij.

[0101] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are areas for writing image data, and image data is written alternately to the first buffer and the second buffer by toggling the index numbers N1 / N2 every operating period δ based on the instruction command on the display list DL.

[0102] The writing operation of the drawing circuit 74 corresponds to the reading operation of the display circuit 71, so that image data written to the first buffer in one operation cycle is read by the display circuit 71 in the next operation cycle, and in the operation cycle in which the image data in the first buffer is read, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, and the first buffer and second buffer are used alternately as the "writing area" and the "reading area".

[0103] In this embodiment, index spaces reserved in any area of ​​the VRAM 53 or expansion RAM 54 are used as general work spaces other than the frame buffer FB and the space for expanding compressed data. These various index spaces can be reserved when needed and can be released when not needed, but when an index space is reserved / released, the contents of the index table IDXTBL, which stores the index space in association with the index number, are updated, enabling subsequent consistent operation.

[0104] The index space and the CPU circuit 51 have been explained above, so next, the overall performance circuit 52 will be explained.

[0105] The general effect circuit 52 includes (1) various effect control registers RGij, whose setting values ​​that define internal operations are set by the effect control CPU 57; (2) a data transfer circuit 70 that executes data transmission and reception between circuits inside and outside the chip; (3) an index table IDXTBL that manages an index space that is a working area secured in the VRAM 53 and the expansion RAM 54; (4) a preloader 72 that executes a preload operation that reads and accesses the external ROM 55 prior to a drawing operation; and (5) a GDEC (Graphics Decoder) circuit that decodes compressed data for image effects read from the external ROM 55. ) 73, (6) a drawing circuit 74 that generates one frame of image data for the display device DS in a frame buffer FB by appropriately combining decoded still image data and video data, (7) multiple display circuits 71 that read the image data generated by the drawing circuit 74 from the frame buffer FB and output it after appropriate image processing, (8) an output selection unit 76 that appropriately selects and outputs the output of the multiple display circuits 71, (9) an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs it, (10) an audio processing unit SND that executes audio effects based on the audio command list VC, (11) a motor control unit MT_CTL that executes motor effects, and (12) a lamp control unit L_CTL that executes lamp effects (see FIG. 5(a)). The audio processing unit SND includes an audio decoder that decodes compressed data for audio effects read from the external ROM 55.

[0106] The motor performance is executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the predetermined performance control register RGij for the motor performance and the control data (motor drive data) copied to the expansion RAM 54. The lamp performance is also executed in the same way based on the control operation of the performance control CPU 57, specifically, based on the set value of the predetermined performance control register RGij for the lamp performance and the control data (lamp drive data) copied to the expansion RAM 54.

[0107] 5(b) illustrates the relationship between the CPU bus unit 56, CG bus IF unit 55a, extended RAM IF unit 54a, and VRAM IF unit 53a and the performance control register RGij, external ROM 55, extended RAM 54, and VRAM 53. As illustrated, the CG compressed data acquired from the external ROM 55 is supplied to the GDEC circuit 73 via the CG bus IF unit 55a and data transfer circuit 70, and the decompressed (decoded) data is expanded in a predetermined index space secured in the extended RAM 54 or VRAM 53.

[0108] As explained above, in this embodiment, an ACC area for storing still images is allocated in the VRAM 53, and a page area for storing video frames is allocated in the extended RAM 54. Decoded data for still images and videos is then stored in a predetermined index space in the ACC area / page area. It should be noted that decompressed data of compressed CG data acquired from the external ROM 55 may also be transferred as preload data to the preload area of ​​the extended RAM 54.

[0109] Next, the display circuit 71 will be described with reference to FIG. 7. The display circuit 71 is a circuit that reads image data from the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and outputs the data. The final image processing includes, for example, scaling processing by a scaler that enlarges or reduces the image to a similar shape, subtle color correction processing, and dithering processing that minimizes quantization error of the entire image. These image processing operations are performed uniformly based on the setting values ​​of the performance control register RGij (display register). The digital RGB signal that has undergone the uniform image processing is then output together with horizontal and vertical synchronization signals.

[0110] As shown in Fig. 7, three display circuits A / B / C are provided that perform the above operations in parallel, but in this embodiment, since there is only one display device, only the frame buffer FB (=FBa) is reserved for the display circuit A. However, if frame buffers FBa to FBc are reserved, it is also possible to drive two other display devices that can perform independent image presentations.

[0111] Next, returning to Fig. 5(a), the data transfer circuit 70 will be explained. The data transfer circuit 70 is a circuit that performs data transfer operations between the internal resources of the overall performance circuit 52 and an external storage medium as the transfer source or transfer destination in a DMA (Direct Memory Access) manner. Fig. 8 is a block diagram showing the internal configuration of this data transfer circuit 70 together with the related circuit configuration.

[0112] The transfer sources of the data transfer circuit 70 in this embodiment include the CPU address space via the CPU bus unit 56, the external ROM 55, the expansion RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the transfer destinations of the data transfer circuit 70 include the CPU register port PORT, the CPU address space, the expansion RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0113] Here, the CPU address space refers to a storage area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus unit 56, and the performance control CPU 57 can arbitrarily access it via R / W.

[0114] Furthermore, virtual work areas such as page areas and arbitrary areas are defined in the expansion RAM 54 and VRAM 53, and index spaces specified by index numbers are secured / released within these virtual work areas. Therefore, the operation of the data transfer circuit 70 is executed by referring to an index table IDXTBL that stores the relationship between the index spaces and real address spaces. The index spaces secured in the expansion RAM 54 or VRAM 53 can also be set as the data transfer source or data transfer destination of the data transfer circuit 70. Therefore, data in the frame buffer FB secured in an arbitrary area of ​​the VRAM 53 can also be transferred to the expansion RAM 54.

[0115] 8, the transfer size that the data transfer circuit 70 can transfer is 32 bits × (01h to 4000_0000h) when passing through data relay units CH0 to CH1, and 32 bits × (01h to 100_0000h) when passing through data relay units CH2 to CH4. That is, the data transfer circuit 70 of this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h represents a hexadecimal number, and the upper limit of the transfer size is specifically 32 × 1,073,741,824 bits when passing through data relay units CH0 to CH1, and 32 × 16,777,216 bits when passing through data relay units CH2 to CH4.

[0116] 8, the data transfer circuit 70 is configured to receive necessary data from the external ROM 55 via an arbitration circuit ICM that has a router function and arbitrates access paths, and to transmit and receive necessary data to and from the VRAM 53 and the extended RAM 54. The external ROM 55, VRAM 53, and extended RAM 54 are accessed via a CG bus IF unit 55a, a VRAM IF unit 53a, and an extended RAM IF unit 54a.

[0117] This data transfer circuit 70 is composed of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five channel data relay units CH0 to CH4. As explained above, the CPU register port PORT is configured to be R / W accessible from the performance control CPU 57.

[0118] The data relay unit CH0 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages and a checksum circuit. Each of the data relay units CH1 to CH4 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages. The data relay units CH2 to CH4 are unidirectionally connected to the drawing circuit 74, preloader 72, and audio processing unit SND.

[0119] On the other hand, the CPU data FIFO circuit and the data relay units CH0-CH1 are configured to be capable of bidirectional communication, so that a predetermined amount of data set in the data transfer register is sent and received from a predetermined transfer source set in the data transfer register to a predetermined transfer destination set in the data transfer register via the CPU data FIFO circuit or the data relay units CH0-CH1.

[0120] Regardless of which path is taken among the data relay units CH0 to CH4, the amount of data to be transferred (transfer data size) must be set in 32-bit units, as described above, and there are also certain restrictions on the start addresses of the transfer source and destination. Specifically, the start addresses of the transfer source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in the VRAM 53 and expansion RAM 54. The transfer source start address in the external ROM 55 is also set in 32-bit units.

[0121] When data passes through the data relay units CH0 to CH1, the source and / or destination of the transfer is the external ROM 55, VRAM 53, or expansion RAM 54, and when data passes through the CPU data FIFO circuit connected to the CPU register port PORT, the source or destination of the transfer is the CPU address space, which naturally includes the built-in RAM 59.

[0122] While the data relay units CH0 to CH1, which are capable of two-way communication, have been described above, data relay units CH2 to CH4 form one-way communication paths. The performance control CPU 57 can then write-access the CPU register port PORT in 32-bit units via the CPU bus unit 56, thereby transmitting the display list DL and voice command list VC in the DL buffer BUF of the internal RAM 59 to the data relay units CH2 to CH4 in one direction.

[0123] In addition, the internal RAM 59 can be selected as the data transfer source, so that data can be transferred via the data relay units CH2 to CH4 (without going through the CPU register port PORT) with the DL buffer BUF as the data transfer source and the drawing circuit 74, preloader 72, or audio processing unit SND as the data transfer destination.

[0124] In this case, the start address of the data transfer source internal RAM 59 is specified in 8-bit units, so the lower 7 bits of the start address of the DL buffer BUF must be 0. Also, regardless of whether the data is transferred via the CPU register port PORT or not, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0125] In any case, the data relay units CH2, CH3, and CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via the data relay unit CH2, and to the preloader 72 via the data relay unit CH3. Also, a voice command list VC of a predetermined data transfer size is transferred to the audio processing unit SND via the data relay unit CH4.

[0126] As described above, in this embodiment, the transfer paths for the display list DL and the voice command list VC are (1) a first path that passes through the CPU register port PORT, and (2) a second path that does not pass through the CPU register port PORT, and either of these can be used. This is also true for other data, which have (1) a first path that passes through the CPU register port PORT and data relay units CH0 to CH4, and (2) a second path that passes only through the data relay units CH0 to CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, and the second path is used for data transfers in which the performance control CPU 57 is not directly involved (DMA operations).

[0127] 8, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, when the first path is used, once 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data will be transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as a channel data FIFO). In other words, if less than 32 levels of data are written to the CPU data FIFO circuit, no data transfer to the channel data FIFO occurs, and when the 32nd level of data is written, the 32 levels of accumulated data are transferred to the channel data FIFO, and then the data is transferred to the next destination. On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, it is possible that the data in the CPU data FIFO circuit will end up at less than 32 levels, but when the cumulative size of the written data reaches the transfer size previously set in the data transfer register, the accumulated data of less than 32 levels will be transferred to the channel data FIFO and the next destination.

[0128] As described above, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value that is an integer multiple of 32 bits, regardless of whether the transfer is via the first path or the second path. The instruction commands that make up the display list DL and the voice commands that make up the voice command list VC are all configured as an integer multiple of 32 bits. Therefore, in this embodiment, there is no restriction on the number of commands in the display list DL or the voice command list VC, allowing for a free list configuration, and there is no need to adjust the total data size by adding dummy commands or the like.

[0129] 9A and 9B show the operation of transferring the display list DL to the drawing circuit 74 via the CPU register port PORT and the data relay unit CH2 (FIG. 9A), the operation of transferring the display list DL from the internal RAM 59 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9B), and the operation of transferring the rewrite list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9C).

[0130] Figures 9(d) and 9(e) show the operation of transferring a display list DL to the preloader 72 via the CPU register port PORT and the data relay unit CH3, and the operation of transferring a display list DL from the internal RAM 59 to the preloader 72 via the data relay unit CH3.

[0131] Also, Figures 9(f) and 9(g) show the operation of transferring the voice command list VC to the voice processing unit SND via the CPU register port PORT and the data relay unit CH4, and the operation of transferring the voice command list VC from the built-in RAM 59 to the voice processing unit SND via the data relay unit CH4.

[0132] The CPU circuit 51 starts the operations of the drawing circuit 74, preloader 72, and audio processing unit SND prior to the start of operation of the data transfer circuit 70, so that the drawing circuit 74 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 executes the necessary preloading operations based on the transferred display list DL. The transferred display list DL is analyzed by a display list analyzer built into the drawing circuit 74 and preloader 72, and processing is executed according to the type of instruction command. Furthermore, the audio processing unit SND starts or progresses audio performance based on the transferred audio command list VC.

[0133] Note that data other than the display list DL and the voice command list VC in the CPU address space can be transmitted to the data relay units CH0 to CH4 via the CPU bus unit 56, and then further via the CPU register port PORT, or directly. The data relay units CH0 to CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or the expansion RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar, and the data relay units CH0 to CH1 that receive data via the arbitration circuit ICM transfer the data to a predetermined destination in the CPU address space either via the CPU register port PORT, or directly.

[0134] Next, the preloader 72 will be described, but it is optional whether or not to utilize the preloader 72. When the display list analyzer interprets the display list DL transferred from the data relay unit CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data in the external ROM 55 referenced by the LOADTX command to the preload area of ​​the expansion RAM 54 (see FIG. 6(b)).

[0135] Furthermore, the preloader 72 stores a rewrite list DL' in which the reference destination of the CG data for the LOADTX command is rewritten to the address after transfer in the DL buffer BUF' (see FIG. 6(a)) of the VRAM 53. The DL buffer BUF' and the preload area are reserved in advance during the initial processing after the CPU is reset.

[0136] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM and data relay unit CH2 of the data transfer circuit 70 when the drawing operation of the drawing circuit 74 starts (see FIG. 9(c)). The drawing circuit 74 then executes the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external ROM 55 based on a LOADTX command or the like is quickly obtained from the preload area of ​​the expansion RAM 54 as preload data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is put into operation in a normal device configuration.

[0137] In this embodiment, since the preload area is set in the external expansion RAM 54, which has sufficient storage capacity, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. That is, multiple preloading is realized by appropriately setting the operating period of the preloader 72, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the overall performance circuit 52 during intermittent operation.

[0138] However, in the following explanation, for the sake of convenience, an embodiment without multiple preloading will be described, and therefore the preloader 72 of the embodiment will complete the preloading operation for one frame during one operation period δ. In this embodiment, the operation period δ during intermittent operation of the overall performance circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS.

[0139] Next, the drawing circuit 74 sequentially analyzes the instruction command sequences of the display list DL and the rewrite list DL′ transferred via the data transfer circuit 70, and works in cooperation with the GDEC circuit 73, the geometry engine, etc. to draw one frame of an image of the display device DS in the frame buffer FB secured in the VRAM 53.

[0140] As described above, when the preloader 72 is activated, the CG data in the rewrite list DL' is referenced not in the external ROM 55 but in the preload area set in the expansion RAM 54. This allows for rapid sequential access to CG data that occurs while the rendering circuit 74 is rendering, making it possible to render high-resolution moving images with rapid movement without any problems.

[0141] Regardless of whether the preloader 72 is enabled or disabled, even if data bit corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect this. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to that of a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the drawing circuit 74 starts operating.

[0142] In this embodiment, a time setting register TO capable of setting a timeout time is provided to detect an operational abnormality in the drawing circuit 74. The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to be started based on the value set in a predetermined drawing register (drawing operation permission register).

[0143] When a predetermined timeout time is set in the time setting register TO and start information is set in the drawing operation permission register, the drawing circuit 74 starts operation, and in response, the timeout monitoring circuit monitors the memory access cycle. If no memory access is made after the timeout time has elapsed, an abnormality flag in a predetermined drawing register is set ON and an abnormality interrupt is initiated.

[0144] Although it is possible to deal with this abnormal interrupt by starting an interrupt processing program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag for each operation cycle δ of the overall performance circuit 52. Specifically, if the abnormal flag is ON, the screen update for that operation cycle is skipped even if the operation of the drawing circuit 74 has been completed.

[0145] Here, if measures such as activating the WDT 58 or resetting the drawing circuit 74 are taken, as in the configurations of Patent Documents 1 and 2, there is a risk that an unnatural screen display will appear, but in this embodiment, the appearance of an abnormal screen is easily prevented with minimal measures. Also, the timeout period to be monitored can be set arbitrarily taking into consideration the arrangement of commands such as the LOADTX command in the display list DL and the access time of the external ROM 55, etc., thereby achieving optimal monitoring operation.

[0146] In the above configuration, the memory access cycle is monitored from the start to the end of the drawing circuit 74 operation, but instead of or in addition to this configuration, it is preferable to adopt a configuration that monitors the operation time from the start to the end of the GDEC circuit 73 operation. In this case, too, an optimal value can be set in the time setting register TO' taking into account the texture data capacity, thereby achieving optimal monitoring operation.

[0147] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding CG compressed data, and ends the monitoring operation when the decoding ends. Note that, like the former configuration, when a timeout occurs, an abnormality flag in a specified drawing register is set to ON, an abnormality interrupt is initiated, and when an abnormality is detected, screen updates are skipped for that operating cycle. Note that this embodiment uses a flag polling method that checks the ON / OFF state of the abnormality flag for each operating cycle δ of the overall performance circuit 52. However, a configuration may also be adopted in which an abnormality interrupt processing program is initiated to skip screen updates for the operating cycle in which a problem occurred.

[0148] Next, the image filter circuit 75 is a circuit that functions based on instruction commands (filter execution commands) written in the display list DL and performs appropriate filter processing on textures temporarily stored in the VRAM 53 or the extended RAM 54. In other words, the image filter circuit 75 of the embodiment does not perform a uniform filter operation based on the setting value of the performance control register RGij, but rather allows for free filter processing of required image data by arbitrarily writing appropriate instruction commands in the display list DL.

[0149] The content of the filter processing is determined by the selection of a filter execution command and the setting parameters of the selected command, but the executable filter processing includes (1) FIR (Finite Impulse Response) filter processing, (2) downsampling processing, and (3) linear interpolation processing. Here, downsampling processing is a process different from the scaling processing in the display circuit 71 that operates based on the setting value of the performance control register RGij (display register).

[0150] That is, downsampling does not reduce an image to a similar shape as scaling does, but involves reducing the image only in the vertical or horizontal direction. Although not limited to this, downsampling reduces the texture by calculating the average value of the image information of pixels in a predetermined range surrounding the target pixel and performing a thinning process such as moving average processing.

[0151] 10(a) is a diagram illustrating an example of an operation in which FIR filter processing is executed twice consecutively using a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be filtered should be saved (command process L20), and then the LOADTX command retrieves the reference texture from the external ROM 55 specified by the command setting parameters, and saves the decoded image data in the destination index space (command process L21).

[0152] The following SETFTINDEX command sets the index space where the resultant texture will be saved (command process L22), and the SETFTSAMP command and SETFTCOEF command set the filter coefficients and other information (command process L23), before executing the FIR filter process with the FTEXECFIR command (command process L24). Note that the SETFTINDEX command distinguishes between specifying an index space for the reference texture or an index space for the resultant texture, depending on the setting parameters of the command.

[0153] As shown in Figure 10(b), the image data expanded in the index space for the reference texture specified by the instruction command L20 undergoes FIR filter processing specified by the instruction command L23, and then is stored in the index space for the result texture specified by the instruction command L22.

[0154] Next, the SETFTINDEX command sets the index space of the reference texture (command process L25), and the SETTXINDEX command sets the index space where the resultant texture will be saved (command process L26). In command L25, the image data after the filter process is set as the reference texture, so the resultant texture specified by command L22 is changed to the reference texture by command L25.

[0155] After that, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command process L27), after which the necessary FIR filter processing is executed using the FTEXECFIR command (command process L28).The image data after filtering is then stored in the index space specified by instruction command L26, so by executing the SPRITE command after activating the SETTXMODE command (command process L29), the image data that has undergone FIR filtering will be drawn in an appropriate rectangular section in the virtual drawing space.

[0156] 10(c) is a diagram illustrating an example of an operation in which scaling processing is performed using a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be scaled should be saved (command process L30), and then the LOADTX command retrieves the reference texture from the external ROM 55 specified by the setting parameters of that command (command process L31).

[0157] Next, the SETTXINDEX command is used to set an index space for storing auxiliary data required for scaling (command process L32). The auxiliary data is plane information extracted from the reference texture and characterizes the reference texture. The reason why such auxiliary data is important is that the scaling process of this embodiment involves deformations of dissimilar shapes, not similar shapes, and therefore appropriate interpolation processing is performed to eliminate unnaturalness in the image after deformation.

[0158] Therefore, in the scaling process of this embodiment, following command L32, the FTEXECGRD command is written to generate auxiliary information (plane information) in the index space specified by command L32 (command process L33). The necessary preparations are completed with the commands up to this point, so next, the SETTXINDEX command is used to set the index space to be used as the texture (command process L34), and after setting the necessary information with the SETTXSAMP command, the scaling process is executed with the SETTXMODE command (command process L35).

[0159] As a result of the above, the image data after scaling is saved in the index space specified by instruction command L34, so by activating the SETTXMODE command and then executing the SPRITE command (command processing L36), the image data after scaling is drawn in an appropriate rectangular section in the virtual drawing space.

[0160] The image filter circuit 75 has been described above, but the GDEC circuit 73 performs decoding processing by software processing corresponding to each compression algorithm for compressed data such as streaming video, still images, and other α values. In this embodiment, streaming video is divided into S streams, IP streams, and IPB streams, and the frames that make up the streaming video are composed of an appropriate combination of I pictures, S pictures, P pictures, or B pictures.

[0161] An I (Intra coded) picture refers to an intra (intra-picture) coded picture, and refers to image data obtained by compressing an input image as is, independent of other pictures. On the other hand, an S picture is image data that is predictively coded by referring to the I pictures immediately before and after it, and has the advantage of a higher compression rate than an I picture. The S stream video of this embodiment is a video that combines these I pictures and S pictures, and by arranging the I pictures according to a fixed cycle, random access and reverse playback starting from the I picture can be performed, thereby realizing effective image presentation. Note that S stream video that does not include S pictures is also possible, and S stream video without S pictures is essentially the same as I stream video.

[0162] Next, a P picture (Predictive coded) is image data that undergoes forward predictive coding, which predicts the current frame from a temporally past frame, and is predictively coded from an I picture or P picture located in the past. On the other hand, a B picture (Bidirectional coded) is image data that undergoes bidirectional predictive coding, which performs forward prediction as well as backward prediction, which predicts the current frame from a future frame, and is predictively coded from an I picture or P picture located in the past and future.

[0163] Generally, inter-frame prediction techniques include forward prediction, which predicts the current frame from a past frame, backward prediction, which predicts the current frame from a future frame, and bidirectional prediction, which performs backward prediction in addition to forward prediction.B pictures perform bidirectional prediction, which allows for improved prediction accuracy.

[0164] Therefore, in this embodiment, in addition to S-stream video, which is a combination of I-pictures and S-pictures, it is configured to be able to play IP-stream video and IPB-stream video, which are appropriate combinations of I-pictures, P-pictures, and B-pictures. Note that IP-stream video is made up of a combination of I-pictures and P-pictures, and IPB-stream video is made up of a combination of I-pictures, P-pictures, and S-pictures.

[0165] As is clear from the above relationship, with S stream video containing S pictures and IPB stream video, the need for backward predictive coding means that I pictures and P pictures that are to be played back later in time must be acquired and decoded prior to acquiring S pictures and B pictures.

[0166] Therefore, this embodiment is configured so that one LOADTX command can specify multiple textures, i.e., main-frame CG data and sub-frame CG data. Here, main-frame refers to CG frame data that should be played at the current timing, and sub-frame refers to CG frame data that should be played at a different timing.

[0167] For example, in an S picture, predictive coding is performed by referring to the nearest (previous or next) I picture, so in an S stream video that consists of a series of I pictures and S pictures, the CG data for the S picture as the main frame and the I picture as the sub-frame can be obtained and decoded with a single LOADTX command.

[0168] Furthermore, since bidirectional predictive coding is performed on B pictures (bidirectional coded), it is necessary to reserve CG data of past frames and CG data of future frames in a decoded state prior to the decoding process of the B picture. Therefore, in this embodiment, when playing IPB stream video, it is necessary to reserve a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space with sufficient capacity to store reference images, and is reserved in any area of ​​the VRAM 53 or expansion RAM 54 and identified by a unique index number.

[0169] Figure 11 explains the playback procedure for IPB video streams, with the playback operation progressing from top to bottom of the page. Figure 11 is divided horizontally into six sections, showing, from left to right, (1) the LOADTX command on the display list DL, (2) pictures constituting the IPB video stream, (3) mainframe and subframe decoding processing, (4) reference image decoding processing, (5) reference buffer where the reference images are stored, and (6) index space (expansion space) where the decoded images displayed on the display screen are stored.

[0170] The downward arrow in the first column indicates the transition of the operating cycle of the general performance circuit 52 (GDEC circuit 73), which operates intermittently, and the downward arrow in the sixth column indicates the display order of the images displayed on the display device DS. In the following explanation, for convenience, a group of video frames played at timings T1 to T7 is referred to as a GOP (Group Of Picture), but the GOP can be changed as appropriate based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0171] First, the LOADTX command at timing T1 to play back an I-picture specifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the sub-frame by the embedded parameters of the command, as well as the index number of the expansion space where the decoded data should be stored.

[0172] Therefore, the I picture (I1) acquired based on the instruction of the LOADTX command at timing T1 is decoded and stored in the first reference buffer for storing past frames together with the original decompression space. Furthermore, a P picture (P1) is acquired based on the instruction of the LOADTX command at timing T1, and its decoded data is stored as a reference image in the second reference buffer for storing future frames. Although not limited to this, the reference image is stored in a compressed state using a special technique.

[0173] Next, the LOADTX command at timing T2 specifies only a B picture (B1) as the main frame. Then, as a bidirectional prediction operation, image data B1 of the current frame is reproduced based on the I picture (I1) in the first reference buffer, and the P picture (P1) and B picture (B1) in the second reference buffer, and saved in the playout space. The same is true for the subsequent LOADTX command at timing T3, where image data B2 of the current frame is reproduced based on the I picture (I1) in the first reference buffer, and the P picture (P1) and B picture (B2) in the second reference buffer, and saved in the playout space.

[0174] Next, the LOADTX command at timing T4 when a P picture should be played back instructs that the P picture (P1) serving as the main frame should be retrieved from the second reference buffer by the embedded parameters of the command, and also specifies the address of the P picture (P2) serving as the sub-frame.

[0175] Therefore, at timing T4, the P picture (P1) in the second reference buffer, which has been compressed using a special method, is decompressed and saved in the decompression space, and the P picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. Furthermore, a future P picture (P2) is acquired in response to the instruction of the LOADTX command at timing T4, and its decoded data is saved in the second reference buffer as a reference image for the future frame.

[0176] The subsequent operations at timings T5 and T6 are substantially the same as those at timings T2 and T3. That is, at timing T5, a B3 picture image based on the P picture (P1) in the first reference buffer, the P picture (P2) in the second reference buffer, and the B picture (B3) is rendered in the rendering space based on bidirectional prediction. At timing T6, a B4 picture image based on the P picture (P1) in the first reference buffer, the P picture (P2) in the second reference buffer, and the B picture (B4) is rendered in the rendering space.

[0177] Next, the LOAD command at timing T7 instructs that a P picture (P2) serving as a main frame should be retrieved from the second reference buffer. The address of the I picture (I2), a sub-frame, is also specified. Therefore, at timing T7, the P picture (P2) in the second reference buffer is decompressed and stored in the decompression space. The LOADTX command at timing T7 also instructs that an I picture (I2) be retrieved, and the decoded data is stored in the second reference buffer as a reference image for a future frame.

[0178] At the next timing T9, an instruction is issued to retrieve an I-picture (I2) as a main frame from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the decompression space, and the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. Note that the LOAD command at timing T9 specifies the address of the P-picture (P3), which is a sub-frame, so the P-picture (P3) is retrieved and its decoded data is saved in the second reference buffer as a reference image for a future frame.

[0179] 12(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT in which 64-track processing blocks are arranged so that they can operate in parallel, a post-processing unit BK consisting of a master effect unit, a master volume unit, an output protection unit, and a serializer, and a mixer MX that transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0180] As shown in the figure, the pre-processing unit FT is provided with 64 decoders that receive compressed audio data (compressed phrase data) from the external memory 55. Meanwhile, the post-processing unit BK is configured to be able to output audio signals SDOUTA to SDOUTD of four paths A / B / C / D as serial data together with the clock signal SBCLK and the control signal SLRCLK via a serializer. The serial data SDOUTA to SDOUTD of the four paths A / B / C / D each contain right data R and left data L on one data line, and depending on whether the control signal SLRCLK is in an H level period or an L level period, it is determined whether the serial data SDOUTA at that timing is left data L or right data R.

[0181] Next, the internal operation of the preprocessing unit FT will be explained. The phrase data decompressed by the decoder has its volume adjusted appropriately in the primary volume, secondary volume, and panpot units. Here, the primary volume and secondary volume are responsible for two-stage volume adjustment, and the panpot unit adjusts the volume ratio between the left and right speakers. The specific operations of the primary volume, secondary volume, and panpot units are each specified by a voice command listed in the voice command list VC.

[0182] Phrase data is audio data that realizes one unit of audio performance, and includes one unit of audio performance such as a piece of background music for one song, sound effects, or shouts. One phrase data is output to eight paths from the panpot section of the pre-processing section FT. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing sections FT) are arranged to be able to operate in parallel, and up to 64 phrase data can be output to the mixer MX. The audio data collected on eight paths, which are left and right audio R / L on four paths A / B / C / D, is transmitted to the post-processing section BK.

[0183] The panpot section can adjust the volume ratio between the left and right speakers, so for example, the panpot section of the first track can set the left and right volume ratio to maximum:zero and output only to the first line of mixer MX, while the panpot section of the second track can set the left and right volume ratio to zero:maximum and output only to the second line of mixer MX. As a result, for example, the first phrase data, which is the left audio, will be output only to the first line, and the second phrase data, which is the right audio, will be output only to the second line, making it possible to play in stereo with the left and right speakers of system A.

[0184] Next, the internal operation of the post-processing unit BK will be explained. The master effect performs audio filtering, and the master volume determines the volume. The specific operations are specified by the voice commands listed in the voice command list VC. The master volume is used, for example, to provide a silent warning that instantly silences the volume effect, while the master effect is used, for example, to provide a warning that the sound quality will be changed drastically.

[0185] 12(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands written in the voice command list VC. Here, a START command that instructs the start of playback of specific phrase data, a PAUSE command that instructs the stop of playback of specific phrase data, a RESUME command that instructs the restart of playback of specific phrase data, and a STOP command that instructs the end of playback of specific phrase data are shown as examples. The voice command list VC is composed of one or more voice commands written therein, but must be terminated by a predetermined end command EOSC.

[0186] First, in the voice command list VC1, the start of reproduction of 64 types of phrase data is instructed by voice commands START1 to START64. Therefore, when the decoding process of the 64 types of compressed phrase data is completed, the reproduction operation of the 64 types of phrase data is started.

[0187] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of the phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC2 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0188] The voice command list VC can be output not only at the start and end of phrase data playback, but also at any necessary timing in the operation cycle δ (= 1 / 30 seconds) of the overall performance circuit 52. In other words, the display list DL is output for each operation cycle δ of the overall performance circuit 52, but the voice command list VC is generally output irregularly.

[0189] Next, a description will be given of the rendering pipeline processing that can be executed in the rendering circuit 74. FIG. 13(a) illustrates a portion of the rendering circuit 74 that is relevant to the rendering pipeline processing. The display list analyzer sequentially analyzes the instruction commands written in the display list DL and transfers the instruction commands to an appropriate internal circuit according to their type. Note that in FIG. 13(a), the instruction commands are specifically referred to as rendering commands, and in the following description, the instruction commands may also be referred to as rendering commands.

[0190] The internal circuits that receive the drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands written in the display list DL in the order they are written, and transfers the drawing commands to the corresponding internal circuits one after another (see Figure 13(a)).

[0191] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that transfers the configuration data of the display list DL in sequence, and in general, the operating speed of the internal circuitry of the drawing circuit 74 is much slower than the transfer speed of the configuration data of the display list DL.

[0192] Therefore, the internal circuit that receives the drawing commands is provided with a standby queue that stores drawing commands before processing begins, and the display list analyzer puts the drawing commands into the standby queue on the condition that there is space in the standby queue. In other words, the display list analyzer stalls (temporarily stops) the putting operation until the standby queue becomes empty, so there is no risk of the drawing commands being lost. Note that the numbers shown for the standby queue are merely an example of the number of stages in the queue.

[0193] As explained above, the instruction commands written in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture load commands such as the LOADTX command for reading image material (texture) from the external ROM 55 and decoding (decompressing / expanding) it; (3) filter execution commands that specify the filter processing to be performed on the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space; and (5) pipeline commands related to drawing pipeline operations.

[0194] 13(a), an index table control command (1) is transferred to the control circuit of the index table IDXTBL, a texture load command (2) is transferred to the GDEC circuit 73, and a filter execution command (3) is transferred to the image filter circuit 75, and each is processed appropriately by the circuit to which it is transferred. Specifically, the GDEC circuit 73 operates based on the transferred drawing command (texture load command), obtains the required texture, and expands the decompressed data into the decode space.

[0195] Furthermore, the index table IDXTBL is updated as appropriate by the functioning of the control circuit for the index table IDXTBL. The image filter circuit 75 performs a specified filter process on a predetermined reference texture and stores the filter process result in a predetermined index space (see FIG. 10). When a predetermined drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS functions to transmit and receive data at high speed between the VRAM 53 and the expansion RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74 and is a circuit separate from the data transfer circuit 70.

[0196] When using the data transfer circuit 70, the CPU circuit 51 must set the type of source medium and transfer start address, the type of destination medium and receiving start address, and transfer size in a specified performance control register RGij (data transfer register), but the high-speed transfer circuit TRNS has the advantage that it can be easily made to function when necessary by an instruction command (transfer execution command) from the display list DL, and can also perform high-speed transfer of two-dimensional data in units of index space.However, in a control program that is constantly functioning, it is not easy in terms of program configuration to use the data transfer circuit 70 only when necessary.

[0197] As explained above, the rendering pipeline operation is performed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer that manages the front-to-back relationship of polygons and whether or not pixels are displayed, and is configured to execute an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO as needed.

[0198] That is, the rendering pipeline processing is executed from upstream to downstream, passing through all or some of the processes in the following order: Process IA → Process TL (Process VB) → Process RS → Process TX → Process PS → Process PX → Process RO. Each process operates in parallel, but since the downstream processes take longer to complete the execution of rendering commands, the number of stages in the waiting queue that stores the rendering commands input to each process is configured so that it is not less than the number of stages in the waiting queue on the upstream side.

[0199] As shown in Figure 13(a), the number of stages in the waiting queue is 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages, corresponding to process IA → process TL → process RS → process TX → process PS → process PX → process RO, and the number of stages at each process is the same as or greater than the number of stages in the waiting queue upstream.

[0200] The pipeline commands described above are setting commands that specify the operation details of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the operating parameters required for the necessary internal circuits, such as the geometry engine.

[0201] In this embodiment, as shown in FIG. 13(b), the rendering pipeline is composed of process IA, process TL, process RS, process TX, process PS, process PX, and process RO. First, the input assembler process IA acquires the vertex stream of a three-dimensional 3D rendering object, which is usually defined in local coordinates, stores the information necessary for subsequent processing, and outputs vertex data having predetermined vertex information.

[0202] In this process IA, in addition to the setting commands for process IA (pipeline commands), drawing commands such as DRAW and DRAWD are used. The DRAW command specifies the start address of the memory (external ROM 55 in this embodiment) that stores a series of vertex streams, and the number of vertices.

[0203] On the other hand, a DRAWD command has a series of vertex streams embedded in it. The specific operation of the DRAW command and the DRAWD command is specified by the embedded information of each command and the setting commands for process IA. Note that a vertex color (RGBA color information) can be specified for each vertex in the vertex stream, but if a vertex color is not specified, a default value is set as the vertex information in the input assembler process IA. Here, RBG refers to color information of R=Red, B=Blue, and G=Green, and A is an alpha value α that indicates opacity and is used in the alpha blending process when overlapping images.

[0204] The following geometry engine process TL performs matrix operations to transform the vertex coordinates of the 3D drawing object and lighting processing related to light sources, etc., on the vertex data output from the input assembler process IA. The coordinate transformation process performs view matrix operations to transform local coordinates into view coordinates and matrix operations for projective transformation (perspective projection).

[0205] Here, the view coordinate system is a coordinate system in which the viewpoint is the origin and the point at infinity (0,0,-∞) is the line of sight. In projective transformation, in order to realize a sense of perspective that corresponds to the placement position of the 3D drawing object, the view coordinate system is transformed into the clip coordinate system by enlarging or reducing the shape of the 3D drawing object.

[0206] The specific content of the matrix operation is specified by the setting command (pipeline command) for the TL process, and the execution of a specified geometry matrix operation is instructed by the DRAW command or DRAWD command. Therefore, process IA and process TL can be executed together with a single drawing command (DRAW / DRAWD). However, in either case, the execution result of the geometry matrix operation by the drawing command (DRAW / DRAWD) is saved in the vertex buffer VB.

[0207] The geometry engine process TL is not essential, and when a vertex stream defined by clip coordinates is obtained from the external ROM 55, the information passes through the input assembler process IA and is stored directly in the vertex buffer VB. The input assembler process IA and the geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to be able to store a maximum of 256 vertices.

[0208] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB, and pixel data for 3D drawing objects is generated after removing polygons that do not need to be drawn by converting from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc. In other words, a three-dimensional 3D image object is determined to be placed at a predetermined position and with a predetermined orientation in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0209] To generate primitives, a triangle drawing method such as a triangle list, triangle strip, or triangle fan, or a line drawing method such as a line list, line strip, or line fan can be selected and used as appropriate.

[0210] In addition, in the rasterizer process RS, in addition to setting commands (pipeline commands) for the RS process that specifically define the processing content, drawing commands DRAW command, DRAWD command, DRAWI command, and SPRITE command are used as appropriate.

[0211] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB, while the DRAW command generates and draws primitives based on a vertex stream obtained from the external ROM 55, and the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0212] Therefore, the rasterizer process RS can be executed without going through the geometry engine process TL. For example, in the case of a two-dimensional (2D) drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color for each vertex.

[0213] Next, in the texture sampler process TX, the index space to be used as the texture and the texture coordinates for each pixel are specified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are calculated appropriately.

[0214] In these steps TX and PS, and the following step PX, in addition to the setting commands (pipeline commands) in each step, the drawing commands DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate. With the DRAW, DRAWD, or DRAWI command, a texture is pasted into the area surrounded by specified vertices, and with the SPRITE command, a texture is pasted into a specified rectangular area.

[0215] Then, in the subsequent pixel drawing process PX, the drawing color and background color are combined, and tone mapping and inverse tone mapping are performed to adjust contrast. In this PX process, pixel data containing predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the pixel drawing position is input for each pixel from the frame buffer FB.

[0216] The final rendering step RO refers to the depth and stencil buffers and performs a pixel test to determine whether or not to display the pixel based on the pixel's depth and stencil information, and then performs alpha blending on overlapping multiple drawing objects before writing the completed drawing object to the frame buffer FB. Writing to the frame buffer FB is nothing more than drawing in the virtual drawing space shown in Figure 6, and normally the SPRITE command is used.

[0217] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the rendering process RO can also use the CLEAR command, which fills the frame buffer FB with a single color, and the CLEARZ command, which fills the depth and stencil buffers with a single color. The CLEAR command is used to clear the frame buffer FB prior to the start of drawing operations, and the CLEARZ command is used when depth information and stencil information are not required.

[0218] In this way, in the present invention, all or some of the series of drawing pipeline steps function, and two-dimensional or three-dimensional drawing objects are written one after another into the frame buffer FB, ultimately completing the image data for one frame of the display device.

[0219] Figure 14 is a process diagram showing various rendering modes that use all or part of the rendering pipeline processes. First, the rendering mode in Figure 14(a) is an operating mode that uses the above-mentioned CLEAR command and CLEARZ command, and only the render process RO functions.

[0220] 14(b), the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO function. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the vertices of the window coordinate system, but this offset value is related to the rectangular area where the SPRITE command is pasted.

[0221] In actual operation, the SETTXINDEX command sets the destination index space, the LOADTX command retrieves a specified texture and deploys it in the index space, and the SPRITE command secures this deployed texture in a specified location. The deployed texture information is then referenced and ultimately written to the frame buffer FB. In principle, video playback and playback of simple still images are achieved in this sprite drawing mode.

[0222] The rendering mode shown in Figure 14(c) is an example of an operation in which triangle rendering and line rendering are performed using all processes of the rendering pipeline. Note that the only difference between triangle rendering and line rendering is the method of generating primitives. In either case, primitives are identified and rendered based on the vertex stream of the 3D rendering object supplied to the input assembler process IA.

[0223] 14(d) shows a drawing operation using the DRAW command, DRAWD command, etc., in which pixel data for a drawing object is generated in the rasterizer process RS without performing coordinate transformation processing. This operation is typically used when displaying a two-dimensional (2D) drawing object, the contour of which can be identified by a vertex stream, on a display screen.

[0224] Figures 14(e) and (f) show operation modes when vertex data is stored in the vertex buffer VB, and are divided into (e) when coordinate transformation processing is performed and (f) when coordinate transformation processing is not performed. These operations are executed by the DRAW command and DRAWD command. Figure 14(g) shows an operation mode that uses vertex data stored in the vertex buffer VB, and is executed by the DRAWI command.

[0225] As described above, the rendering pipeline of this embodiment can be used in various ways. For example, playback of 2D still images and streaming video (S stream, IPB stream, IP stream) requires simple sprite rendering, so the playback operation is realized in the operating mode of Figure 14(b), as described above.

[0226] As explained above, the display analyzer determines the drawing commands in the display list DL and transfers them to the processing blocks of the pipeline steps corresponding to the drawing commands. The transferred drawing commands are then first put into the waiting queues of the respective pipeline steps, and the processing corresponding to the drawing commands is executed in the order of their entry.

[0227] However, the operation of the data transfer circuit 70 that transfers the display list DL is much faster than the progress of this rendering pipeline, so if, for example, you want to display multiple 3D rendering objects on the screen and also other 2D rendering objects on the screen, you will have to wait a long time for the execution of the SPRITE command in the rendering process RO.

[0228] In other words, since it takes a certain amount of time to process the coordinate transformation matrix for a 3D drawing object, a large number of sprite commands will accumulate in the standby queue of, for example, an RO process. However, in this embodiment, as explained above, the input of drawing commands is put on hold until the standby queue is empty (stall state), and moreover the number of stages in the standby queue of a downstream process is the same as or greater than the number of stages in the standby queue of an upstream process, so the commands written in the display list DL can be executed smoothly in the order they are written.

[0229] Note that the execution of a drawing command transferred from the waiting queue is also put on hold (stall state) until the necessary start conditions are met, so that inconsistent drawing operations such as rewriting the index space do not occur.

[0230] Having explained the circuit configuration above, we will now explain the control operation by the CPU circuit 51. As explained above, when power is turned on, a reset period occurs prior to the start of the control operation, during which the system reset signal SYS is maintained at L level for a predetermined period of time.

[0231] During this reset period, first, one or two oscillator circuits that control the operation of the integrated performance circuit 52 and the built-in CPU circuit 51 start oscillating, and wait for the oscillation frequency of each system clock to stabilize. Next, the internal circuit of the composite chip 50 is initialized in synchronization with each system clock, and predetermined default values ​​are set in the performance control register RGij and the operation control register REG. Hereinafter, this operation will be referred to as a hardware reset to distinguish it from the software reset described below.

[0232] When this hardware reset period ends, the performance control CPU 57 of the built-in CPU circuit 51 executes the boot program stored in the external ROM 55 and transfers the control program and control data from the external ROM 55 to the extended RAM 54. Thereafter, the performance control CPU 57 continues control operations based on the control program transferred to the extended RAM 54.

[0233] The control operations executed by the performance control CPU 57 are as shown in Figure 15, and include a main process (a) consisting of an initial process and subsequent regular process, a timer interrupt process (b) that is started every 1 mS, a VBLANK interrupt process (c) that is started in response to a VBLANK signal output from the general performance circuit 52 at the start of the vertical blanking period of the display device DS, and a reception interrupt process (not shown) for receiving the control command CMD. The VBLANK signal is generated every 1 / 60 seconds.

[0234] As shown in Figure 15(b), in the timer interrupt process, a sensor signal is acquired to grasp the motor position, etc. (ST20), and when necessary, a lamp effect or a motor effect is started or progressed (ST21). In this embodiment, the lamp effect is realized by the operation of the effect control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor effect is realized by the operation of the effect control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. In addition, in the VBLANK interrupt process, which is activated in response to the VBLANK signal, the interrupt counter VCNT is incremented and the process ends (ST25), as shown in Figure 15(c).

[0235] First, the main processing will be described for the case where the preloader 72 is not utilized. As shown in Fig. 15(a), first, an initial setting process (ST1) is executed, and appropriate setting values ​​are set in the performance control register RGij of the overall performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0236] The setting process for the performance control register RGij includes the process of reserving appropriate virtual working areas (AAC area, page area, arbitrary area) in the VRAM 53 and the extended RAM 54 (see Figures 6(a) and 6(b)), and the process of reserving index space essential for game control operations, such as the frame buffer FB. As explained above, the frame buffer FB is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0237] The start address of the shared area (used as the AAC area in this embodiment) secured in the VRAM 53 is set in 4k byte units (the lower 15 bits are zero), and the area size is secured as an integer multiple of 4k bytes. Also, the page area secured in the expansion RAM 54 is set in 32k byte units (the lower 18 bits are zero), and the area size is secured as an integer multiple of 32k bytes.

[0238] The set values ​​in the operation control register REG include operation parameters for the watchdog timer WDT 58, which include an operation start instruction and a counter value. The WDT 58 in this embodiment is configured to count down an initial value (counter value), and by reloading the counter value before the count value reaches zero (underflow), activation of the WDT 58 is prevented.

[0239] On the other hand, when the count value underflows, a WDT reset request is generated, and the WDT 58 is activated, resulting in a software reset state. Then, as a standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG except for specified registers are returned to their initial values ​​(default values), and the WDT 58 stops operating. Note that the register value that is exceptionally maintained is the register that indicates the operating state of the WDT.

[0240] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether to initialize the internal circuit, and (2) whether to initialize the system clock circuit even if initialization is performed, can be arbitrarily selected by setting a corresponding value in a predetermined operation control register REG during the initial setting process after a hardware reset. Therefore, in this embodiment, based on the set value in the predetermined operation control register REG, when a software reset is performed, the internal circuit is not initialized and game operation resumes from the processing of step ST1.

[0241] Thus, in this embodiment, unlike the configurations of Prior Art Documents 1 and 2, even if the WDT 58 underflows, the hardware reset state is not entered, which has the advantage that the game operation can be resumed quickly. After the software reset, the WDT stops operating, so there is no risk of the software reset operation being repeatedly initiated.

[0242] When the initial setting process (ST1) including the above processes is completed, the intermittently executed steady-state process (ST2 to ST10) starts. As shown as step ST2 in Figure 15(a), the steady-state process starts when the interrupt counter VCNT becomes VCNT≧2, so the operation period (operation cycle) δ of the steady-state process is 1 / 30 seconds, corresponding to the operation period (1 / 60 seconds) of the VBLANK signal.

[0243] Then, in the processing of step ST3, after resetting the interrupt counter VCNT, it is determined whether or not the operation start conditions for starting normal operation are met. Specifically, a predetermined performance control register RGij indicating the operating state of the drawing circuit 74 is accessed for READ, and it is determined at this timing whether or not the drawing circuit 74 has completed the drawing operation based on the display list DL of the previous operation cycle. Also, in the drawing operation of the previous operation cycle, it is determined whether or not the memory access period of the drawing circuit 74 has exceeded the timeout time set in the time setting register TO based on the ON / OFF state of a predetermined abnormality flag.

[0244] If the abnormality flag is ON because the memory access of the drawing circuit 74 has taken an abnormally long time, even if the drawing circuit 74 has finished the drawing operation, it is determined that the operation start conditions have not been met, and the process proceeds to the performance command analysis process of step ST9.

[0245] The reason for skipping steps ST4 to ST8 is to avoid unreasonable screen display, since the memory access of the drawing circuit 74 is taking an abnormally long time, and there is a possibility that normal image data is not being generated, including bit garbled command data.

[0246] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21, and if a control command CMD has been received, the control command CMD is analyzed and necessary processing is performed. Here, the necessary processing includes a process for preparing to start a new variable performance based on the control command CMD that instructs the start of a variable performance, and a process for starting an error notification based on the control command CMD that indicates the occurrence of an error.

[0247] Next, the counter value is reloaded into the watchdog timer WDT 58, thereby preventing the watchdog timer 58 from starting (ST10). As explained above, even in the event of an abnormality that causes the watchdog timer 58 to start, the combined chip 50 of this embodiment enters a software reset state, which is different from a hardware reset. This completes the operation of this operation cycle, so the process proceeds to step ST2 and waits for the next VBLANK interrupt.

[0248] Although the above has explained the case where the operation start conditions are not satisfied, normally, after the judgment process of step ST3, the image data to be read by the display circuit 71 is identified based on the set value of the predetermined display register RGij, and the operation of the display circuit is started (ST4). As explained above, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the set value of the predetermined display register RGij so that they toggle between each other.

[0249] Specifically, the index number N1 / N2 of the first buffer or second buffer specified as the "write area" by the display list DL of the previous operation cycle is set. By executing this step ST4, the "write area" of the previous operation cycle changes to the "read area" of the current operation cycle, so that the display circuit 71 outputs the image data completed by the drawing circuit 74 in the immediately previous operation cycle to the display device DS. In other words, the processing of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0250] After the processing of step ST4, which has the above significance, is completed, the performance control CPU 57 then completes a display list DL that specifies the image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) in the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see FIG. 8).

[0251] In principle, the display list DL is created every time with its contents changed for each operation cycle, but the leading area of ​​the display list DL contains a command that specifies the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double buffer structure, with index numbers N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternately specifies the frame buffer FB with index number N1 and the frame buffer FB with index number N2, rotating the "write area."

[0252] The performance control CPU 57 issues the display list DL thus completed to the general performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN that centrally manages image performance, audio performance, lamp performance, and motor performance (ST7), and if it is the necessary performance timing, issues a voice command list VC to the audio processing unit SND to start or progress the audio performance (ST8).

[0253] When the start time of the motor or lamp performance managed by the performance scenario EN is reached, the timer interrupt process (FIG. 15(b)) executes the motor or lamp performance based on the corresponding motor drive data or lamp drive data. The processes of steps ST9 to ST10 following step ST8 are as described above.

[0254] 16(a) and 16(b) are flowcharts showing the specific contents of the display list DL issuing process (ST6), and Fig. 16(c) is a schematic diagram showing the operation contents of the DL issuing process (ST6). As explained with reference to Fig. 9, the display list DL issuing process can be performed in two ways: by accessing the CPU register port PORT by write access in 32-bit units (Fig. 9(a)), or by not accessing the CPU register port PORT (Fig. 9(b)). The operation contents of each are shown in Fig. 16.

[0255] First, referring to Figure 16(a), the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and also sets the total size of the transfer data in a specified transfer register RGij (ST30).

[0256] Here, the display list DL has different contents for each operation cycle, but is issued after being terminated by a predetermined end command EODL. In this embodiment, the instruction commands used for the display list DL, including the end command EODL, are one word or multiple words (=N*32 bits), so there is no need to adjust the amount of data. In other words, the total size of the transfer data set in the transfer register RGij is any value that is an integer multiple of 32 bits.

[0257] Next, the performance control CPU 57 sets the number of writes corresponding to the total size of the transfer data in the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the instructions to start the operation of the drawing circuit 74 and the data transfer circuit 70 are realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively.

[0258] Next, the performance control CPU 57 checks that the 130-stage CPU data FIFO circuit is not full, and writes the configuration data of the display list DL to the CPU register port PORT in 32-bit units (ST35).Then, it continues the write operation while decrementing the management counter CN (ST36, ST37).

[0259] As explained above, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, in principle, when 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data is transferred to data relay unit CH2, but when the set value for transfer register RGij (total size of transfer data) is reached, the accumulated data in the CPU data FIFO circuit at that time is transferred to data relay unit CH2.

[0260] The above process completes the DL issuing process (ST6) via the CPU register port PORT, but next, Figure 16(b) shows an example in which the data transfer circuit 70 reads the display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and also sets the total size of the transfer data and the starting address of the list buffer BUF in the specified transfer register RGij (ST41).

[0261] As explained above, the starting address of the list buffer BUF set in the internal RAM 59 must be set in 8-bit units, so the lowest 7 bits of the starting address of the DL buffer BUF are set to zero. This address condition applies not only to the starting address of the list buffer BUF that stores the display list DL, but also to the starting address of the list buffer BUF that stores the voice command list VC.

[0262] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). Note that these operation instructions are also realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation upon completion of the transfer of a predetermined amount of data. Therefore, after processing step ST43, the performance control CPU 57 can immediately proceed to another process following the display list issuance process (ST6).

[0263] In this case as well, when the amount of transfer data reaches the set value (total size of transfer data) in the transfer register RGij, the data stored in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0264] The above has explained the process of issuing a display list DL based on Figures 16(a) and 16(b), but when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as Figures 16(a) and 16(b) (see Figures 9(f) and 9(g)).

[0265] That is, the voice command list VC listing the voice commands is terminated with a predetermined end command EOSC before being issued. Note that a voice command, including the end command EOSC, is one word or multiple words (=N*32 bits), so no adjustment processing of the data amount is required.

[0266] The above has been a description of the case where the preloader 72 is not used, but the main processing when the preloader 72 is used is as shown in Fig. 17(a). The processing content shown in Fig. 17(a) is similar to the processing content shown in Fig. 15(a).

[0267] However, as shown in FIG. 17(a), (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 (ST60) instead of the drawing circuit 74, and (b) this display list DL is rewritten by the preloader 72 to become a rewrite list DL', but the rewrite list DL' rewritten in the previous operation cycle is acquired by the drawing circuit 74 (ST41) prior to the processing of step ST5, which is different from the processing of FIG. 15(a).

[0268] 17(a), the issue process (ST60) for issuing the display list DL to the preloader 72 is almost the same as that of Figures 16(a) and 16(b), except that the issue destination is changed to the preloader 72. The outline of the operation is as shown in Figures 9(d) and 9(e), and in response to the change in the issue destination to the preloader 72, the data relay unit CH2 is changed to the data relay unit CH3 (data transfer channel CH3), but other than that, the operation is the same as that of Figures 16(a) and 16(b), and the corresponding operations are shown in Figures 17(b) and 17(c).

[0269] On the other hand, the process of acquiring the rewrite list DL' by the drawing circuit 74 (ST41 in FIG. 17) is shown in FIG. 17(d). As shown in FIG. 9(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see FIG. 6(a)).

[0270] In the processing of step ST41 in Fig. 17, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Fig. 17(d)). Next, the total size of the rewrite list DL', which is the transfer data, and the starting address of the preload buffer in which the rewrite list DL' is stored are set in a predetermined transfer register RGij (ST51).

[0271] Since the starting address in VRAM 53 must be set in 32-bit units, the starting address of the preload buffer that stores the rewrite list DL' must have the lower 31 bits set to zero, and in this embodiment, the preload buffer is allocated at a location that meets this condition.

[0272] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST52) and starts the operation of the data transfer circuit 70 (ST53). Note that these operation instructions are realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and upon completion of the data transfer, the data transfer circuit 70 ends its operation.

[0273] Although the first embodiment of the present invention has been described above, the specific description does not particularly limit the present invention and can be modified as appropriate. For example, in the above embodiment, a configuration was described in which, when the memory access period of the drawing circuit 74 or the decoding processing time is prolonged, the abnormality is detected by flag polling processing, but it goes without saying that abnormal interrupt processing may also be utilized.

[0274] Figure 15(d) shows an example of a configuration for such a case. When a drawing abnormality interrupt occurs, only the drawing circuit 74 is reset individually (ST23), the operating parameters required for the operation of the drawing circuit 74 are reset, the stack area is appropriately released (ST24), and the process proceeds to step ST9.

[0275] [Configuration example of first embodiment] (Configuration example M1) Here, the gaming machine GM as the first embodiment described above can be expressed as having a configuration as the following configuration example M1. That is, the gaming machine GM as the configuration example M1 is an image control means for issuing a display list that specifies the display content to be displayed on the display device; and image generating means configured to operate based on the display list and generate two-dimensional or three-dimensional still image data and / or video image data in a predetermined frame buffer, the image generation means is configured to be able to execute all or part of a plurality of steps including an acquisition step capable of acquiring vertex data corresponding to an image contour, a primitive step of generating an appropriate primitive based on the vertex data, and an image generation step of generating image data required for the frame buffer; The display list issued at a predetermined timing specifies basic data to be decoded and a rendering area into which the basic data will be decoded, and then describes one or more first commands that instruct decoding processing, and one or more second commands that appropriately specify a drawing area of ​​the frame buffer and instruct drawing of the texture in the drawing area, The image generating means is configured to operate based on the display list and generate predetermined still image data in the frame buffer without going through the acquisition step or the primitive step.

[0276] According to the gaming machine GM as the above configuration example M1, even in the case of an advanced two-dimensional or three-dimensional image presentation, it is possible to execute a smooth and appropriate image control operation.

[0277] (Configuration example M2) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M2. That is, the gaming machine GM as the configuration example M2 is an image control means for issuing a display list that specifies the display content to be displayed on the display device; and image generating means configured to operate based on the display list and generate two-dimensional or three-dimensional still image data and / or video image data in a predetermined frame buffer, the image generation means is configured to be able to execute all or part of a plurality of steps including an acquisition step capable of acquiring vertex data corresponding to an image contour, a primitive step of generating an appropriate primitive based on the vertex data, and an image generation step of generating image data required for the frame buffer; The display list issued at a predetermined timing specifies basic data to be decoded and a rendering area into which the basic data will be decoded, and then describes one or more first commands that instruct decoding processing, and one or more second commands that appropriately specify a drawing area of ​​the frame buffer and instruct drawing of the texture in the drawing area, The image generating means is configured to operate based on the display list and generate predetermined moving image data in the frame buffer without going through the acquisition step or the primitive step.

[0278] According to the gaming machine GM as the above configuration example M2, even in the case of an advanced two-dimensional or three-dimensional image presentation, it is possible to execute smooth and appropriate image control operations.

[0279] (Configuration example M3) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M3. That is, the gaming machine GM as the configuration example M3 is A gaming machine comprising: an image control means for issuing a display list that specifies display content to be displayed on a screen of a display device; and an image generation means for generating image data that realizes the display content based on the display list and basic data of an appropriate storage means, The display list issued at a predetermined timing includes one or more first commands that specify the basic data and the area where the basic data is expanded, and then instructs the execution of a read process and a decode process of the basic data; one or more second commands specifying the decoded data of the expansion area, a filter process to be performed on the decoded data, and parameters defining the content of the filter process, and instructing the execution of the filter process; Image data based on the first command and the second command of the display list is configured to be displayable on the display device.

[0280] According to the gaming machine GM as the above configuration example M3, even with sophisticated image presentation, the first command and the second command written in the display list can be used to smoothly and appropriately execute image control operations.

[0281] (Configuration example M4) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M4. That is, the gaming machine GM as the configuration example M4 is an image control means for issuing a display list that specifies the display content to be displayed on the screen of the display device; and image generating means having a drawing circuit for generating image data for realizing the display contents based on the display list and basic data of an appropriate storage means, The image control means has a setting means for setting an appropriate abnormality determination time in a predetermined register of the image generation means, The image generating means a monitoring means for monitoring a memory access time interval by the drawing circuit and / or a decoding execution time for decoding the basic data; and a determining means for determining that an abnormal situation has occurred when the memory access time interval or the decoding execution time exceeds the abnormality determining time.

[0282] According to the gaming machine GM as the above configuration example M4, abnormal situations can be properly grasped, and therefore even with sophisticated image presentation, smooth and appropriate image control operations can be executed.

[0283] (Configuration example M5) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M5. That is, the gaming machine GM as the configuration example M5 is an image control means for issuing a display list that specifies the display content to be displayed on the screen of the display device; an image generating means for generating image data for realizing the display content based on the display list and basic data that has been appropriately compressed and stored, the display list includes a decode command for instructing decoding of the basic data in relation to video playback; The predetermined decode command is configured so that the first and second basic data can be specified by one command.

[0284] According to the gaming machine GM as the above configuration example M5, it is possible to execute smooth and appropriate image control operations even in the case of complex and advanced image presentations.

[0285] (Configuration example M6) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M6. That is, the gaming machine GM as the configuration example M6 is a CPU means for issuing first information specifying an image rendering by the display device and second information specifying an audio rendering; VDP means for generating image data for realizing the image presentation based on the first information issued by the CPU means and basic image data stored in an appropriate storage means; a sound means for realizing the sound effects based on the second information issued by the CPU means and basic sound data stored in an appropriate storage means; A gaming machine configured by providing a monitoring means for constantly monitoring the operation of all or part of the CPU means, the VDP means, and the sound means in a single circuit element, When the monitoring means detects an abnormal state, an arbitrarily set reset operation different from the hardware reset operation at power-on can be executed.

[0286] According to the gaming machine GM as the above configuration example M6, the abnormal reset operation can be optimized, so that even with sophisticated image presentation, smooth and appropriate image control operation can be executed.

[0287] (Configuration example M7) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M7. That is, the gaming machine GM as the configuration example M7 is a CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A gaming machine provided with a transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The first information and / or the second information is configured to be stored in an address area of ​​an internal RAM or an external RAM, starting from a start address where the bits below a predetermined number are zero.

[0288] According to the gaming machine GM as the above configuration example M7, the control burden on the CPU means in data transfer is reduced and the setting of the start address of the transfer process is simplified, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0289] (Configuration example M8) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M8. That is, the gaming machine GM as the configuration example M8 is a CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A gaming machine provided with a transfer means for transferring the first information and the second information to the first circuit and the second circuit in units of a predetermined transfer size, The first information and / or second information is composed of a list of instruction commands that are an integer multiple N (N≧1) of a reference size, and the transfer size is an integer multiple M (M≧1) of the reference size, so that the number of instruction commands in the first information and / or second information can be any number.

[0290] According to the gaming machine GM as the above configuration example M8, the degree of freedom in configuring the instruction commands for the first information and / or the second information is increased, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0291] (Configuration example M9) Moreover, the gaming machine GM according to this embodiment can be expressed as having a configuration as the following configuration example M9. That is, the gaming machine GM as the configuration example M9 is a CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A gaming machine provided with a transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The CPU means The data constituting the first information and the second information is written to a predetermined write port in units of a predetermined write size.

[0292] According to the gaming machine GM as the above configuration example M9, the transfer means can be made to function based on the management of the CPU means, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0293] (Configuration example M10) Moreover, the gaming machine GM as this embodiment can be expressed as having a configuration as the following configuration example M10. That is, the gaming machine GM as the configuration example M10 is a CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A gaming machine provided with a transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The transmission path for the first information and / or the transmission path for the second information is configured so that one transmission circuit can be selected from a plurality of options.

[0294] According to the gaming machine GM as the above configuration example M10, the optimum transmission path can be selected, so that even with sophisticated image presentation, smooth and appropriate image control operations can be executed.

[0295] [Modification of the first embodiment] The initialization of the CPU circuit 51 may be configured to follow the procedure below. The system clock frequency is set, and the method for loading the boot program for initializing the CPU circuit 51 is set. The system clock frequency is set by referencing predetermined terminal information that has been set in advance. The method for loading the boot program is also set by referencing predetermined terminal information, and a memory device for reading the boot program is selected according to the terminal information. Here, the terminal information is set in advance so that the performance control ROM (external ROM 55) is set as the memory device. Once these processes are completed, a hardware reset is performed.

[0296] Next, the CPU circuit 51 executes standby processing until the initialization of the overall performance circuit 52 is complete. The overall performance circuit 52 references predetermined terminal information and executes a hardware reset by confirming that the information indicates initialization for a certain period of time. This initializes each circuit unit included in the overall performance circuit 52. Here, the overall performance circuit 52 may be configured to reference the predetermined terminal information, or the CPU circuit 51 may be configured to initialize the overall performance circuit 52 by referencing the predetermined terminal information. Then, once the initialization of the overall performance circuit 52 is completed and a stable clock is supplied from the system clock, the reset state of each circuit unit of the overall performance circuit 52 is released, and the functions of each circuit unit become available. The CPU circuit 51 executes standby processing until this series of processing is complete. At this time, the standby processing of the CPU circuit 51 may be configured to wait for a predetermined period of time, or may be configured to end the standby processing by referring to or confirming at least one of the following: referring to predetermined terminal information, checking a predetermined built-in register, or confirming that the system clock supply has stabilized. Also, if the standby process is not completed after a predetermined time has elapsed (initialization of the overall performance circuit 52 is not completed for some reason), the standby process may be configured to continue until initialization of the overall performance circuit 52 is completed, or the hardware reset may be performed again when a predetermined time has elapsed or by a watchdog timer.

[0297] Once the initialization of the overall performance circuit 52 is complete, the next step is to set the number of operating CPU cores. In the initial state immediately after a hardware reset, only one of the four CPU cores is operating, so the number of CPU cores to be used is changed and processing is performed to activate the stopped cores. If the processing efficiency of the CPU circuit 51 is emphasized, it is desirable to operate all CPU cores, but if the content of the performance control does not require a high processing load, it may be set to use only some of the CPU cores.

[0298] Next, the system executes processing to change the settings for the recovery method when an abnormality occurs in each circuit section from the initial state as necessary. For example, it executes processing to change the settings for the method of determining an abnormal state of the system clock and the recovery method, and the reset operation when a timeout occurs in the watchdog timer, etc.

[0299] Next, power-saving functions are set for each circuit section. This makes it possible to turn off the system clock and power supplied to some circuit sections. In other words, by turning off the clock and power for unused circuits and circuits in standby mode (such as the LED controller and motor controller inside the composite chip, not shown), it becomes possible to reduce power consumption.

[0300] Next, the display output clock and sound clock are initialized. The frequencies and supply sources of the display output clock and sound clock are set in built-in registers, and then a reset process is executed. As a result, the values ​​set in the built-in registers are reflected as clock control parameters during initialization. The CPU circuit 51 is configured to wait until the initialization of the display output clock and sound clock is complete before using the display circuit 71 and the audio processing unit SND. At this time, the CPU circuit 51 may be configured to wait a predetermined time until the initialization of the display output clock and sound clock is complete, or may be configured to end the standby process by referencing or confirming at least one of predetermined terminal information, predetermined built-in registers, or stabilizing the system clock supply. Furthermore, if the standby process is not completed after the predetermined time has elapsed (if the initialization of the display output clock and sound clock is not completed for some reason), the standby process may be continued until the initialization of the display output clock and sound clock is completed, or may be configured to execute a hardware reset again after the predetermined time has elapsed or by a watchdog timer. Here, the configuration may be such that the sound clock is initialized after the display output clock has been initialized, or the display output clock and the sound clock are initialized in parallel.

[0301] The initialization of the drawing circuit 74 may be configured as follows. The drawing circuit 74 is initialized by setting a predetermined value in a predetermined register. During initialization, it is possible to confirm that the drawing circuit 74 is being initialized by the status register having a specific value. The initialization of the drawing circuit 74 at this time is performed as follows. First, when a predetermined value is set in a predetermined register, a clearing process is performed so that the internal parameters set in the display list DL are set to their initial values. Next, the drawing circuit 74 is controlled to its initial state, and the GDEC circuit 73 and image filter circuit 75 are initialized in sequence. After that, the index table INDXTBL is initialized, and then all index spaces in the page area and AAC area are released. After that, the information in the optional area and page area is cleared.

[0302] The drawing circuit 74 may be configured to have a first status register for checking the overall status of the drawing circuit 74 and a second status register for checking the progress of the analysis of the display list DL. Similarly, the drawing circuit 74 may also have separate registers for checking the progress of the drawing process for the input assembler process IA, geometry engine process TL, rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, render process RO, stencil buffer, vertex buffer, frame buffer cache, GDEC circuit 73, image filter circuit, and other components. By checking the contents of these internal status registers, the CPU circuit 51 can check the progress of the drawing process for each functional block. Of course, it is desirable that the contents of the internal status registers remain unchanged even when drawing commands unrelated to the functional blocks are executed, and that the contents of the internal status registers change only for the functional blocks that are actually used.

[0303] The following configuration may be adopted so that the drawing commands written in the display list DL are drawn in the order they are written in the display list DL. For example, in a case where image data drawn by a drawing command written earlier in the display list DL is used as texture by a drawing command written later, a configuration may be adopted in which a standby process is executed to wait for the command analysis process and / or command execution process of the later drawing command until the drawing process of the image data by the earlier drawing command is completed.

[0304] Furthermore, if a drawing command that does not exist in the display list DL is described due to a malfunction or error, the display list DL itself may be discarded, or only the non-existent drawing command may be treated as an error and discarded. In this case, abnormality information indicating that an abnormal drawing command is included may be checked in a predetermined register. In such cases, an error interrupt process may be executed, which occurs only when an abnormality occurs. Furthermore, if an abnormal drawing command is included, if the command size of the drawing command is abnormal, or if the display list DL itself is abnormal, an error information indicating that the drawing circuit 74 is abnormal may be checked in a predetermined register. In such cases, an error interrupt process may be executed, which occurs only when an abnormality occurs.

[0305] Furthermore, when it is detected that the display list DL contains an abnormal command as described above, or when there are no read and / or write requests to the VRAM 53 for a certain period of time, the drawing circuit 74 may be configured to be initialized by writing a predetermined value to a predetermined register.

[0306] The image filter circuit 75 may be configured so that the filtering process on the texture by the image filter circuit 75 and the processing by the drawing circuit 74 are executed independently and in parallel. When the drawing circuit 74 receives a display, the display list DL is analyzed, and an execution request is sent from the drawing circuit 74 to the image filter circuit 75. In accordance with the execution request, the image filter circuit 75 is configured to read image data to be the texture from the VRAM 53 or CGROM (external ROM 55), and write the processing results to the VRAM 53 or expansion RAM 54. These processes by the image filter are executed independently and in parallel with the analysis process of the display list DL by the drawing circuit 74 and other drawing processes.

[0307] The image filter circuit 75 may be configured to include a FIFO circuit. This allows the contents of drawing commands related to filtering for the image filter circuit 75 to be queued in the FIFO circuit along with execution parameters. It is also desirable to configure the queued execution parameters so that they are not affected by filtering by drawing commands already being executed. It is also desirable for the FIFO circuit to have multiple stages (e.g., four stages), and it is desirable to configure the display list analyzer to stall and not analyze any drawing commands beyond this stage until there is free space in the FIFO circuit within the image filter circuit 75. It is also desirable to configure the image filter circuit 75 so that the free space in the FIFO circuit can be checked using a specified register. It is also desirable for the CPU circuit 51, the drawing circuit 74, or the display list analyzer to check the free space in the FIFO circuit within the image filter circuit 75 by referencing a specified register, and if there is free space, to analyze the drawing command and / or send the contents of the drawing command along with the execution parameters to the free space in the FIFO circuit within the image filter circuit 75.

[0308] If an abnormality occurs within the image filter circuit 75, the filter processing currently being executed may be interrupted. Furthermore, if the texture being referenced by the image filter circuit 75 is stored in an AAC area, the AAC area may be released. Furthermore, the cause of the abnormality may be recorded in a predetermined register. It is desirable that the image filter circuit 75 then notifies the drawing circuit 74 of the abnormal termination and continues to execute the next filter processing.

[0309] 2. Second Embodiment Next, a second embodiment will be described. The second embodiment proposes various configurations relating to the isolated transmission of electrical signals in a communication board. In the following description, parts that are similar to parts that have already been described will be given the same reference numerals and description thereof will be omitted.

[0310] FIG. 18 is a block diagram for explaining a schematic circuit configuration of the gaming machine GMA as the second embodiment. As shown in the figure, the gaming machine GMA as the second embodiment is equipped with the main control board 21, presentation interface board 22, presentation control board 23, LCD interface board 24, display device DS, payout control board 25, and launch control board 26 described in the first embodiment, as well as an external terminal board 81 for the frame, a gaming ball payout device 84, a full detection sensor 82, and a front door open sensor 83. In Figure 18, of the components described in Figure 3(a), those other than those relating to the second embodiment are omitted from the illustration (for example, power supply board 20, lamp drive board 30, lamp drive board 31, game board relay board 32, motor / lamp drive board 37, etc.), but the gaming machine GMA of the second embodiment also has these components.

[0311] As shown in the figure, an external centralized terminal board for the frame 81 is connected to the payout control board 25, and the main control board 21 is able to transmit specified game information (e.g., jackpot information, number of winning balls information, pattern change execution information, etc.) to an externally installed hall computer HC via the payout control board 25 and this external centralized terminal board for the frame 43. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 21 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0312] In addition, the payout control board 25 is connected to a game ball payout device 84 and also to a ball lending machine 80. The ball dispensing machine 80 is provided outside the gaming machine GMA and executes processing to cause the payout control board 25 to execute the ball dispensing operation. The main roles of the payout control board 25 are to receive payout control commands from the main control board 21, control the payout of prize balls from the game ball payout device 84 based on the payout control commands, send status signals to the main control board 21, and control the ball lending operation based on the communication results with the ball lending machine 80.

[0313] The game ball payout device 84 is provided with a supply shortage detection sensor (not shown) that detects a shortage of game balls and a ball counting sensor (not shown) that detects the game balls (prize balls) that are paid out, and the payout control board 25 is capable of receiving each of these detection signals. In addition, the game ball payout device 84 is provided with a payout motor 84a that drives a ball payout mechanism unit (not shown) for paying out game balls, and the payout control board 25 is capable of transmitting a control signal for controlling the payout motor 84a.

[0314] In addition, the payout control board 25 is connected to a full detection sensor 82 that detects whether the upper tray 8 is full of game balls, and a front door open sensor 83 that detects whether the aforementioned front door member (glass door and front panel 7) is open.

[0315] The payout control board 25 is capable of transmitting various status signals to the main control board 21 based on detection signals from the full detection sensor 82, the front door open sensor 83, the aforementioned out-of-supply detection sensor, and the ball counting sensor. These status signals include a ball jam signal indicating a full state, a door open signal indicating at least the front door is open, an out-of-supply signal indicating a shortage of game balls from the game ball payout device 84, a count error signal indicating a shortage of prize balls or an abnormality in the ball counting sensor, and a payout completion signal indicating the completion of the payout operation. Based on these status signals, the main control board 21 monitors the open state of the front door (door open error), whether the payout operation of the game ball payout device 84 is normal (out-of-supply error), and the full state of the upper tray 8 (ball jam error).

[0316] The payout control board 25 is also capable of transmitting an authorization signal to the launch control board 26 to authorize launch. Based on the authorization signal output from the payout control board 25, the launch control board 26 controls the energization of the launch solenoid, thereby realizing the launch of game balls by operating the launch handle 10. Specifically, the launch of game balls is permitted under the following conditions: a launch authorization signal is output from the payout control board 25 (launch authorization signal ON state), a touch sensor (not shown) provided on the launch handle 10 detects that the player is touching the handle, and a launch stop switch (not shown) provided on the launch handle 10 has not been operated. Therefore, when the launch authorization signal is not output (launch authorization signal OFF state), no launch operation is performed even if the launch handle 10 is operated, and no game balls are launched. Furthermore, the launch strength of the game balls can be changed depending on the amount of operation of the launch handle 10. Furthermore, when the payout control board 25 detects the above-mentioned ball jam error, it sends a ball jam signal to the main control board 21 and stops outputting the launch permission signal to the launch control board 26 (launch permission signal OFF), and controls the firing operation to stop until the upper tray 8 is no longer full. In addition, the payout control board 25 outputs a launch permission signal to the launch control board 26 on the condition that the main control board 21 has instructed the launch permission.

[0317] [2.1 Overview of communication functions with external devices and communication board configuration] Here, the gaming machine GMA of this embodiment is equipped with a communication board for performing signal communication with an external device. Specifically, the gaming machine GMA of this embodiment is equipped with a payout control board 25 for performing signal communication with a ball dispensing machine 80, which is an external device of the gaming machine GMA.

[0318] FIG. 19 is an explanatory diagram of an example of signals communicated between the payout control board 25 and the ball dispenser 80. The payout control board 25 sends and receives various control signals related to ball lending operations between the ball lending machine 80, such as the BRDY signal, BRQ signal, EXS signal, and PRDY signal shown in the figure.

[0319] The BRDY signal is a signal transmitted from the ball lending machine 80 to the gaming machine to indicate that the player has turned on a ball lending switch (not shown) provided on the gaming machine GMA and that the machine is in the ball lending operation. Although an illustrated explanation is omitted, a signal indicating the operation state of the ball lending switch is input directly to the ball lending machine 80, and the ball lending machine 80 outputs a BRDY signal to the payout control board 25, indicating that the ball lending switch has been turned on and that the machine is in the ball lending operation. In this example, the BRDY signal is a signal that falls, for example, from H level to L level in response to the ball lending switch being turned ON.

[0320] The BRQ signal is a signal that requests the gaming machine to dispense one unit (for example, 25 balls) of balls from the ball dispenser 80. In this example, the BRQ signal is a signal that falls, for example, from H level to L level at the timing indicating a request for one unit of dispense operation.

[0321] When the BRQ signal falls to L level while the BRDY signal is at L level, a ball lending operation for one unit is initiated. If the BRDY signal is at H level when the ball lending operation is completed, or if the BRDY signal changes to H level within a predetermined time after the completion of the ball lending operation, the ball lending operation is no longer executed. Therefore, the BRDY signal can be considered a "ball lending permission command," and the BRQ signal can be considered a "ball lending start command." In other words, as long as the BRDY signal is at L level, the ball lending operation is permitted. In this example, when the BRQ signal falls within this permitted period, the payout operation (lending operation) of one unit of game balls is initiated in response.

[0322] On the other hand, the PRDY signal is a signal that transmits from the payout control board 25 to the ball lending machine 80 that the gaming machine GMA is capable of ball lending operation. In this example, the PRDY signal is a signal that indicates that the L level is capable of ball lending operation.

[0323] The EXS signal is a signal that transmits from the payout control board 25 to the ball dispensing machine 80 that a request for one unit of ball dispensing operation via the BRQ signal has been received and that the dispensing operation has been completed. In this example, the EXS signal is a signal that becomes L level from the time a request for one unit of ball dispensing operation via the BRQ signal is received until the time the dispensing operation is completed, and becomes H level at other times. In other words, the EXE signal is a signal that indicates the period from when a request for one unit of ball lending operation is received by the BRQ signal until the ball lending operation is completed.

[0324] FIG. 20 is a diagram showing an example of the arrangement of various electronic components on the dispensing control board 25. As shown in the figure, resistors (R1 to R65, etc.), capacitors (C1 to C59, etc.), various diodes (D1 to D8, ZD1, LED1 to LED4, etc.), various filters (FLT1 to FLT7, etc.), and various integrated circuits (Integrated Circuits: IC1 to IC14, etc.) are arranged on the dispensing control board 25. In addition, various connectors (CN1 to CN12) are arranged on the payout control board 25. The payout control board 25 is electrically connected to other boards in the gaming machine GMA and external devices via these connectors.

[0325] 18, in this example, the connector CN3 is a connector for connecting to the main control board 21. Also, the connectors CN2 and CN8 are connectors for connecting to the launch control board 26, the connector CN4 is a connector for connecting to the frame external terminal board 81, and the connector CN6 is a connector for connecting to the game ball payout device 84 (payout motor 84a). Furthermore, the connector CN7 is a connector for connecting to the ball dispensing machine 80. In this example, the above-mentioned BRDY signal, BRQ signal, PRDY signal, and EXS signal are transmitted and received via this connector CN7.

[0326] Here, an insulating transmission means for providing electrical insulation on the signal communication path between the dispensing control board 25 and the external device is implemented on the dispensing control board 25. Specifically, in this example, a photocoupler PC for providing electrical insulation on the signal communication path between the dispensing control board 25 and the ball dispenser 80 is implemented on the dispensing control board 25 (see Figure 20). In this example, five photocouplers PC, PC1 to PC5, are implemented, and these photocouplers PC1 to PC5 are located on the payout control board 25 in relatively close proximity to the connector CN7 for connecting to the ball dispensing machine 80.

[0327] The signals sent and received between the payout control board 25 and the ball dispenser 80, i.e., the above-mentioned BRDY signal, BRQ signal, PRDY signal, and EXS signal, are sent and received via a corresponding one of these photocouplers PC1 to PC5.

[0328] The signal paths for the signals transmitted to and received from the ball dispensing machine 80, such as the BRDY signal, BRQ signal, PRDY signal, and EXS signal, will be described below with reference to the circuit diagrams of Figures 21 to 24.

[0329] FIG. 21 is a circuit diagram showing the connection between the connector CN7 and each photocoupler PC. In this example, the connector CN7 is a six-terminal connector. As shown in the figure, terminal 1 of connector CN7 is the transmitting terminal for the PRDY signal (the terminal for transmitting the signal from the payout control board 25 to the ball dispensing machine 80), terminal 2 is the transmitting terminal for the EXS signal, terminal 3 is the receiving terminal for the VL signal, terminal 4 is the receiving terminal for the BRDY signal, terminal 5 is the receiving terminal for the BRQ signal, and terminal 6 is the ground terminal.

[0330] The VL signal is a signal of a power supply common to the interface, and is, for example, a DC 18V power supply signal. As shown in the figure, the VL signal is input to the dispensing control board 25 side as a P-OUT signal via a photocoupler PC5. In photocoupler PC5, a photodiode is inserted between terminals 3 and 6 of connector CN7, so that a current corresponding to the VL signal flows from terminal 3 to terminal 6 via the photodiode. As a result of this current flowing through the photodiode in response to the VL signal, a current corresponding to the VL signal flows through the collector of the phototransistor in photocoupler PC5. This produces a P-OUT signal corresponding to the VL signal on the secondary side of photocoupler PC5.

[0331] Here, the primary side of the photocoupler PC means the side where a photodiode (electrical to optical conversion means) is provided, and the secondary side of the photocoupler PC means the side where a phototransistor (optical to electrical conversion means) is provided.

[0332] Of the photocouplers PC1 to PC4, photocoupler PC1 is used to transmit (send) the PRDY signal, photocoupler PC2 is used to transmit (send) the EXE signal, photocoupler PC3 is used to transmit (receive) the BRDY signal, and photocoupler PC4 is used to transmit (receive) the BRQ signal. For convenience, in the following explanation, the PRDY signal input to photocoupler PC1 will be referred to as the "P-RDY signal," and the EXS signal input to photocoupler PC2 will be referred to as the "P-EXS signal." Similarly, the BRDY signal output from photocoupler PC3 will be referred to as the "B-RDY signal," and the BRQ signal output from photocoupler PC4 will be referred to as the "B-RQ signal."

[0333] In photocoupler PC1, the anode of the photodiode is connected to a DC power supply such as DC 12V via resistor R36, and the cathode is connected to the transmission line of the P-RDY signal (a signal that indicates whether the PRDY signal is at H level or L level).The collector of the phototransistor in photocoupler PC1 is connected to terminal 1 of connector CN7 via resistor R20, and the emitter is connected to terminal 6 of connector CN7. As a result, a PRDY signal based on the P-RDY signal is supplied to terminal 1 of connector CN7 via photocoupler PC1. The signal transmission path of the PRDY signal is electrically insulated by photocoupler PC1.

[0334] In photocoupler PC2, the anode of the photodiode is connected to a DC power supply such as DC 12V via resistor R37, and the cathode is connected to the transmission line of the P-EXS signal (the signal that forms the basis of the EXS signal).The collector of the phototransistor in photocoupler PC2 is connected to terminal 2 of connector CN7 via resistor R21, and the emitter is connected to terminal 6 of connector CN7. As a result, an EXS signal based on the P-EXS signal is supplied to the second terminal of the connector CN7 via the photocoupler PC2, and the signal transmission path of the EXS signal is electrically insulated by the photocoupler PC2.

[0335] In photocoupler PC3, the anode of the photodiode is connected to terminal 3 of connector CN7 via resistor R22, and the cathode is connected to terminal 4 of connector CN7. The collector of the phototransistor in photocoupler PC3 is connected to a DC power supply such as DC 12V via resistor R39, and a transmission line for a B-RDY signal (a signal indicating whether the BRDY signal is H level or L level) is connected to the connection point between the collector and resistor R39. An RC circuit consisting of resistor R38 and capacitor C23 is inserted in this B-RDY signal transmission line. The emitter of the phototransistor in photocoupler PC3 is grounded. As a result, the B-RDY signal based on the BRDY signal input to terminal 4 of connector CN7 is supplied to the transmission line of the B-RDY signal via photocoupler PC3, and the signal transmission path of the BRDY signal is electrically isolated by photocoupler PC3.

[0336] In photocoupler PC4, the anode of the photodiode is connected to terminal 3 of connector CN7 via resistor R23, and the cathode is connected to terminal 5 of connector CN7. The collector of the phototransistor in photocoupler PC4 is connected to a DC power supply such as DC 12V via resistor R41, and a transmission line for a B-RQ signal (a signal indicating whether the BRQ signal is H level or L level) is connected to the connection point between the collector and resistor R41. An RC circuit consisting of resistor R40 and capacitor C24 is inserted in this B-RQ signal transmission line, and the emitter of the phototransistor in photocoupler PC4 is grounded. As a result, a B-RQ signal based on the BRQ signal input to terminal 5 of connector CN7 is supplied to the transmission line of the B-RQ signal via photocoupler PC4, and the signal transmission path of the BRQ signal is electrically isolated by photocoupler PC4.

[0337] Specific examples of paths for the BRDY signal, BRQ signal, EXS signal, PRDY signal, and P-OUT signal will be described with reference to the circuit diagrams of FIGS. Figure 22 <1> <2> As shown in the figure, the B-RDY signal, B-RQ signal, and P-OUT signal from photocouplers PC3, PC4, and PC5 are output as a BRDY signal, a BRQ signal, and a P-OUT signal, respectively, via integrated circuit IC5 on the dispensing control board 25.

[0338] The BRDY and BRQ signals output from the integrated circuit IC5 are <3> As shown in Figure 1, the data is input to the integrated circuit IC6 in the dispensing control board 25. The integrated circuit IC6 and the integrated circuit IC13 in the figure generate the PRDY signal and the EXS signal based on the BRDY signal and the BRQ signal. <5> As shown in FIG. 1, the PRDY signal and EXS signal are output from the integrated circuit IC13.

[0339] In addition, the POUT signal output from the integrated circuit IC5 (see Figure 22 <2> (see Figure 24) <4> As shown, the signal is input to the integrated circuit IC1 on the dispensing control board 25 via resistor R45.

[0340] The PRDY signal and EXS signal (Fig. 23) output from the integrated circuit IC13 <5> (see Figure 22) <6> <7> As shown in Fig. 21, these signals are output as a P-RDY signal and a P-EXS signal, respectively, via an integrated circuit IC11 in the dispensing control board 25. Specifically, these signals are output to photocouplers PC1 and PC2, respectively (see Fig. 21).

[0341] [2.2 Example of board configuration as an embodiment] Next, a configuration example of the dispensing control board 25 as the second embodiment will be described. 25 is a diagram showing an example of a wiring pattern on the front surface (component mounting surface) of dispensing control board 25, and FIG. 26 is a diagram showing an example of a wiring pattern on the back surface of dispensing control board 25. As shown in FIG. Here, in the various electronic boards provided in the gaming machine GMA, including the payout control board 25, various electronic components such as resistors, capacitors, diodes, integrated circuits, etc. are mounted on the front side and not on the back side.

[0342] As shown in the figure, the dispensing control board 25 has a substantially rectangular outer shape when viewed from above. In other words, the surface shape is substantially rectangular.

[0343] First, as a common feature on both the front and back sides, the dispensing control board 25 has through electrodes Tt formed in various places that penetrate the thickness of the board, and printed wiring as signal lines Ls and a ground Gn, which is a printed pattern as ground (GND), are formed on both the front and back sides.

[0344] The signal line Ls is a wiring for transmitting various signals handled by the dispensing control board 25, such as signals output from the integrated circuit IC, signals sent and received through the connector CN, and signals input to the integrated circuit IC. On both the front and back surfaces of the substrate, several signal lines Ls are wired so as to electrically connect different through electrodes Tt. Furthermore, on the surface of the substrate, signal lines Ls can be formed that are wired so as to electrically connect different electronic components without using the through electrodes Tt.

[0345] Here, when considering the photocoupler PC as the electrical isolation means as a reference, the circuits electrically connected to the photocoupler PC on the payout control board 25 can be broadly divided into the inner circuit Ci, which is the circuit electrically connected to other boards within the gaming machine GMA via connectors CN3, CN4, etc., and the outer circuit Co, which is the circuit electrically connected to an external device (ball dispensing machine 80) via connector CN7.

[0346] The region indicated by "Ai" in the drawing represents a region in which the through electrodes Tt connected to the terminals of the connectors CN3, CN4, and CN6 are formed (see also FIG. 20 above). Moreover, the region indicated by "Ao" in the drawing represents a region where the through electrodes Tt connected to the terminals of the connector CN7 are formed.

[0347] Furthermore, in the figure, the region indicated by "Api" represents a region in which a through electrode Tt is formed, which is connected to a terminal of the photocoupler PC that is electrically connected to the inner circuit Ci. Here, the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci corresponds to the anode terminal and cathode terminal of the photodiode in the photocouplers PC on the transmitting side, which are photocouplers PC1 and PC2, and corresponds to the collector terminal and emitter terminal of the phototransistor in the photocouplers PC on the receiving side, which are photocouplers PC3 to PC5. In the following description, the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci will be referred to as the "inner terminal." Moreover, the region indicated by "Apo" in the figure represents a region in which a through electrode Tt is formed, which is connected to the terminal of the photocoupler PC on the side electrically connected to the outer circuit Co. The terminal of the photocoupler PC on the side electrically connected to the outer circuit Co corresponds to the collector terminal and emitter terminal of the phototransistor in the photocouplers PC on the transmitting side, which are photocouplers PC1 and PC2, and corresponds to the anode terminal and cathode terminal of the photodiode in the photocouplers PC on the receiving side, which are photocouplers PC3 to PC5. In the following description, the terminal of the photocoupler PC that is electrically connected to the outer circuit Co will be referred to as the "outer terminal."

[0348] The inner circuit Ci will have a circuit area including at least through electrodes Tt for connectors CN3, CN4, and CN6 shown in area Ai, through electrodes Tt for connectors CN that are electrically connected to other boards within the gaming machine GMA, and through electrodes Tt for the inner terminals of the photocoupler PC shown in area Api. The area of ​​the outer circuit Co has at least a circuit area including a through electrode Tt for the connector CN7 indicated by an area Ao and a through electrode Tt for the outer terminal of the photocoupler PC indicated by an area Apo.

[0349] In this embodiment, the ground Gn of the inner circuit Ci and the outer circuit Co is a solid ground. The solid ground refers to a ground formed by a solid pattern. The solid pattern here refers to a printed wiring pattern that has a portion wider than the linear signal line Ls and a portion that surrounds the signal line Ls.

[0350] In addition, in this embodiment, the inner circuit Ci and the outer circuit Co are each formed across the front and back surfaces of the dispensing control board 25 via the through electrodes Tt.

[0351] In the dispensing control board 25 in this embodiment, a separation section Dv is formed which separates the area of ​​the inner circuit Ci from the area of ​​the outer circuit Co. In this example, the separation portion Dv is formed between the inner circuit Ci and the outer circuit Co as a portion where the ground Gn (solid ground) of each circuit is not formed.

[0352] As can be understood from the previous description of the regions Api and Apo, in this embodiment, each photocoupler PC is disposed on the separation portion Dv.

[0353] Furthermore, as can be seen by comparing Figures 25 and 26, in this embodiment, on both the front and back sides of the dispensing control board 25, the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci are separated by a separation section Dv.

[0354] In addition, in this example, the position and shape of the separation unit Dv are approximately the same on both the front and back sides of the dispensing control board 25. The position of the separation unit Dv here naturally means the position in the surface direction of the dispensing control board 25. Furthermore, "substantially the same" here does not only mean "completely the same" but also includes the range of tolerances allowed in the printing process of the print pattern. For example, it is sufficient if the position and shape of the separation portion Dv on the front and back surfaces are specified to be the same in design, and tolerances that occur in the actual pattern printing process should be allowed.

[0355] Furthermore, in the dispensing control board 25 of this example, the separation pattern in the board surface direction between the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci is the same on the front and back sides. In other words, the position and shape in the board surface direction of the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci are approximately the same on the front and back sides.

[0356] (2.2.1 Configuration example A) Here, according to the explanation with reference to the above-mentioned FIGS. 25 and 26, it can be said that the gaming machine GMA of this embodiment has the following configuration as "Configuration Example A". In other words, the gaming machine (GMA) as configuration example A is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board is formed with an outer circuit (Co) which is a circuit that is electrically connected to the external device, and an inner circuit (Ci) which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (Dv) that separates the outer circuit area from the inner circuit area, and an insulating transmission means is arranged on the separation section, and the outer circuit and inner circuit are each formed across the front and back surfaces of the communication board, and the outer circuit area and the inner circuit area are separated on each of the front and back surfaces of the communication board.

[0357] In the gaming machine as the above-described configuration example A, the outer circuit and inner circuit regions are separated not only on one side of the communication board but also on the other side. Therefore, it is possible to improve the insulation between the inner circuit and the outer circuit, and to improve the resistance to external noise (input noise from the external device side).

[0358] The gaming machine as the above-mentioned configuration example A has the following configuration. That is, in the gaming machine as configuration example A, the positions and shapes of the separation parts are substantially the same on the front and back sides. In this way, by making the position and shape of the separation section on the front and back surfaces of the communication board approximately identical, the separation distance in the board surface direction between the inner circuit on the front surface and the outer circuit on the back surface, and the separation distance in the board surface direction between the outer circuit on the front surface and the inner circuit on the back surface, are prevented from becoming shorter than the width of the separation section, thereby improving the insulation between the inner / outer circuits even between the front and back surfaces of the board, and further improving resistance to external noise.

[0359] Furthermore, the gaming machine as the above-mentioned configuration example A has the following configuration. That is, in the gaming machine of configuration example A, the separation pattern in the communication board surface direction between the outer circuit area and the inner circuit area is the same on the front and back sides. In other words, the shapes and areas of the outer circuit area and the inner circuit area are the same on the front and back of the communication board, and the shapes and areas of the separation parts are also the same on the front and back of the communication board. By making the shape and area of ​​the separation section the same on the front and back of the communication board, it is possible to improve the insulation between the inner circuit and the outer circuit, and to improve resistance to external noise.

[0360] The gaming machine as the above-mentioned configuration example A has the following configuration. That is, in the gaming machine of configuration example A, the grounds of the outer circuit area and the inner circuit area are solid grounds. This separates the outer and inner circuits into regions including the solid ground. Therefore, it is possible to improve the insulation between the inner circuit and the outer circuit, and to improve the resistance to external noise.

[0361] (2.2.2 Configuration example B) FIG. 27 is an explanatory diagram of an example of the arrangement of the photocouplers PC in this embodiment. As shown in the figure, photocouplers PC1 to PC5 are arranged on the isolation section Dv. Specifically, in this example, the separation section Dv is formed to have a straight section Sp parallel to the board edge of the dispensing control board 25, and the photocoupler PC is arranged on this straight section Sp. More specifically, the straight section Sp is formed with a straight section Sp1 parallel to the short side (short side) of the dispensing control board 25 and a straight section Sp2 parallel to the long side (longitudinal side), as shown in the figure, and photocouplers PC1 and PC2 are arranged on the straight section Sp1, and photocouplers PC3, PC4, and PC5 are arranged on the straight section Sp2.

[0362] At this time, each photocoupler PC is arranged so that its side extending in the direction separating the inner terminal and the outer terminal is perpendicular to the linear portion Sp located below.

[0363] According to the explanation with reference to FIG. 27, it can be said that the gaming machine GMA as this embodiment has a configuration as the following configuration example B. In other words, the gaming machine (same GMA) as configuration example B is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board is formed with an outer circuit (same Co), which is a circuit that is electrically connected to the external device, and an inner circuit (same Ci), which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (same Dv) that separates the outer circuit area from the inner circuit area, and the separation section has a straight section (same Sp) parallel to the edge of the communication board, and the insulating transmission means is arranged in the straight section.

[0364] By arranging the insulating transmission means in a straight section parallel to the edge of the substrate, rather than arranging the insulating transmission means in a separation section that is diagonal or curved relative to the edge of the substrate, it is possible to arrange the insulating transmission means in a direction parallel to the edge of the substrate. Therefore, the efficiency of arranging the insulating transmission means on the communication board can be improved.

[0365] Moreover, the gaming machine as the configuration example B has the following configuration. That is, in the gaming machine as the above-described configuration example B, a plurality of insulated transmission means are arranged in the linear portion. This allows an increase in the number of insulating transmission means arranged in a direction parallel to the edge of the board, thereby saving space required for arranging the insulating transmission means.

[0366] Furthermore, the gaming machine as configuration example B has the following configuration. That is, in the gaming machine as the above-described configuration example B, the separation section has a plurality of straight sections, and the two or more straight sections are each provided with an insulated transmission means. This increases the area where the insulating transmission means can be arranged in a direction parallel to the edge of the board, thereby improving the degree of freedom in arranging the insulating transmission means.

[0367] (2.2.3 Configuration example C) FIG. 28 is an explanatory diagram of the positions of various connectors CN on the dispensing control board 25 in this embodiment. As shown in the figure, in the dispensing control board 25 of this embodiment, connectors CN3, CN4, CN6, CN8, etc., which are connectors (internal connectors) for making electrical connections with other boards, and connector CN7, which is a connector (external connector) for making electrical connections with an external device such as a ball dispensing machine 80, are arranged side by side at one end of the dispensing control board 25 (see also Figure 20). Specifically, in this example, these internal connectors and external connectors are arranged side by side at one long side portion (end of one long side) of the dispensing control board 25.

[0368] According to the explanation with reference to FIG. 28, it can be said that the gaming machine GMA as this embodiment has a configuration as the following configuration example C. In other words, the gaming machine (same GMA) as configuration example C is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board is formed with an outer circuit (same Co), which is a circuit that is electrically connected to the external device, and an inner circuit (same Ci), which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (same Dv), which separates the outer circuit area from the inner circuit area, and the insulating transmission means is arranged on the separation section, and an external connector (connector CN7) for electrical connection with the external device is provided in the outer circuit area, and internal connectors (connectors CN3, CN4, CN6, CN8, etc.) for electrical connection with other boards are provided in the inner circuit area, and the external connector and internal connector are arranged side by side at one end of the communication board.

[0369] This improves insulation by separating the inner and outer circuits, while aligning the internal and external connectors at one end of the board to prevent the connector positions from varying, thereby enabling the area on the board to be expanded so that other components can overlap while avoiding the connector positions. Therefore, it is possible to improve the insulation from the external device side while increasing the freedom of component placement in the gaming machine.

[0370] Moreover, the gaming machine as the configuration example C has the following configuration. That is, in the gaming machine of the above-mentioned configuration example C, the surface shape of the communication board is made to be approximately rectangular, and the external connector and the internal connector are arranged side by side on the long side of the communication board. Here, various circuit boards in a gaming machine are fixed to the gaming machine main body at the four corners of the circuit board with screws or the like. Under this premise, if the external connector and the internal connector were arranged side by side on the short sides of the circuit board, the distance to the circuit board fixing point on the side opposite the side on which the connector is provided would be long when the connector cable is inserted or removed, resulting in increased stress on the circuit board. On the other hand, if the external connector and the internal connector were arranged side by side on the long sides of the circuit board as described above, the distance to the circuit board fixing point on the side opposite the side on which the connector is provided would be relatively short, thereby alleviating the stress on the circuit board when the connector cable is inserted or removed.

[0371] (2.2.4 Configuration example D) FIG. 29 is a schematic cross-sectional view for explaining an example of a formation pattern of separation portion Dv and ground Gn in dispensing control board 25 of this embodiment. The figure shows the inner terminal ti and outer terminal to of the photocoupler PC. As mentioned above, the "inner terminal" refers to the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci, and the "outer terminal" refers to the terminal that is electrically connected to the outer circuit Co. Here, if the photocoupler PC is for transmission, the inside terminal ti corresponds to the primary terminal of the photocoupler PC (the terminal connected to the photodiode) and the secondary terminal (the terminal connected to the phototransistor), and if the photocoupler PC is for reception, the inside terminal ti corresponds to the secondary terminal. Conversely, if the photocoupler PC is for transmission, the outside terminal to corresponds to the secondary terminal, and if the photocoupler PC is for reception, the outside terminal to corresponds to the primary terminal.

[0372] In the figure, the inner circuit through electrode Tti represents the through electrode Tt that is connected to the inner terminal ti of the photocoupler PC among the through electrodes Tt that penetrate the substrate portion 42a of the dispensing control board 25 in the thickness direction, and the outer circuit through electrode Tto represents the through electrode Tt that is connected to the outer terminal to of the photocoupler PC.

[0373] Here, as shown in the figure, the inner end of the inner-circuit Through-electrode Tti is referred to as the inner end IEi, and the inner end of the outer-circuit Through-electrode Tto is referred to as the inner end IEo. Note that the inside and outside of the terminals mentioned here are based on the center of the photocoupler PC, with the side closer to the center being referred to as the inner side and the side farther from the center being referred to as the outer side.

[0374] In the dispensing control board 25 of this example, the ground Gn of the inner circuit Ci (solid ground in this example) and the ground Gn of the outer circuit Co (also solid ground in this example) are each formed to extend into the area from the inner end IEi of the inner-circuit through electrode Tti to the inner end IEo of the outer-circuit through electrode Tto. Specifically, in this example, the ground Gn of the inner circuit Ci and the ground Gn of the outer circuit Co reach the bottom of the photocoupler PC.

[0375] Here, the region from the inner end IEi to the inner end IEo is referred to as an electrode inner end region Ait. Furthermore, the portion of the ground Gn of the inner circuit Ci that exists within the electrode inner end region Ait is referred to as the extension region Agi, and the portion of the ground Gn of the outer circuit Co that exists within the electrode inner end region Ait is referred to as the extension region Ago.

[0376] In the dispensing control board 25 of this example, the extension areas Agi, Ago and separation portion Dv are formed so as to satisfy the following conditions. That is, the condition is that the electrode inner inter-end region Ait is divided into approximately three equal parts by the extension regions Agi, Ago, and the separation portion Dv.

[0377] In Figure 29, only the placement area of ​​one photocoupler PC is shown as a representative, but in this example, in all placement areas of photocouplers PC1 to PC5, extension areas Agi, Ago, and separation portions Dv are formed so as to satisfy the above conditions.

[0378] Here, in the electrode inner end region Ait located below the photocoupler PC, it is generally considered desirable to increase the width of the separator Dv to improve insulation. However, it has been newly discovered that increasing the width of the separator Dv to prioritize insulation results in a tradeoff: the width of the solid ground of the inner circuit Ci and the outer circuit Co becomes narrower, which makes it easier for external noise to be mixed into the transmission signal of the photocoupler PC. In other words, if the width of the solid ground in the electrode inner end region Ait is narrow, the noise suppression effect on the transmission signal of the photocoupler PC is likely to be reduced.

[0379] Therefore, in this example, in the electrode inner inter-end region Ait, the solid ground of the outer circuit Co, the separation portion Dv, and the solid ground of the inner circuit Ci are arranged in approximately three equal parts. This makes it possible to prevent the insulating effect of the isolation portion Dv and the noise suppression effect of the solid ground from being overemphasized on one side, and to achieve a balance between these insulating and noise suppression effects.

[0380] Here, the results of a simulation by the inventors showed that when the error from perfect third division exceeds 13%, a change begins to appear in the balance between the insulating effect of the separator Dv and the noise suppression effect of the solid ground. From this result, the division into approximately thirds means that the error from perfect third division is within 13%, preferably within 12%, and more preferably within 10%.

[0381] Although the above description has been given of an example in which the above conditions are satisfied for all of the photocouplers PC, this is not essential, and a configuration in which the above conditions are not satisfied for some of the photocouplers PC may also be employed.

[0382] In this example, in the inside circuit Ci and the outside circuit Co, the signal line Ls from the terminal of the photocoupler PC is drawn out not to the separation part Dv side but to the side opposite to the separation part Dv. Specifically, as exemplified by the signal lines Ls from the through electrodes Tt in the region Api in Figures 25 and 26 and the signal lines Ls from the through electrodes Tt in the region Apo, in this example, all of the signal lines Ls from the terminals of the photocoupler PC are drawn out to the side opposite the separation section Dv, rather than to the separation section Dv side.

[0383] If the signal line Ls were to be drawn from the terminal of the photocoupler PC to the separation portion side, a solid ground would be required on the separation portion Dv side to cover the signal line Ls, which would force the width of the separation portion Dv to be narrowed accordingly.By drawing the signal line Ls from the terminal of the photocoupler PC to the side opposite the separation portion Dv as described above, the width of the separation portion Dv can be increased, thereby improving the noise suppression effect.

[0384] From the above description, it can be said that the gaming machine GMA according to this embodiment has a configuration as the following configuration example D. That is, the gaming machine (same GMA) as configuration example D is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board has an outer circuit (same Co), which is a circuit that is electrically connected to the external device, and an inner circuit (same Ci), which is a circuit that is electrically connected to other boards inside the gaming machine, and the outer circuit and inner circuit are each formed across the front and back surfaces of the communication board, and at least on the front surface, the ground (same Gn) of the outer circuit area and the inner circuit area is solid ground, and a separation section (same Dv) is formed that separates the outer circuit area and the inner circuit area, and the insulating transmission means is arranged on the separation section. The inner circuit has an inner circuit through-electrode (Tti) that is connected to either the primary or secondary terminal of the insulated transmission means and penetrates the communication board, and the outer circuit has an outer circuit through-electrode (Tto) that is connected to the other of the primary or secondary terminal of the insulated transmission means and penetrates the communication board, and the electrode inner end area (Ait) on the surface, which is the area from the inner end (IEo) of the outer circuit through-electrode to the inner end (IEi) of the inner circuit through-electrode, is divided into approximately three equal parts by the solid ground area (extension area Ago) of the outer circuit, the separation area, and the solid ground area (extension area Agi) of the inner circuit.

[0385] This makes it possible to prevent the insulating effect of the separator and the noise suppression effect of the solid ground from being overemphasized in one direction, thereby achieving a balance between these insulating and noise suppression effects.

[0386] Moreover, the gaming machine as the configuration example D has the following configuration. That is, in the gaming machine of configuration example D, in the inner circuit and the outer circuit, the signal line (same Ls) from the terminal of the insulated transmission means is drawn out to the side opposite to the separation part, not to the separation part side.

[0387] This allows the width of the separating portion to be increased, thereby improving the noise suppression effect.

[0388] (2.2.5 Configuration examples E, F) FIG. 30 is an explanatory diagram regarding the width of the separation portion Dv. As shown in the figure, the minimum width of the separation portion Dv is set to width D1. In this example, width D1 is set to the width of the straight line portions Sp1 and Sp2. Furthermore, the width of the signal line Ls formed on the dispensing control board 25 is defined as width D2.

[0389] In the dispensing control board 25 of this embodiment, the width D1 of the separation portion Dv is larger than the width D2 of the signal line Ls (D1>D2) (see also Figures 25 and 26 above). In this example, width D1 is greater than width D2 on both the front and back surfaces of dispensing control board 25. In this example, the width D1 of the separation section Dv is set to be greater than the maximum value of the width D2, i.e., the width of the widest signal line Ls. In this example, this is also true for both the front and back surfaces of the dispensing control board 25.

[0390] As described above, by making the width D1 of the separation portion Dv wider than the width D2 of the signal line Ls, it is possible to improve the insulation between the inner circuit Ci and the outer circuit Co, and to improve resistance to external noise.

[0391] Here, on the dispensing control board 25, an insulating portion IS is formed between the ground Gn, which is a solid ground, and the signal line Ls, to electrically insulate the ground Gn from the signal line Ls. If the width of this insulating portion IS is width D3, in the dispensing control board 25 of this embodiment, the width D1 of the separation portion Dv is wider than the width D3 of the insulating portion IS (D1>D3) (see also Figures 25 and 26 above). In this example, width D1 is greater than width D3 on both the front and back surfaces of dispensing control board 25. In addition, in this example, on both the front and back surfaces of the dispensing control board 25, the width D1 of the separation portion Dv is greater than the maximum value of the width D3, that is, the width of the widest insulating portion IS.

[0392] As described above, by making the width D1 of the separation portion Dv wider than the width D3 of the insulating portion IS, it is possible to improve the insulation between the inner circuit Ci and the outer circuit Co, and to improve resistance to external noise.

[0393] From the above description, it can be said that the gaming machine GMA according to this embodiment has the configuration of the following configuration example E. In other words, the gaming machine (same GMA) as configuration example E is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board is formed with an outer circuit (same Co), which is a circuit that is electrically connected to the external device, and an inner circuit (same Ci), which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (same Dv), which separates the outer circuit area from the inner circuit area, and an insulating transmission means is arranged on the separation section, and the minimum width of the separation section is thicker than the width of the signal line formed on the communication board.

[0394] This improves the insulation between the inner circuit and the outer circuit, and improves resistance to external noise.

[0395] Moreover, the gaming machine as configuration example E has the following configuration. In other words, in the gaming machine of configuration example E, in the inner circuit and outer circuit, the signal line from the terminal of the insulated transmission means is pulled out to the side opposite the separation section, rather than to the separation section side (see the explanation of configuration example D above). This allows the width of the separating portion to be increased, thereby improving the noise suppression effect.

[0396] Furthermore, from the above explanation, it can be said that the gaming machine GMA as an embodiment has a configuration as the following configuration example F. In other words, the gaming machine (GMA) as configuration example F is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board is formed with an outer circuit (Co) which is a circuit that is electrically connected to the external device, and an inner circuit (Ci) which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (Dv) that separates the outer circuit area from the inner circuit area, and an insulating transmission means is arranged on the separation section, the ground (Gn) of the outer circuit area and the inner circuit area is a solid ground, and the minimum width of the separation section is thicker than the width of the insulating section (IS) between the signal line (Ls) formed on the communication board and the solid ground. This improves the insulation between the inner circuit and the outer circuit, and improves resistance to external noise.

[0397] Moreover, the gaming machine as the configuration example F has the following configuration. In other words, in the gaming machine of configuration example F, in the inner circuit and outer circuit, the signal line from the terminal of the insulated transmission means is pulled out to the side opposite the separation section, rather than to the separation section side (see the explanation of configuration example D above). This allows the width of the separating portion to be increased, thereby improving the noise suppression effect.

[0398] [2.3 First Modification (Configuration Example G)] FIG. 32 is an explanatory diagram of a dispensing control board 25A as a first modified example. Dispensing control board 25A as the first modified example differs from dispensing control board 25 mainly in the formation pattern of separation section Dv. In this case, the separation portion Dv is formed to have a first portion P1 extending in a first direction, which is a direction approximately parallel to one side of the dispensing control board 25A, a second portion P2 extending from the end of the first portion P1 in a direction different from the first direction, and a third portion P3 extending in the first direction from the end of the second portion P2 opposite the connection portion with the first portion P1 so as to be opposite the first portion P1. Specifically, in this example, the first direction is a direction approximately parallel to the short side of the dispensing control board 25A ("direction V" in the figure), and therefore the first part P1 and the third part P3 both extend in the direction V. Also, in this example, the second part P2 is a part that extends in a direction approximately parallel to the long side of the dispensing control board 25A ("direction H" in the figure).

[0399] The separation portion Dv including the first portion P1, the second portion P2, and the third portion P3 has a generally U-shape as shown in the figure. In the example of Fig. 31, the outer circuit Co is surrounded by the generally U-shaped portion of the separation portion Dv.

[0400] As a result of the formation of the roughly U-shaped separation portion Dv as described above, part of the area of ​​the inner circuit Ci will extend around to the back side of the area of ​​the outer circuit Co on the substrate, as shown by "Ar" in the figure. Hereinafter, a region in which one of the inner circuit Ci and outer circuit Co wraps around to the back of the other, such as the region indicated by "Ar", will be referred to as a "wraparound region Ar".

[0401] Here, in this example, of the first part P1 and the third part P3, which are parts extending in the above-mentioned first direction (V direction in this example) in the separation part Dv, the part that is in contact with the wraparound area Ar as described above is referred to as the third part P3, and the part that is not in contact with the wraparound area Ar is referred to as the first part P1.

[0402] In this case, the photocouplers PC arranged on the separation unit Dv are five, namely, photocoupler PC11 to photocoupler PC15. Although not shown in the figure, each of these photocouplers PC11 to PC15 has information indicating the product model number printed in a predetermined orientation on its top surface. In particular, the same product is used for photocouplers PC14 and PC15, and the model number information is printed in the same orientation. For example, the model number information is printed so that the side on which the secondary terminals are formed is at the bottom of the text. Since photocouplers PC14 and PC15 are the same product, their exterior colors are the same.

[0403] The photocoupler 14 is used as a transmitting photocoupler PC that transmits signals from the inner circuit Ci to the outer circuit Co, and the photocoupler PC15 is used as a receiving photocoupler PC that transmits signals from the outer circuit Co to the inner circuit Ci. In this example, the transmitting photocoupler PC14 is used to transmit either the PRDY signal or the EXS signal, and the receiving photocoupler PC15 is used to transmit either the BRDY signal or the BRQ signal.

[0404] As shown in the figure, in this example, the photocouplers PC11 to PC13 are arranged on the first portion P1 of the isolation portion Dv. It should be noted that there are no particular limitations on which photocoupler PC of the photocouplers PC11 to PC13 is used for transmission and which is used for reception, or which signal each photocoupler PC transmits.

[0405] As shown in the figure, in this example, the transmitting photocoupler PC14 is arranged alongside the photocouplers PC11 to PC13 on the first part P1 of the separation section Dv, and the receiving photocoupler PC15 is arranged on the third part P3 of the separation section Dv.

[0406] Here, the transmitting photocoupler PC14 has its primary terminal connected to the inner circuit Ci and its secondary terminal connected to the outer circuit Co, while the receiving photocoupler PC15 has its primary terminal connected to the outer circuit Co and its secondary terminal connected to the inner circuit Ci. However, with the above configuration, when connecting the primary and secondary terminals of the transmitting photocoupler PC14 and the receiving photocoupler PC15 in this way, it is possible to align the mounting orientations of the photocouplers PC14 and PC15. By aligning the mounting orientation, the printing orientation of these photocouplers PC14 and PC15 can also be aligned, making it easier to identify the photocouplers PC14 and PC15 on the board. Also, when mounting components on the board, photocouplers PC14 and PC15 can be mounted in the same orientation, so there is no need to rotate the robot arm, improving the efficiency of the mounting work. Therefore, for the photocouplers PC14 and PC15 mounted on the dispensing control board 25A, it is possible to improve the ease of component confirmation while also improving the efficiency of the mounting work.

[0407] In the above example, the transmitting photocoupler PC14 is arranged in the first portion P1 and the receiving photocoupler PC15 is arranged in the third portion P3, but it is also possible to arrange the photocoupler PC14 in the third portion P3 and the photocoupler PC in the first portion P1. In this case, the mounting orientation of the photocouplers PC14 and PC15 is opposite to that in FIG. 31. As can be understood from this point of view, the photocoupler PC14 may be disposed in either the first portion P1 or the third portion P3, and the photocoupler PC15 may be disposed in the other of the first portion P1 or the third portion P3.

[0408] Here, in the payout control board 25A, an internal connector (here, symbolized as "CNi"), which is a connector CN electrically connected to other boards within the gaming machine GMA, is arranged in the area of ​​the inner circuit Ci, and an external connector (here, symbolized as "CNo"), which is a connector CN electrically connected to the ball dispensing machine 80 as an external device, is arranged in the area of ​​the outer circuit Co. In this example, the internal connector CNi and the external connector CNo have a roughly rectangular shape when viewed from above, and are arranged so that their long sides extend in a direction roughly parallel to the long sides of the dispensing control board 25A. Here, the long sides of the dispensing control board 25A can be rephrased as a direction roughly perpendicular to direction V1 (hereinafter referred to as the "third direction"), taking direction V as the extension direction of the first part P1 and the third part P3 in the separation section Dv as the reference. In this example, the third direction is a direction roughly parallel to the long sides of the dispensing control board 25A.

[0409] Of these internal connectors CNi and external connectors CNo, the connector that has the shortest total distance from the photocoupler PC14 and the photocoupler PC15 is defined as the nearby connector. In this example, the nearby connector corresponds to the external connector CNo.

[0410] In the dispensing control board 25A of this example, the photocouplers PC14 and PC15 are arranged spaced apart in the third direction, with the center line Lc of the nearby connector in the third direction as the boundary.

[0411] In the figure, the flow of the transmission signal transmitted from photocoupler PC14 via external connector CNo and the flow of the reception signal received from external connector CNo via photocoupler PC15 are schematically represented by dashed arrows. As can be seen by looking at these dashed arrows, by arranging photocouplers PC14 and PC15 at a distance in the third direction with the center line Lc of the adjacent connector as the boundary as described above, it is possible to form the wiring for the transmission signal and the reception signal as far apart as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise in the transmission and reception wiring.

[0412] In the above, an example was given in which the wraparound region Ar is formed as a region in which a part of the inner circuit Ci wraps around to the back side of the outer circuit Co. However, it is also possible to form the wraparound region Ar conversely as a region in which a part of the outer circuit Co wraps around to the back side of the inner circuit Ci, as shown in FIG. In this case, the area surrounded by the substantially U-shaped area formed by the first portion P1, the second portion P2, and the third portion P3 in the separation portion Dv is the area of ​​the inner circuit Ci.

[0413] Even with the configuration of Figure 32, the same effect can be obtained by placing photocoupler PC14 in either the first part P1 or the third part P3, and photocoupler PC15 in the other of the first part P1 or the third part P3, in the same manner as in Figure 31.

[0414] In this case, the nearby connector for photocouplers PC14 and PC15 is the internal connector CNi, and in this case, photocouplers PC14 and PC15 are arranged apart in the third direction (in this example, a direction approximately parallel to the long side of the dispensing control board 25A) of the internal connector CNi as the nearby connector, with the center line Lc' in the third direction as the boundary. This also makes it possible to form the wiring for the transmission signal and the wiring for the reception signal as far apart as possible, thereby reducing mutual interference due to radiation noise from the respective wirings for transmission and reception.

[0415] From the above description, it can be said that the gaming machine GMA as the first modified example has a configuration as the following configuration example G. In other words, the gaming machine (GMA) as configuration example G is equipped with a communication board on which an insulating transmission means (photocoupler PC) is implemented that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit that is electrically connected to the external device, and an inner circuit (Ci) which is a circuit that is electrically connected to other boards inside the gaming machine, as well as a separation section (Dv) that separates the outer circuit area from the inner circuit area, and is equipped with a transmitting insulating transmission means (photocoupler PC14) that transmits signals from the inner circuit to the outer circuit and a receiving insulating transmission means (photocoupler PC15) that transmits signals from the outer circuit to the inner circuit as insulating transmission means. The separation portion has a first portion (P1) extending in a first direction that is approximately parallel to one side of the communication board, a second portion (P2) extending from an end of the first portion in a direction different from the first direction, and a third portion (P3) extending in the first direction from an end of the second portion opposite the connection portion with the first portion so as to face the first portion, and the transmitting isolated transmission means is arranged in either the first portion or the third portion, and the receiving isolated transmission means is arranged in the other of the first portion or the third portion.

[0416] This makes it possible to align the mounting orientation of the transmitting isolation transmission means and the receiving isolation transmission means. By aligning the mounting orientation, the printing orientation of the transmitting and receiving isolated transmission means can also be aligned, making it easier to identify the transmitting and receiving isolated transmission means on the board. Also, when mounting components on the board, since the transmitting and receiving isolated transmission means and the receiving isolated transmission means can be mounted in the same orientation, there is no need to rotate the robot arm, which improves the efficiency of the mounting work. Therefore, it is possible to improve the ease of checking the components of the transmission and reception isolated transmission means mounted on the communication board, and also improve the efficiency of the mounting work.

[0417] Moreover, the gaming machine as the configuration example G has the following configuration. That is, in the gaming machine of configuration example G, the communication board is provided with an internal connector (CNi) that is arranged in the inner circuit area and makes electrical connection with other boards, and an external connector (CNo) that is arranged in the outer circuit area and makes electrical connection with an external device, and the internal connector and external connector have a substantially rectangular shape when viewed from above and are arranged so that their long sides extend in a third direction that is a direction substantially perpendicular to one side of the communication board, and when the connector of the internal connector and external connector that has the smallest total distance from the transmitting insulating transmission means and the receiving insulating transmission means is defined as the nearby connector, the transmitting insulating transmission means and the receiving insulating transmission means are arranged at a distance in the third direction, with the center line of the nearby connector in the third direction as the boundary. According to the above configuration, the transmitting isolated transmission means and the receiving isolated transmission means are arranged apart in the third direction on different sides of the center line of the nearby connector, so that it is possible to form the wiring for the transmitting signal and the wiring for the receiving signal on the communication board with as much separation as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise in the transmission and reception wiring.

[0418] [2.4 Second Modification (Configuration Example H)] Here, in the above, examples of signals transmitted and received between external devices via the photocoupler PC are relatively low-speed signals such as the BRDY signal, BRQ signal, PRDY signal, and EXS signal, but it is also possible to consider a configuration in which not only low-speed signals but also high-speed signals are transmitted and received between external devices via the photocoupler PC. The terms "low-speed signal" and "high-speed signal" used here are based on the average period of change in the signal value (signal level), and a "high-speed signal" refers to a signal whose average period is faster than that of a "low-speed signal." Furthermore, with regard to "low-speed signal" and "high-speed signal," a "high-speed signal" can be defined as a signal transmitted via serial communication in which the signal level changes in synchronization with a clock of a predetermined frequency (i.e., the rate is limited by the clock), while a "low-speed signal" can be defined as a signal that is not rate-limited by the clock.

[0419] FIG. 33 is a diagram for explaining an example of the configuration of a dispensing control board 25B as a second modified example that can be adopted when sending and receiving both low-speed signals and high-speed signals with an external device as described above. In the dispensing control board 25B shown in Figure 33, the formation pattern of the separation section Dv, the arrangement of the photocouplers PC11 to PC13, and the shapes and arrangement positions of the internal connector CNi and external connector CNo are the same as in Figure 31, so duplicate explanations will be avoided.

[0420] In this case, the photocouplers PC11 to PC13 are photocouplers PC that transmit low-speed signals. On the other hand, photocouplers PC16 and PC17 shown in the figure are implemented as photocouplers PC for transmitting high-speed signals. The photocoupler PC16 is a transmitting photocoupler PC that transmits high-speed signals from the inner circuit Ci to the outer circuit Co, and the photocoupler PC17 is a receiving photocoupler PC that transmits high-speed signals from the outer circuit Co to the inner circuit Ci.

[0421] In this example, the photocouplers PC11 to PC13 are arranged on the first portion P1 of the isolation portion Dv. The photocoupler PC16 is arranged on the first portion P1 alongside the photocouplers PC11 to PC13, and the photocoupler PC17 is arranged on the third portion P3. As a result, photocoupler PC16 and photocoupler PC17 are spaced apart in a direction approximately parallel to one side of the dispensing control board 25B (in this example, a direction approximately parallel to the long side of the dispensing control board 25B: hereinafter referred to as the ``side parallel direction'').

[0422] In the second variant dispensing control board 25B, photocouplers PC11 to PC13 that transmit low-speed signals are arranged at a first interval, while photocouplers PC16 and PC17 that transmit high-speed signals are arranged at a second interval that is wider than the first interval.

[0423] The transmission signals of the photocouplers PC16 and PC17 that transmit high-speed signals are faster than the transmission signals of the photocouplers PC11 to PC13 that transmit low-speed signals, and there is a risk of radiation noise being generated in the signal line Ls connected to the photocouplers PC16 and PC17. With the above configuration, it is possible to reduce the possibility that the signal line Ls connected to the photocoupler PC16 and the signal line Ls connected to the photocoupler PC17 will be mutually affected by radiation noise. Therefore, the accuracy of high-speed signal communication can be improved.

[0424] In the above, it is assumed that the photocouplers PC11 to PC13 are arranged at equal intervals as the first interval, but the photocouplers PC11 to PC13 may be arranged at non-equidistant intervals. In this case, the arrangement interval of the photocouplers PC16 and PC17 that transmit high-speed signals should be wider than the arrangement interval of the pair of photocouplers PC11 and PC12 or the arrangement interval of the pair of photocouplers PC12 and PC13, whichever is wider.

[0425] Here, as shown in Figure 33, in the dispensing control board 25B, the internal connector CNi and the external connector CNo have an approximately rectangular shape when viewed from above, and are arranged so that their long sides extend in the direction parallel to the above-mentioned sides of the dispensing control board 25B (the direction in which photocouplers PC16 and PC17 are separated). The photocouplers PC16 and PC17 are arranged apart in the direction parallel to the side, separated by the center line Lc in the direction parallel to the side of the nearby connectors for these photocouplers PC16 and PC17 (the connectors CN whose total distance from each photocoupler PC is the smallest).

[0426] This makes it possible to form the wiring for the transmission signals by the photocouplers PC16 and PC17 as far apart as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise in the wiring that transmits high-speed signals via the photocouplers PC16 and PC17.

[0427] 33 shows an example in which the wraparound region Ar is formed as a region in which a part of the inner circuit Ci wraps around to the back side of the outer circuit Co, but it is also possible to form the wraparound region Ar as a region in which a part of the outer circuit Co wraps around to the back side of the inner circuit Ci, as shown in Fig. 34. In this case, as in the case of Fig. 32, the region surrounded by the approximately U-shaped region formed by the first portion P1, the second portion P2, and the third portion P3 in the separation portion Dv is the region of the inner circuit Ci.

[0428] Even in the configuration of Figure 34, the same effect as in the first modified example can be obtained by placing the photocoupler PC16 in either the first part P1 or the third part P3, and the photocoupler PC17 in the other of the first part P1 or the third part P3, in the same manner as in the case of Figure 33.

[0429] In this case, the nearby connector for photocouplers PC16 and PC17 is the internal connector CNi, and in this case, photocouplers PC16 and PC17 are arranged at a distance in the side-parallel direction, with the center line Lc' in the side-parallel direction of the internal connector CNi as the nearby connector (in this example, the direction approximately parallel to the long side of the dispensing control board 25B) as the boundary. This also makes it possible to form the wiring for the transmission signals by the photocouplers PC16 and PC17 as far apart as possible, thereby reducing mutual interference caused by radiation noise on each wiring that transmits high-speed signals via these photocouplers PC16 and PC17.

[0430] From the above description, it can be said that the gaming machine GMA as the first modified example has a configuration as the following configuration example H. In other words, the gaming machine (same GMA) as configuration example H is equipped with a communication board (payout control board 25B) on which an insulating transmission means (photocoupler PC) is implemented to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (same Co), which is a circuit electrically connected to the external device, and an inner circuit (same Ci), which is a circuit electrically connected to other boards inside the gaming machine, and is also formed with a separation section (same Dv), which separates the outer circuit area from the inner circuit area, and is configured to be able to perform both low-speed signal communication and high-speed signal communication for signal communication with the external device. The insulating transmission means for performing low-speed signal communication includes a first low-speed insulating transmission means (any of photocouplers PC11 to PC13) and a second low-speed insulating transmission means (any of photocouplers PC11 to PC13), and the insulating transmission means for performing high-speed signal communication includes a first high-speed insulating transmission means (photocoupler PC16) and a second high-speed insulating transmission means (photocoupler PC17).On the separation section, the first low-speed insulating transmission means and the second low-speed insulating transmission means are arranged at a first interval, while the first high-speed insulating transmission means and the second high-speed insulating transmission means are arranged at a second interval that is wider than the first interval.

[0431] The transmission signal of the high-speed insulated transmission means is faster than the transmission signal of the low-speed insulated transmission means, and there is a risk of radiation noise being generated in the signal line connected to the high-speed insulated transmission means. With the above configuration, it is possible to reduce the possibility that the signal line connected to the first high-speed insulated transmission means and the signal line connected to the second high-speed insulated transmission means will be affected by radiation noise from each other. Therefore, the accuracy of high-speed signal communication can be improved.

[0432] Moreover, the gaming machine as the configuration example H has the following configuration. That is, in the gaming machine of configuration example H, the communication board is provided with an internal connector (Ci) that is arranged in the inner circuit area and makes electrical connection with other boards, and an external connector (Co) that is arranged in the outer circuit area and makes electrical connection with an external device, the first high-speed insulated transmission means and the second high-speed insulated transmission means are arranged at a distance in the side-parallel direction, which is a direction approximately parallel to one side of the communication board, the internal connector and the external connector have a substantially rectangular shape when viewed from above and are arranged so that their long sides extend in the side-parallel direction of the communication board, and when the connector of the internal connector and the external connector that has the smallest total distance from the first high-speed insulated transmission means and the second high-speed insulated transmission means is defined as the nearby connector, the first high-speed insulated transmission means and the second high-speed insulated transmission means are arranged at a distance in the side-parallel direction, with the center line of the nearby connector in the side-parallel direction as the boundary.

[0433] This makes it possible to form the wiring for the transmission signals by the first and second high-speed insulated transmission means as far apart as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise from the wiring that transmits high-speed signals.

[0434] Regarding the dispensing control board 25B as the second variant, the above example illustrates a configuration in which the separation section Dv has a first part P1, a second part P2, and a third part P3, as in the case of the first variant, and a photocoupler PC16 is placed in either the first part P1 or the third part P3, and a photocoupler PC17 is placed in the other of the first part P1 or the third part P3, but it is not essential to adopt this configuration in the second variant.

[0435] In addition, in the above example, the photocoupler PC16 is the transmitting photocoupler PC and the photocoupler PC17 is the receiving photocoupler PC, but a configuration in which both of these photocouplers PC16 and PC17 are the transmitting or receiving photocouplers PC is also conceivable.

[0436] [2.5 Other Modifications] Although the second embodiment has been described above, the present invention is not limited to the specific examples described so far, and various modified configurations can be adopted. For example, although a photocoupler is used as the isolated transmission means in the above example, the present invention can be suitably applied widely to cases where an isolated transmission means of a photoelectric conversion type is used as the isolated transmission means. The present invention can also be suitably applied to cases where an isolated transmission means of a type other than an photoelectric conversion type is used as the isolated transmission means, such as an electromagnetic isolated transmission means such as a transformer.

[0437] Furthermore, in the above example, the communication board of the present invention is configured as a payout control board having a payout control (loan control) function for game balls, but it is not essential for the communication board of the present invention to have the payout control function, and it is sufficient if it has at least the function of communicating with an external device.

[0438] In the above description, it is assumed that signal transmission via the isolated transmission means on the communication board is between an external device such as the ball dispenser 80, but signal transmission via the isolated transmission means can also be between the communication board and another board within the gaming machine. In this case, the communication board can be configured as a communication relay board that relays communication between a game control board that controls the progress of the game and a performance control board that controls the performance means, and the isolated transmission means provides electrical insulation on the signal communication path between the game control board and the performance control board. This configuration makes it possible to prevent noise generated on the performance control board from being mixed into the game control board. Furthermore, when the insulating transmission means of the communication board is configured to provide electrical insulation on the signal communication path between the control boards within the gaming machine as described above, it is possible to adopt the configurations described above as configuration examples A to H for the communication board.

[0439] 3. Third Embodiment [3.1 Structure of the gaming machine in the third embodiment] Next, a third embodiment will be described. The third embodiment relates to a method of presenting the results of a win or loss.

[0440] The overall structure of the gaming machine GMB as the third embodiment will be described with reference to Figures 35 and 36. Figure 35 is a perspective view showing the appearance of the gaming machine GMB, and Figure 36 is a perspective view of the gaming machine GMB with the front frame G7 opened. In the following description, the right direction as seen from a player facing the gaming machine GMB is referred to as the right direction of the gaming machine GMB, and the left direction as seen from a player facing the gaming machine GMB is referred to as the left direction of the gaming machine GMB. The vertically upward direction is referred to as the upward direction of the gaming machine GMB, and the vertically downward direction is referred to as the downward direction of the gaming machine GMB. The direction from the gaming machine GMB toward the player facing the gaming machine GMB is referred to as the forward direction of the gaming machine GMB, and the direction from the player facing the gaming machine GMB is referred to as the rearward direction of the gaming machine GMB. The left-right direction of the gaming machine GMB is the same as the width direction of the gaming machine GMB.

[0441] The GMB gaming machine is a so-called smart pachinko machine that circulates game balls enclosed inside and is used for playing games.

[0442] As shown in Figures 35 and 36, the gaming machine GMB comprises a wooden outer frame G3, an inner frame G5 attached to the outer frame G3 by a hinge mechanism G4 so as to be openable and closable, and a front frame G7 attached to the inner frame G5 by the hinge mechanism G4 so as to be openable and closable. The hinge mechanisms G4 are provided at the upper and lower left ends of the gaming machine GMB. The inner frame G5 is formed in a picture frame shape and holds a gaming board G9 inside.

[0443] The front frame G7 holds a transparent glass G11 in the center, and a side unit G13 is provided so as to surround all or part of the periphery of the transparent glass G11. The side unit G13 has a decorative shape that matches the theme of the gaming machine GMB, and may be equipped with LEDs, movable accessories, and other presentation means inside to create a presentation effect that conveys the atmosphere of the game to the player. The side unit G13 is replaceably attached to the front frame G7.

[0444] A key cylinder G15 for unlocking the door is provided at the right end of the front frame G7. By inserting a key into this key cylinder G15 and operating it to one side, the locked state of the front frame G7 relative to the inner frame G5 is released, allowing the front frame G7 to be opened to the front. By operating it to the other side, the locked state of the inner frame G5 relative to the outer frame G3 is released, allowing the inner frame G5 to be opened to the front.

[0445] A front operation panel G17 is disposed below the front frame G7. A handle device G19 for launching game balls from the launching device G31 is provided on the right end side of the front operation panel G17.

[0446] A game ball count indicator G21 and a counting switch G23 are provided on the left side of the front operation panel G17. The game ball count indicator G21 is composed of a 6-digit, 7-segment LED and displays the number of game balls managed by the gaming machine GMB (the number of game balls owned by the player: hereinafter referred to as the "managed game ball count"). The counting switch G23 accepts an operation input from the player to transfer the managed game ball count to a valuable medium (card) in the game ball etc. lending device.

[0447] The front operation panel G17 is also provided with operation buttons G25 that can be operated by the player. The operation buttons G25 include a performance button G25a, a direction key G25b, a brightness change button G25c, and a volume change button G25d. The effect button G25a is operable (input acceptable) during a predetermined input acceptance period, and can bring about changes in the effect by performing a predetermined operation (pressing, tapping repeatedly, pressing and holding, etc.). The effect button G25a also serves as an operator for instructing the confirmation of an item selected by the directional key G25b. A vibration device G77 (see FIG. 41) is attached to the effect button G25a, and the vibration device G77 can vibrate the effect button G25a at a predetermined timing, thereby further enhancing the effect of the effect. The direction keys G25b are controls that allow users such as players and hall staff to select various items, give direction instructions, etc. The direction keys G25b include an up key located on the top for pointing up, a left key located on the left for pointing left, a right key located on the right for pointing right, and a down key located on the bottom for pointing down. The brightness change button G25c is an operator for adjusting the brightness of the performance LEDG27 for the performance, and is configured to include a plus button for increasing the brightness of the performance LEDG27 and a minus button for decreasing the brightness of the performance LEDG27. The volume change button G25d is an operator for adjusting the volume of the sound output from the speaker G29, and includes a plus button for increasing the volume and a minus button for decreasing the volume.

[0448] A plurality of LEDs G27 for effect are provided in appropriate positions on the front frame G7, and are controlled to various lighting modes and light colors (collectively referred to as light-emitting states). A large number of LEDs G27 for effect are provided around the gaming machine GMB, for example, on the periphery of the front frame G7, in the side unit G13, and in the gaming board G9, and their lighting is controlled by the effect control board G120.

[0449] Additionally, a plurality of speakers G29 that output sound are provided around the gaming machine GMB, for example, on the periphery of the front frame G7. The multiple speakers G29 enable so-called stereophonic sound reproduction or multi-channel sound reproduction for sounds related to the performance.

[0450] The inner frame G5 is provided with a circulation mechanism G30 including a launching device G31 and a lifting device G33 below the game board G9. The circulation mechanism G30 circulates game balls within the gaming machine GMB. The launching device G31 launches game balls toward the game area G37 with a strength corresponding to the amount of operation (rotation angle) of the handle G19a of the handle device G19 by the player. The lifting device G33 transports game balls discharged from the game area G37 (game board G9) to the launching device G31. The lifting device G33 incorporates a polishing device that polishes the game balls while lifting them.

[0451] Next, the configuration of the game board G9 will be described with reference to Figures 37 and 38. Figure 37 is a front view of the game board G9. Figure 38 is a cross-sectional perspective view of the AA cross section in Figure 37.

[0452] As shown in Figures 37 and 38, the game board G9 is provided with an outer rail G35 and an inner rail G36 for guiding the launched game ball. The outer rail G35 extends in an arc shape from the lower left end, passing through the upper center end in the left-right direction and extending to the upper right. The roughly circular area surrounded by the outer rail G35 forms the game area G37, and the area outside the roughly circular area forms the non-game area. The game area G37 is a space formed between the game board G9 and the transparent glass G11, and is an area where game balls can flow down. The inner rail G36 extends in an arc shape from the slightly lower left end to the upper left end along the outer rail G35. The area sandwiched between the outer rail G35 and the inner rail G36 is formed as a game ball guide path G35a. The game ball guide path G35a is a path along which game balls launched from the launching device G31 pass, and guides the game balls launched from the launching device G31 to the game area G37.

[0453] The game area G37 is divided into a left game area G37a and a right game area G37b by a center ornament G39 provided in the center. The center ornament G39 has a center vertex G39a that protrudes most upward to divide the left game area G37a and the right game area G37b. The center vertex G39a does not have to be in the center in the left-right direction, but may be formed at a position shifted to the right or left from the center. A game ball launched by the launching device G31 at a predetermined launch strength that does not exceed the center apex G39a flows down the left game area G37a, and a game ball launched at a predetermined launch strength or more that exceeds the center apex G39a flows down the right game area G37b.

[0454] The game area G37 is provided with a collision stopper G38 that is continuous with the upper right end of the outer rail G35. The collision stopper G38 is arranged at a position along the outer rail G35, so that game balls launched by the launching device G31 with a predetermined launch strength or higher collide with the collision stopper G38 and are guided to the right game area G37b.

[0455] In addition, a backflow prevention member G40 is provided at the upper left end of the inner rail G36. The backflow prevention member G40 is biased counterclockwise by a spring (not shown) so as to block the game ball guide path G35a, and can rotate clockwise around the upper left end of the inner rail G36 as a fulcrum by a game ball entering the game area G37 from the game ball guide path G35a. This allows the backflow prevention member G40 to prevent a game ball that has entered the game area G37 from flowing back into the game ball guide path G35a.

[0456] A special symbol 1 start port G41 is provided at the center lower side of the game board G9. The special symbol 1 start port G41 is a winning port related to the start condition of the variable display operation of the first special symbol (hereinafter referred to as special symbol 1, and may be abbreviated as special symbol 1) on the main display G63, and is configured as a fixed start port.

[0457] A special symbol 2 start port G43 is provided on the right side of the game board G9. The special symbol 2 start port G43 is a winning port related to the start conditions for the variable display operation of the second special symbol (hereinafter referred to as special symbol 2, and may also be abbreviated as special symbol 2) on the main display G63, and is configured as a variable start port whose opening and closing is controlled by the normal electric device G45.

[0458] The normal electric device G45 can be switched between an open state that allows a game ball to enter the special pattern 2 starting hole G43 and a closed state that makes it difficult or impossible for a game ball to enter the special pattern 2 starting hole G43 by operating the movable piece G45a.

[0459] Above the special symbol 2 start port G43 in the right gaming area G37b, there is provided a normal symbol start port G47 through which the gaming ball can pass. This normal symbol start port G47 is a gate related to the variable display operation of the normal symbol on the main display G63.

[0460] A large prize opening G49 is provided below the special symbol 2 starting opening G43 in the right game area G37b. The large prize opening G49 is controlled to open and close by a special electric device G51. By operating the movable piece G51a, the special electric device G51 can be switched between an open state that allows game balls to enter the large prize opening G49 and a closed state that makes it difficult or impossible for game balls to enter the large prize opening G49.

[0461] In addition, a plurality of winning holes G53 are provided on the left and right lower sides of the game area G37. In addition, an outlet G55 is provided at the lower center end of the game area G37, and game balls that do not enter any of the winning holes are discharged from the game area G37 through the outlet G55.

[0462] In addition, only game balls that have flowed down the left game area G37a can enter the special pattern 1 starting hole G41, but game balls that have flowed down the right game area G37b may also be able to enter. In addition, only game balls that have flowed down the right game area G37b can enter the special pattern 2 starting port G43, the normal pattern starting port G47, and the big prize port G49, but game balls that have flowed down the left game area G37a may also be able to enter or pass through.

[0463] In the gaming machine GMB, when a game ball enters one of the various winning holes provided in the game area G37, the number of prize balls set for the winning hole into which the game ball entered (for example, 3 balls for the special pattern 1 starting hole G41, 1 ball for the special pattern 2 starting hole G43, 15 balls for the large winning hole G49, and 5 balls for the winning hole G53) is paid out.

[0464] An LCD unit (liquid crystal display device) G57 and an illumination panel G59 are provided in the area surrounded by the center ornament G39 in the center of the game board G9. The LCD unit G57 displays, for example, three decorative symbols G201a to G201c (see FIG. 42) in a variable or static manner, and displays various images (still images and moving images) for various effects, according to the control of the effect control board G120 described later. There are provided a plurality of types of decorative symbols G201 including different numbers and symbols, and the result of the big win lottery, which will be described later, is notified to the player by the combination of the three decorative symbols G201a to G201c that are stopped and displayed.

[0465] The illumination panel G59 is made of a plate-shaped transparent synthetic resin material and is positioned closer to the player (front side) than the LCD unit G57, facing the LCD unit G57. The illumination panel G59 has predetermined patterns such as letters, figures, symbols, and designs formed by uneven processing on the front or back surface. When light is not incident from the side of the illumination panel G59, the patterns are invisible or difficult to see, but when light is incident from the side, the patterns emit diffused light, making them visible to the player.

[0466] A space is formed between the LCD unit G57 and the illumination panel G59, and one or more movable body accessories G61 are arranged in this space. Figure 37 illustrates one of the multiple movable body accessories G61. The movable device G61 is positioned in front of the LCD unit G57, and is normally retracted to a position where it cannot be seen by the player, as shown by the dashed line in Figure 37. As shown by the solid line in Figure 37, the movable device G61 is driven by the movable motor G61a (see Figure 41) while the decorative pattern G201 is being displayed in a changing manner (while special patterns 1 and 2 are being displayed in a changing manner), and moves to the front of the LCD unit G57, giving the player a sense of anticipation of a big hit.

[0467] A main display G63 consisting of a dot display is provided in the non-play area at the lower left of the gaming board G9. Also, a fourth symbol display G65 consisting of a dot display is provided at the lower right of the LCD unit G57 on the gaming board G9.

[0468] 39 is a diagram illustrating the main display G63 and the fourth symbol display G65. The main display G63 is controlled by the main control board G100, and displays (notifies) information about the progress of the game by lighting, blinking, and extinguishing the LED. Note that, hereinafter, lighting, blinking, and extinguishing of the LED will be collectively referred to as "lighting display." 39(a), the main display G63 is provided with a special symbol 1 display G63a that performs a variable display operation (lighting display) of special symbol 1, a special symbol 2 display G63b that performs a variable display operation of special symbol 2, and a normal symbol display G63c that performs a variable display operation of normal symbols. The main display G63 is also provided with a special symbol 1 reserved number display G63d that displays the reserved number of special symbol 1, a special symbol 2 reserved number display G63e that displays the reserved number of special symbol 2, a normal symbol reserved number display G63f that displays the reserved number of normal symbols, a round display G63g that displays the specified number of rounds (maximum number of rounds) related to a jackpot, a game status display G63h that displays the game status (time-shortened state, high probability state), and a right-hit display G63i that prompts the player to hit the right. Note that right-hitting refers to the player operating the handle G19a to launch the game ball toward the right game area G37b. The right-hit indicator G63i is an indicator for informing the player that launching the game ball toward the right game area G37b is more advantageous than launching the game ball toward the left game area G37a.

[0469] The fourth symbol display G65 is controlled by the performance control board G120, and notifies information about the progress of the game by lighting up the LED. As shown in Figure 39 (b), the fourth symbol display G65 is provided with a special symbol 1 display G65a that performs a variable display operation of the special symbol 1, and a special symbol 2 display G65b that performs a variable display operation of the special symbol 2. In addition, the fourth symbol display G65 is provided with a special symbol 1 reserved number display G65c that displays the reserved number of special symbol 1, a special symbol 2 reserved number display G65d that displays the reserved number of special symbol 2, and a right hit display G65e that prompts the player to hit right.

[0470] [3.2 Control configuration of gaming machine in third embodiment] 40 and 41 are block diagrams showing the control configuration of the gaming machine GMB. The control configuration of the gaming machine GMB will be described with reference to the block diagrams of Fig. 40 and Fig. 41. The gaming machine GMB of this embodiment is mainly composed of a main control board G100 that is responsible for overall control related to the progress of the game (game operation control), a frame control board G110 that is responsible for overall control related to the management of the number of gaming balls (prize balls) and control related to the management of gaming balls (launching, circulation), a presentation control board G120 that receives presentation control commands from the main control board G100 and is responsible for overall control of the execution of presentations by the presentation means, a power supply board G130 that generates and supplies the power supply voltage required for the gaming machine GMB from an external power source, a gaming ball etc. lending device connection terminal board G140 that is connected to the gaming ball etc. lending device, a decorative relay board G150 on which components related to the presentation means are mounted or connected, a front frame relay board G160, an upper decorative board G170, and a decorative board G180.

[0471] (3.2.1 Main control board) The main control board G100 is equipped with a main control unit G101 and a system reset circuit G103. The main control unit G101 is a microprocessor equipped with a CPU (Central Processing Unit), ROM (Read Only Memory), and RWM (Read / Write Memory). The ROM stores control programs for controlling game operations as well as various data required for game operation control. The RWM functions as a work area and buffer memory. The CPU controls game operations by executing control programs stored in the ROM.

[0472] The system reset circuit G103 detects when the power is turned on, when the power is turned off, or when there is a power abnormality, and outputs a system reset signal to reset the main control unit G101. Although not shown in the figure, the main control unit G101 also has a CTC (Counter Timer Circuit) for realizing periodic interrupts, a function for generating pulse output at a fixed period (bit rate generator), and a time measurement function, an interrupt controller circuit that performs interrupt enable / disable functions such as timer interrupts that issue interrupt signals, a watchdog timer (WDT) circuit that monitors for abnormal operation of the control program, an IAT (Inhibit Running Outside Designated Area) circuit that monitors whether the program is being executed correctly within a pre-set address range, and a counter circuit (random number generation circuit) for generating random numbers within a certain range (hard random number values) in a hardware manner.

[0473] The counter circuit is comprised of a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timing, and functions as a 16-bit counter as a whole. The main control unit G101 sends instructions to the sampling circuit depending on the processing status, thereby obtaining the number indicated by the random number generation circuit as a random number (0 to 65535) for determining a jackpot, and using the random number for determining a jackpot for use in the jackpot lottery. The random number for determining a jackpot is obtained by adding a software random number generated by appropriate software processing and a hard random number to prevent cheating, such as aiming for a jackpot.

[0474] The main control board G100 is connected to a special symbol 1 start port switch G41a that detects the entry of a game ball into the special symbol 1 start port G41, a special symbol 2 start port switch G43a that detects the entry of a game ball into the special symbol 2 start port G43, a normal symbol start port switch G47a that detects the passage of a game ball into the normal symbol start port G47, a prize port switch G53a that detects the entry of a game ball into the prize port G53, and a special prize port switch G49a that detects the entry of a game ball into the special prize port G49. The detection signals output from these switches are input to the main control unit G101. Therefore, the main control unit G101 can determine which prize port the game ball has entered (passed through) based on the detection signals from each switch.

[0475] In addition, the main control board G100 is connected to a large prize opening solenoid G51b that operates a special electric role G51 (movable piece G51a) that opens and closes the large prize opening G49, and a normal electric role solenoid G45b that operates a normal electric role G45 (movable piece G45a) that opens and closes the special symbol 2 starting opening G43. The main control unit G101 outputs control signals to control these solenoids.

[0476] The game board G9 is also provided with a magnetic sensor G67 for detecting magnetism, a radio wave sensor G69 for detecting radio waves, and a vibration sensor G71 for detecting vibrations, and these sensors are connected to the main control board G100. Signals from these sensors are input to the main control unit G101.

[0477] Furthermore, a main display G63 is connected to the main control board G100. The main control unit G101 outputs a control signal for lighting up the main display G63.

[0478] The main control board G100 is connected to the frame control board G110 so that they can communicate with each other. The main control board G100 (main control unit G101) mainly sends control commands containing information about prize balls and launch control signals indicating whether or not game balls can be launched to the frame control board G110. The main control board G100 also receives from the frame control board G110 a door open signal indicating the opening of the front frame G7, an RWM clear signal for clearing the RWM, a power supply abnormality signal indicating a power supply abnormality, and a frame communication confirmation signal for confirming communication. Furthermore, the main control board G100 receives drive power (DC35VA, DC12VA, DC5VA, backup power supply) from the frame control board G110.

[0479] The main control board G100 transmits various performance control commands, including information about the special symbol variation display game and information about errors, to the performance control board G120. However, in order to prevent fraud such as cheating, the main control board G100 only transmits signals to the performance control board G120, and is configured for one-way communication in which it cannot receive signals from the performance control board G120.

[0480] (3.2.2 Frame control board) The frame control board G110 is equipped with a frame control unit G111, an RWM clear switch G112a, a game ball count clear switch G112b, a ball removal switch G112c, an error release switch G112d, a performance indicator G113, a system reset circuit G114, a power supply abnormality signal generation circuit G115, a launch control circuit G116 and a backup power supply generation circuit G117.

[0481] The frame control unit G111 is a microprocessor equipped with a CPU, ROM, and RWM. The ROM stores control programs for managing the number of game balls and controlling the launching device G31 and lifting device G33, as well as various data required for these controls. The RWM functions as a work area and buffer memory. The CPU executes the control programs stored in the ROM to manage the number of game balls and control the launching device G31 and lifting device G33.

[0482] The RWM clear switch G112a, the game ball count clear switch G112b, the ball removal switch G112c, and the error reset switch G112d are push button switches. If the RWM clear switch G112a was pressed when the power was turned on, the frame control unit G111 clears the RWM and sends an RWM clear signal to the main control board G100. Upon receiving the RWM clear signal, the main control unit G101 clears a predetermined area of ​​the RWM.

[0483] If the game ball count clear switch G112b is pressed when the power is turned on, the frame control unit G111 clears the game ball count it manages. When the game ball count is cleared, 0 is displayed on the game ball count display G21.

[0484] When the ball removal switch G112c is pressed when the power is turned on, the frame control unit G111 performs a ball removal process to discharge the game balls enclosed in the gaming machine GMB to the outside. Specifically, the frame control unit G111 drives the lifting motor G33a on the condition that the lifting entrance switch G33f (described later) detects a game ball.

[0485] If the error reset switch G112d is pressed when a specific error occurs, the frame control unit G111 resets the specific error that has occurred.

[0486] The performance indicator G113 is configured, for example, with a 6-digit, 8-segment (7-segment + 1 dot) display. The performance indicator G113 is controlled by the frame control unit G111, and displays game performance information calculated based on game results over a predetermined period (for example, every 6,000 games). Game performance information includes the consecutive feature ratio, feature ratio, and base. The consecutive feature ratio is the proportion of the number of prize balls that result from winning into the large prize slot G49 out of the total number of prize balls. The feature ratio is the proportion of the number of prize balls that result from winning into the special pattern 2 start slot G43 and the number of prize balls that result from winning into the large prize slot G49 out of the total number of prize balls. The base is the proportion of the total number of prize balls that result from winning into the game balls that have been shot out. The performance indicator G113 can switch between displaying game performance information for each predetermined period (each section).

[0487] The system reset circuit G114 detects when the power is turned on, when the power is turned off, or when there is a power supply abnormality, and outputs a system reset signal to reset the frame control unit G111.

[0488] The power supply abnormality signal generating circuit G115 monitors voltage drops in the drive power (5V DC voltage (DC5VA), 12V DC voltage (DC12VA)) supplied from the power supply board G130, and outputs a power supply abnormality signal to the main control unit G101 when the voltage drops below a predetermined threshold. The power supply abnormality signal generating circuit G115 may also monitor voltage drops in 24V AC voltage (AC24V).

[0489] The launch control circuit G116 controls the launch of game balls from the launch device G31 by controlling the drive of the launch device G31 (ball feed solenoid G31a, launch solenoid G31b).

[0490] The backup power generation circuit G117 generates a backup power (VBB) that is supplied to the RWMs of the main control unit G101 and the frame control unit G111 when the power is cut off. The RWMs of the main control unit G101 and the frame control unit G111 that receive the backup power (VBB) can retain (back up) stored data for a certain period of time even when a power cut occurs.

[0491] A door open sensor G73 provided on the inner frame G5 is connected to the frame control board G110. When the door open sensor G73 detects at least one of the fact that the front frame G7 is open relative to the inner frame G5 and the fact that the inner frame G5 is open relative to the outer frame G3, it outputs a door open signal to the main control board G100 via the frame control board G110.

[0492] The circulation mechanism G30 provided in the inner frame G5 is provided with a lifting motor G33a, an out ball switch G33b, a foul ball switch G33c, an excess position detection switch G33d, an insufficient position detection switch G33e, a lifting inlet switch G33f, a lifting outlet switch G33g, and a lifting position detection switch G33h, which are connected to the frame control board G110.

[0493] The circulation mechanism G30 is formed with a pre-lifting path along which game balls discharged from the game area G37 are guided, a lifting path along which game balls that have passed through the pre-lifting path are lifted, and a post-lifting path along which game balls lifted up on the lifting path are guided to the launching device G31. In the circulation mechanism G30, game balls discharged from the game area G37 are guided to the lowest end of the lifting path through a pre-lifting path. The game balls guided to the lowest end of the lifting path are lifted upward within the lifting path by the lifting device G33. Then, the game balls that reach the highest end of the lifting path are sent to a post-lifting path and then guided to the launching device G31 through the post-lifting path.

[0494] The lifting motor G33a is controlled by the frame control unit G111 and rotates a lifting section, such as a spiral member, arranged in the lifting path. The rotated lifting section guides game balls that have reached the downstream end of the pre-lifting path into the lifting path and lifts game balls that have accumulated in the lifting path upward. The rotating lifting section also sends game balls from the top end of the lifting path to the post-lifting path.

[0495] The out ball switch G33b, foul ball switch G33c, excessive position detection switch G33d, insufficient position detection switch G33e, lifting entrance switch G33f, and lifting exit switch G33g are switches that detect game balls, and when a game ball is detected, they output a detection signal to the frame control board G110 (frame control unit G111).

[0496] The out ball switch G33b is arranged on the upstream side of the pre-lift path, and detects a game ball (out ball) that is discharged from the game area G37 and guided to the pre-lift path. The foul ball switch G33c is arranged on a foul ball merging path connected between the positions where the out ball switch G33b and the excess position detection switch G33d are respectively arranged on the pre-lifting path, and detects game balls that are launched from the launching device G31 and do not reach the game area G37 but are returned to the pre-lifting path through the foul ball merging path.

[0497] The over-position detection switch G33d and the under-position detection switch G33e are arranged downstream of the out ball switch G33b on the pre-lift path at a predetermined distance, and detect game balls remaining in the pre-lift path. The over-position detection switch G33d is arranged upstream of the under-position detection switch G33e on the pre-lift path. Then, when the power is turned on, if the excess position detection switch G33d does not detect any game balls and the insufficient position detection switch G33e detects game balls, that is, if there are game balls at the position where the insufficient position detection switch G33e is located and there are no game balls at the position where the excess position detection switch G33d is located, the frame control unit G111 determines that the normal number of game balls are enclosed in the gaming machine GMB. On the other hand, if the under-detection switch G33e did not detect any game balls when the power was turned on, the frame control unit G111 determines that there are not enough game balls in the gaming machine GMB. Conversely, if the over-detection switch G33d detected any game balls when the power was turned on, the frame control unit G111 determines that there are too many game balls in the gaming machine GMB. In other words, in these cases, the frame control unit G111 determines that the correct number of game balls are not included in the gaming machine GMB. In this case, the frame control unit G111 sends a signal indicating that the correct number of game balls are not included to the main control unit G101, and the main control unit G101 sends a presentation control command indicating that the correct number of game balls are not included to the presentation control unit G121. The presentation control unit G121 then notifies the hall staff, etc., by displaying the information on the LCD unit G57, etc.

[0498] The li...

Claims

[Claim 1] A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, A gaming machine characterized in that the first information and / or the second information are configured to be stored in an address area of ​​an internal RAM or an external RAM starting from a starting address where a predetermined number of bits or less are zero.

Images