Game machine

Abstract

To aim for technical improvement in a game machine.SOLUTION: A game machine according to the present invention is provided with CPU means for generating first information specifying an image performance by a display device and second information specifying an audio performance, and transfer means for transferring the first information and the second information to a first circuit and a second circuit via a predetermined transmission path. The transmission path for the first information and / or the transmission path for the second information is configured so that one transmission circuit can be selected from a plurality of options.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a technology relating to gaming machines such as pinball gaming machines. [Background technology]

[0002] A pinball game machine such as a pachinko machine is configured with a pattern start opening on the game board, a pattern display section that displays a series of pattern change patterns based on multiple displayed patterns, and a large prize opening with an opening / closing plate that opens and closes. When a detection switch provided in the pattern start opening detects the passage of a game ball, the machine enters a winning state, and after the game ball is paid out as a prize ball, the displayed pattern in the pattern display section changes for a predetermined period of time. After that, when the pattern stops in a predetermined manner such as 7·7·7, the machine enters a large win state, and the large prize opening is repeatedly opened, creating a game state that is advantageous to the player.

[0003] Whether or not such a game state occurs is determined by a jackpot lottery that is executed on the condition that a game ball enters the symbol start hole, and the above-mentioned symbol change operation is based on the result of this lottery. For example, if the lottery result is a winning state, a presentation operation called a reach action is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, even if the winning state is not won, a similar reach action may be executed, and in this case, the player will pay close attention to the progress of the presentation operation while strongly hoping for a jackpot state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol change operation, the player is guaranteed a jackpot state.

[0004] The following patent documents can be cited as examples of related prior art. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2021-040883 A [Patent Document 2] JP 2020-065707 A [Patent Document 3] JP 2020-022673 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a technical improvement to gaming machines. [Means for solving the problem]

[0007] The gaming machine of the present invention is provided with a CPU means for generating first information specifying an image presentation by a display device and second information specifying an audio presentation, and a transfer means for transferring the first information and the second information to a first circuit and a second circuit via a predetermined transmission path, and is characterized in that the transmission path for the first information and / or the transmission path for the second information are configured so that one transmission circuit can be selected from a plurality of options. Effect of the Invention

[0008] According to the present invention, it is possible to achieve technical improvements in gaming machines. [Brief description of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a gaming machine according to a first embodiment; [Diagram 2] 2 is a front view showing a gaming area of ​​the gaming machine of FIG. 1. [Diagram 3] 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] This illustrates the internal configurations of the performance interface board, the performance control board, and the liquid crystal interface board. [Diagram 5] FIG. 2 is a circuit block diagram illustrating a composite chip including associated circuit elements. [Figure 6] 1 is a diagram for explaining an index space and a virtual drawing space. [Figure 7]1 is a diagram illustrating a display circuit. [Figure 8] 4 is a diagram illustrating an internal configuration of a data transfer circuit. [Figure 9] 11 is a diagram for explaining a transfer operation of a display list and a voice command list. [Figure 10] 11 is a diagram for explaining a filter process based on a display list. [Figure 11] 1 is a diagram for explaining the procedure for playing IPB stream video. [Figure 12] 4 is a diagram illustrating an internal configuration and a control procedure of an audio processing unit. [Figure 13] 1 is a diagram for explaining a drawing pipeline process of a drawing circuit. [Figure 14] FIG. 2 is a process diagram illustrating various rendering modes that utilize all or part of the rendering pipeline steps. [Figure 15] 13 is a flowchart explaining the control operation of a performance control CPU that does not include a preload operation. [Figure 16] 16 is a flowchart illustrating a part of FIG. 15. [Figure 17] 13 is a flowchart explaining the control operation of the performance control CPU, including the preload operation. [Figure 18] A block diagram for explaining the schematic circuit configuration of a gaming machine as a second embodiment. [Figure 19] An explanatory diagram of an example of signals communicated between the payout control board and the ball dispensing machine in the second embodiment. [Figure 20] A diagram showing an example of the arrangement of various electronic components on a dispensing control board in the second embodiment. [Figure 21] FIG. 11 is a circuit diagram showing a connection between an external connector and each insulating transmission means in a second embodiment. [Figure 22] 13 is a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. FIG. [Figure 23]FIG. 11 is also a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. [Figure 24] FIG. 11 is also a circuit diagram for explaining an example of specific paths of a BRDY signal, a BRQ signal, an EXS signal, a PRDY signal, and a P-OUT signal in the second embodiment. [Diagram 25] A diagram showing an example of a wiring pattern on the surface (component mounting surface) of a dispensing control board in the second embodiment. [Figure 26] A diagram showing an example of a wiring pattern on the back surface of a dispensing control board in the second embodiment. [Figure 27] FIG. 11 is an explanatory diagram of an example of the arrangement of insulating transmission means in the second embodiment. [Figure 28] An explanatory diagram of the positions of various connectors on the dispensing control board in the second embodiment. [Figure 29] A schematic cross-sectional view to explain an example of the formation pattern of separation parts and grounds in a dispensing control board as a second embodiment. [Diagram 30] FIG. 11 is an explanatory diagram regarding the width of a separation portion in a second embodiment. [Diagram 31] An explanatory diagram of a communication board provided in a gaming machine as a first modified example in the second embodiment. [Diagram 32] An explanatory diagram of a communication board provided in a gaming machine as another example of the first modified example in the second embodiment. [Diagram 33] An explanatory diagram of a communication board provided in a gaming machine as a second modified example in the second embodiment. [Diagram 34] An explanatory diagram of a communication board provided in a gaming machine as another example of the second modified example in the second embodiment. [Diagram 35] FIG. 11 is an oblique view showing the appearance of a gaming machine according to a third embodiment. [Diagram 36] An oblique view of the gaming machine with the front frame open. [Figure 37] FIG. [Figure 38] FIG. [Figure 39] 13 is a diagram explaining the main display device and the fourth pattern display device. FIG. [Diagram 40] 2 is a block diagram showing the control configuration of the gaming machine. [Diagram 41] 2 is a block diagram showing the control configuration of the gaming machine. [Diagram 42] FIG. 13 is a diagram illustrating a screen displayed on the LCD unit. [Diagram 43] 13 is a flowchart showing the main processing on the main control side. [Diagram 44] 13 is a flowchart showing the main control side timer interrupt processing. [Diagram 45] 13 is a flowchart showing a main process on a frame control side. [Diagram 46] 13 is a flowchart showing a frame control side timer interrupt process. [Figure 47] 13 is a flowchart showing main processing on the performance control side. [Figure 48] 13 is a flowchart showing the timer interrupt processing on the performance control side. [Figure 49] A diagram showing an example of a jackpot determination table and a pattern table. [Figure 50] FIG. 13 is a diagram showing an example of a fluctuation pattern table. [Figure 51] FIG. 13 is a diagram showing the presentation means used when executing a SP presentation. [Figure 52] FIG. 13 is a diagram explaining the flow of the SP performance. [Diagram 53] FIG. 13 shows an example of a SP presentation. [Figure 54] FIG. 13 shows an example of a SP presentation. [Figure 55] FIG. 13 shows an example of a SP presentation. [Figure 56] FIG. 13 shows an example of a SP presentation. [Figure 57] A figure showing a time chart of the presentation means in the notification presentation at the time of a jackpot. [Figure 58] FIG. 13 shows an example of a SP presentation. [Figure 59]FIG. 13 shows an example of a SP presentation. [Figure 60] FIG. 13 shows an example of a SP presentation. [Figure 61] FIG. 13 shows an example of a SP presentation. [Figure 62] A diagram showing the LED lighting pattern during notification performance. [Figure 63] 13A and 13B are diagrams showing modified examples of the light emission pattern. [Figure 64] FIG. 2 is a diagram illustrating a configuration of a main display device. [Figure 65] 2 is a diagram illustrating a circuit configuration around a main control unit on a main control board. FIG. [Figure 66] 4 is a diagram illustrating a circuit configuration related to display control of a main display on a main control board. FIG. [Figure 67] FIG. 4 is a diagram illustrating a circuit configuration of a main display board. [Figure 68] FIG. 2 is a view of the gaming machine from the rear side. [Figure 69] 1A and 1B are diagrams illustrating the structure of a frame control board. [Figure 70] 13 is a diagram explaining the configuration of a game ball number display device. FIG. [Figure 71] 10 is a diagram illustrating the circuit configuration around the frame control unit on the frame control board. FIG. [Figure 72] 13 is a diagram for explaining a circuit configuration related to display control of a performance indicator on a frame control board. FIG. [Figure 73] 13 is a diagram illustrating the circuit configuration around a predetermined connector on the frame control board. FIG. [Figure 74] A diagram explaining the circuit configuration of the game ball number display board. [Figure 75] A diagram explaining the structure of the fourth pattern display device. [Figure 76] A diagram showing a portion of the circuit configuration of the decorative relay board, which relays between the performance control board and the fourth pattern display board. [Figure 77] A diagram explaining the circuit configuration of the fourth pattern display board. [Figure 78] FIG. 11 is a diagram showing a circuit configuration of a main control board in the first modified example. [Figure 79] A diagram explaining the fourth pattern display device in variant example 2. [Figure 80] This is a diagram showing various values ​​related to the LEDs of the main display, performance display, number of game balls display, and fourth pattern display. [Figure 81] FIG. 13 is a diagram showing various values ​​related to the LEDs of the main display and performance display A in the first modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. <1. First embodiment> <2. Second embodiment> [2.1 Overview of communication functions with external devices and communication board configuration] [2.2 Example of substrate configuration as the second embodiment] (2.2.1 Configuration example A) (2.2.2 Configuration example B) (2.2.3 Configuration example C) (2.2.4 Configuration example D) (2.2.5 Configuration examples E, F) [2.3 First modified example (configuration example G)] [2.4 Second Modification (Configuration Example H)] [2.5 Other variations] <3. Third embodiment> [3.1 Structure of the gaming machine in the third embodiment] [3.2 Control configuration of the gaming machine in the third embodiment] (3.2.1 Main control board) (3.2.2 Frame control board) (3.2.3 Power supply board) (3.2.4 Performance control board) [3.3 Overview of operation] (3.3.1 Game Status) (3.3.2 Special symbol variation display game) (3.3.3 Jackpot Games) (3.3.4 Normal symbol variation display game) (3.3.5 Screen displayed on LCD unit) [3.4 Processing the main control board] (3.4.1 Main control side main processing) (3.4.2 Master control side timer interrupt processing) [3.5. Processing of frame control board] (3.5.1 Main processing on the frame control side) (3.5.2 Timer interrupt processing on frame control side) [3.6 Processing of the performance control board] (3.6.1 Main processing on the performance control side) (3.6.2 Performance control side timer interrupt processing) [3.7 Effects based on fluctuation patterns] (3.7.1 Drawing for special variable display game in main control unit) (3.7.2 Production methods used in SP production) (3.7.3 SP Production) [3.8 Lighting patterns of LEDs for performances] [3.9 Configuration example of the third embodiment] <4. Fourth embodiment> [4.1 LEDs on the main control board] [4.2 LEDs on the Frame Control Board] [4.3 LEDs on the performance control board] [4.4 Modification of the fourth embodiment] (4.4.1 Variation 1) (4.4.2 Variation 2) [4.5 Configuration example of the fourth embodiment]

[0011] <1. First embodiment> FIG. 1 is a perspective view showing a gaming machine GM as a first embodiment. This gaming machine GM is configured as a pachinko machine, and is configured to have a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached to be openable and closable via a hinge 2 fixed to the outer frame 1. A game board 5 is detachably attached to the inner frame 3 from the front side, not from the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be openable and closable. In this specification, the glass door 6 and the front panel 7 are collectively referred to as a front door member. The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may be referred to as a gaming frame.

[0012] Illuminated lamps such as LED lamps are arranged in an approximate C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right positions and on the lower side of the glass door 6. The two speakers arranged on the upper side are configured to output the sounds of the left and right channels R and L, respectively, and the speaker on the lower side is configured to output low-pitched sounds.

[0013] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0014] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is not normally functional, but when the game state becomes a button chance state, a built-in lamp is lit and the button becomes operable. The button chance state is a game state that is provided as necessary.

[0015] In addition, a rotary switch type volume switch VLSW is located below the chance button 11, and the player can adjust the speaker volume in eight steps from silent level (=0) to the maximum level (=7) by operating the volume switch VLSW. The speaker volume is initially set by a setting switch (not shown) that can be operated only by the attendant, and the initially set volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume regardless of the initially set volume by the attendant or the volume set by the player.

[0016] An operation panel 12 for operating the ball lending machine is provided on the right side of the upper tray 8, and includes a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of a specified amount of game balls, and a return switch that commands the return of the card when the game ends.

[0017] As shown in Fig. 2, a guide rail 13 consisting of an outer rail and an inner rail made of metal is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in the approximate center of the guide rail 13. A movable performance body (not shown) is stored in a concealed state below the central opening HO, and during a movable advance notice performance, the movable performance body rises and becomes exposed, thereby realizing an advance notice performance with a predetermined reliability. Here, the advance notice performance is a performance that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the advance notice performance means the probability that the jackpot state will occur.

[0018] A display device DS consisting of a large (for example, 1280 pixels wide x 1024 pixels high) liquid crystal color display is disposed in the central opening HO. The display device DS is composed of a main liquid crystal display section MONI and an LED backlight section BL, and is a device that variably displays specific symbols related to a jackpot state, as well as displays background images and various characters in an animated manner. This display device DS has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right section. The special symbol display sections Da-Dc may execute reach effects that anticipate the arrival of a jackpot state, and appropriate advance notice effects are executed in and around the special symbol display sections Da-Dc.

[0019] In the game area where the game balls fall, there are arranged a first symbol start hole 15a, a second symbol start hole 15b, a first big prize hole 16a, a second big prize hole 16b, a normal prize hole 17, and a gate 18. Each of these prize holes 15 to 18 has a detection switch inside so that it can detect the passage of the game ball.

[0020] Above the first symbol start opening 15a, there is disposed a performance stage 14 configured so that the game ball that enters from the introduction opening IN can enter the first symbol start opening 15 after moving in a seesaw or roulette shape. When the game ball enters the first symbol start opening 15, the special symbol display sections Da to Dc are configured to start varying.

[0021] The second pattern starting opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0022] The normal symbol display unit 19 displays normal symbols. When a gaming ball passing through the gate 18 is detected, the normal symbols change for a predetermined period of time and then stop displaying a stopping symbol determined by a random number value for lottery extracted at the time the gaming ball passes through the gate 18.

[0023] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening and closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first symbol starting opening 15a, and the second large prize opening 16b is configured to correspond to the first symbol starting opening 15b.

[0024] In other words, when a game ball enters the first pattern start opening 15a, the special pattern display sections Da to Dc begin to change in size, and then, when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the sliding plate of the first large prize opening 16a opens forward, facilitating the entry of the game ball.

[0025] On the other hand, as a result of the change action started by the entry of the game ball into the second symbol start hole 15b, when a predetermined jackpot symbol is aligned in the special symbol display section Da-Dc, a special game as a second jackpot is started, and the opening and closing plate of the second big prize entry hole 16b is opened to facilitate the entry of the game ball. The game value of the special game (jackpot state) varies depending on the aligned jackpot symbols, but which game value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the game ball.

[0026] In a typical jackpot state, after the opening and closing plate of the big prize opening 16 is opened, the opening and closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered the prize. This operation continues for a maximum of, for example, 15 times, and is controlled to be in a state advantageous to the player. If the stopped pattern after the change of the special pattern display sections Da to Dc is a specific pattern among the special patterns, a special privilege is given in which the game after the end of the special game will be in a high probability state (probability state).

[0027] Fig. 3(a) is a block diagram showing the overall circuit configuration of the gaming machine GM that realizes each of the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT arranged on the payout control board 25. As shown in Figure 3(a), this gaming machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) along with the AC 24V, a main control board 21 that is responsible for overall game control operations, a presentation interface board 22 equipped with a digital amplifier 29 for sound presentation and the like, a presentation control board 23 that executes lamp presentation, sound presentation and image presentation in a unified manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the presentation control board 23 and the display device DS, a payout control board 25 that controls the payout motor M based on the control commands CMD' received from the main control board 21 to pay out gaming balls, and a launch control board 26 that launches gaming balls in response to player operations.

[0028] Fig. 4 is a somewhat detailed diagram of a portion of Fig. 3(a), and shows the schematic internal configuration of the performance interface board 22, performance control board 23, and liquid crystal interface board 24. As shown in Fig. 4 and Fig. 3(a), the performance interface board 22, performance control board 23, and liquid crystal interface board 24 are directly connected to male and female connectors without going through wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made complex and advanced, the storage space of the entire board can be minimized, and noise resistance can be improved by shortening the connection lines.

[0029] As shown in Fig. 3(a), the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

[0030] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 with built-in computer circuits such as a general performance circuit 52 and a built-in CPU circuit 51. These control boards 21, 25, 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are sometimes referred to functionally as the main control unit 21, the performance control unit 23, and the payout control unit 25 in this specification. Note that the performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0031] This gaming machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Fig. 3(a) and a board side member GM2 fixed to the back of the gaming board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 on the outside of that, and is fixedly installed in the gaming hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a change in the model, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All members except the frame side member GM1 are board side members GM2.

[0032] As shown in the dashed frame in Fig. 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to appropriate positions in the inner frame 3. Meanwhile, a main control board 21 and a performance control board 23 are fixed to the back of the game board 5 together with a display device DS and other circuit boards. The frame side member GM1 and the board side member GM2 are electrically connected by centralized connectors C1 to C3 arranged in one place.

[0033] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0034] The DC 35V is used as a driving power source for the ball feed solenoid and launch solenoid in relation to the launching operation of the game ball, and as a driving power source for the electromagnetic solenoid that opens and closes the electric tulip (variable winning device) and the large winning port 16. The DC 12V is used as a driving power source for the LED lamps and motors controlled by each control board, and as a power source voltage for the digital amplifier, while the DC 5V is used as a power source voltage for the one-chip microcomputer of the payout control board 25 and the main control board 21, and as a power source voltage for the logic elements mounted on each control board. The DC 5V is also stepped down in level by the DC / DC converter of the performance interface board 22 and the performance control board 23, and the stepped down voltages of various levels are used as power source voltages for various computer circuits (such as the composite chip 50).

[0035] The backup power supply BAK is a DC 5V power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0036] On the other hand, after the power is cut off, the backup power supply BAK holds the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power is cut off after the power is turned on. Note that the backup power supply board 33 is equipped with an electric double layer capacitor that can hold the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0037] In this embodiment, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT is configured to have a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that uses a DC voltage of 5V received from the power supply board 20 as a power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs a detection signal ABN (power supply abnormality signal) of H level based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

[0038] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power supply drops abnormally for some reason (normally due to a power cut), the photocoupler PH turns OFF, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the power supply abnormality signal ABN of an abnormal level executes a backup process to store necessary information in its own built-in RAM. As explained above, the information in the built-in RAM is maintained by the backup power supply BAK, so that the game operation before the power cut can be resumed after the power is turned on.

[0039] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 which has built-in computer circuits such as an overall performance circuit 52 and an built-in CPU circuit 51, and the LCD interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) which stores performance data, and a power supply control circuit SPY.

[0040] In this embodiment, the overall performance circuit 52 built into the composite chip 50 includes a video processing unit VDP (Video Display Processor), an audio processing unit SND (Audio Processor), a motor control unit MT_CTL, and a lamp control unit L_CTL. Based on the control from the built-in CPU circuit 51, the overall performance circuit 52 performs intermittent operation with an operation period δ (= 1 / 30 seconds) to perform image performance using the display device DS, audio performance driving the speaker via the digital amplifier 29, motor performance rotating the performance motors M1 to Mn to move the role objects, and lamp performance blinking LED lamps. In the following description, the built-in CPU circuit 51 may be abbreviated as the CPU circuit 51.

[0041] When the power is turned on, the reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20, and resets the power supply to the internal circuitry and other electronic elements of the composite chip 50. As explained above, the internal circuitry of the composite chip 50 includes a video processing section VDP (Video Display Processor) and an audio processing section SND (Audio Processor), and the power reset signal is nothing but a system reset signal SYS of the composite chip 50, which synchronously resets the power supply to the CPU circuit 51 and the overall performance circuit 52.

[0042] In this embodiment, during the L assertion period of the system reset signal SYS, all internal circuits are initialized uniformly, and default values ​​are set in the performance control register RGij of the composite chip 50. After that, when the system reset signal SYS transitions to H level, the boot program is started, and the necessary initial setting operation is performed on the performance control register RGij. On the other hand, when the DC voltage of 5V drops (usually when the power is cut off), the system reset signal SYS drops to L level, so that the CPU circuit 51 and the general performance circuit 52 of the performance control board 23 are in a stopped state.

[0043] As described later, this embodiment is configured so that the system reset signal SYS does not change even if the WDT (Watch Dog Timer) circuit 58 is activated, and all internal circuits are not initialized uniformly even in the event of an abnormality that activates the WDT 58. That is, this embodiment is configured so that a predetermined internal circuit that is arbitrarily selected is initialized.

[0044] Next, the clock circuit 38 and the performance data memory 39 mounted on the liquid crystal interface board 24 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 continues, and the game performance information stored in the performance data memory 39 is permanently stored and held (non-volatile).

[0045] The clock circuit 38 is configured to be able to output an interrupt signal (RTC interrupt) to the CPU circuit 51. The RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is started after a predetermined time has elapsed, but in this embodiment, an alarm interrupt IRQ_RTC that updates the daily game performance information at the end of business each day is used.

[0046] As shown in Fig. 3(a), the payout control board 25 and the main control unit 21 are each equipped with reset circuits RST1 and RST2, and are configured so that when the power is turned on, a power reset signal is generated and each computer circuit is power reset. In this way, in this embodiment, the main control unit 21, the payout control unit 25, and the performance interface board 22 are each equipped with reset circuits RST1 to RST3, and for example, the system reset signal generated by the power supply board 20 is not transmitted between the circuit boards. In other words, since there is no wiring cable that transmits the system reset signal, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0047] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the dispensing control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, each CPU is forcibly reset. Also, the main control unit 21 is provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcomputer of each control unit 21, 25.

[0048] As shown in Fig. 3(a), the main control unit 21 receives a prize ball count signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN from the payout control unit 25. The status signal CON includes, for example, a supply out signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

[0049] The main control unit 21 also receives switch signals from detection switches built into each winning hole 16-18 on the game board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Each switch signal indicating the winning status of the symbol start hole 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0050] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connection connector C2 (see Fig. 3(a) and Fig. 4). The 12V DC voltage is the power supply voltage for the digital amplifier 29, and is also used as the drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the play frame and is used as the drive voltage for solenoids that reciprocate movable objects.

[0051] Meanwhile, the DC voltage 5V is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to a DC / DC converter DC to generate 3.3V (see FIG. 4). The generated DC voltage 3.3V becomes the base voltage for the power reset signal (system reset signal) SYS generated by the reset circuit RST3. The DC voltage 5V distributed to the performance interface board 22 is also distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC. The DC voltage 3.3V distributed to the performance control board 23 is then supplied as a power supply voltage to the composite chip 50 and external ROM 55.

[0052] As shown in Fig. 4, two DC / DC converters DC1 and DC2 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the VRAM 53 and the expansion RAM 54. Therefore, the DC voltage of 1.5V is also supplied to the VRAM 53 and the expansion RAM 54 as the power supply voltage.

[0053] As shown in Fig. 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Fig. 4, the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 57 obtains the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0054] 4, the input buffer 44 of the performance interface board 22 receives switch signals of the chance button 11 and the volume switch VLSW from the frame relay board 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW, and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0055] The performance interface board 22 is also connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43 in FIG. 4. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position of the role object, which is the movable performance body (the rotational positions of the performance motors M1 to Mn), and transmits these to the motor control unit MT_CTL of the performance control board 23.

[0056] The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers serial signals received from the lamp control unit L_CTL and the motor control unit MT_CTL of the performance control board 23 to each driver IC. The serial signals are specifically lamp (motor) drive signals SDATA and clock signals CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronous manner, and lamp performances using numerous LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn are executed.

[0057] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the driver IC of the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 output by the lamp control unit L_CTL via the frame relay board 36 in synchronization with the clock signal CK0. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO 62) changes to an active level, thereby updating the lighting state of the lamp group CH0 all at once.

[0058] The above also applies to the lamp drive board 30, and the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for the lamp group CH1 output from the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually the PIO 62) changes to an active level, the lighting states of the lamp group CH1 are updated all at once.

[0059] Meanwhile, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 by receiving a lamp drive signal transmitted in clock synchronous manner from the motor control unit MT_CTL, and drives the performance motor group M1 to Mn, which is composed of a plurality of stepping motors, by receiving a motor drive signal transmitted in clock synchronous manner. Since the lamp drive signal and the motor drive signal are the same type of serial signal, a series of composite serial signals SDATA2 are output from the motor control unit MT_CTL in synchronization with the clock signal CK2, and the driver IC that receives this updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0060] In this embodiment, for the motor lamp drive board 31, the motor control unit MT_CTL is in charge of the motor performance and the lamp performance for convenience, so the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Note that the lamp drive signals SDATA0 and SDATA1 for the lamp drive board 37 and the lamp drive board 30 may also be configured to be output from the motor control unit MT_CTL.

[0061] 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is chip-selected by a chip select signal, the CPU circuit 51 can arbitrarily access the internal register (having a 4-bit address value).

[0062] In addition, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus. When the chip is selected, the game performance information and other data stored in the SRAM (performance data memory) 39 can be appropriately read / written by the CPU circuit 51.

[0063] In addition, a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL is mounted on the liquid crystal interface board 24. Specifically, the power supply control circuit SPY controls the start timing of supplying power supply voltages of 12V and 5V to the display device DS and the backlight board BL with a control signal STBY, and controls the brightness of the backlight light and the start timing of light emission with a control signal PWM.

[0064] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 which incorporates a CPU circuit 51 and an overall performance circuit 52, a VRAM 53 which is rapidly accessed via R / W from the CPU circuit 51 and the overall performance circuit 52, an expansion RAM 54 which can store large amounts of data, and an external ROM 55 which stores CG data and other data in a non-volatile manner.

[0065] The VRAM 53 is capable of high-speed access with a theoretical transfer speed of about 102 GB / sec, and has a storage capacity of about 48 MB. The VRAM 53 is primarily used for (1) storing reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see FIG. 5(a)). It can also (2) store a copy of data in the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0066] The expansion RAM 54 can operate at a theoretical transfer rate of about 17.0 GB / sec, has a storage capacity of about 1 GB, and can be used in the same manner as the VRAM 53. That is, the expansion RAM 54 can be used (1) to store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) to store copies of data in the external ROM 55, and (3) as a work area for the CPU circuit 51.

[0067] The external ROM 55 in this embodiment is a non-volatile storage device that stores a boot program that starts when the power is turned on, a control program for the CPU circuit 51 that realizes performance control, control data including lamp drive data, CG compressed data for image performance, and audio compressed data for audio performance. The storage capacity of the external ROM 55 is about 256 GB at maximum, but since high-speed access is not possible, in this embodiment, a part of the data in the external ROM 55 is transferred to the extended RAM 54 when the power is turned on. Specifically, the control program and control data that operate the CPU circuit 51 are transferred and copied from the external ROM 55 to the extended RAM 54 by the boot program stored in the external ROM 55 when the power is turned on.

[0068] 5(a) is a circuit block diagram illustrating the composite chip 50 constituting the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL and a voice command list VC, and an overall performance circuit 52 that executes image performances based on the display list DL and voice performances based on the voice command list VC, as well as lamp and motor performances. The CPU circuit 51 and the overall performance circuit 52 are connected via a CPU bus unit 56 that relays data transmitted and received between them.

[0069] First, the CPU bus section 56 located between the CPU circuit 51 and the overall performance circuit 52 will be described. As shown in Fig. 5(a), the CPU bus section 56 is connected to the VRAM 53, the expansion RAM 54, and the external ROM 55 via the VRAM IF section 53a, the expansion RAM IF section 54a, and the CG bus IF section 55a. Therefore, in this embodiment, the VRAM 53, the expansion RAM 54, and the external ROM 55 can be accessed not only by the overall performance circuit 52, but also by the CPU circuit 51.

[0070] The VRAMIF section 53a, the extended RAMIF section 54a, and the CG busIF section 55a are connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via an arbitration circuit ICM (Inter Connect Module) (not shown). The arbitration circuit ICM is located between each functional block of the overall performance circuit 52 and the VRAMI / F section 53a, the extended RAMI / F section 54a, and the CG busI / F section 55a, and arbitrates data requests issued by each functional block as appropriate to establish the necessary connection relationships.

[0071] In any case, the CPU circuit 51 of this embodiment can access the VRAM 53, the expansion RAM 54, and the external ROM 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external ROM 55 to the expansion RAM 54 when the power is turned on, the CPU circuit 51 does not access the external ROM 55. In other words, after the copy operation, the CPU circuit 51 executes a control operation based on the control program and control data copied to the expansion RAM 54.

[0072] This CPU circuit 51 can read / write access various performance control registers RGij to control the internal operation of the overall performance circuit 52. The data transfer circuit 70 can also transmit and receive data between the CPU circuit 51 and the overall performance circuit 52 via the CPU bus unit 56. The data transmission from the CPU circuit 51 to the overall performance circuit 52 includes the issuance of a display list DL and a voice command list VC.

[0073] As shown on the right side of Figure 5(a), the overall performance circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphic Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND, and the performance control register RGij is used to enable the CPU circuit 51 to appropriately control the internal circuits of the overall performance circuit 52.

[0074] Therefore, the performance control register RGij is broadly divided into (1) data transfer register, (2) display register, (3) preload register, (4) GDEC register, (5) drawing register, (6) image filter register, (7) index table register, (8) MT_CTL register, (9) L_CTL register, (10) sound register, etc. corresponding to each of the above circuits (1) to (10), and a system control register is provided for overall system control (see Figure 5 (b)). Note that the system control register and each of the registers (1) to (10) for the individual circuits are actually composed of multiple register groups that are further divided.

[0075] Based on the above, the CPU circuit 51 will be described. The CPU circuit 51 is a circuit with the same performance as a general-purpose one-chip microcomputer, and as shown on the left side of Fig. 5(a), it is configured with a performance control CPU 57 that comprehensively controls image / audio / lamp / motor performance based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU when the program goes out of control, an internal RAM 59 with a storage capacity of about 2MB that is used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without passing through the performance control CPU 57, a serial input / output port (SIO) 61 with multiple input ports Si and output ports So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output ports Po, and an operation control register REG in which a setting value is set to control the internal configuration of the CPU circuit 51.

[0076] For convenience, the term "input / output port" is used in this specification, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0077] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB through the input circuit 64p. The 3-bit encoder output and 1-bit switch signal are supplied to the parallel input / output port 62 through the input / output circuit 64p.

[0078] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby starting the reception interrupt process. Therefore, the performance control CPU 57, which has grasped the control command CMD based on the reception interrupt process, will unify the control of the sound performance, lamp performance, motor performance, and image performance corresponding to this control command CMD through a performance drawing, etc. The parallel input / output port 62 outputs the operation control signals ENABLE0 to ENABLE1 for the lamp performance via the input / output circuit 64p.

[0079] Also, the serial input / output port (SIO) 61 is configured to be able to transmit and receive a serious signal via the input / output circuit 63s. Therefore, as shown by the dashed line in Fig. 5(a), a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA can also be output via the input / output circuit 63s internally connected to the serial input / output port SIO 61. However, in this embodiment, the lamp / motor performance is realized by using the lamp control unit L_CTL and the motor control unit MT_CTL of the overall performance circuit 52 without using the serial input / output port 61.

[0080] Incidentally, a DL buffer BUF for sequentially updating and storing a display list DL in which a series of instruction commands specifying one frame of the display device DS are listed is secured in the built-in RAM 59 of the CPU circuit 51. Moreover, this DL buffer BUF is configured by partitioning areas, and also sequentially updating and storing a voice command list VC specifying the performance contents of the voice performance.

[0081] In this embodiment, the instruction commands of the display list DL that specifies one frame of the display screen include (1) an index table control command related to the index table IDXTBL that manages the index space, (2) texture load commands such as the LOADTX command for reading and decoding (decompressing / expanding) image material (texture) from the external ROM 55, (3) filter execution commands that specify filter processing for the decompressed image data, (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space, (5) pipeline commands related to drawing pipeline operation, and (6) overall control commands that specify the overall operation of the overall performance circuit 52, all of which are configured as an integer multiple (>0) of 32 bits. The display list DL is configured to end with a predetermined end command EODL (32 bits long) after listing an appropriate number of instruction commands. Also, the voice command list VC, which specifies the operation of the voice processing unit SND that executes the voice performance, lists an appropriate number of voice commands and then ends with a predetermined end command EOSC (32-bit length). Here, the voice commands are roughly divided into track-related commands that specify the operation of the pre-processing unit FT shown in Fig. 12(a), master effect-related commands that specify the operation of the post-processing unit BK shown in Fig. 12(a), and other system-related commands, and each voice command is composed of an integer multiple (>0) of 32 bits.

[0082] As described later, the rendering pipeline operation of this embodiment is executed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB secured as an index space, and the depth / stencil buffer, and is configured to include an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The above-mentioned (5) pipeline command functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0083] Incidentally, texture is generally a concept referring to the feel and texture of an object's surface, but in this specification, image data before and after decoding is collectively referred to as texture. For example, sprite image data that makes up a still image, frame image data that makes up one frame of a video, and pasted image data that is pasted onto drawing primitives such as triangular polygons and quadrilateral polygons are also referred to as texture.

[0084] Then, (2) the texture is read out from external ROM 55 and decoded by the LOADTX command, which is a texture load command, (5) the source image data is set to be a texture by the SETTXINDEX command, which is a texture sampler process TX command included in the pipeline commands, and (4) the texture is virtually rendered in the virtual rendering space shown in Figure 6(c) by the SPRITE command, which is a rendering command. The contents rendered in the virtual rendering space are output to the display device DS via the frame buffer FB, which will be described later.

[0085] The index space managed by the index table control command (1) above means a one-dimensional or two-dimensional memory work area (logical address space) used by the overall performance circuit 52 during drawing operations, etc. This index space is specified as a one-dimensional or two-dimensional logical address space by the index number written in the instruction command of the display list DL.

[0086] That is, in this embodiment, an index space is reserved in an appropriate location of memory (VRAM 53 and expansion RAM 54) accessible as a memory work area, and this is specified by an index number. Also, VRAM 53 and expansion RAM 54 are divided into virtual work areas (AAC area, page area, arbitrary area), and index space can be reserved for each (see FIG. 6(a) and FIG. 6(b)). Therefore, the index number becomes a unique value for each virtual work area, and texture load commands, filter execution commands, drawing commands, pipeline commands, etc. are simplified.

[0087] It also allows individual operation for each virtual work area (AAC area, page area, arbitrary area). For example, in the AAC area, index space is automatically secured as an area for expanding decoded data, and is automatically released. Therefore, index numbers are not required in the ACC area.

[0088] In terms of specific control operations, the virtual work areas (AAC area, page area, arbitrary area) are defined in the initial processing after power-on, and the necessary index space is secured in the necessary virtual work area at the necessary timing thereafter. The secured index space is then linked to the index number and managed by the index table IDXTBL, thereby realizing operations based on the index number thereafter.

[0089] The relationship between the virtual working area and the actual working areas, which are the VRAM 53 and the expansion RAM 54, will be explained below. First, the VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other optional areas. Specifically, in the initial processing after power-on, an appropriate top address and area data size for the VRAM 53 are set in the corresponding performance control register RGij, thereby securing the shared area of ​​the VRAM 53. Then, areas other than the shared area secured in the VRAM 53 automatically become optional areas of the VRAM 53 (FIG. 6(a)).

[0090] The shared area secured in the VRAM 53 can be used as an ACC area that does not require management of index numbers, and as a page area that requires management of index space by index numbers. Therefore, when using a shared area, it is necessary to specify that an index space is secured in the AAC area with the SETTXINDEX command, and then specify the size and storage address of the texture (image material) with the LOADTX command, and the decompressed data of the read texture can be expanded in the index space that is automatically secured in the ACC area.

[0091] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, for still images and I stream moving images (S stream moving images composed only of I pictures, which will be described later), decoded data is developed in the AAC area of ​​the VRAM 53. That is, in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as an AAC area.

[0092] Next, in the initial processing after power-on, the top address and area data size on the expansion RAM 54 are set in the corresponding performance control register RGij, so that the page area of ​​the expansion RAM 54 is secured, and the other area becomes the arbitrary area of ​​the expansion RAM 54 (FIG. 6(b)). Here, the arbitrary area means an area in the expansion RAM 54 and the VRAM 53 that is allowed to be used arbitrarily, and not only can the index space be secured, but other uses are also possible. Therefore, in this embodiment, a preload area for pre-transferring (preloading) the CG data acquired from the external ROM 55 is secured in the arbitrary area of ​​the expansion RAM 54 (see FIG. 6(b)), and a preload buffer for storing the rewrite list DL' obtained by the preloader 72 rewriting the display list DL is secured in the arbitrary area of ​​the VRAM 53 (see FIG. 6(a)).

[0093] Furthermore, in this embodiment, the control programs and control data stored in the external ROM 55 are transferred and copied to any area of ​​the extended RAM 54 when the power is turned on (see FIG. 6(b)). Of course, all or part of the control programs and control data may be transferred and copied to the VRAM 53 instead of the extended RAM 54. Furthermore, without being limited to the control programs and control data, a configuration may also be adopted in which all or part of CG compressed data and audio compressed data CG data are also transferred and copied to the RAMs 53 and 54.

[0094] In any case, the index space can be appropriately allocated in the extended RAM 54 and VRAM 53 in (1) the ACC area, (2) the VRAM page area, (3) the VRAM arbitrary area, (4) the extended RAM page area, and (5) the extended RAM arbitrary area, but in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as the AAC area. However, the area allocated as the shared area in the VRAM 53 can be used as both a page area and an AAC area, so the following explanation will be given with this point in mind.

[0095] When reserving an index space in the page area of ​​the VRAM 53, it is necessary to set an index number and a space size in a predetermined performance control register RGij for the VRAM. Also, the index space in the page area of ​​the extended RAM 54 is reserved by setting an index number and a space size in a predetermined performance control register RGij for the extended RAM. In this embodiment, the page area of ​​the extended RAM 54 is used to develop video frames. In addition, in the page area, the top address of the index space is appropriately determined based on internal processing, so there is the convenience of not needing to manage the top address. In other words, in the page area, when reserving an index space, there is no need to worry about overlap with an existing index space.

[0096] On the other hand, when a two-dimensional index space is reserved in an arbitrary area of ​​the VRAM 53 or an arbitrary area of ​​the extended RAM 54, it is necessary to set the index number, the top address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. Note that in the case of a one-dimensional index space, the vertical size is not necessary.

[0097] In this way, when the index space is reserved in an arbitrary area, the start address and size can be set in detail, and there is an advantage that the memory can be used efficiently. Therefore, in this embodiment, the image data for one frame of the display device DS is completed and the frame buffer FB is reserved as a two-dimensional index space in an arbitrary area of ​​the VRAM 53 (see FIG. 6(a)). It goes without saying that the frame buffer FB may be reserved in an arbitrary area of ​​the expansion RAM 54.

[0098] The frame buffer FB allocated in any area of ​​the VRAM 53 corresponds to the drawing area of ​​a virtual drawing space that is the drawing target of drawing commands such as the SPRITE command. Figure 6(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the frame buffer FB that stores image data to be output to the display device DS.

[0099] One frame of image data for the display screen is written into the frame buffer FB by the drawing circuit 74, while one frame of image data for the display screen is read out by the display circuit 71. This frame buffer FB has a double buffer structure made up of a pair of index spaces, and is made up of a first buffer with index number N1 and a second buffer with index number N2.

[0100] For the display circuit 71, the first buffer and the second buffer are read-out areas for image data, and the image data in the first buffer and the second buffer are read out in sequence for each operating period δ by toggling the index numbers N1 / N2 based on the embedded information in a specified display register RGij.

[0101] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are write areas for image data, and image data is written alternately to the first buffer and the second buffer by toggling the index numbers N1 / N2 for each operating period δ based on the instruction command on the display list DL.

[0102] The writing operation of the drawing circuit 74 corresponds to the reading operation of the display circuit 71, so that image data written to the first buffer in one operation cycle is read by the display circuit 71 in the next operation cycle, and in the operation cycle in which the image data in the first buffer is read, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, and the first buffer and the second buffer are used alternately as the "writing area" and the "reading area".

[0103] In this embodiment, the general working space used is index space secured in any area of ​​the VRAM 53 or the extended RAM 54, excluding the frame buffer FB and the decompression space for compressed data. These various index spaces can be secured when necessary and released when not required, but when an index space is secured / released, the contents of the index table IDXTBL, which stores the index space in association with the index number, are updated, enabling subsequent consistent operation.

[0104] The index space and the CPU circuit 51 have been explained above. Next, the overall performance circuit 52 will be explained.

[0105] The overall presentation circuit 52 includes (1) various presentation control registers RGij, whose internal operation is determined by the presentation control CPU 57; (2) a data transfer circuit 70 that transmits and receives data between circuits inside and outside the chip; (3) an index table IDXTBL that manages an index space, which is a working area secured in the VRAM 53 and the expansion RAM 54; (4) a preloader 72 that can perform a preload operation to access the external ROM 55 for reading prior to a drawing operation; and (5) a Graphic Decoder (GDEC) circuit that decodes compressed data for image presentation read from the external ROM 55. ) 73, (6) a drawing circuit 74 that generates one frame of image data for the display device DS in a frame buffer FB by appropriately combining the decoded still image data and video data, (7) a plurality of display circuits 71 that reads the image data generated by the drawing circuit 74 in the frame buffer FB and outputs the image data after appropriate image processing, (8) an output selection unit 76 that appropriately selects and outputs the output of the plurality of display circuits 71, (9) an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs the converted signal, (10) a voice processing unit SND that executes voice effects based on a voice command list VC, (11) a motor control unit MT_CTL that executes motor effects, and (12) a lamp control unit L_CTL that executes lamp effects (see FIG. 5(a)). The voice processing unit SND includes a voice decoder that decodes compressed data for voice effects read from the external ROM 55.

[0106] The motor performance is executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the performance control register RGij for the motor performance and the control data (motor drive data) copied to the expansion RAM 54. The lamp performance is also executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the performance control register RGij for the lamp performance and the control data (lamp drive data) copied to the expansion RAM 54.

[0107] 5(b) illustrates the relationship between the CPU bus unit 56, the CG bus IF unit 55a, the extended RAM IF unit 54a, and the VRAM IF unit 53a, and the performance control register RGij, the external ROM 55, the extended RAM 54, and the VRAM 53. As illustrated, the CG compressed data acquired from the external ROM 55 is supplied to the GDEC circuit 73 via the CG bus IF unit 55a and the data transfer circuit 70, and the decompressed (decoded) data is expanded in a predetermined index space secured in the extended RAM 54 or the VRAM 53.

[0108] As described above, in this embodiment, an ACC area for developing still images is reserved in the VRAM 53, and a page area for developing video frames is reserved in the expansion RAM 54. Then, decoded data of still images and videos is developed in a predetermined index space of the ACC area / page area. Note that decompressed data of compressed CG data acquired from the external ROM 55 may be transferred to the preload area of ​​the expansion RAM 54 as preload data.

[0109] Next, the display circuit 71 will be described with reference to Fig. 7. The display circuit 71 is a circuit that reads image data from the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and outputs the data. The final image processing includes, for example, a scaling process of a scaler that enlarges / reduces the image to a similar shape, a subtle color correction process, and a dithering process that minimizes the quantization error of the entire image. These image processes are uniformly executed based on the setting value of the performance control register RGij (display register). Then, the digital RGB signal that has undergone the uniform image processing is output together with a horizontal synchronization signal, a vertical synchronization signal, and the like.

[0110] As shown in Fig. 7, three display circuits A / B / C are provided that perform the above operations in parallel, but in this embodiment, since there is only one display device, only a frame buffer FB (=FBa) is reserved for the display circuit A. However, if frame buffers FBa to FBc are reserved, it is also possible to drive two other display devices that can perform independent image presentations.

[0111] Next, returning to Fig. 5(a), the data transfer circuit 70 will be explained. The data transfer circuit 70 is a circuit that executes data transfer operations between the internal resources of the overall performance circuit 52 and the external storage medium as the transfer source and transfer destination in a DMA (Direct Memory Access) manner. Fig. 8 is a block diagram showing the internal configuration of this data transfer circuit 70 together with the related circuit configuration.

[0112] The transfer sources of the data transfer circuit 70 in this embodiment include the CPU address space via the CPU bus unit 56, the external ROM 55, the expansion RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the transfer destinations of the data transfer circuit 70 include the CPU register port PORT, as well as the CPU address space, the expansion RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0113] Here, the CPU address space means a storage area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus section 56, and the performance control CPU 57 can arbitrarily access it via R / W.

[0114] Moreover, virtual work areas such as page areas and arbitrary areas are defined in the expansion RAM 54 and VRAM 53, and index spaces specified by index numbers are secured / released within these virtual work areas, so that the operation of the data transfer circuit 70 is executed by referring to an index table IDXTBL that stores the relationship between the index spaces and real address spaces. The index spaces secured in the expansion RAM 54 or VRAM 53 can also be set as the data transfer source or data transfer destination of the data transfer circuit 70. Therefore, data of the frame buffer FB secured in an arbitrary area of ​​the VRAM 53 can also be transferred to the expansion RAM 54.

[0115] 8, the transfer size that the data transfer circuit 70 can transfer is 32 bits x (01h to 4000_0000h) when passing through the data relay units CH0 to CH1, and 32 bits x (01h to 100_0000h) when passing through the data relay units CH2 to CH4. That is, the data transfer circuit 70 of this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h means a hexadecimal number, and the upper limit of the transfer size is specifically 32 x 1,073,741,824 bits when passing through the data relay units CH0 to CH1, and 32 x 16,777,216 bits when passing through the data relay units CH2 to CH4.

[0116] 8, the data transfer circuit 70 is configured to receive necessary data from the external ROM 55 via an arbitration circuit ICM that has a router function and arbitrates access paths, and to transmit and receive necessary data to and from the VRAM 53 and the extended RAM 54. The external ROM 55, VRAM 53, and extended RAM 54 are accessed via a CG bus IF unit 55a, a VRAM IF unit 53a, and an extended RAM IF unit 54a.

[0117] This data transfer circuit 70 is composed of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five channel data relay units CH0 to CH4. As explained above, the CPU register port PORT is configured to be R / W accessible from the performance control CPU 57.

[0118] The data relay unit CH0 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages and a checksum circuit. Each of the data relay units CH1 to CH4 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages. The data relay units CH2 to CH4 are connected in one direction to the drawing circuit 74, the preloader 72, and the sound processing unit SND.

[0119] On the other hand, the CPU data FIFO circuit and the data relay units CH0-CH1 are configured to be capable of bidirectional communication, so that a predetermined amount of data set in the data transfer register is transmitted and received from a predetermined transfer source set in the data transfer register to a predetermined transfer destination set in the data transfer register via the CPU data FIFO circuit or the data relay units CH0-CH1.

[0120] Regardless of which path is taken among the data relay units CH0 to CH4, the amount of data to be transferred (transfer data size) must be set in 32-bit units as described above, and there are also certain limitations on the start addresses of the transfer source and destination. Specifically, the start addresses of the transfer source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in the VRAM 53 and expansion RAM 54. The transfer source start address in the external ROM 55 is also set in 32-bit units.

[0121] When passing through the data relay units CH0-CH1, the transfer source and / or transfer destination is the external ROM 55, the VRAM 53, or the expansion RAM 54, and when passing through the CPU data FIFO circuit connected to the CPU register port PORT, the transfer source or transfer destination is the CPU address space. The CPU address space naturally includes the built-in RAM 59.

[0122] The data relay units CH0-CH1 capable of bidirectional communication have been described above, but the data relay units CH2-CH4 form one-way communication paths. The performance control CPU 57 can transmit the display list DL and voice command list VC in the DL buffer BUF of the built-in RAM 59 one-way to the data relay units CH2-CH4 by write accessing the CPU register port PORT in 32-bit units via the CPU bus unit 56.

[0123] In addition, the internal RAM 59 can also be selected as the data transfer source, so that data can be transferred via the data relay units CH2 to CH4 (without going through the CPU register port PORT) with the DL buffer BUF as the data transfer source and the drawing circuit 74, the preloader 72, or the audio processing unit SND as the data transfer destination.

[0124] In this case, the start address of the data transfer source built-in RAM 59 is specified in 8-bit units, so the lowest 7 bits of the start address of the DL buffer BUF must be 0. Also, regardless of whether the data is transferred via the CPU register port PORT or not, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0125] In any case, the data relay unit CH2, the data relay unit CH3, and the data relay unit CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the voice processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via the data relay unit CH2, and to the preloader 72 via the data relay unit CH3. Also, a voice command list VC of a predetermined data transfer size is transferred to the voice processing unit SND via the data relay unit CH4.

[0126] As described above, in this embodiment, the transfer paths of the display list DL and the voice command list VC are prepared as follows: (1) a first path that passes through the CPU register port PORT; and (2) a second path that does not pass through the CPU register port PORT; either of these can be used. The same is true for other data; there is (1) a first path that passes through the CPU register port PORT and data relay units CH0 to CH4; and (2) a second path that passes only through the data relay units CH0 to CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, and the second path is used for data transfers in which the performance control CPU 57 is not directly involved (DMA operation).

[0127] 8, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, when the first path is used, when 1024-bit data is accumulated in the CPU data FIFO circuit, the accumulated data is transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as a channel data FIFO). That is, if data less than 32 stages is written to the CPU data FIFO circuit, the data transfer to the channel data FIFO does not occur, and when the 32nd stage data is written, the 32nd stage of accumulated data is transferred to the channel data FIFO, and the data is further transferred to the next destination. On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, the data in the CPU data FIFO circuit may end up less than 32 stages, but when the cumulative size of the written data reaches the transfer size previously set in the data transfer register, the accumulated data less than 32 stages will be transferred to the channel data FIFO and the next destination.

[0128] Thus, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value of an integer multiple of 32 bits, regardless of whether the transfer is via the first path or the second path. The instruction commands constituting the display list DL and the voice commands constituting the voice command list VC are all composed of an integer multiple of 32 bits. Therefore, in this embodiment, there is no restriction on the number of commands in the display list DL or the voice command list VC, and any list configuration can be adopted. Also, there is no need to adjust the total data size by adding dummy commands, etc.

[0129] 9A shows the operation of transferring the display list DL to the drawing circuit 74 via the CPU register port PORT and the data relay unit CH2 (FIG. 9A), the operation of transferring the display list DL from the internal RAM 59 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9B), and the operation of transferring a rewrite list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9C).

[0130] Figures 9(d) and 9(e) show the operation of transferring a display list DL to the preloader 72 via the CPU register port PORT and the data relay unit CH3, and the operation of transferring a display list DL from the internal RAM 59 to the preloader 72 via the data relay unit CH3.

[0131] Also, Figures 9(f) and 9(g) show the operation of transferring the voice command list VC to the voice processing unit SND via the CPU register port PORT and the data relay unit CH4, and the operation of transferring the voice command list VC from the built-in RAM 59 to the voice processing unit SND via the data relay unit CH4.

[0132] The CPU circuit 51 starts the operations of the drawing circuit 74, the preloader 72, and the sound processing unit SND prior to the start of operation of the data transfer circuit 70, so that the drawing circuit 74 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 executes necessary preload operations based on the transferred display list DL. The transferred display list DL is judged by a display list analyzer built into the drawing circuit 74 and the preloader 72, and processing according to the type of instruction command is executed. Also, the sound processing unit SND starts or progresses sound performance based on the transferred sound command list VC.

[0133] Note that data other than the display list DL and the voice command list VC in the CPU address space can be transmitted to the data relay units CH0 to CH4 via the CPU bus unit 56, and then further via the CPU register port PORT, or directly. The data relay units CH0 to CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or the expansion RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar, and the data relay units CH0 to CH1 that receive data via the arbitration circuit ICM transfer the data to a predetermined destination in the CPU address space via the CPU register port PORT, or directly.

[0134] Next, the preloader 72 will be described, but it is optional whether or not to utilize the preloader 72. When the display list analyzer interprets the display list DL transferred from the data relay unit CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data in the external ROM 55 referenced by the LOADTX command to the preload area of ​​the expansion RAM 54 (see FIG. 6(b)).

[0135] Furthermore, the preloader 72 stores a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in the DL buffer BUF' (see FIG. 6(a)) of the VRAM 53 in response to the above-mentioned LOADTX command. Note that the DL buffer BUF' and the preload area are secured in advance during the initial processing after the CPU is reset.

[0136] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM and data relay unit CH2 of the data transfer circuit 70 when the drawing operation of the drawing circuit 74 begins (see FIG. 9(c)). The drawing circuit 74 then executes the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external ROM 55 based on a LOADTX command or the like is quickly obtained from the preload area of ​​the expansion RAM 54 as preload data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is put into operation in a normal device configuration.

[0137] In this embodiment, since the preload area is set in the external expansion RAM 54, which has a sufficient storage capacity, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. In other words, multiple preloading is realized by appropriately setting the operation period of the preloader 72, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operation cycle δ of the overall performance circuit 52 during intermittent operation.

[0138] However, in the following explanation, for the sake of convenience, an embodiment without multiple preloading will be explained, so the preloader 72 of the embodiment will complete the preloading operation for one frame during one operation period 6. In this embodiment, the operation period 6 during intermittent operation of the overall performance circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS.

[0139] Next, the drawing circuit 74 sequentially analyzes the instruction command sequence of the display list DL and the rewrite list DL' transferred via the data transfer circuit 70, and works together with the GDEC circuit 73 and the geometry engine to draw one frame's worth of image of the display device DS in the frame buffer FB secured in the VRAM 53.

[0140] As described above, when the preloader 72 is operated, the CG data in the rewrite list DL' is referenced not to the external ROM 55 but to a preload area set in the expansion RAM 54. Therefore, sequential access to the CG data that occurs during the execution of drawing by the drawing circuit 74 can be quickly executed, and high-resolution moving images with fast movement can be drawn without any problems.

[0141] Incidentally, regardless of whether the preloader 72 is enabled or disabled, even if data bit corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect this. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to that of a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the drawing circuit 74 starts operating.

[0142] In this embodiment, a time setting register TO capable of setting a timeout time is provided to detect an operational abnormality of the drawing circuit 74. The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to be started based on a set value in a predetermined drawing register (drawing operation permission register).

[0143] When a predetermined timeout time is set in the time setting register TO and start information is set in the drawing operation permission register, the drawing circuit 74 starts operation, and in response, the timeout monitoring circuit monitors the memory access cycle. If no memory access is performed even after the timeout time has elapsed, the abnormality flag of a predetermined drawing register is set ON and an abnormality interrupt is initiated.

[0144] Although it is possible to deal with this abnormal interrupt by starting an interrupt processing program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag for each operation cycle δ of the overall performance circuit 52. Specifically, when the abnormal flag is ON, even if the operation of the drawing circuit 74 is completed, the screen update for that operation cycle is skipped to deal with the problem.

[0145] Here, as in the configurations of Patent Documents 1 and 2, if a measure to activate the WDT 58 or a measure to reset the drawing circuit 74 is taken, there is a risk of an unnatural screen display appearing, but in this embodiment, the appearance of an abnormal screen is easily prevented with a minimum of measures. Also, the timeout period to be monitored can be set arbitrarily taking into consideration the arrangement of the LOADTX command in the display list DL, the access time of the external ROM 55, etc., and therefore an optimal monitoring operation can be realized.

[0146] In the above configuration, the memory access period is monitored from the start of operation of the drawing circuit 74 to its end, but instead of or in addition to this configuration, it is preferable to adopt a configuration that monitors the operation time from the start of operation of the GDEC circuit 73 to its end. In this case, too, an optimal value can be set in the time setting register TO' taking into account the data capacity of the texture, thereby achieving optimal monitoring operation.

[0147] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding the CG compressed data, and ends the monitoring operation at the end of the decoding. In addition, as in the former configuration, when a timeout occurs, the abnormality flag of a specified drawing register is set ON and an abnormality interrupt is started, and when an abnormality is detected, screen updates in that operation cycle are skipped. In this embodiment, a flag polling method is adopted in which the ON / OFF state of the abnormality flag is checked every operation cycle δ of the overall performance circuit 52, but a configuration in which an abnormality interrupt processing program is started and screen updates in the operation cycle in which a problem occurs may also be adopted.

[0148] Next, the image filter circuit 75 is a circuit that functions based on instruction commands (filter execution commands) written in the display list DL, and executes appropriate filter processing on textures temporarily stored in the VRAM 53 or the expansion RAM 54. That is, the image filter circuit 75 of the embodiment does not perform a uniform filter operation based on the setting value in the performance control register RGij, but rather enables free filter processing on required image data by arbitrarily writing appropriate instruction commands in the display list DL.

[0149] The content of the filter processing is determined by the selection of a filter execution command and the setting parameters of the selected command, but the executable filter processing includes (1) FIR (Finite Impulse Response) filter processing, (2) downsampling processing, and (3) linear interpolation processing. Here, the downsampling processing is a process different from the scaling processing in the display circuit 71 that operates based on the setting value in the performance control register RGij (display register).

[0150] That is, downsampling does not reduce an image to a similar shape as in scaling, but includes an operation of reducing an image only in the vertical direction or only in the horizontal direction. Although not limited to this, downsampling reduces the texture by calculating the average value of the image information of pixels in a predetermined range surrounding the target pixel and performing a thinning process such as a moving average process.

[0151] 10(a) is a diagram for explaining an example of an operation in which FIR filter processing is executed twice in succession by a filter execution command. First, the SETFTINDEX command sets the destination index space in which the reference texture to be filtered should be saved (command process L20), and then the LOADTX command retrieves the reference texture from the external ROM 55 specified by the command setting parameters, and saves the decoded image data in the destination index space (command process L21).

[0152] The following SETFTINDEX command sets the index space in which the resultant texture will be saved (command process L22), and the SETFTSAMP command and SETFTCOEF command set filter coefficients and other information (command process L23), before executing FIR filter processing with the FTEXECFIR command (command process L24).The SETFTINDEX command distinguishes between specifying an index space for the reference texture or an index space for the resultant texture, depending on the setting parameters of the command.

[0153] As shown in Figure 10(b), the image data expanded in the index space for the reference texture specified by the instruction command L20 is subjected to FIR filtering processing specified by the instruction command L23, and then stored in the index space for the result texture specified by the instruction command L22.

[0154] Next, the SETFTINDEX command sets the index space of the reference texture (command process L25), and the SETTXINDEX command sets the index space in which the resultant texture is to be saved (command process L26). In command L25, the image data after the filter process is set as the reference texture, so the resultant texture specified by command L22 is changed to the reference texture by command L25.

[0155] Thereafter, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command process L27), after which the necessary FIR filter processing is executed using the FTEXECFIR command (command process L28).The image data after filter processing is then stored in the index space specified by command L26, so by executing the SPRITE command after functioning the SETTXMODE command (command process L29), the image data that has undergone FIR filter processing will be drawn in an appropriate rectangular section in the virtual drawing space.

[0156] 10(c) is a diagram for explaining an example of an operation in which scaling processing is executed by a filter execution command. First, a SETFTINDEX command is used to set a storage index space in which to store the reference texture to be scaled (command process L30), and then a LOADTX command is used to obtain the reference texture from the external ROM 55 specified by the setting parameters of the command (command process L31).

[0157] Next, the SETTXINDEX command is used to set an index space for storing auxiliary data required for enlargement / reduction (command process L32). Here, the auxiliary data is plane information extracted from the reference texture, and is information that characterizes the reference texture. The reason why such auxiliary data is an issue is that the scaling process of the embodiment includes deformations of dissimilar shapes that are not similar shapes, and therefore appropriate complementation processes are performed to eliminate the unnaturalness of the image after deformation.

[0158] Therefore, in the scaling process of this embodiment, following command L32, the FTEXECGRD command is written to generate auxiliary information (plane information) in the index space defined by command L32 (command process L33). The necessary preparations are completed with the commands up to this point, so next, the index space to be used as the texture is set with the SETTXINDEX command (command process L34), and the necessary information is set with the SETTXSAMP command, after which the scaling process is executed with the SETTXMODE command (command process L35).

[0159] As a result of the above, the image data after scaling is stored in the index space specified by command L34, so by executing the SPRITE command after activating the SETTXMODE command (command process L36), the image data after scaling is drawn in an appropriate rectangular section of the virtual drawing space.

[0160] The image filter circuit 75 has been described above, but the GDEC circuit 73 executes decoding processing by software processing corresponding to each compression algorithm for compressed data such as streaming video, still images, and other α values. In the case of this embodiment, streaming video is divided into S stream, IP stream, and IPB stream, and the frames constituting the streaming video are composed of an appropriate combination of I pictures, S pictures, P pictures, or B pictures.

[0161] An I (Intra coded) picture means an intra (intra-picture) coded picture, and refers to image data obtained by compressing an input picture as it is, independent of other pictures. On the other hand, an S picture is image data that performs predictive coding by referring to the I pictures immediately before and after, and has the advantage of having a higher compression rate than an I picture. The S stream video of this embodiment is a video combining these I pictures and S pictures, and by arranging the I pictures according to a certain period, it is possible to perform random access and reverse playback starting from the I picture, thereby realizing effective image presentation. It is also possible to have an S stream video that does not include an S picture, and an S stream video without an S picture is substantially the same as an I stream video.

[0162] Next, a P picture (Predictive coded) is image data that performs forward predictive coding to predict the current frame from a past frame in time, and predictive coding is performed from an I picture or P picture located in the past in time. On the other hand, a B picture (Bidirectional coded) is image data that performs bidirectional predictive coding to execute backward prediction to predict the current frame from a future frame in addition to forward prediction, and predictive coding is performed from an I picture or P picture located in the past and future in time.

[0163] Generally, inter-frame prediction techniques include forward prediction, which predicts the current frame from a past frame, backward prediction, which predicts the current frame from a future frame, and bidirectional prediction, which performs backward prediction in addition to forward prediction.B pictures perform bidirectional prediction, which allows for improved prediction accuracy.

[0164] Therefore, in this embodiment, in addition to S stream video that combines I pictures and S pictures, it is configured to be possible to play IP stream video and IPB stream video that appropriately combine I pictures, P pictures, and B pictures. Note that IP stream video is composed of a combination of I pictures and P pictures, and IPB stream video is composed of a combination of I pictures, P pictures, and S pictures.

[0165] As is clear from the above relationship, with S stream video containing S pictures and IPB stream video, the need for backward predictive coding makes it necessary to acquire and decode I pictures and P pictures that are to be played back later in time prior to acquiring S pictures and B pictures.

[0166] Therefore, this embodiment is configured so that one LOADTX command can specify multiple textures, that is, main frame CG data and sub-frame CG data. Here, main frame refers to CG frame data that should be played back at the current timing, and sub-frame refers to CG frame data that should be played back at a different timing.

[0167] For example, in an S picture, predictive coding is performed by referring to the nearest I picture (the previous or next). Therefore, in an S stream video that consists of successive I pictures and S pictures, the CG data for the S picture as the main frame and the I picture as the sub-frame may be obtained and decoded with a single LOADTX command.

[0168] In addition, since bidirectional predictive coding is performed for B pictures (bidirectional coded), it is necessary to secure CG data of past frames and CG data of future frames in a decoded state prior to the decoding process of B pictures. Therefore, in this embodiment, when playing IPB stream video, it is necessary to secure a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space having a capacity sufficient to store reference images, and is secured in an arbitrary area of ​​the VRAM 53 or the extended RAM 54, and is identified by a unique index number.

[0169] Fig. 11 is a diagram explaining the playback procedure of IPB streaming video, with the playback operation progressing from the top to the bottom of the page. Fig. 11 is divided horizontally into six sections, which show, from the left, (1) the LOADTX command on the display list DL, (2) pictures constituting the IPB streaming video, (3) main frame and subframe decoding processing, (4) reference image decoding processing, (5) reference buffer where the reference images are stored, and (6) index space (expansion space) where the decoded images displayed on the display screen are stored.

[0170] The downward arrow in the first column indicates the transition of the operation cycle of the general performance circuit 52 (GDEC circuit 73) which operates intermittently, and the downward arrow in the sixth column indicates the display order of the images displayed on the display device DS. In the following explanation, for convenience, a group of video frames played at timings T1 to T7 is called a GOP (Group Of Picture), but the GOP can be changed appropriately based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0171] First, the LOADTX command at timing T1 to play back an I-picture specifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the sub-frame by the embedded parameters of the command, as well as the index number of the expansion space in which the decoded data is to be stored.

[0172] Therefore, the I-picture (I1) acquired based on the instruction of the LOADTX command at timing T1 is decoded and stored in the first reference buffer that stores past frames together with the original expansion space. Also, a P-picture (P1) is acquired based on the instruction of the LOADTX command at timing T1, and the decoded data is stored as a reference image in the second reference buffer that stores future frames. Although not limited to this, the reference image is stored in a state compressed by a special method.

[0173] Next, the LOADTX command at timing T2 specifies only the B picture (B1) as the main frame. Then, as a bidirectional predictive operation, image data B1 of the current frame is reproduced based on the I picture (I1) of the first reference buffer, the P picture (P1) of the second reference buffer, and the B picture (B1) and stored in the storage space. The same is true for the LOADTX command at the following timing T3, which reproduces image data B2 of the current frame based on the I picture (I1) of the first reference buffer, the P picture (P1) of the second reference buffer, and the B picture (B2) and stored in the storage space.

[0174] Next, in the LOADTX command at timing T4 when the P picture is to be played back, the embedded parameters of the command instruct that the P picture (P1) as the main frame should be obtained from the second reference buffer, and the address of the P picture (P2) as the subframe is specified.

[0175] Therefore, at timing T4, the P picture (P1) in the second reference buffer, which has been compressed using a special method, is decompressed and saved in the decompression space, and the P picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. Also, a future P picture (P2) is obtained in response to an instruction from the LOADTX command at timing T4, and the decoded data is saved in the second reference buffer as a reference image for the future frame.

[0176] The operations at the subsequent times T5 and T6 are substantially the same as those at the times T2 and T3. That is, at the time T5, a B3 picture image based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B3) is rendered in the rendering space based on the bidirectional prediction. At the time T6, a B4 picture image based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B4) is rendered in the rendering space.

[0177] Next, the LOAD command at timing T7 instructs that the P picture (P2) as the main frame should be obtained from the second reference buffer. Also, the address of the I picture (I2) as the sub-frame is specified. Therefore, at timing T7, the P picture (P2) in the second reference buffer is decompressed and stored in the expansion space, and the I picture (I2) is obtained by the instruction of the LOADTX command at timing T7, and the decoded data is stored in the second reference buffer as a reference image for a future frame.

[0178] At the next timing T9, an instruction is given to obtain an I-picture (I2) as a main frame from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the expansion space, and the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. Note that the LOAD command at timing T9 specifies the address of the P-picture (P3), which is a subframe, so the P-picture (P3) is obtained and its decoded data is saved in the second reference buffer as a reference image for a future frame.

[0179] 12(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT in which 64-track processing blocks are arranged so as to be able to operate in parallel, a post-processing unit BK consisting of a master effect unit, a master volume unit, an output protection unit, and a serializer, and a mixer MX that transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0180] As shown in the figure, the pre-processing unit FT is provided with 64 decoders that receive audio compression data (compressed phrase data) from the external memory 55. Meanwhile, the post-processing unit BK is configured to be able to output audio signals SDOUTA-SDOUTD of four paths A / B / C / D as serial data together with a clock signal SBCLK and a control signal SLRCLK via a serializer. The serial data SDOUTA-SDOUTD of the four paths A / B / C / D includes right data R and left data L on each data line, and depending on whether the control signal SLRCLK is in an H level period or an L level period, it is specified whether the serial data SDOUTA at that timing is left data L or right data R.

[0181] Next, the internal operation of the preprocessing unit FT will be explained. The phrase data decompressed by the decoder has its volume appropriately adjusted in the primary volume, secondary volume, and panpot unit. Here, the primary volume and secondary volume are responsible for two-stage volume adjustment, and the panpot unit adjusts the volume ratio between the left and right speakers. The specific operation contents of the primary volume, secondary volume, and panpot unit are each specified by the voice command written in the voice command list VC.

[0182] Incidentally, phrase data is audio data that realizes one unit of audio performance, and includes one piece of background sound, sound effects, calls, and other audio performance units. One phrase data is output to eight paths from the panpot section of the pre-processing section FT. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing sections FT) are arranged to be able to operate in parallel, and up to 64 phrase data can be output to the mixer MX, and the audio data collected into eight paths, which are the left and right audio R / L of the four paths A / B / C / D, is transmitted to the post-processing section BK.

[0183] In the panpot section, the volume ratio of the left and right speakers can be adjusted, so for example, in the panpot section of the first track, the left and right volume ratio can be set to maximum:zero and output only to the first line of the mixer MX, while in the panpot section of the second track, the left and right volume ratio can be set to zero:maximum and output only to the second line of the mixer MX. Therefore, for example, the first phrase data, which is the left audio, is output only to the first line, and the second phrase data, which is the right audio, is output only to the second line, making it possible to play in stereo on the left and right speakers of system A.

[0184] Next, the internal operation of the post-processing unit BK will be described. The master effect executes audio filter processing, and the master volume determines the final volume. The specific operation contents are specified by the voice commands written in the voice command list VC. The master volume is used, for example, for a silent warning that instantly silences the volume effect, and the master effect is used, for example, for a sound change warning that drastically changes the sound quality.

[0185] Fig. 12(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands written in the voice command list VC. Here, a START command for instructing the start of playback of specific phrase data, a PAUSE command for instructing the stop of playback of specific phrase data, a RESUME command for instructing the restart of playback of specific phrase data, and a STOP command for instructing the end of playback of specific phrase data are shown as examples. Note that the voice command list VC is composed of one or more voice commands written therein, but must be terminated by a predetermined end command EOSC.

[0186] First, in the voice command list VC1, the start of reproduction of 64 types of phrase data is instructed by voice commands START1 to START64. Therefore, when the decoding process of the 64 types of compressed phrase data is completed, the reproduction operation of the 64 types of phrase data is started.

[0187] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of the phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC2 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0188] The voice command list VC can be output not only at the start and end of playback of phrase data, but also at any necessary timing in the operation period δ (= 1 / 30 seconds) of the overall performance circuit 52. That is, the display list DL is output every operation period δ of the overall performance circuit 52, but the voice command list VC is generally output irregularly.

[0189] Next, a description will be given of the rendering pipeline process executable in the rendering circuit 74. Fig. 13(a) illustrates a portion of the rendering circuit 74 that is related to the rendering pipeline process. The display list analyzer sequentially analyzes the instruction commands written in the display list DL, and transfers the instruction commands to an appropriate internal circuit according to their type. Note that in Fig. 13(a), the instruction commands are particularly written as rendering commands, and in the following description, the instruction commands may be referred to as rendering commands.

[0190] The internal circuits that receive the drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands written in the display list DL in the order in which they are written, and transfers the drawing commands one after another to the corresponding internal circuits (see Figure 13(a)).

[0191] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that transfers the configuration data of the display list DL in sequence, and generally, the operating speed of the internal circuitry of the drawing circuit 74 is much slower than the transfer speed of the configuration data of the display list DL.

[0192] Therefore, the internal circuit that receives the drawing command is provided with a standby queue that accumulates drawing commands before processing begins, and the display list analyzer puts the drawing command into the standby queue on the condition that there is space in the standby queue. In other words, the display list analyzer stalls (temporarily stops) the input operation until the standby queue becomes empty, so there is no risk of losing the drawing command. Note that the numbers shown for the standby queue are merely an example showing the number of stages in the queue.

[0193] As explained earlier, the instruction commands written in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture load commands such as the LOADTX command for reading image material (texture) from external ROM 55 and decoding (decompressing / expanding) it; (3) filter execution commands that specify the filter processing to be performed on the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space; and (5) pipeline commands related to drawing pipeline operations.

[0194] 13(a), an index table control command (1) is transferred to the control circuit of the index table IDXTBL, a texture load command (2) is transferred to the GDEC circuit 73, and a filter execution command (3) is transferred to the image filter circuit 75, and each is processed appropriately by the destination circuit. Specifically, the GDEC circuit 73 operates based on the transferred drawing command (texture load command), obtains the necessary texture, and loads the decompressed data into the decode space.

[0195] Furthermore, the index table IDXTBL is updated appropriately by the control circuit of the index table IDXTBL. The image filter circuit 75 performs a specified filter process on a specified reference texture and stores the filter process result in a specified index space (see FIG. 10). When a specified drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS functions to transmit and receive data at high speed between the VRAM 53 and the expansion RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74, and is a circuit separate from the data transfer circuit 70.

[0196] When using the data transfer circuit 70, the CPU circuit 51 must set the type of source medium and transfer start address, the type of destination medium and receiving start address, and transfer size in a specified performance control register RGij (data transfer register), but the high-speed transfer circuit TRNS has the simplicity of being able to function when necessary by an instruction command (transfer execution command) in the display list DL, and has the advantage of being able to transfer two-dimensional data at high speed in units of index space. Note that, in a control program that is constantly functioning, using the data transfer circuit 70 only when necessary is not easy in terms of program configuration.

[0197] As explained above, the rendering pipeline operation is performed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer which manages the anterior-posterior relationship of polygons and whether or not pixels are displayed, and is configured to execute an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO as required.

[0198] That is, the rendering pipeline process is executed from upstream to downstream, passing through all or some of the processes in the order of process IA → process TL (process VB) → process RS → process TX → process PS → process PX → process RO. Each process operates in parallel, but since the downstream process takes longer to complete the execution of rendering commands, the number of stages in the waiting queue that accumulates the rendering commands input to each process is configured so as not to be less than the number of stages in the waiting queue on the upstream side.

[0199] As shown in FIG. 13(a), the number of stages in the waiting queue is 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages, corresponding to process IA → process TL → process RS → process TX → process PS → process PX → process RO, and the number of stages at each process is the same as or greater than the number of stages in the upstream waiting queue.

[0200] The pipeline commands described above are setting commands that stipulate the operation of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the operating parameters required for the necessary internal circuits, such as the geometry engine.

[0201] In this embodiment, as shown in FIG. 13(b), the rendering pipeline is composed of process IA, process TL, process RS, process TX, process PS, process PX, and process RO. First, the input assembler process IA acquires a vertex stream of a three-dimensional 3D rendering object, which is usually defined in local coordinates, stores information required for subsequent processing, and outputs vertex data having specified vertex information.

[0202] In this process IA, in addition to the setting commands for process IA (pipeline commands), drawing commands such as DRAW and DRAWD are used. The DRAW command specifies the top address of the memory (external ROM 55 in this embodiment) in which a series of vertex streams are stored, and the number of vertices.

[0203] On the other hand, in the DRAWD command, a series of vertex streams are embedded in the command. The specific operation contents of the DRAW command and the DRAWD command are specified by the embedded information of each command and the setting command for the process IA. Note that in the vertex stream, a vertex color (RGBA color information) can be specified for each vertex, but if the vertex color is not specified, a default value is set as the vertex information in the input assembler process IA. Here, RBG means color information of R=Red, B=Blue, G=Green, and A is an alpha value α indicating opacity, and is used in the alpha blending process when compositing images by overlapping them.

[0204] In the subsequent geometry engine process TL, a matrix operation for transforming the vertex coordinates of the 3D drawing object and a lighting process for light sources are performed on the vertex data output from the input assembler process IA. In the coordinate transformation process, a view matrix operation for transforming local coordinates into view coordinates and a matrix operation for projective transformation (perspective projection) are performed.

[0205] Here, the view coordinate system has the viewpoint as its origin and the line of sight to infinity (0,0,-∞). In projective transformation, in order to realize a sense of perspective corresponding to the placement position of a 3D drawing object, the view coordinate system is transformed into the clip coordinate system by enlarging / reducing the shape of the 3D drawing object.

[0206] The specific content of the matrix operation is specified by the setting command (pipeline command) for the TL process, and the execution of a specified geometry matrix operation is instructed by the DRAW command or DRAWD command. Therefore, the process IA and the process TL can be executed together by one drawing command (DRAW / DRAWD). However, in either case, the execution result of the geometry matrix operation by the drawing command (DRAW / DRAWD) is saved in the vertex buffer VB.

[0207] The geometry engine process TL is not essential, and when a vertex stream defined by clip coordinates is obtained from the external ROM 55, the information passes through the input assembler process IA and is stored directly in the vertex buffer VB. The input assembler process IA and the geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to store a maximum of 256 vertices.

[0208] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB, and pixel data of a 3D drawing object is generated after removing polygons that do not need to be drawn by conversion from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc. In other words, a three-dimensional 3D image object is determined to be placed at a predetermined position and with a predetermined attitude in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0209] To generate primitives, a triangle drawing method such as a triangle list, triangle strip, or triangle fan, and a line drawing method such as a line list, line strip, or line fan can be appropriately selected and used.

[0210] In addition, in the rasterizer process RS, in addition to the setting commands (pipeline commands) for the RS process that specifically define the processing contents, drawing commands DRAW command, DRAWD command, DRAWI command, and SPRITE command are used as appropriate.

[0211] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB, whereas the DRAW command generates and draws primitives based on a vertex stream obtained from the external ROM 55, and the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0212] Therefore, the rasterizer process RS can be executed without going through the geometry engine process TL. For example, in the case of a two-dimensional 2D drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color for each vertex.

[0213] Next, in the texture sampler process TX, the index space to be used as the texture is specified, and the texture coordinates for each pixel are specified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are appropriately calculated.

[0214] In these steps TX and PS, and in the following step PX, in addition to the setting commands (pipeline commands) in each step, the drawing commands DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate. In the DRAW, DRAWD, and DRAWI commands, the texture is pasted into the area surrounded by specified vertices, and in the SPRITE command, the texture is pasted into a specified rectangular area.

[0215] Then, in the subsequent pixel drawing process PX, the drawing color and background color are mixed, and tone mapping and inverse tone mapping for adjusting contrast are performed. In this PX process, pixel data having predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the pixel drawing position is input for each pixel from the frame buffer FB.

[0216] The final rendering process RO refers to the depth / stencil buffer etc., performs a pixel test to determine whether or not to display the pixel based on the pixel's depth information and stencil information, and writes the completed drawing object to the frame buffer FB after processing such as alpha blending for overlapping multiple drawing objects. Writing to the frame buffer FB is nothing more than drawing in the virtual drawing space shown in Figure 6, and normally the SPRITE command is used.

[0217] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the rendering process RO can use the CLEAR command, which fills the frame buffer FB with a single color, and the CLEARZ command, which fills the depth-stencil buffer with a single color. The CLEAR command is used to clear the frame buffer FB prior to the start of drawing operations, and the CLEARZ command is used when depth information or stencil information is not required.

[0218] In this way, in the present invention, all or some of the series of drawing pipeline steps function to write two-dimensional or three-dimensional drawing objects one after another into the frame buffer FB, ultimately completing one frame's worth of image data for the display device.

[0219] Figure 14 is a process diagram showing various rendering modes that utilize all or part of the rendering pipeline process. First, the rendering mode in Figure 14(a) is an operation mode that uses the above-mentioned CLEAR command and CLEARZ command, and only the render process RO functions.

[0220] 14(b), the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO function. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the vertices in the window coordinate system, but this offset value is related to the rectangular area to which the SPRITE command is pasted.

[0221] The actual operation is as follows: the SETTXINDEX command sets the destination index space, the LOADTX command gets a specified texture and expands it into the above index space, and the SPRITE command secures this expanded texture in a specified position. The expanded texture information is then referenced and finally written to the frame buffer FB. In principle, video playback and playback of still images of simple shapes are achieved in this sprite drawing mode.

[0222] The drawing mode shown in Fig. 14(c) is an example of operation for triangle drawing and line drawing using all the processes of the drawing pipeline. Note that the only difference between triangle drawing and line drawing is the method of generating primitives. In either case, primitives are identified and drawn based on the vertex stream of the 3D drawing object supplied to the input assembler process IA.

[0223] 14(d) shows a drawing operation using the DRAW command, DRAWD command, etc., in which pixel data for a drawing object is generated in the rasterizer process RS without performing a coordinate transformation process. This operation is typically used when a two-dimensional 2D drawing object, the contour of which can be identified by a vertex stream, is displayed on a display screen.

[0224] Figures 14(e) and (f) show operation modes when vertex data is stored in the vertex buffer VB, and are divided into (e) where coordinate transformation processing is performed and (f) where coordinate transformation processing is not performed. These operations are executed by the DRAW command or the DRAWD command. Figure 14(g) shows an operation mode that uses the vertex data stored in the vertex buffer VB, and is executed by the DRAWI command.

[0225] As described above, the rendering pipeline of this embodiment can be used in various ways. For example, playback of 2D still images and streaming video (S stream, IPB stream, IP stream) requires simple sprite drawing, so the playback operation is realized in the operating mode of Figure 14(b) as described above.

[0226] As described above, the display analyzer judges the drawing commands in the display list DL and transfers them to the processing blocks of the pipeline steps corresponding to the drawing commands. The transferred drawing commands are then first put into the waiting queues of the pipeline steps, and the processing corresponding to the drawing commands is executed in the order of their input.

[0227] However, since the operation of the data transfer circuit 70, which transfers the display list DL, is much faster than the progress of this rendering pipeline, for example, if you want to display multiple 3D rendering objects on the screen and also other 2D drawing objects on the screen, there will be a long wait for the execution of the SPRITE command in the rendering process RO.

[0228] That is to say, since it takes a certain amount of time to process a coordinate transformation matrix for a 3D drawing object, for example, a large number of SPRITE commands will accumulate in the standby queue of an RO process, etc. However, in this embodiment, as explained above, the input of drawing commands is put on hold until the standby queue is empty (stall state), and moreover the number of stages in the standby queue of the downstream process is the same as or greater than the number of stages in the standby queue of the upstream process, so that the commands written in the display list DL can be operated smoothly in the order in which they are written.

[0229] Note that drawing commands transferred from the waiting queue are also put on hold (stalled) until the necessary start conditions are met, so that inconsistent drawing operations such as rewriting the index space do not occur.

[0230] Having described the circuit configuration above, we now turn to a description of the control operation by the CPU circuit 51. As described above, when the power is turned on, prior to the start of the control operation, a reset period occurs during which the system reset signal SYS is maintained at the L level for a predetermined period of time.

[0231] During this reset period, first, one or two oscillator circuits that control the operation of the general performance circuit 52 and the built-in CPU circuit 51 start oscillating, and wait for the oscillation frequency of each system clock to stabilize. Next, the internal circuit of the composite chip 50 is initialized in synchronization with each system clock, and a predetermined default value is set in the performance control register RGij and the operation control register REG. Hereinafter, this operation will be referred to as a hardware reset in this specification to distinguish it from a software reset, which will be described later.

[0232] When this hardware reset period ends, the performance control CPU 57 of the built-in CPU circuit 51 executes the boot program stored in the external ROM 55 and transfers the control program and control data from the external ROM 55 to the extended RAM 54. Then, the performance control CPU 57 continues the control operation based on the control program transferred to the extended RAM 54.

[0233] The control operation executed by the performance control CPU 57 is as shown in Fig. 15, and includes a main process (a) consisting of an initial process and the subsequent regular process, a timer interrupt process (b) that is started every 1 ms, a VBLANK interrupt process (c) that is started upon receiving a VBLANK signal output from the general performance circuit 52 at the start timing of the vertical blanking period of the display device DS, and a reception interrupt process (not shown) for receiving a control command CMD. The VBLANK signal is generated every 1 / 60 seconds.

[0234] As shown in Fig. 15(b), in the timer interrupt process, a sensor signal is acquired to grasp the motor position, etc. (ST20), and when necessary, a lamp performance or a motor performance is started or progressed (ST21). In this embodiment, the lamp performance is realized by the operation of the performance control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor performance is realized by the operation of the performance control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. Also, in the VBLANK interrupt process that is started upon receiving the VBLANK signal, as shown in Fig. 15(c), the interrupt counter VCNT is incremented and the process ends (ST25).

[0235] First, the main process will be described in the case where the preloader 72 is not utilized. As shown in Fig. 15(a), first, an initial setting process (ST1) is executed, and appropriate setting values ​​are set in the performance control register RGij of the overall performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0236] The setting process for the performance control register RGij includes the process of reserving an appropriate virtual working area (AAC area, page area, arbitrary area) in the VRAM 53 and the extended RAM 54 (see Fig. 6(a) and Fig. 6(b)), and the process of reserving an index space essential for game control operations, such as the frame buffer FB. As explained above, the frame buffer FB is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0237] The start address of the shared area (used as the AAC area in this embodiment) secured in the VRAM 53 is set in 4k byte units (the lower 15 bits are zero), and the area size is secured as an integer multiple of 4k bytes. The page area secured in the expansion RAM 54 is set in 32k byte units (the lower 18 bits are zero), and the area size is secured as an integer multiple of 32k bytes.

[0238] Moreover, the set value in the operation control register REG includes operation parameters for the watchdog timer WDT 58, and these operation parameters include an operation start instruction and a counter value. The WDT 58 in the embodiment is configured to count down an initial value (counter value), and by reloading the counter value before the count value reaches an underflow where it becomes zero, activation of the WDT 58 is prevented.

[0239] On the other hand, when the count value underflows, a WDT reset request is generated, and the WDT 58 starts, resulting in a software reset state. Then, as a standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG except for certain registers are returned to their initial values ​​(default values), and the WDT 58 stops operating. Note that the only register whose value is exceptionally maintained is the register indicating the operating state of the WDT.

[0240] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether to initialize the internal circuitry, and (2) whether to initialize the system clock circuitry even if the internal circuitry is initialized, can be arbitrarily selected by setting corresponding values ​​in a specified operation control register REG during the initial setting process after a hardware reset. Therefore, in this embodiment, based on the set value in the specified operation control register REG, the internal circuitry is not initialized during a software reset, and the game operation is resumed from the process of step ST1.

[0241] Thus, in this embodiment, unlike the configurations of Prior Art Documents 1 and 2, even if the WDT 58 underflows, the hardware reset state is not entered, so there is an advantage that the game operation can be quickly resumed. Note that after the software reset, the WDT stops operating, so there is no risk of the software reset operation being repeatedly started.

[0242] When the initial setting process (ST1) including the above processes is completed, the intermittently executed steady-state process (ST2 to ST10) is started. As shown as step ST2 in Fig. 15(a), the steady-state process is started when the interrupt counter VCNT becomes VCNT>=2, so that the operation period (operation cycle) δ of the steady-state process is 1 / 30 seconds corresponding to the operation period (1 / 60 seconds) of the VBLANK signal.

[0243] Then, in the process of step ST3, after resetting the interrupt counter VCNT, it is judged whether or not the operation start condition for starting the normal operation is satisfied. Specifically, a predetermined performance control register RGij indicating the operation state of the drawing circuit 74 is accessed for READ, and it is judged whether or not the drawing circuit 74 has finished the drawing operation based on the display list DL of the previous operation cycle at this timing. Also, in the drawing operation of the previous operation cycle, it is judged whether or not the memory access period of the drawing circuit 74 has exceeded the timeout time set in the time setting register TO based on the ON / OFF state of a predetermined abnormality flag.

[0244] If the abnormality flag is ON because memory access by the drawing circuit 74 has taken an abnormally long time, even if the drawing circuit 74 has finished drawing operation, it is determined that the operation start condition is not satisfied, and the process proceeds to the performance command analysis process of step ST9.

[0245] The processing of steps ST4 to ST8 is skipped in order to avoid an unreasonable screen display, since there is a possibility that normal image data, including garbled bits in the instruction command, is not being generated since the memory access of the drawing circuit 74 is taking an abnormally long time.

[0246] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21, and if a control command CMD has been received, the control command CMD is analyzed and necessary processing is executed. Here, the necessary processing includes a process for preparing to start a new variable performance based on a control command CMD that instructs the start of a variable performance, and a process for starting an error notification based on a control command CMD that indicates the occurrence of an error.

[0247] Next, the counter value is reloaded into the watchdog timer WDT 58 to prevent the watchdog timer 58 from starting (ST10). As explained above, even in the event of an abnormality that would cause the watchdog timer 58 to start, the composite chip 50 of this embodiment goes into a software reset state that is different from a hardware reset. This completes the operation of the current operation cycle, so the process moves to step ST2 to wait for the next VBLANK interrupt.

[0248] Although the above describes the case where the operation start conditions are not satisfied, normally, after the judgment process of step ST3, the display circuit 71 specifies the image data to be read based on the set value of the specified display register RGij, and starts the operation of the display circuit (ST4). As described above, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the set value of the specified display register RGij so that they are switched in a toggle manner.

[0249] Specifically, the index number N1 / N2 of the first buffer or the second buffer specified as the "write area" by the display list DL of the previous operation cycle is set. By executing this step ST4, the "write area" of the previous operation cycle changes to the "read area" of the current operation cycle, so that the display circuit 71 outputs the image data completed by the drawing circuit 74 in the immediately previous operation cycle to the display device DS. That is, the process of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0250] When the processing of step ST4 having the above significance is completed, the performance control CPU 57 then completes a display list DL that specifies image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see FIG. 8).

[0251] In principle, the display list DL is created every time with its contents changed for each operation cycle, but the leading area of ​​the display list DL contains a command that specifies the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double-buffer structure with index numbers N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternates between the frame buffer FB with index number N1 and the frame buffer FB with index number N2 to rotate the "write area."

[0252] The performance control CPU 57 issues the display list DL thus completed to the general performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN that centrally manages the image performance, audio performance, lamp performance, and motor performance (ST7), and if it is a necessary performance timing, issues a voice command list VC to the voice processing unit SND to start or progress the audio performance (ST8).

[0253] In addition, when the start time of the motor performance or lamp performance managed by the performance scenario EN is reached, the timer interrupt process (FIG. 15(b)) executes the motor performance or lamp performance based on the corresponding motor drive data or lamp drive data. The process of steps ST9 to ST10 following step ST8 is as described above.

[0254] Fig. 16(a) and Fig. 16(b) are flow charts showing the specific contents of the display list DL issuing process (ST6), and Fig. 16(c) is a schematic diagram showing the operation contents of the DL issuing process (ST6). As explained with reference to Fig. 9, the display list DL issuing process includes a case where the CPU register port PORT is accessed by write in 32-bit units (Fig. 9(a)), and a case where the CPU register port PORT is not accessed (Fig. 9(b)). The operation contents of each case are shown in Fig. 16.

[0255] First, referring to FIG. 16(a), the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and sets the total size of the transfer data in a specified transfer register RGij (ST30).

[0256] Here, the display list DL is issued with a termination command EODL, the contents of which differ for each operation cycle. In this embodiment, the instruction command used for the display list DL, including the termination command EODL, is one word or multiple words (=N*32 bits), so no adjustment process for the amount of data is required. In other words, the total size of the transfer data set in the transfer register RGij is an arbitrary value that is an integer multiple of 32 bits.

[0257] Next, the performance control CPU 57 sets the number of writes corresponding to the total size of the transfer data in the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the instruction to start the operation of the drawing circuit 74 and the data transfer circuit 70 is realized by a setting process to a predetermined drawing register RGij and a transfer register RGij, respectively.

[0258] Next, the performance control CPU 57 writes the configuration data of the display list DL in 32-bit units to the CPU register port PORT while checking that the 130-stage CPU data FIFO circuit is not full (ST35). Then, it continues the write operation while decrementing the management counter CN (ST36, ST37).

[0259] As explained above, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, in principle, when 1024-bit data is accumulated in the CPU data FIFO circuit, the accumulated data is transferred to the data relay unit CH2, but when the set value (total size of the transfer data) of the transfer register RGij is reached, the accumulated data in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0260] The above process ends the DL issuing process (ST6) via the CPU register port PORT, but next, Fig. 16 (b) shows an example in which the data transfer circuit 70 reads out a display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and sets the total size of the transfer data and the top address of the list buffer BUF in a specified transfer register RGij (ST41).

[0261] As explained above, since the top address of the list buffer BUF set in the internal RAM 59 must be set in 8-bit units, the lowest 7 bits of the start address of the DL buffer BUF are zero. This address condition applies not only to the top address of the list buffer BUF that stores the display list DL, but also to the top address of the list buffer BUF that stores the voice command list VC.

[0262] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). These operation instructions are also realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation when the transfer of a predetermined size of data is completed. Therefore, after the processing of step ST43, the performance control CPU 57 can immediately move on to another process following the display list issuing process (ST6).

[0263] In this case as well, when the amount of transfer data reaches the set value (total size of transfer data) in the transfer register RGij, the data stored in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0264] The above describes the process of issuing a display list DL based on Figures 16(a) and 16(b). However, when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as that shown in Figures 16(a) and 16(b) (see Figures 9(f) and 9(g)).

[0265] That is, the voice command list VC in which the voice commands are listed is terminated with a predetermined end command EOSC before being issued. Note that the voice command, including the end command EOSC, is one word or multiple words (=N*32 bits), so no adjustment processing of the data amount is required.

[0266] Although the above describes the case where the preloader 72 is not used, the main processing when the preloader 72 is used is as shown in Fig. 17(a). The processing content shown in Fig. 17(a) is similar to the processing content in Fig. 15(a).

[0267] However, as shown in FIG. 17(a), (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 (ST60) instead of the drawing circuit 74, and (b) this display list DL is rewritten by the preloader 72 to become a rewrite list DL', but the rewrite list DL' rewritten in the previous operation cycle is acquired by the drawing circuit 74 (ST41) prior to the processing of step ST5, which is different from the processing of FIG. 15(a).

[0268] 17(a), the issue process (ST60) for issuing the display list DL to the preloader 72 is substantially the same as that of FIG. 16(a) and (b), except that the issue destination is changed to the preloader 72. The outline of the operation is as shown in FIG. 9(d) and FIG. 9(e), and in response to the change in the issue destination to the preloader 72, the data relay unit CH2 is changed to the data relay unit CH3 (data transfer channel CH3), but otherwise the operation is the same as that of FIG. 16(a) and FIG. 16(b), and the corresponding operations are shown in FIG. 17(b) and FIG. 17(c).

[0269] On the other hand, the process of acquiring the rewrite list DL' by the drawing circuit 74 (ST41 in FIG. 17) is shown in FIG. 17(d). As shown in FIG. 9(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see FIG. 6(a)).

[0270] In the process of step ST41 in Fig. 17, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Fig. 17(d)). Next, the total size of the rewrite list DL', which is the transfer data, and the top address of the preload buffer in which the rewrite list DL' is stored are set in a predetermined transfer register RGij (ST51).

[0271] Since the starting address in VRAM 53 needs to be set in 32-bit units, the starting address of the preload buffer that stores the rewrite list DL' needs to have the lowest 31 bits set to zero; in this embodiment, the preload buffer is allocated at a position that satisfies this condition.

[0272] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST52) and starts the operation of the data transfer circuit 70 (ST53). These operation instructions are realized by setting the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation when the data transfer is completed.

[0273] Although the first embodiment of the present invention has been described above, the specific description does not particularly limit the present invention and can be changed as appropriate. For example, in the above embodiment, a configuration was described in which, when the memory access period of the drawing circuit 74 or the decoding process time is prolonged, the abnormality is detected by flag polling processing, but it goes without saying that abnormal interrupt processing may also be utilized.

[0274] FIG. 15(d) shows an example of a configuration for such a case. When a drawing abnormality interrupt occurs, only the drawing circuit 74 is reset individually (ST23), and the operating parameters required for the operation of the drawing circuit 74 are reconfigured. The stack area is then appropriately released (ST24), and the process proceeds to step ST9.

[0275] [Configuration Example of First Embodiment] (Configuration example M1) Here, the gaming machine GM as the first embodiment described above can be expressed as having a configuration as the following configuration example M1. That is, the gaming machine GM as the configuration example M1 is an image control means for issuing a display list that specifies the display contents to be displayed on a display device; and an image generating means configured to generate two-dimensional or three-dimensional still image data and / or video image data in a predetermined frame buffer based on the display list, the image generating means is configured to be capable of executing all or a part of a plurality of steps including an acquisition step capable of acquiring vertex data corresponding to an image contour, a primitive step of generating an appropriate primitive based on the vertex data, and an image generating step of generating image data required for the frame buffer; the display list issued at a predetermined timing specifies basic data to be decoded and an expansion area into which the basic data is to be decoded, and then describes one or more first commands for instructing a decoding process, and one or more second commands for appropriately specifying a drawing area of ​​the frame buffer and instructing drawing of the texture in the drawing area, The image generating means is configured to operate based on the display list and generate predetermined still image data in the frame buffer without going through the acquisition step or the primitive step.

[0276] According to the gaming machine GM as the above configuration example M1, even in the case of advanced two-dimensional or three-dimensional image presentation, it is possible to execute smooth and appropriate image control operations.

[0277] (Configuration example M2) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M2. That is, the gaming machine GM as the configuration example M2 is an image control means for issuing a display list that specifies the display contents to be displayed on a display device; and an image generating means configured to generate two-dimensional or three-dimensional still image data and / or video image data in a predetermined frame buffer based on the display list, the image generating means is configured to be capable of executing all or a part of a plurality of steps including an acquisition step capable of acquiring vertex data corresponding to an image contour, a primitive step of generating an appropriate primitive based on the vertex data, and an image generating step of generating image data required for the frame buffer; the display list issued at a predetermined timing specifies basic data to be decoded and an expansion area into which the basic data is to be decoded, and then describes one or more first commands for instructing a decoding process, and one or more second commands for appropriately specifying a drawing area of ​​the frame buffer and instructing drawing of the texture in the drawing area, The image generating means is configured to operate based on the display list and to be able to generate predetermined moving image data in the frame buffer without going through the acquisition step or the primitive step.

[0278] According to the gaming machine GM as the above configuration example M2, even in the case of advanced two-dimensional or three-dimensional image presentation, smooth and appropriate image control operation can be executed.

[0279] (Configuration example M3) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M3. That is, the gaming machine GM as the configuration example M3 is, A gaming machine comprising: an image control means for issuing a display list that specifies display contents to be displayed on a screen of a display device; and an image generating means for generating image data for realizing the display contents based on the display list and basic data of an appropriate storage means, The display list issued at a predetermined timing includes one or more first commands for specifying the basic data and a development area of ​​the basic data, and for instructing execution of a read process and a decode process of the basic data; one or more second commands specifying the decoded data of the expansion area, a filter process to be performed on the decoded data, and parameters defining the content of the filter process, and instructing the execution of the filter process; Image data based on the first command and the second command of the display list is configured to be displayable on the display device.

[0280] According to the gaming machine GM serving as the above-mentioned configuration example M3, even in the case of a sophisticated image presentation, a smooth and appropriate image control operation can be executed by the first command and the second command written in the display list.

[0281] (Configuration example M4) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M4. That is, the gaming machine GM as the configuration example M4 is an image control means for issuing a display list that specifies display contents to be displayed on a screen of a display device; and an image generating means having a drawing circuit for generating image data for realizing the display contents based on the display list and basic data of an appropriate storage means, The image control means has a setting means for setting an appropriate abnormality determination time in a predetermined register of the image generating means, The image generating means includes: a monitoring means for monitoring a memory access time interval by the drawing circuit and / or a decoding execution time for decoding the basic data; and a determination means for determining that an abnormality has occurred when the memory access time interval or the decode execution time exceeds the abnormality determination time.

[0282] According to the gaming machine GM as the above configuration example M4, since an abnormal situation can be properly grasped, even in the case of a highly advanced image presentation, a smooth and appropriate image control operation can be executed.

[0283] (Example configuration M5) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M5. That is, the gaming machine GM as the configuration example M5 is, an image control means for issuing a display list that specifies display contents to be displayed on a screen of a display device; and an image generating means for generating image data for realizing the display contents based on the display list and basic data that has been appropriately compressed and stored. the display list includes a decode command for instructing decoding of the basic data with respect to video playback, The predetermined decode command is configured to be able to specify the first and second basic data with one command.

[0284] According to the gaming machine GM as the above configuration example M5, even in the case of complex and highly advanced image presentation, it is possible to execute smooth and appropriate image control operations.

[0285] (Configuration example M6) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M6. That is, the gaming machine GM as the configuration example M6 is A CPU means for issuing first information specifying an image presentation by the display device and second information specifying an audio presentation; VDP means for generating image data for realizing the image presentation based on the first information issued by the CPU means and basic image data in an appropriate storage means; a sound means for realizing the sound performance based on the second information issued by the CPU means and basic sound data in an appropriate storage means; A gaming machine comprising a single circuit element and a monitoring means for constantly monitoring the operation of all or a part of the CPU means, the VDP means, and the sound means, When the monitoring means detects an abnormal state, an arbitrarily set reset operation different from the hardware reset operation at power-on can be executed.

[0286] According to the gaming machine GM serving as the above-mentioned configuration example M6, the abnormal reset operation can be optimized, so that even with advanced image presentation, a smooth and appropriate image control operation can be executed.

[0287] (Configuration example M7) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M7. That is, the gaming machine GM as the configuration example M7 is A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The first information and / or the second information is configured to be stored in an address area of ​​an internal RAM or an external RAM, starting from a start address where a predetermined number of bits or less are zero.

[0288] According to the gaming machine GM having the above configuration example M7, the control burden in data transfer on the CPU means is reduced and the setting of the start address of the transfer process is simplified, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0289] (Configuration example M8) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M8. That is, the gaming machine GM as the configuration example M8 is A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A game machine including a transfer means for transferring the first information and the second information to a first circuit and a second circuit in a unit of a predetermined transfer size, The first information and / or the second information is composed of a list of instruction commands that are an integer multiple N (N≧1) of a reference size, and the transfer size is an integer multiple M (M≧1) of the reference size, so that the number of instruction commands in the first information and / or the second information can be any number.

[0290] According to the gaming machine GM as the above configuration example M8, the freedom of configuration of the instruction commands for the first information and / or the second information is increased, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0291] (Configuration example M9) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M9. That is, the gaming machine GM as the configuration example M9 is A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The CPU means includes: The data constituting the first information and the second information is written to a predetermined write port in units of a predetermined write size.

[0292] According to the gaming machine GM as the above configuration example M9, the transfer means can be made to function based on the management of the CPU means, so that even with advanced image presentation, smooth and appropriate image control operations can be executed.

[0293] (Configuration example M10) Further, the gaming machine GM according to the present embodiment can be expressed as having a configuration as the following configuration example M10. That is, the gaming machine GM as the configuration example M10 is A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, The transmission path for the first information and / or the transmission path for the second information is configured so that one transmission circuit can be selected from a plurality of options.

[0294] According to the gaming machine GM serving as the above configuration example M10, since the optimal transmission path can be selected, even in the case of a sophisticated image presentation, a smooth and appropriate image control operation can be executed.

[0295] [Modification of the first embodiment] The initialization of the CPU circuit 51 may be configured to follow the procedure below. The frequency of the system clock is set, and the method of loading a boot program for performing initial settings of the CPU circuit 51 is also set. The frequency of the system clock is set by referencing predefined terminal information. The method of loading the boot program is also set by referencing predefined terminal information, and a memory device for reading the boot program is selected according to the terminal information. Here, the terminal information is predefined so that the performance control ROM (external ROM 55) is set as the memory device. Once these processes are completed, a hardware reset is performed.

[0296] Next, the CPU circuit 51 executes standby processing until the initialization of the overall performance circuit 52 is completed. The overall performance circuit 52 executes a hardware reset by referring to the predetermined terminal information and confirming that the information indicates initialization for a certain period of time. This initializes each circuit unit included in the overall performance circuit 52. Here, the overall performance circuit 52 may be configured to refer to the predetermined terminal information, or the CPU circuit 51 may be configured to initialize the overall performance circuit 52 by referring to the predetermined terminal information. Then, when the initialization of the overall performance circuit 52 is completed and a stable clock is supplied from the system clock, the reset state of each circuit unit of the overall performance circuit 52 is released and the function of each circuit unit becomes usable. Until this series of processing is completed, the CPU circuit 51 executes standby processing. At this time, the standby processing of the CPU circuit 51 may be configured to wait for a predetermined time set in advance, or may be configured to end the standby processing by referring to or confirming at least one of the following, such as referring to the predetermined terminal information, checking a predetermined built-in register, or confirming that the supply of the system clock has stabilized. Also, if the standby process is not completed even after a predetermined time has elapsed (initialization of the overall performance circuit 52 is not completed for some reason), the standby process may be configured to continue until initialization of the overall performance circuit 52 is completed, or the hardware reset may be executed again after a predetermined time has elapsed or by a watchdog timer.

[0297] When the initialization of the overall performance circuit 52 is completed, the number of CPU cores in operation is set. In the initial state immediately after executing a hardware reset, only one of the four CPU cores is in operation, so the number of CPU cores to be used is changed and a process is executed to make the stopped cores in an active state. When the processing efficiency of the CPU circuit 51 is emphasized, it is preferable to operate all CPU cores, but when the content of the performance control does not require a high processing load, it may be set to use only some of the CPU cores.

[0298] Next, the system executes processing to change the settings of the recovery method when each circuit part goes into an abnormal state from the initial state as necessary. For example, the system executes processing to change the method of determining an abnormal state of the system clock and the recovery method, and the reset operation when a timeout occurs in the watchdog timer, to the desired contents.

[0299] Next, power saving function settings are made for each circuit section. This makes it possible to turn off the system clock and power supplied to some circuit sections. In other words, by turning off the clock and power for unused circuits and circuits in standby mode (such as the LED controller and motor controller inside the composite chip, not shown), it becomes possible to reduce power consumption.

[0300] Next, the display output clock and the sound clock are initialized. The frequencies and supply sources of the display output clock and the sound clock are set in the built-in register, and then the reset process is executed. As a result, the values ​​set in the built-in register are reflected as parameters for clock control during the initialization. The CPU circuit 51 is configured to wait for the completion of the initialization of the display output clock and the sound clock, and then use the display circuit 71 and the sound processing unit SND. At this time, the CPU circuit 51 may be configured to wait for a predetermined time set in advance until the initialization of the display output clock and the sound clock is completed, or may be configured to end the standby process by referring to or confirming at least one of predetermined terminal information, checking a predetermined built-in register, or confirming that the supply of the system clock has stabilized. In addition, if the standby process is not completed even after the predetermined time has elapsed (initialization of the display output clock and the sound clock is not completed for some reason), the standby process may be continued until the initialization of the display output clock and the sound clock is completed, or the hardware reset may be executed again at the timing when the predetermined time has elapsed or by a watchdog timer. Here, the configuration may be such that the sound clock is initialized after the display output clock has been initialized, or the display output clock and the sound clock are initialized in parallel.

[0301] The initialization of the drawing circuit 74 may be configured as follows. The drawing circuit 74 is initialized by setting a predetermined value in a predetermined register. During initialization, it is possible to confirm that the drawing circuit 74 is being initialized by the status register being set to a specific value. The initialization of the drawing circuit 74 at this time is performed as follows. First, when a predetermined value is set in a predetermined register, a clear process is performed so that the internal parameters set in the display list DL are set to their initial values. Next, the drawing circuit 74 is controlled to the initial state, and the GDEC circuit 73 and the image filter circuit 75 are initialized in sequence. After that, the index table INDXTBL is initialized, and then the index spaces of the page area and the AAC area are all opened. After that, the information of the arbitrary area and the page area is cleared.

[0302] The internal status registers for the drawing circuit 74 may be configured to have a first status register capable of checking the overall status of the drawing circuit 74 and a second status register capable of checking the progress of the analysis of the display list DL. Similarly, the input assembler process IA, the geometry engine process TL, the rasterizer process RS, the texture sampler process TX, the texture process PS, the pixel drawing process PX, the render process RO, the stencil buffer, the vertex buffer, the frame buffer cache, the GDEC circuit 73, the image filter circuit, and the like in the drawing circuit 74 may each be configured to have a register for checking the progress of the drawing process. The CPU circuit 51 can check the progress of the drawing process for each functional block by checking the contents of these internal status registers. Of course, it is desirable to configure the internal status registers to have no change even if a drawing command unrelated to a functional block is executed, and the contents of the internal status registers to change only for the functional blocks that are actually used.

[0303] Regarding the drawing commands described in the display list DL, the following configuration may be adopted so that drawing results can be obtained in the order described in the display list DL. For example, in a case where image data drawn by a drawing command described earlier in the display list DL is used as texture by a drawing command described later, a configuration may be adopted in which a standby process is executed to wait for command analysis process and / or command execution process of the later drawing command until the drawing process of the image data by the earlier drawing command is completed.

[0304] Also, when a drawing command that does not exist in the display list DL is described due to a malfunction or a glitch, the display list DL itself may be discarded, or only the non-existent drawing command may be treated as an error and discarded. At that time, abnormality information indicating that an abnormal drawing command is included may be confirmed in a predetermined register. In such a case, an error interrupt process that occurs only when an abnormality occurs may be executed. In addition, when an abnormal drawing command is included, when the command size of the drawing command is abnormal, or when the display list DL itself is abnormal, an abnormality information indicating that the drawing circuit 74 is abnormal may be confirmed in a predetermined register. In such a case, an error interrupt process that occurs only when an abnormality occurs may be executed.

[0305] In addition, when it is detected that the display list DL contains an abnormal command as described above, or when there are no read and / or write requests to the VRAM 53 for a certain period of time, the drawing circuit 74 may be configured to be initialized by writing a specified value to a specified register.

[0306] Regarding the image filter circuit 75, the filtering process for the texture by the image filter circuit 75 and the processing by the drawing circuit 74 may be configured to be executed independently and in parallel. When the drawing circuit 74 receives a display, analysis of the display list DL is executed, and an execution request is sent from the drawing circuit 74 to the image filter circuit 75. In accordance with the execution request, the image filter circuit 75 is configured to read image data to be the texture from the VRAM 53 or CGROM (external ROM 55), and write the processing result to the VRAM 53 or the expansion RAM 54. These processes by the image filter are executed independently and in parallel with the analysis process of the display list DL by the drawing circuit 74 and other drawing processes.

[0307] A FIFO circuit may be provided in the image filter circuit 75. This allows the contents of drawing commands related to the filter processing for the image filter circuit 75 to be queued in the FIFO circuit together with the execution parameters. It is also preferable that the queued execution parameters are not affected by the filter processing by drawing commands that are already being executed. It is also preferable that the FIFO circuit has multiple stages (e.g., four stages), and it is also preferable that drawing commands beyond this stage are stalled in the display list analyzer and command analysis is not performed until there is space in the FIFO circuit in the image filter circuit 75. It is also preferable that the free space in the FIFO circuit in the image filter circuit 75 can be confirmed by a specified register. It is also preferable that the CPU circuit 51, the drawing circuit 74, or the display list analyzer is configured to check the free space in the FIFO circuit in the image filter circuit 75 by referring to a specified register, and if there is space, to analyze the drawing command and / or transmit the contents of the drawing command together with the execution parameters to the free space in the FIFO circuit in the image filter circuit 75.

[0308] When an abnormality occurs in the image filter circuit 75, the filter process currently being executed may be interrupted. When the texture being referenced by the image filter circuit 75 is stored in an AAC area, the AAC area may be released. The cause of the abnormality may be recorded in a predetermined register. After that, the image filter circuit 75 notifies the drawing circuit 74 of the abnormal end, and desirably operates to continue executing the next filter process.

[0309] <2. Second embodiment> Next, a second embodiment will be described. The second embodiment proposes various configurations relating to the insulated transmission of electrical signals in a communication board. In the following description, parts that are similar to parts that have already been described will be given the same reference numerals and description thereof will be omitted.

[0310] FIG. 18 is a block diagram for explaining a schematic circuit configuration of the gaming machine GMA as the second embodiment. As shown in the figure, the gaming machine GMA as the second embodiment is equipped with the main control board 21, presentation interface board 22, presentation control board 23, LCD interface board 24, display device DS, payout control board 25, and launch control board 26 described in the first embodiment, and also has an external terminal board 81 for the frame, a gaming ball payout device 84, a full-capacity detection sensor 82, and a front door open sensor 83. In Figure 18, of the components described in Figure 3(a), those parts other than those related to the second embodiment are omitted from the illustration (for example, power supply board 20, lamp drive board 30, lamp drive board 31, game board relay board 32, motor / lamp drive board 37, etc.), but the gaming machine GMA of the second embodiment also has these components.

[0311] As shown in the figure, an external centralized terminal board for the frame 81 is connected to the payout control board 25, and the main control board 21 is capable of transmitting specified game information (e.g., jackpot information, number of winning balls information, pattern change execution information, etc.) via the payout control board 25 and through this external centralized terminal board for the frame 43 to an externally installed hall computer HC. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 21 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0312] In addition, a game ball dispensing device 84 is connected to the dispensing control board 25, and a ball lending machine 80 is also connected to it. The ball lending machine 80 is provided outside the gaming machine GMA, and executes processing to cause the payout control board 25 to execute the ball lending operation. The main roles of the payout control board 25 are to receive payout control commands from the main control board 21, control the payout of prize balls from the game ball payout device 84 based on the payout control commands, send status signals to the main control board 21, and control the ball lending operation based on the communication results with the ball lending machine 80.

[0313] The game ball payout device 84 is provided with a supply shortage detection sensor (not shown) that detects a shortage of game balls and a ball counting sensor (not shown) that detects the game balls (prize balls) being paid out, and the payout control board 25 is capable of receiving each of these detection signals. In addition, the game ball payout device 84 is provided with a payout motor 84a that drives a ball payout mechanism not shown in the figure for paying out game balls, and the payout control board 25 is capable of transmitting a control signal for controlling the payout motor 84a.

[0314] In addition, a full detection sensor 82 that detects when the upper tray 8 is full of game balls, and a front door open sensor 83 that detects the open state of the aforementioned front door member (glass door and front panel 7) are connected to the payout control board 25.

[0315] The payout control board 25 is capable of transmitting various status signals to the main control board 21 based on detection signals from the full detection sensor 82, the front door open sensor 83, the above-mentioned supply shortage detection sensor, and the ball counting sensor. These status signals include a ball jamming signal indicating a full state, a door open signal indicating that at least the front door is open, a supply shortage signal indicating a supply shortage of game balls from the game ball payout device 84, a counting error signal indicating a shortage of prize balls paid out or an abnormality has occurred in the ball counting sensor, and a payout completion signal indicating that the payout operation has been completed, and are configured to be capable of transmitting various status signals. Based on these status signals, the main control board 21 monitors the open state of the front door (door open error), whether the payout operation of the game ball payout device 84 is normal or not (supply shortage error), the full state of the upper tray 8 (ball jamming error), etc.

[0316] The payout control board 25 is also capable of transmitting an authorization signal to the launch control board 26 to permit launch. Based on the authorization signal being output from the payout control board 25, the launch control board 26 controls the energization of the launch solenoid, and realizes the launching of the game ball by operating the launch handle 10. Specifically, the launching of the game ball is permitted under the conditions that the launch authorization signal is output from the payout control board 25 (launch authorization signal ON state), a touch sensor (not shown) provided on the launch handle 10 detects that the player is touching the handle, and a launch stop switch (not shown) provided on the launch handle 10 is not operated. Therefore, when the launch authorization signal is not output (launch authorization signal OFF state), the launching operation is not executed even if the launch handle 10 is operated, and the game ball is not launched. Also, the launch strength of the game ball can be changed according to the amount of operation of the launch handle 10. In addition, when the payout control board 25 detects the above-mentioned ball jam error, it sends a ball jam signal to the main control board 21 and stops outputting the launch permission signal to the launch control board 26 (launch permission signal OFF), and controls the firing operation to stop until the full state of the upper tray 8 is resolved. In addition, the payout control board 25 outputs a launch permission signal to the launch control board 26 on the condition that launch permission is instructed by the main control board 21.

[0317] [2.1 Overview of communication functions with external devices and communication board configuration] Here, the gaming machine GMA of this embodiment is provided with a communication board for performing signal communication with an external device. Specifically, the gaming machine GMA of this embodiment is provided with a payout control board 25 for performing signal communication with a ball dispensing machine 80 which is an external device of the gaming machine GMA.

[0318] Figure 19 is an explanatory diagram of an example of signals communicated between the payout control board 25 and the ball dispenser 80. The payout control board 25 sends and receives various control signals related to ball lending operations between the ball lending machine 80, such as the BRDY signal, BRQ signal, EXS signal, and PRDY signal shown in the figure.

[0319] The BRDY signal is a signal that is transmitted from the ball lending machine 80 to the gaming machine to indicate that the player has turned on a ball lending switch (not shown) provided on the gaming machine GMA and is in the ball lending operation. Although an illustrated explanation is omitted, a signal indicating the operation state of the ball lending switch is directly input to the ball lending machine 80, and the ball lending machine 80 outputs a BRDY signal to the payout control board 25 indicating that the ball lending switch has been turned on and the ball lending operation is in progress. In this example, the BRDY signal is a signal that falls, for example, from H level to L level in response to the ball lending switch being turned ON.

[0320] The BRQ signal is a signal that requests the gaming machine to dispense one unit (for example, 25 balls) of balls from the ball dispenser 80. In this example, the BRQ signal is a signal that falls from H level to L level at the timing indicating a request for a unit of dispense operation.

[0321] When the BRQ signal falls to L level while the BRDY signal is at L level, one unit of ball lending operation is started. If the BRDY signal is at H level when the ball lending operation is completed, or if the BRDY signal changes to H level within a predetermined time after the completion of the ball lending operation, the ball lending operation is no longer executed. Therefore, the BRDY signal can be considered as a "ball lending permission command", and the BRQ signal can be considered as a "ball lending start command". In other words, as long as the BRDY signal is at L level, the ball lending operation is permitted, and in this example, when the BRQ signal falls within this permission period, the payout operation (lending operation) of one unit of game balls is started in response to this.

[0322] On the other hand, the PRDY signal is a signal that transmits from the payout control board 25 to the ball lending machine 80 that the gaming machine GMA is capable of ball lending operation. In this example, the PRDY signal is a signal that indicates that the L level is capable of ball lending operation.

[0323] The EXS signal is a signal that transmits from the payout control board 25 to the ball lending machine 80 that a request for one unit of ball lending operation by the BRQ signal has been accepted and that the lending operation has been completed. In this example, the EXS signal is a signal that becomes L level from the time when a request for one unit of ball lending operation by the BRQ signal is accepted until the lending operation is completed, and becomes H level during other periods. In other words, the EXE signal is a signal that indicates the period from when a request for one unit of ball lending operation is received by the BRQ signal to when that ball lending operation is completed.

[0324] FIG. 20 is a diagram showing an example of the arrangement of various electronic components on the dispensing control board 25. As shown in the figure, resistors (R1 to R65, etc.), capacitors (C1 to C59, etc.), various diodes (D1 to D8, ZD1, LED1 to LED4, etc.), various filters (FLT1 to FLT7, etc.), and various integrated circuits (Integrated Circuits: IC1 to IC14, etc.) are arranged on the dispensing control board 25. In addition, various connectors (CN1 to CN12) are arranged on the payout control board 25. The payout control board 25 is electrically connected to other boards in the gaming machine GMA and external devices via these connectors.

[0325] 18, in this example, the connector CN3 is a connector for connecting to the main control board 21. The connectors CN2 and CN8 are connectors for connecting to the launch control board 26, the connector CN4 is a connector for connecting to the frame external terminal board 81, and the connector CN6 is a connector for connecting to the game ball payout device 84 (payout motor 84a). Furthermore, the connector CN7 is a connector for connecting to the ball dispensing machine 80. In this example, the above-mentioned BRDY signal, BRQ signal, PRDY signal, and EXS signal are transmitted and received via this connector CN7.

[0326] Here, the dispensing control board 25 is equipped with an insulating transmission means for providing electrical insulation on the signal communication path between the board and the external device. Specifically, the dispensing control board 25 in this example is equipped with a photocoupler PC for providing electrical insulation on the signal communication path between the board and the ball dispenser 80 (see FIG. 20). In this example, five photocouplers PC1 to PC5 are implemented, and these photocouplers PC1 to PC5 are positioned on the payout control board 25 relatively close to the connector CN7 for connecting to the ball dispensing machine 80.

[0327] The signals transmitted between the payout control board 25 and the ball dispensing machine 80, i.e., the above-mentioned BRDY signal, BRQ signal, PRDY signal, and EXS signal, are transmitted and received via a corresponding one of these photocouplers PC1 to PC5.

[0328] The signal paths for the signals transmitted to and from the ball dispensing machine 80, that is, the BRDY signal, the BRQ signal, the PRDY signal, and the EXS signal, will be described below with reference to the circuit diagrams of Figures 21 to 24.

[0329] FIG. 21 is a circuit diagram showing the connection between the connector CN7 and each photocoupler PC. In this example, the connector CN7 is a six-terminal connector. As shown in the figure, terminal 1 of connector CN7 is a transmitting terminal for the PRDY signal (a signal transmitting terminal from the payout control board 25 to the ball dispensing machine 80), terminal 2 is a transmitting terminal for the EXS signal, terminal 3 is a receiving terminal for the VL signal, terminal 4 is a receiving terminal for the BRDY signal, terminal 5 is a receiving terminal for the BRQ signal, and terminal 6 is a ground terminal.

[0330] The VL signal is a signal of a power supply common to the interface, and is, for example, a DC 18V power supply signal. As shown in the figure, the VL signal is input to the dispensing control board 25 side as a P-OUT signal via photocoupler PC5. In photocoupler PC5, a photodiode is inserted between terminals 3 and 6 of connector CN7, so that a current corresponding to the VL signal flows from terminal 3 to terminal 6 via the photodiode. As a result of a current corresponding to the VL signal flowing through the photodiode in this way, a current corresponding to the VL signal flows through the collector of the phototransistor of photocoupler PC5. As a result, a P-OUT signal corresponding to the VL signal is obtained on the secondary side of photocoupler PC5.

[0331] Here, the primary side of the photocoupler PC means the side on which a photodiode (electrical to optical conversion means) is provided, and the secondary side of the photocoupler PC means the side on which a phototransistor (optical to electrical conversion means) is provided.

[0332] Of the photocouplers PC1 to PC4, photocoupler PC1 is for transmitting (sending) the PRDY signal, photocoupler PC2 is for transmitting (sending) the EXE signal, photocoupler PC3 is for transmitting (receiving) the BRDY signal, and photocoupler PC4 is for transmitting (receiving) the BRQ signal. For the sake of convenience, in the following explanation, the PRDY signal input to photocoupler PC1 will be referred to as the "P-RDY signal," and the EXS signal input to photocoupler PC2 will be referred to as the "P-EXS signal." Similarly, the BRDY signal output from photocoupler PC3 will be referred to as the "B-RDY signal," and the BRQ signal output from photocoupler PC4 will be referred to as the "B-RQ signal."

[0333] In photocoupler PC1, the anode of the photodiode is connected to a DC power supply of, for example, DC 12V via resistor R36, and the cathode is connected to a transmission line of a P-RDY signal (a signal indicating whether the PRDY signal is at H level or L level).The collector of the phototransistor in photocoupler PC1 is connected to terminal 1 of connector CN7 via resistor R20, and the emitter is connected to terminal 6 of connector CN7. As a result, a PRDY signal based on the P-RDY signal is supplied to terminal 1 of the connector CN7 via the photocoupler PC1. The signal transmission path of the PRDY signal is electrically insulated by the photocoupler PC1.

[0334] In the photocoupler PC2, the anode of the photodiode is connected to a DC power supply of, for example, DC 12 V via resistor R37, and the cathode is connected to the transmission line of the P-EXS signal (the signal that is the basis of the EXS signal).The collector of the phototransistor in the photocoupler PC2 is connected to terminal 2 of the connector CN7 via resistor R21, and the emitter is connected to terminal 6 of the connector CN7. As a result, an EXS signal based on the P-EXS signal is supplied to the second terminal of the connector CN7 via the photocoupler PC2, and the signal transmission path of the EXS signal is electrically insulated by the photocoupler PC2.

[0335] In the photocoupler PC3, the anode of the photodiode is connected to the third terminal of the connector CN7 via a resistor R22, and the cathode is connected to the fourth terminal of the connector CN7. The collector of the phototransistor in the photocoupler PC3 is connected to a DC power supply such as DC12V via a resistor R39, and a transmission line of the B-RDY signal (a signal indicating whether the BRDY signal is at H level or L level) is connected to the connection point between the collector and the resistor R39. An RC circuit consisting of a resistor R38 and a capacitor C23 is inserted in the transmission line of the B-RDY signal. The emitter of the phototransistor in the photocoupler PC3 is grounded. As a result, the B-RDY signal based on the BRDY signal input to terminal 4 of connector CN7 is supplied to the B-RDY signal transmission line via photocoupler PC3, and the signal transmission path of the BRDY signal is electrically isolated by photocoupler PC3.

[0336] In photocoupler PC4, the anode of the photodiode is connected to terminal 3 of connector CN7 via resistor R23, and the cathode is connected to terminal 5 of connector CN7. The collector of the phototransistor in photocoupler PC4 is connected to a DC power supply such as DC12V via resistor R41, and a transmission line of a B-RQ signal (a signal indicating whether the BRQ signal is at H level or L level) is connected to the connection point between the collector and resistor R41. An RC circuit consisting of resistor R40 and capacitor C24 is inserted in this transmission line of the B-RQ signal, and the emitter of the phototransistor in photocoupler PC4 is grounded. As a result, a B-RQ signal based on the BRQ signal input to terminal 5 of connector CN7 is supplied to the transmission line of the B-RQ signal via photocoupler PC4, and the signal transmission path of the BRQ signal is electrically isolated by photocoupler PC4.

[0337] Specific examples of paths for the BRDY signal, the BRQ signal, the EXS signal, the PRDY signal, and the P-OUT signal will be described with reference to the circuit diagrams of FIGS. Figure 22 <1> <2> As shown in FIG. 1, the B-RDY signal, B-RQ signal, and P-OUT signal from photocouplers PC3, PC4, and PC5 are output as a BRDY signal, a BRQ signal, and a POUT signal, respectively, via integrated circuit IC5 in dispensing control board 25.

[0338] The BRDY and BRQ signals output from the integrated circuit IC5 are as shown in Figure 23. <3> As shown in FIG. 1, the signal is input to integrated circuit IC6 in dispensing control board 25. The integrated circuit IC6 and the integrated circuit IC13 in the figure generate the PRDY signal and the EXS signal based on the BRDY signal and the BRQ signal. <5> As shown in FIG. 1, the PRDY signal and the EXS signal are output from the integrated circuit IC13.

[0339] In addition, the POUT signal output from the integrated circuit IC5 (Figure 22 <2> (see Fig. 24) <4> As shown in FIG. 1, the signal is input to the integrated circuit IC1 in the dispensing control board 25 via resistor R45.

[0340] The PRDY and EXS signals output from the integrated circuit IC13 (Figure 23 <5> (see Fig. 22) <6> <7> As shown in FIG. 21, these are output as a P-RDY signal and a P-EXS signal, respectively, via an integrated circuit IC11 in the dispensing control board 25. Specifically, these are output to photocouplers PC1 and PC2, respectively (see FIG. 21).

[0341] [2.2 Example of substrate configuration as an embodiment] Next, a configuration example of the dispensing control board 25 according to the second embodiment will be described. FIG. 25 is a diagram showing an example of a wiring pattern on the front surface (component mounting surface) of dispensing control board 25, and FIG. 26 is a diagram showing an example of a wiring pattern on the back surface of dispensing control board 25. Here, in various electronic boards provided in the gaming machine GMA, including the payout control board 25, various electronic components such as resistors, capacitors, diodes, integrated circuits, etc. are mounted on the front side and not on the back side.

[0342] As shown in the figure, the dispensing control board 25 has a generally rectangular outer shape when viewed from above. In other words, the surface shape is generally rectangular.

[0343] First, as a common feature on both the front and back sides, the dispensing control board 25 has through electrodes Tt formed in various places that penetrate the thickness direction of the board, and printed wiring as signal lines Ls and ground Gn, which is a printed pattern as ground (GND), are formed on both the front and back sides.

[0344] The signal line Ls is wiring for transmitting various signals handled by the dispensing control board 25, such as signals output from the integrated circuit IC, signals sent and received through the connector CN, and signals input to the integrated circuit IC. On both the front and back surfaces of the substrate, some signal lines Ls are wired so as to electrically connect different through electrodes Tt. Furthermore, on the surface of the substrate, signal lines Ls may be formed that are wired so as to electrically connect different electronic components without passing through the through electrodes Tt.

[0345] Here, when considering the photocoupler PC as the electrical isolation means, the circuits electrically connected to the photocoupler PC on the payout control board 25 can be broadly divided into the inner circuit Ci, which is the circuit electrically connected to other boards in the gaming machine GMA via connectors CN3, CN4, etc., and the outer circuit Co, which is the circuit electrically connected to an external device (ball dispensing machine 80) via connector CN7.

[0346] In the figure, the region indicated by "Ai" represents a region in which the through electrodes Tt connected to the terminals of the connectors CN3, CN4, and CN6 are formed (see also FIG. 20 above). Moreover, the region indicated by "Ao" in the drawing represents a region in which a through electrode Tt to be connected to a terminal of the connector CN7 is formed.

[0347] Furthermore, in the figure, the region indicated by "Api" represents a region in which a through electrode Tt is formed, which is connected to a terminal of the photocoupler PC that is electrically connected to the inner circuit Ci. Here, the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci corresponds to the anode terminal and cathode terminal of the photodiode in the photocouplers PC1 and PC2 on the transmitting side, and corresponds to the collector terminal and emitter terminal of the phototransistor in the photocouplers PC3 to PC5 on the receiving side. In the following description, the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci is referred to as the "inner terminal." Moreover, the region indicated as "Apo" in the figure represents a region in which a through electrode Tt is formed, which is connected to a terminal in the photocoupler PC that is electrically connected to the outer circuit Co. The terminal in the photocoupler PC that is electrically connected to the outer circuit Co corresponds to the collector terminal and emitter terminal of the phototransistor in the photocouplers PC1 and PC2 on the transmitting side, and corresponds to the anode terminal and cathode terminal of the photodiode in the photocouplers PC3 to PC5 on the receiving side. In the following description, the terminal of the photocoupler PC that is electrically connected to the outer circuit Co is referred to as the "outer terminal."

[0348] The inner circuit Ci has at least a circuit area including through electrodes Tt for connectors CN3, CN4, and CN6 shown in area Ai, which are electrically connected to other boards within the gaming machine GMA, and through electrodes Tt for the inner terminals of the photocoupler PC shown in area Api. The area of ​​the outer circuit Co has at least a circuit area including a through electrode Tt for the connector CN7 shown in area Ao and a through electrode Tt for the outer terminal of the photocoupler PC shown in area Apo.

[0349] In this embodiment, the ground Gn of the inner circuit Ci and the outer circuit Co is a solid ground. The term "solid ground" refers to a ground formed by a solid pattern. The solid pattern referred to here means a printed wiring pattern that has a portion wider than the linear signal line Ls and has a portion that surrounds the signal line Ls.

[0350] In addition, in this embodiment, the inner circuit Ci and the outer circuit Co are each formed across the front and back surfaces of the dispensing control board 25 via the through electrodes Tt.

[0351] In the dispensing control board 25 in this embodiment, a separation section Dv is formed which separates the area of ​​the inner circuit Ci from the area of ​​the outer circuit Co. In this example, the separation portion Dv is formed between the inner circuit Ci and the outer circuit Co as a portion where the ground Gn (solid ground) of each circuit is not formed.

[0352] As can be understood from the above description of the regions Api and Apo, in this embodiment, each photocoupler PC is disposed on the separation portion Dv.

[0353] Also, as can be seen by comparing Figures 25 and 26, in this embodiment, on both the front and back sides of the dispensing control board 25, the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci are separated by a separation section Dv.

[0354] In this example, the position and shape of the separation part Dv are substantially the same on the front and back sides of the dispensing control board 25. The position of the separation part Dv here naturally means the position in the surface direction of the dispensing control board 25. In addition, "substantially the same" does not mean only "completely the same" but also includes the range of tolerance in the printing process of the print pattern. For example, it is sufficient if the position and shape of the separation portion Dv on the front and back sides are determined to be the same in design, and tolerance occurring in the actual pattern printing process should be tolerated.

[0355] Furthermore, in the dispensing control board 25 of this example, the separation pattern in the board surface direction between the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci is the same on the front and back sides. In other words, the position and shape in the board surface direction of the area of ​​the outer circuit Co and the area of ​​the inner circuit Ci are approximately the same on the front and back sides.

[0356] (2.2.1 Configuration example A) Here, according to the explanation with reference to the above-mentioned FIG. 25 and FIG. 26, it can be said that the gaming machine GMA of this embodiment has a configuration as the following "configuration example A". In other words, the gaming machine (GMA) of configuration example A is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) is mounted to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, and a separation section (Dv) which separates the outer circuit area from the inner circuit area is formed, an insulating transmission means is arranged on the separation section, and the outer circuit and inner circuit are each formed across the front and back surfaces of the communication board, and the outer circuit area and the inner circuit area are separated on each of the front and back surfaces of the communication board.

[0357] In the gaming machine of configuration example A as described above, the outer circuit and inner circuit areas are separated not only on one side of the communication board but also on the other side. Therefore, the insulation between the inner circuit and the outer circuit can be improved, and the resistance to external noise (input noise from an external device) can be improved.

[0358] The gaming machine as the above configuration example A has the following configuration. That is, in the gaming machine as configuration example A, the positions and shapes of the separation parts are substantially the same on both the front and back sides. In this way, by making the position and shape of the separation part on the front and back sides of the communication board approximately identical, the separation distance in the board surface direction between the inner circuit on the front side and the outer circuit on the back side, and the separation distance in the board surface direction between the outer circuit on the front side and the inner circuit on the back side are prevented from becoming shorter than the width of the separation part, thereby improving the insulation between the inner / outer circuits even between the front and back sides of the board, and further improving resistance to external noise.

[0359] Furthermore, the gaming machine as the above configuration example A has the following configuration. That is, in the gaming machine of configuration example A, the separation pattern in the communication board surface direction between the outer circuit area and the inner circuit area is the same on the front and back sides. In other words, the shapes and areas of the outer circuit area and the inner circuit area are the same on the front and back of the communication board, and the shapes and areas of the separation parts are also the same on the front and back of the communication board. By making the shape and area of ​​the separation portion the same on the front and back of the communication board, it is possible to improve the insulation between the inner circuit and the outer circuit, and to improve resistance to external noise.

[0360] The gaming machine as the above configuration example A has the following configuration. That is, in the gaming machine of configuration example A, the ground of the outer circuit area and the inner circuit area are solid ground. This separates the outer circuit from the inner circuit in terms of area, including the solid ground. Therefore, the insulation between the inner circuit and the outer circuit can be improved, and the resistance to external noise can be improved.

[0361] (2.2.2 Configuration example B) FIG. 27 is an explanatory diagram of an example of the arrangement of photocouplers PC in this embodiment. As shown in the figure, photocouplers PC1 to PC5 are disposed on a separation section Dv. Specifically, in this example, the separation section Dv is formed to have a straight section Sp parallel to the board end edge of the dispensing control board 25, and the photocoupler PC is disposed on this straight section Sp. More specifically, the straight section Sp is formed with a straight section Sp1 parallel to the short side (short side) of the dispensing control board 25 and a straight section Sp2 parallel to the long side (longitudinal side) as shown in the figure, and photocouplers PC1 and PC2 are disposed on the straight section Sp1, and photocouplers PC3, PC4, and PC5 are disposed on the straight section Sp2.

[0362] At this time, each photocoupler PC is disposed so that its own side extending in the direction separating the inner terminal and the outer terminal is perpendicular to the straight line portion Sp located below.

[0363] According to the explanation with reference to FIG. 27, it can be said that the gaming machine GMA as this embodiment has a configuration as the following configuration example B. In other words, the gaming machine (GMA) of configuration example B is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball lending machine 80) is implemented, and the communication board is formed with an outer circuit (Co) which is a circuit that is electrically connected to the external device, and an inner circuit (Ci) which is a circuit that is electrically connected to other boards inside the gaming machine, and a separation section (Dv) that separates the outer circuit area from the inner circuit area, and the separation section has a straight section (Sp) parallel to the edge of the communication board, and the insulating transmission means is arranged on the straight section.

[0364] By arranging the insulating transmission means on a straight section parallel to the end edge of the substrate, rather than arranging the insulating transmission means on a separation section that is angled or curved relative to the end edge of the substrate, it is possible to arrange the insulating transmission means in a direction parallel to the end edge of the substrate. Therefore, the efficiency of arranging the insulating transmission means in the communication board can be improved.

[0365] Moreover, the gaming machine as the configuration example B has the following configuration. That is, in the gaming machine as the above-mentioned configuration example B, a plurality of insulated transmission means are arranged in the straight section. This makes it possible to increase the number of insulating transmission means arranged in a direction parallel to the end sides of the board, thereby enabling space saving in the arrangement space for the insulating transmission means.

[0366] Furthermore, the gaming machine as configuration example B has the following configuration. That is, in the gaming machine as the above-mentioned configuration example B, the separation section has a plurality of straight sections, and the two or more straight sections are each provided with an insulated transmission means. This increases the area where the insulating transmission means can be arranged in a direction parallel to the edge of the board, improving the degree of freedom in arranging the insulating transmission means.

[0367] (2.2.3 Configuration example C) FIG. 28 is an explanatory diagram of the positions of various connectors CN on the dispensing control board 25 in this embodiment. As shown in the figure, in the payout control board 25 of this embodiment, connectors CN3, CN4, CN6, CN8, etc., which are connectors (internal connectors) for electrically connecting with other boards, and connector CN7, which is a connector (external connector) for electrically connecting with an external device such as a ball dispensing machine 80, are arranged side by side at one end of the payout control board 25 (also see FIG. 20). Specifically, in this example, these internal connectors and external connectors are arranged side by side at one long side portion (end of one long side) of the payout control board 25.

[0368] According to the explanation with reference to FIG. 28, it can be said that the gaming machine GMA as this embodiment has a configuration as the following configuration example C. That is, the gaming machine (GMA) of configuration example C is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) is mounted to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, and a separation section (Dv) which separates the outer circuit area from the inner circuit area is formed, and an insulating transmission means is arranged on the separation section, an external connector (connector CN7) for electrically connecting with the external device is provided in the outer circuit area, and internal connectors (connectors CN3, CN4, CN6, CN8, etc.) for electrically connecting with other boards are provided in the inner circuit area, and the external connector and internal connector are arranged side by side at one end of the communication board.

[0369] This improves insulation by separating the inner and outer circuits, while aligning the internal and external connectors to one end of the board, preventing variation in the connector positions and enabling the area on the board in which other components can be overlapped to avoid the connector positions to be expanded. Therefore, it is possible to improve the insulation from the external device while increasing the freedom of component placement in the gaming machine.

[0370] Moreover, the gaming machine as the configuration example C has the following configuration. That is, in the gaming machine of the above-mentioned configuration example C, the surface shape of the communication board is substantially rectangular, and the external connector and the internal connector are arranged side by side on the long side of the communication board. Here, various boards in the gaming machine are fixed to the gaming machine main body at the four corners of the board by screws or the like. On this premise, if the external connector and the internal connector are arranged side by side on the short side of the board, the stress on the board increases when the connector cable is inserted and removed, because the distance to the board fixing point on the side opposite to the side on which the connector is provided becomes longer. On the other hand, if the external connector and the internal connector are arranged side by side on the long side of the board as described above, the distance to the board fixing point on the side opposite to the side on which the connector is provided becomes relatively shorter, so that the stress on the board when the connector cable is inserted and removed can be alleviated.

[0371] (2.2.4 Configuration example D) FIG. 29 is a schematic cross-sectional view for explaining an example of a formation pattern of separation portion Dv and ground Gn in dispensing control board 25 of the present embodiment. In the figure, the photocoupler PC has an inner terminal ti and an outer terminal to. As mentioned above, the "inner terminal" refers to the terminal of the photocoupler PC that is electrically connected to the inner circuit Ci, and the "outer terminal" refers to the terminal that is electrically connected to the outer circuit Co. Here, when the photocoupler PC is for transmission, the inside terminal ti corresponds to the primary terminal of the photocoupler PC (the terminal connected to the photodiode) and the secondary terminal (the terminal connected to the phototransistor), and when the photocoupler PC is for reception, the secondary terminal corresponds. Conversely, when the photocoupler PC is for transmission, the outside terminal to corresponds to the secondary terminal, and when the photocoupler PC is for reception, the primary terminal corresponds.

[0372] In the figure, the inner circuit through electrode Tti represents the through electrode Tt that is connected to the inner terminal ti of the photocoupler PC among the through electrodes Tt that penetrate the substrate portion 42a of the dispensing control substrate 25 in the thickness direction, and the outer circuit through electrode Tto represents the through electrode Tt that is connected to the outer terminal to of the photocoupler PC.

[0373] Here, as shown in the figure, the inner end of the inner circuit through electrode Tti is referred to as the inner end IEi, and the inner end of the outer circuit through electrode Tto is referred to as the inner end IEo. Note that the inside and outside of the terminals mentioned here are based on the center of the photocoupler PC, with the side closer to the center being the inside and the side farther from the center being the outside.

[0374] In the dispensing control board 25 of this example, the ground Gn of the inner circuit Ci (solid ground in this example) and the ground Gn of the outer circuit Co (also solid ground in this example) are formed so as to extend into the area from the inner end IEi of the inner circuit through electrode Tti to the inner end IEo of the outer circuit through electrode Tto. Specifically, in this example, the ground Gn of the inner circuit Ci and the ground Gn of the outer circuit Co reach the lower part of the photocoupler PC.

[0375] Here, the region from the inner end IEi to the inner end IEo is referred to as an electrode inner end region Ait. In addition, the portion of the ground Gn of the inner circuit Ci that exists within the electrode inner end region Ait is referred to as the extension region Agi, and the portion of the ground Gn of the outer circuit Co that exists within the electrode inner end region Ait is referred to as the extension region Ago.

[0376] In the dispensing control board 25 of this example, the extension areas Agi, Ago and separation portion Dv are formed so as to satisfy the following conditions. That is, the condition is that the electrode inner inter-end region Ait is divided into approximately three equal parts by the extension regions Agi, Ago and the separation portion Dv.

[0377] In Figure 29, only the placement portion of one photocoupler PC is shown as a representative example, but in this example, in all placement portions of photocouplers PC1 to PC5, extension regions Agi, Ago, and separation portions Dv are formed so as to satisfy the above conditions.

[0378] Here, in the electrode inner end region Ait located below the photocoupler PC, it is generally considered desirable to increase the width of the separation portion Dv in order to improve insulation. However, it has been newly discovered that if the width of the separation portion Dv is increased in order to prioritize insulation, the tradeoff is that the width of the solid ground of the inner circuit Ci and the outer circuit Co becomes narrower, which makes it easier for external noise to be mixed into the transmission signal by the photocoupler PC. In other words, if the width of the solid ground is narrow in the electrode inner end region Ait, the noise suppression effect on the transmission signal by the photocoupler PC is easily reduced.

[0379] Therefore, in this example, in the electrode inner end region Ait, the solid ground of the outer circuit Co, the separation portion Dv, and the solid ground of the inner circuit Ci are arranged to be divided into approximately three equal parts. This makes it possible to prevent the insulating effect of the isolation portion Dv and the noise suppression effect of the solid ground from being overemphasized on one side, and makes it possible to achieve a balance between these insulating effect and noise suppression effect.

[0380] Here, as a result of simulations performed by the present inventors, when the error from perfect third division exceeds 13%, a change begins to appear in the balance between the insulating effect of the separation part Dv and the noise suppression effect of the solid ground. From this result, the division into approximately thirds means an error from perfect third division within 13%, preferably within 12%, and more preferably within 10%.

[0381] Although an example has been described above in which the above conditions are satisfied for all of the positions of the photocouplers PC, this is not essential, and a configuration in which the positions of some of the photocouplers PC do not satisfy the above conditions is also possible.

[0382] Here, in this example, in the inside circuit Ci and the outside circuit Co, the signal line Ls from the terminal of the photocoupler PC is led out to the side opposite the separation part Dv, not to the separation part Dv side. Specifically, as illustrated by the signal line Ls from the through electrode Tt in region Api and the signal line Ls from the through electrode Tt in region Apo in Figures 25 and 26, in this example, all of the signal lines Ls from the terminals of the photocoupler PC are pulled out to the side opposite the separation section Dv, rather than to the side of the separation section Dv.

[0383] If the signal line Ls were to be drawn from the terminal of the photocoupler PC to the separation section side, a solid ground would be required on the separation section Dv side to cover the signal line Ls, and the width of the separation section Dv would have to be narrowed accordingly. By drawing the signal line Ls from the terminal of the photocoupler PC to the side opposite the separation section Dv as described above, the width of the separation section Dv can be increased, and the noise suppression effect can be improved.

[0384] From the above description, it can be said that the gaming machine GMA according to this embodiment has a configuration as the following configuration example D. That is, the gaming machine (GMA) of configuration example D is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) that provides electrical insulation on the signal communication path between the external device (ball dispensing machine 80) is implemented, and the communication board has an outer circuit (Co) which is a circuit that is electrically connected to the external device, and an inner circuit (Ci) which is a circuit that is electrically connected to other boards inside the gaming machine, and each of the outer circuit and inner circuit is formed across the front and back surfaces of the communication board, and at least on the front surface, the ground (Gn) of the outer circuit area and the inner circuit area is made into a solid ground, and a separation section (Dv) is formed that separates the outer circuit area and the inner circuit area, and the insulating transmission means is arranged on the separation section. The inner circuit has an inner circuit through electrode (Tti) that is connected to either the primary terminal or the secondary terminal of the insulated transmission means and passes through the communication board, and the outer circuit has an outer circuit through electrode (Tto) that is connected to the other of the primary terminal or the secondary terminal of the insulated transmission means and passes through the communication board, and the electrode inner end area (Ait) on the surface, which is the area from the inner end (IEo) of the outer circuit through electrode to the inner end (IEi) of the inner circuit through electrode, is divided into approximately three equal parts by the solid ground area (extension area Ago) of the outer circuit, the separation area, and the solid ground area (extension area Agi) of the inner circuit.

[0385] This makes it possible to prevent the insulating effect of the separator and the noise suppression effect of the solid ground from being overemphasized on one side, and makes it possible to achieve a balance between these insulating and noise suppression effects.

[0386] Moreover, the gaming machine as the configuration example D has the following configuration. That is, in the gaming machine of configuration example D, in the inner circuit and the outer circuit, the signal line (Ls) from the terminal of the insulated transmission means is drawn out not to the separation part side but to the opposite side to the separation part.

[0387] This makes it possible to increase the width of the separation portion, thereby improving the noise suppression effect.

[0388] (2.2.5 Configuration examples E, F) FIG. 30 is an explanatory diagram regarding the width of the separation portion Dv. As shown in the figure, the minimum width of the separation portion Dv is set to width D1. In this example, width D1 is set to the width of the straight line portions Sp1 and Sp2. Moreover, the width of the signal line Ls formed on the dispensing control board 25 is defined as width D2.

[0389] In the dispensing control board 25 of this embodiment, the width D1 of the separation portion Dv is greater than the width D2 of the signal line Ls (D1>D2) (see also Figures 25 and 26 above). In this example, width D1 > width D2 on both the front and back sides of the dispensing control board 25. In this example, the width D1 of the separation portion Dv is set to be larger than the maximum value of the width D2, that is, the width of the widest signal line Ls. In this example, this is also the same on both the front and back sides of the dispensing control board 25.

[0390] As described above, by making the width D1 of the separation portion Dv larger than the width D2 of the signal line Ls, it is possible to improve the insulation between the inner circuit Ci and the outer circuit Co, and it is possible to improve resistance to external noise.

[0391] Here, on the dispensing control board 25, an insulating section IS is formed between the ground Gn, which is a solid ground, and the signal line Ls, for electrically insulating the ground Gn from the signal line Ls. If the width of this insulating portion IS is width D3, in the dispensing control board 25 of this embodiment, the width D1 of the separation portion Dv is wider than the width D3 of the insulating portion IS (D1>D3) (see also Figures 25 and 26 above). In this example, width D1 > width D3 on both the front and back sides of the dispensing control board 25. In addition, in this example, on both the front and back surfaces of the dispensing control board 25, the width D1 of the separation portion Dv is greater than the maximum value of the width D3, that is, the width of the widest insulating portion IS.

[0392] As described above, by making the width D1 of the separation portion Dv larger than the width D3 of the insulation portion IS, it is possible to improve the insulation between the inner circuit Ci and the outer circuit Co, and it is possible to improve the resistance to external noise.

[0393] From the above description, it can be said that the gaming machine GMA according to this embodiment has a configuration as the following configuration example E. In other words, the gaming machine (GMA) of configuration example E is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) is mounted to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board has an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, as well as a separation section (Dv) which separates the outer circuit area from the inner circuit area, and an insulating transmission means is arranged on the separation section, and the minimum width of the separation section is wider than the width of the signal line formed on the communication board.

[0394] This makes it possible to improve the insulation between the inner circuit and the outer circuit, and to improve resistance to external noise.

[0395] Moreover, the gaming machine as configuration example E has the following configuration. That is, in the gaming machine of configuration example E, in the inner circuit and the outer circuit, the signal line from the terminal of the insulated transmission means is pulled out to the side opposite the separation part, rather than to the separation part side (see the explanation of configuration example D above). This makes it possible to increase the width of the separation portion, thereby improving the noise suppression effect.

[0396] Furthermore, from the above description, it can be said that the gaming machine GMA as an embodiment has a configuration as the following configuration example F. In other words, the gaming machine (GMA) of configuration example F is equipped with a communication board (payout control board 25) on which an insulating transmission means (photocoupler PC) is mounted to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, and a separation section (Dv) which separates the outer circuit area from the inner circuit area is formed, an insulating transmission means is arranged on the separation section, the ground (Gn) of the outer circuit area and the inner circuit area is a solid ground, and the minimum width of the separation section is wider than the width of the insulating section (IS) between the signal line (Ls) formed on the communication board and the solid ground. This makes it possible to improve the insulation between the inner circuit and the outer circuit, and to improve resistance to external noise.

[0397] Moreover, the gaming machine as configuration example F has the following configuration. In other words, in the gaming machine of configuration example F, in the inner circuit and the outer circuit, the signal line from the terminal of the insulated transmission means is pulled out to the side opposite the separation section, rather than to the separation section side (see the explanation of configuration example D above). This makes it possible to increase the width of the separation portion, thereby improving the noise suppression effect.

[0398] [2.3 First modified example (configuration example G)] FIG. 32 is an explanatory diagram of a dispensing control board 25A as a first modified example. The dispensing control board 25A as the first modified example differs from the dispensing control board 25 mainly in the formation pattern of the separation section Dv. In this case, the separation portion Dv is formed to have a first portion P1 extending in a first direction, which is a direction approximately parallel to one side of the dispensing control board 25A, a second portion P2 extending from the end of the first portion P1 in a direction different from the first direction, and a third portion P3 extending in the first direction from the end of the second portion P2 opposite the connection portion with the first portion P1 so as to be opposed to the first portion P1. Specifically, in this example, the first direction is a direction approximately parallel to the short side of the dispensing control board 25A ("direction V" in the figure), and therefore the first part P1 and the third part P3 both extend in the direction V. Also, in this example, the second part P2 is a part extending in a direction approximately parallel to the long side of the dispensing control board 25A ("direction H" in the figure).

[0399] The separation portion Dv including the first portion P1, the second portion P2, and the third portion P3 has a generally U-shaped configuration as shown in the figure. In the example of Fig. 31, the outer circuit Co is surrounded by the generally U-shaped portion of the separation portion Dv.

[0400] As a result of the formation of the approximately U-shaped separation portion Dv as described above, a part of the area of ​​the inner circuit Ci will wrap around to the back side of the area of ​​the outer circuit Co on the substrate, as shown by "Ar" in the figure. Hereinafter, a region in which either the inner circuit Ci or the outer circuit Co wraps around to the back side of the other, such as the region indicated by "Ar", will be referred to as a "wraparound region Ar".

[0401] Here, in this example, of the first part P1 and the third part P3 which are parts extending in the above-mentioned first direction (V direction in this example) in the separation part Dv, the part which is in contact with the above-mentioned wraparound region Ar is referred to as the third part P3, and the part which is not in contact with the wraparound region Ar is referred to as the first part P1.

[0402] In this case, the photocouplers PC arranged on the separation unit Dv are five, namely, photocoupler PC11 to photocoupler PC15. Although not shown in the figure, each of these photocouplers PC11 to PC15 has information indicating the product model number printed in a predetermined direction on the top surface. In particular, the same product is used for photocoupler PC14 and photocoupler PC15, and the model number information is printed in the same direction. For example, the model number information is printed so that the side on which the secondary terminals are formed is below the character string. Note that since photocoupler PC14 and photocoupler PC15 are the same product, their exterior colors are the same.

[0403] The photocoupler 14 is used as a transmitting photocoupler PC that transmits a signal from the inner circuit Ci to the outer circuit Co, and the photocoupler PC15 is used as a receiving photocoupler PC that transmits a signal from the outer circuit Co to the inner circuit Ci. In this example, the transmitting photocoupler PC14 is used to transmit either the PRDY signal or the EXS signal described above, and the receiving photocoupler PC15 is used to transmit either the BRDY signal or the BRQ signal described above.

[0404] As shown in the figure, in this example, photocouplers PC11 to PC13 are disposed on a first portion P1 of the isolation portion Dv. It should be noted that, regarding the photocouplers PC11 to PC13, there are no particular limitations as to which photocoupler PC is used for transmission and which is used for reception, or which signal each photocoupler PC transmits.

[0405] As shown in the figure, in this example, the transmitting photocoupler PC14 is arranged alongside the photocouplers PC11 to PC13 on a first portion P1 of the separation unit Dv, and the receiving photocoupler PC15 is arranged on a third portion P3 of the separation unit Dv.

[0406] Here, the transmitting photocoupler PC14 has its primary terminal connected to the inner circuit Ci and its secondary terminal connected to the outer circuit Co, and the receiving photocoupler PC15 has its primary terminal connected to the outer circuit Co and its secondary terminal connected to the inner circuit Ci. However, with the above configuration, when connecting the primary and secondary terminals of the transmitting photocoupler PC14 and the receiving photocoupler PC15 in this manner, it is possible to align the mounting orientations of the photocouplers PC14 and PC15. By aligning the mounting orientation, the printing orientation of these photocouplers PC14 and PC15 can also be aligned, making it easier to check the photocouplers PC14 and PC15 on the board. Also, when mounting components on the board, photocouplers PC14 and PC15 can be mounted in the same orientation, so there is no need to rotate the robot arm, and the efficiency of the mounting work can be improved. Therefore, for the photocouplers PC14, PC15 mounted on the dispensing control board 25A, it is possible to improve the ease of component confirmation while also improving the efficiency of the mounting work.

[0407] In the above example, the transmitting photocoupler PC14 is disposed on the first portion P1, and the receiving photocoupler PC15 is disposed on the third portion P3, but the photocoupler PC14 may be disposed on the third portion P3, and the photocoupler PC may be disposed on the first portion P1. In this case, the mounting orientation of the photocouplers PC14 and PC15 is opposite to that in FIG. 31. As can be understood from this point, the photocoupler PC14 may be disposed in either the first portion P1 or the third portion P3, and the photocoupler PC15 may be disposed in the other of the first portion P1 or the third portion P3.

[0408] Here, in the payout control board 25A, an internal connector (here designated by the symbol "CNi"), which is a connector CN electrically connected to other boards in the gaming machine GMA, is arranged in the inner circuit Ci area, and an external connector (here designated by the symbol "CNo"), which is a connector CN electrically connected to the ball dispensing machine 80 as an external device, is arranged in the outer circuit Co area. In this example, the internal connector CNi and the external connector CNo have a generally rectangular shape when viewed from above, and are arranged so that their long sides extend in a direction generally parallel to the long sides of the dispensing control board 25A. Here, the long sides of the dispensing control board 25A can be said to be a direction (hereinafter referred to as the "third direction") generally perpendicular to the direction V1, which is the extension direction of the first part P1 and the third part P3 in the separation section Dv. In this example, the third direction is a direction generally parallel to the long sides of the dispensing control board 25A.

[0409] Of these internal connectors CNi and external connectors CNo, the connector that has the smallest total distance from the photocoupler PC14 and the photocoupler PC15 is defined as the nearby connector. In this example, the nearby connector corresponds to the external connector CNo.

[0410] In the present example of the dispensing control board 25A, the photocouplers PC14 and PC15 are arranged spaced apart in the third direction, with the center line Lc in the third direction of the nearby connector as the boundary.

[0411] In the figure, the flow of the transmission signal transmitted from photocoupler PC14 via external connector CNo and the flow of the reception signal received from external connector CNo via photocoupler PC15 are diagrammatically represented by dashed arrows. As can be seen by referring to these dashed arrows, by arranging photocouplers PC14 and PC15 at a distance in the third direction with the center line Lc of the adjacent connector as the boundary as described above, it is possible to form the wiring for the transmission signal and the reception signal as far apart as possible. Therefore, mutual interference caused by radiation noise in the transmission and reception wiring can be reduced.

[0412] In the above, an example was given in which the wraparound region Ar is formed as a region in which a part of the inner circuit Ci wraps around to the back side of the outer circuit Co. However, it is also possible to form the wraparound region Ar conversely as a region in which a part of the outer circuit Co wraps around to the back side of the inner circuit Ci, as shown in FIG. In this case, the region surrounded by the substantially U-shaped region formed by the first portion P1, the second portion P2, and the third portion P3 in the separation portion Dv is the region of the inner circuit Ci.

[0413] Even in the case of the configuration of Figure 32, the same effect can be obtained by placing the photocoupler PC14 in either the first part P1 or the third part P3, and placing the photocoupler PC15 in the other of the first part P1 or the third part P3, in a manner similar to that of Figure 31.

[0414] In this case, the nearby connector for photocouplers PC14 and PC15 is the internal connector CNi, and in this case, the photocouplers PC14 and PC15 are arranged apart in the third direction, with the center line Lc' in the third direction (in this example, the direction approximately parallel to the long side of the dispensing control board 25A) of the internal connector CNi as the nearby connector as the boundary. This also makes it possible in this case to form the wiring for the transmission signal and the wiring for the reception signal as far apart as possible, thereby reducing mutual interference caused by radiation noise from the respective wirings for transmission and reception.

[0415] From the above description, it can be said that the gaming machine GMA as the first modified example has a configuration as the configuration example G below. In other words, the gaming machine (GMA) of configuration example G is equipped with a communication board on which an insulating transmission means (photocoupler PC) is implemented to provide electrical insulation on the signal communication path between the external device (ball dispensing machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, as well as a separation section (Dv) which separates the outer circuit area from the inner circuit area, and is equipped with a transmitting insulating transmission means (photocoupler PC14) which transmits a signal from the inner circuit to the outer circuit, and a receiving insulating transmission means (photocoupler PC15) which transmits a signal from the outer circuit to the inner circuit, as the insulating transmission means. The separation portion has a first portion (P1) extending in a first direction which is a direction approximately parallel to one side of the communication board, a second portion (P2) extending from an end of the first portion in a direction different from the first direction, and a third portion (P3) extending in the first direction from an end of the second portion opposite the connection portion with the first portion so as to be opposed to the first portion, and the transmitting isolated transmission means is disposed in either the first portion or the third portion, and the receiving isolated transmission means is disposed in the other of the first portion or the third portion.

[0416] This makes it possible to align the mounting orientation of the transmitting isolated transmission means and the receiving isolated transmission means. By aligning the mounting orientation, the printing orientation of the transmitting and receiving isolated transmission means can also be aligned, making it easier to check the components of the transmitting and receiving isolated transmission means on the board. Also, since the transmitting and receiving isolated transmission means can be mounted in the same orientation when mounting components on the board, there is no need to rotate the robot arm, and the efficiency of the mounting work can be improved. Therefore, it is possible to improve the ease of checking the components of the transmitting and receiving isolated transmission means mounted on the communication board, and also to improve the efficiency of the mounting work.

[0417] Moreover, the gaming machine as the configuration example G has the following configuration. That is, in the gaming machine of configuration example G, the communication board is provided with an internal connector (CNi) that is arranged in the inner circuit area and electrically connects to other boards, and an external connector (CNo) that is arranged in the outer circuit area and electrically connects to an external device, the internal connector and the external connector have a substantially rectangular shape when viewed from above, and are arranged so that their long sides extend in a third direction that is a direction substantially perpendicular to one side of the communication board, and when the connector of the internal connector and the external connector that has the smallest total distance from the transmitting isolated transmission means and the receiving isolated transmission means is defined as the nearby connector, the transmitting isolated transmission means and the receiving isolated transmission means are arranged at a distance in the third direction, with the center line of the nearby connector in the third direction as the boundary. According to the above configuration, the transmitting isolated transmission means and the receiving isolated transmission means are arranged at a distance in the third direction on different sides of the center line of the nearby connector, so that the wiring for transmitting signals and the wiring for receiving signals can be formed as far apart as possible on the communication board. Therefore, mutual interference caused by radiation noise in the transmission and reception wiring can be reduced.

[0418] [2.4 Second Modification (Configuration Example H)] Here, in the above, relatively low-speed signals such as the BRDY signal, BRQ signal, PRDY signal, and EXS signal are given as examples of signals to be transmitted and received between external devices via the photocoupler PC. However, it is also possible to consider a configuration in which not only low-speed signals but also high-speed signals are transmitted and received between external devices via the photocoupler PC. Regarding the terms "low speed signal" and "high speed signal" used here, low speed and high speed are based on the average period of change in the signal value (signal level), and a "high speed signal" refers to a signal whose average period is faster than that of a "low speed signal." Regarding the terms "low-speed signal" and "high-speed signal," a "high-speed signal" can be defined as a signal transmitted via serial communication in which the signal level changes in synchronization with a clock of a specific frequency (i.e., the rate is limited by the clock), while a "low-speed signal" can be defined as a signal that is not rate-limited by the clock.

[0419] FIG. 33 is a diagram for explaining an example configuration of a dispensing control board 25B as a second modified example that can be adopted when transmitting and receiving both low-speed signals and high-speed signals with an external device as described above. In the dispensing control board 25B shown in Figure 33, the formation pattern of the separation section Dv, the arrangement of the photocouplers PC11 to PC13, and the shapes and arrangement positions of the internal connector CNi and external connector CNo are the same as in Figure 31, so duplicate explanations will be avoided.

[0420] In this case, the photocouplers PC11 to PC13 are photocouplers PC that transmit low-speed signals. On the other hand, photocouplers PC16 and PC17 in the figure are implemented as photocouplers PC for transmitting high-speed signals. The photocoupler PC16 is a transmitting photocoupler PC that transmits high-speed signals from the inner circuit Ci to the outer circuit Co, and the photocoupler PC17 is a receiving photocoupler PC that transmits high-speed signals from the outer circuit Co to the inner circuit Ci.

[0421] In this example, the photocouplers PC11 to PC13 are disposed on the first portion P1 of the isolation portion Dv. The photocoupler PC16 is disposed on the first portion P1 alongside the photocouplers PC11 to PC13, and the photocoupler PC17 is disposed on the third portion P3. As a result, photocoupler PC16 and photocoupler PC17 are spaced apart in a direction approximately parallel to one side of the dispensing control board 25B (in this example, a direction approximately parallel to the long side of the dispensing control board 25B: hereinafter referred to as the ``side parallel direction'').

[0422] In the second variant of the dispensing control board 25B, photocouplers PC11 to PC13 that transmit low-speed signals are arranged at a first interval, while photocouplers PC16 and PC17 that transmit high-speed signals are arranged at a second interval that is wider than the first interval.

[0423] The transmission signals of the photocouplers PC16 and PC17 that transmit high-speed signals are faster than the transmission signals of the photocouplers PC11 to PC13 that transmit low-speed signals, and there is a risk of radiation noise being generated in the signal line Ls connected to the photocouplers PC16 and PC17. With the above configuration, it is possible to reduce the possibility that the signal line Ls connected to the photocoupler PC16 and the signal line Ls connected to the photocoupler PC17 will be mutually affected by radiation noise. Therefore, the accuracy of high-speed signal communication can be improved.

[0424] In the above, it is assumed that the photocouplers PC11 to PC13 are arranged at equal intervals as the first interval, but the photocouplers PC11 to PC13 may be arranged at non-equidistant intervals. In that case, the arrangement interval of the photocouplers PC16 and PC17 that transmit high-speed signals should be wider than the arrangement interval of the pair of photocouplers PC11 and PC12 or the arrangement interval of the pair of photocouplers PC12 and PC13, whichever is wider.

[0425] Here, as shown in Figure 33, in the dispensing control board 25B, the internal connector CNi and the external connector CNo have an approximately rectangular shape when viewed from above, and are arranged so that their long sides extend in the direction parallel to the above-mentioned sides of the dispensing control board 25B (the direction in which photocouplers PC16 and PC17 are separated). Photocouplers PC16 and PC17 are arranged apart in the direction parallel to the side, separated by the center line Lc in the direction parallel to the side of the nearby connector for these photocouplers PC16 and PC17 (the connector CN having the smallest total distance from each photocoupler PC).

[0426] This makes it possible to form the wiring for the transmission signals by the photocouplers PC16 and PC17 as far apart as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise in the wiring that transmits high-speed signals via the photocouplers PC16 and PC17.

[0427] In addition, while Fig. 33 shows an example in which the wraparound region Ar is formed as a region in which a part of the inner circuit Ci wraps around to the back side of the outer circuit Co, it is also possible to form the wraparound region Ar as a region in which a part of the outer circuit Co wraps around to the back side of the inner circuit Ci, as shown in Fig. 34. In this case, similar to the case of Fig. 32, the region surrounded by the approximately U-shaped region formed by the first portion P1, the second portion P2, and the third portion P3 in the separation portion Dv is the region of the inner circuit Ci.

[0428] Even in the configuration of Figure 34, the same effect as in the first modified example can be obtained by arranging the photocoupler PC16 in either the first part P1 or the third part P3, and the photocoupler PC17 in the other of the first part P1 or the third part P3, in the same manner as in the case of Figure 33.

[0429] In this case, the nearby connector for photocouplers PC16 and PC17 is the internal connector CNi, and in this case, the photocouplers PC16 and PC17 are arranged apart in the side-parallel direction, with the center line Lc' in the side-parallel direction of the internal connector CNi as the nearby connector (in this example, the direction approximately parallel to the long side of the dispensing control board 25B) as the boundary. This also makes it possible in this case to form the wiring for the transmission signals by the photocouplers PC16 and PC17 as far apart as possible, thereby reducing mutual interference due to radiation noise in each wiring that transmits high-speed signals via these photocouplers PC16 and PC17.

[0430] From the above description, it can be said that the gaming machine GMA as the first modified example has a configuration as the following configuration example H. In other words, the gaming machine (GMA) of configuration example H is equipped with a communication board (payout control board 25B) on which an insulating transmission means (photocoupler PC) is implemented to provide electrical insulation on the signal communication path with an external device (ball lending machine 80), and the communication board is formed with an outer circuit (Co) which is a circuit electrically connected to the external device, and an inner circuit (Ci) which is a circuit electrically connected to other boards inside the gaming machine, as well as a separation section (Dv) which separates the outer circuit area from the inner circuit area, and is configured to be capable of both low-speed signal communication and high-speed signal communication as signal communication with the external device. The insulating transmission means for performing low-speed signal communication includes a first low-speed insulating transmission means (any of photocouplers PC11 to PC13) and a second low-speed insulating transmission means (any of photocouplers PC11 to PC13), and the insulating transmission means for performing high-speed signal communication includes a first high-speed insulating transmission means (photocoupler PC16) and a second high-speed insulating transmission means (photocoupler PC17). On the separation portion, the first low-speed insulating transmission means and the second low-speed insulating transmission means are arranged at a first interval, while the first high-speed insulating transmission means and the second high-speed insulating transmission means are arranged at a second interval wider than the first interval.

[0431] The transmission signal of the high-speed insulated transmission means is faster than the transmission signal of the low-speed insulated transmission means, and there is a risk of radiation noise being generated in the signal line connected to the high-speed insulated transmission means. With the above configuration, it is possible to reduce the possibility that the signal line connected to the first high-speed insulated transmission means and the signal line connected to the second high-speed insulated transmission means are mutually affected by radiation noise. Therefore, the accuracy of high-speed signal communication can be improved.

[0432] Moreover, the gaming machine as configuration example H has the following configuration. That is, in the gaming machine of configuration example H, the communication board is provided with an internal connector (Ci) that is arranged in the inner circuit area and electrically connects to other boards, and an external connector (Co) that is arranged in the outer circuit area and electrically connects to an external device, the first high-speed insulated transmission means and the second high-speed insulated transmission means are arranged at a distance in the side-parallel direction that is approximately parallel to one side of the communication board, the internal connector and the external connector have a substantially rectangular shape when viewed from above, and are arranged so that their long sides extend in the side-parallel direction of the communication board, and when the connector of the internal connector and the external connector that has the smallest total distance from the first high-speed insulated transmission means and the second high-speed insulated transmission means is defined as the nearby connector, the first high-speed insulated transmission means and the second high-speed insulated transmission means are arranged at a distance in the side-parallel direction, with the center line in the side-parallel direction of the nearby connector as the boundary.

[0433] This makes it possible to form the wiring for the transmission signals by the first and second high-speed insulated transmission means as far apart as possible. Therefore, it is possible to reduce mutual interference caused by radiation noise from each wiring that transmits high-speed signals.

[0434] Regarding the dispensing control board 25B as the second modified example, the above example illustrates a configuration in which the separation section Dv has a first part P1, a second part P2, and a third part P3, as in the first modified example, and a photocoupler PC16 is arranged in either the first part P1 or the third part P3, and a photocoupler PC17 is arranged in the other of the first part P1 or the third part P3, but it is not essential to adopt this configuration in the second modified example.

[0435] In addition, in the above example, the photocoupler PC16 is the transmitting photocoupler PC and the photocoupler PC17 is the receiving photocoupler PC, but a configuration in which both of these photocouplers PC16 and PC17 are the transmitting and receiving photocouplers PC is also conceivable.

[0436] [2.5 Other variations] Although the second embodiment has been described above, the present invention is not limited to the specific examples described so far, and various modified configurations can be adopted. For example, although a photocoupler is exemplified as the isolated transmission means in the above, the present invention can be widely and suitably applied to cases where an isolated transmission means of a photoelectric conversion type is adopted as the isolated transmission means. The present invention can also be suitably applied to cases where an isolated transmission means of a type other than the photoelectric conversion type, such as an electromagnetic isolated transmission means such as a transformer, is adopted as the isolated transmission means.

[0437] In addition, in the above, an example was given of the communication board of the present invention being configured as a payout control board having a payout control (loan control) function for game balls, but it is not essential for the communication board of the present invention to have the payout control function, and it is sufficient that it has at least a function for communicating with an external device.

[0438] In the above, it is assumed that the signal transmission via the insulating transmission means in the communication board is between an external device such as the ball dispenser 80, but the signal transmission via the insulating transmission means may be between the communication board and another board inside the gaming machine. In this case, the communication board may be configured as a communication relay board that relays communication between a game control board that controls the progress of the game and a performance control board that controls the performance means, and the insulating transmission means provides electrical insulation on the signal communication path between the game control board and the performance control board. By adopting such a configuration, it is possible to prevent noise generated on the performance control board from being mixed into the game control board. Furthermore, when the insulating transmission means of the communication board is configured to provide electrical insulation on the signal communication path between the control boards within the gaming machine as described above, it is possible to adopt the configurations described above as configuration example A to configuration example H for the communication board.

[0439] <3. Third embodiment> [3.1 Structure of the gaming machine in the third embodiment] Next, a third embodiment will be described. The third embodiment relates to a technique for presenting results regarding win / loss.

[0440] The overall structure of the gaming machine GMB as the third embodiment will be described with reference to Fig. 35 and Fig. 36. Fig. 35 is a perspective view showing the appearance of the gaming machine GMB, and Fig. 36 is a perspective view of the gaming machine GMB with the front frame G7 opened. In the following description, the right direction as seen by a player facing the gaming machine GMB is the right direction of the gaming machine GMB, and the left direction as seen by a player facing the gaming machine GMB is the left direction of the gaming machine GMB. The vertical upward direction is the upward direction of the gaming machine GMB, and the vertical downward direction is the downward direction of the gaming machine GMB. The direction from the gaming machine GMB toward the player facing the gaming machine GMB is the forward direction of the gaming machine GMB, and the direction from the player facing the gaming machine GMB is the rear direction of the gaming machine GMB. The left and right directions of the gaming machine GMB are the same as the width direction of the gaming machine GMB.

[0441] The GMB gaming machine is a so-called smart pachinko machine that circulates the gaming balls enclosed inside and uses them for play.

[0442] As shown in Figures 35 and 36, the gaming machine GMB includes a wooden outer frame G3, an inner frame G5 attached to the outer frame G3 by a hinge mechanism G4 so as to be openable and closable, and a front frame G7 attached to the inner frame G5 by the hinge mechanism G4 so as to be openable and closable. The hinge mechanism G4 is provided at the upper left end and the lower left end of the gaming machine GMB. The inner frame G5 is formed in a picture frame shape, and holds a gaming board G9 inside.

[0443] The front frame G7 holds a transparent glass G11 in the center, and a side unit G13 is provided so as to surround all or part of the periphery of the transparent glass G11. The side unit G13 is decorated in a shape that matches the theme of the gaming machine GMB, and may be equipped with LEDs, movable accessories, and other presentation means inside to provide a presentation effect that conveys the atmosphere of the game to the player. The side unit G13 is replaceably attached to the front frame G7.

[0444] A key cylinder G15 for unlocking the door is provided at the right end of the front frame G7. By inserting a key into this key cylinder G15 and operating it to one side, the locked state of the front frame G7 relative to the inner frame G5 is released, allowing the front frame G7 to be opened to the front. By operating it to the other side, the locked state of the inner frame G5 relative to the outer frame G3 is released, allowing the inner frame G5 to be opened to the front.

[0445] A front operation panel G17 is disposed below the front frame G7. A handle device G19 for launching game balls from the launch device G31 is provided on the right end side of the front operation panel G17.

[0446] On the left side of the front operation panel G17, a game ball number display G21 and a counting switch G23 are provided. The game ball number display G21 is composed of a 6-digit 7-segment LED, and displays the number of game balls managed by the gaming machine GMB (the number of game balls owned by the player: hereinafter referred to as the managed game ball number). The counting switch G23 accepts an operation input from the player to transfer the managed game ball number to a valuable medium (card) of the game ball etc. lending device.

[0447] The front operation panel G17 is also provided with operation buttons G25 that are operable by the player. The operation buttons G25 include a performance button G25a, a direction key G25b, a brightness change button G25c, and a volume change button G25d. The effect button G25a is operable (input acceptable) during a predetermined input acceptance period, and can bring about changes in the effect by performing a predetermined operation (pressing, tapping repeatedly, pressing and holding, etc.). The effect button G25a also serves as an operator for instructing the confirmation of an item selected by the directional key G25b. A vibration device G77 (see FIG. 41) is attached to the effect button G25a, and the vibration device G77 can vibrate the effect button G25a at a predetermined timing to further enhance the effect of the effect. The directional keys G25b are operators for users such as players and hall staff to select various items, give directions, etc. The directional keys G25b include an up key provided on the upper side for pointing up, a left key provided on the left side for pointing left, a right key provided on the right side for pointing right, and a down key provided on the lower side for pointing down. The brightness change button G25c is an operator for adjusting the brightness of the performance LEDG27 for performance, and includes a plus button for increasing the brightness of the performance LEDG27 and a minus button for decreasing the brightness of the performance LEDG27. The volume change button G25d is an operator for adjusting the volume of the sound output from the speaker G29, and includes a plus button for increasing the volume and a minus button for decreasing the volume.

[0448] A plurality of LEDs G27 for performance, which are controlled to various lighting modes and light colors (collectively referred to as light emission states), are provided at appropriate positions on the front frame G7. A large number of LEDs G27 for performance are provided around the gaming machine GMB, for example, on the periphery of the front frame G7, in the side unit G13, and in the gaming board G9, and are controlled to light by the performance control board G120.

[0449] Further, around the gaming machine GMB, for example around the periphery of the front frame G7, a plurality of speakers G29 for outputting sound are provided. The multiple speakers G29 enable so-called stereophonic reproduction or multi-channel audio reproduction for sounds related to the performance.

[0450] The inner frame G5 is provided with a circulation mechanism G30 including a launching device G31 and a lifting device G33 below the game board G9. The circulation mechanism G30 circulates game balls within the game machine GMB. The launching device G31 launches game balls toward the game area G37 with a strength according to the amount of operation (rotation angle) of the handle G19a of the handle device G19 by the player. The lifting device G33 transports game balls discharged from the game area G37 (game board G9) to the launching device G31. In addition, the lifting device G33 is equipped with a polishing device that polishes the game balls while lifting them.

[0451] Next, the configuration of the game board G9 will be described with reference to Figures 37 and 38. Figure 37 is a front view of the game board G9. Figure 38 is a cross-sectional perspective view of the AA cross section in Figure 37.

[0452] As shown in Figures 37 and 38, the game board G9 is provided with an outer rail G35 and an inner rail G36 for guiding the launched game ball. The outer rail G35 extends in an arc shape from the slightly lower left end in the left-right direction, passes through the upper center end in the left-right direction, and extends to the upper right. The approximately circular area surrounded by the outer rail G35 is formed as the game area G37, and the outside of the approximately circular area is formed as the non-game area. The game area G37 is a space formed between the game board G9 and the transparent glass G11, and is an area where game balls can flow down. The inner rail G36 extends in an arc shape from the lower left end to the upper left end along the outer rail G35. The area between the outer rail G35 and the inner rail G36 is formed as the game ball guide path G35a. The game ball guide path G35a is a path along which the game ball launched from the launching device G31 passes, and guides the game ball launched from the launching device G31 to the game area G37.

[0453] The game area G37 is divided into a left game area G37a and a right game area G37b by a center ornament G39 provided in the center. The center ornament G39 has a center apex G39a protruding most upward to divide the left game area G37a and the right game area G37b. The center apex G39a may be formed at a position shifted to the right or left from the center, not at the center in the left-right direction. A game ball launched by the launching device G31 at less than a predetermined launch strength that does not exceed the center apex G39a will flow down the left game area G37a, and a game ball launched at or above the predetermined launch strength that exceeds the center apex G39a will flow down the right game area G37b.

[0454] The game area G37 is provided with a collision stopper G38 that is continuous with the upper right end of the outer rail G35. The collision stopper G38 is disposed at a position along the outer rail G35, so that the game balls launched by the launching device G31 at a predetermined launch strength or higher are collided with the collision stopper G38 and guided to the right game area G37b.

[0455] In addition, a backflow prevention member G40 is provided at the upper left end of the inner rail G36. The backflow prevention member G40 is biased counterclockwise by a spring (not shown) so as to block the game ball guide path G35a, and can rotate clockwise around the upper left end of the inner rail G36 as a fulcrum by a game ball entering the game area G37 from the game ball guide path G35a. This allows the backflow prevention member G40 to prevent a game ball that has entered the game area G37 from flowing back into the game ball guide path G35a.

[0456] The special symbol 1 start port G41 is provided at the center lower side of the game board G9. The special symbol 1 start port G41 is a winning port related to the start condition of the variable display operation of the first special symbol (hereinafter, referred to as special symbol 1, and may be abbreviated to special symbol 1) in the main display G63, and is configured as a fixed start port.

[0457] A special symbol 2 start port G43 is provided on the right side of the game board G9. The special symbol 2 start port G43 is a winning port related to the start condition of the variable display operation of the second special symbol (hereinafter, referred to as special symbol 2, and sometimes abbreviated to special symbol 2) in the main display G63, and is configured as a variable start port whose opening and closing is controlled by the normal electric role G45.

[0458] The normal electric device G45 can be switched between an open state, which allows the game ball to enter the special pattern 2 starting hole G43, and a closed state, which makes it difficult or impossible for the game ball to enter the special pattern 2 starting hole G43, by operating the movable piece G45a.

[0459] Above the special symbol 2 start port G43 in the right game area G37b, a normal symbol start port G47 through which the game ball can pass is provided. This normal symbol start port G47 is a gate related to the variable display operation of the normal symbol in the main display G63.

[0460] A large prize opening G49 is provided below the special symbol 2 starting opening G43 in the right game area G37b. The large prize opening G49 is controlled to open and close by a special electric device G51. By operating the movable piece G51a, the special electric device G51 can be switched between an open state that allows the game ball to enter the large prize opening G49 and a closed state that makes it difficult or impossible for the game ball to enter the large prize opening G49.

[0461] In addition, a plurality of winning holes G53 are provided on the left and right lower sides of the game area G37. In addition, an outlet G55 is provided at the center lower end of the game area G37, and game balls that do not enter any of the winning holes are discharged from the game area G37 through the outlet G55.

[0462] In addition, only game balls that have flowed down the left game area G37a can enter the special pattern 1 starting hole G41, but game balls that have flowed down the right game area G37b may also be able to enter the special pattern 1 starting hole G41. In addition, only game balls that have flowed down the right game area G37b can enter the special pattern 2 starting hole G43, the normal pattern starting hole G47 and the big prize hole G49, but game balls that have flowed down the left game area G37a may be able to enter or pass through them.

[0463] In the gaming machine GMB, when a game ball enters one of the various winning holes provided in the game area G37, the number of prize balls set for the winning hole into which the game ball entered is paid out (for example, 3 balls for the special pattern 1 starting hole G41, 1 ball for the special pattern 2 starting hole G43, 15 balls for the large winning hole G49, and 5 balls for the winning hole G53).

[0464] In the area surrounded by the center decoration G39 in the center of the game board G9, an LCD unit (liquid crystal display device) G57 and an illumination panel G59 are provided. The LCD unit G57 displays, for example, three decorative patterns G201a to G201c (see FIG. 42) in a variable or stationary manner, and displays various images (still images and moving images) for performance, according to the control of the performance control board G120 described later. The decorative symbols G201 are provided in a number of different types including different numbers and symbols, and the result of a big win lottery, which will be described later, is notified to the player based on the combination of the three decorative symbols G201a to G201c that are stopped and displayed.

[0465] The illumination panel G59 is made of a plate-shaped transparent synthetic resin material, and is disposed facing the LCD unit G57 on the player side (front side) of the LCD unit G57. The illumination panel G59 has predetermined patterns such as letters, figures, symbols, and designs formed by uneven processing on the front or back surface. When light is not incident on the illumination panel G59 from the side, the patterns are invisible or difficult to see, but when light is incident on the side, the patterns emit diffuse light and become visible to the player.

[0466] A space is formed between the LCD unit G57 and the illumination panel G59, and one or more movable body parts G61 are arranged in this space. Figure 37 illustrates one of the multiple movable body parts G61. The movable device G61 is positioned in front of the LCD unit G57, and is normally retracted to a position where it cannot be seen by the player, as shown by the dashed line in FIG. As shown by the solid line in Figure 37, the movable device G61 is driven by the movable motor G61a (see Figure 41) while the decorative pattern G201 is being displayed in a varying manner (while special patterns 1 and 2 are being displayed in a varying manner), and moves to the front of the LCD unit G57, giving the player the expectation of a jackpot.

[0467] A main display G63 made of a dot display is provided in the non-play area at the lower left of the game board G9. Also, a fourth symbol display G65 made of a dot display is provided at the lower right of the LCD unit G57 in the game board G9.

[0468] Fig. 39 is a diagram explaining the main display G63 and the fourth symbol display G65. The main display G63 is controlled by the main control board G100, and displays (notifies) information regarding the progress of the game by turning on, blinking, and turning off the LED. In the following, the turning on, blinking, and turning off of the LED will be collectively referred to as "lighting display." As shown in Fig. 39(a), the main display G63 is provided with a special symbol 1 display G63a for performing the variable display operation (lighting display) of the special symbol 1, a special symbol 2 display G63b for performing the variable display operation of the special symbol 2, and a normal symbol display G63c for performing the variable display operation of the normal symbol. In addition, the main display G63 is provided with a special symbol 1 reserved number display G63d for displaying the reserved number of special symbol 1, a special symbol 2 reserved number display G63e for displaying the reserved number of special symbol 2, a normal symbol reserved number display G63f for displaying the reserved number of normal symbols, a round display G63g for displaying the prescribed number of rounds (maximum number of rounds) related to the jackpot, a game status display G63h for displaying the game status (time-saving status, high probability status), and a right-hit display G63i for encouraging the player to hit right. In addition, right hitting means that the player operates the handle G19a to launch the game ball toward the right game area G37b. The right hitting indicator G63i is an indicator for informing the player that it is more advantageous for the player to launch the game ball toward the right game area G37b than to launch the game ball toward the left game area G37a.

[0469] The fourth symbol display G65 is controlled by the performance control board G120, and notifies information regarding the progress of the game by lighting up an LED. As shown in Fig. 39(b), the fourth symbol display G65 is provided with a special symbol 1 display G65a in which the variable display operation of the special symbol 1 is performed, and a special symbol 2 display G65b in which the variable display operation of the special symbol 2 is performed. In addition, the fourth symbol display G65 is provided with a special symbol 1 reserved number display G65c in which the reserved number of special symbol 1 is displayed, a special symbol 2 reserved number display G65d in which the reserved number of special symbol 2 is displayed, and a right hit display G65e in which the player is prompted to hit right.

[0470] [3.2 Control configuration of the gaming machine in the third embodiment] 40 and 41 are block diagrams showing the control configuration of the gaming machine GMB. The control configuration of the gaming machine GMB will be described with reference to the block diagrams of FIG. The gaming machine GMB of this embodiment is mainly composed of a main control board G100 that is responsible for overall control related to the progress of the game (gaming operation control), a frame control board G110 that is responsible for overall control related to the management of the number of gaming balls (prize balls) and control related to the management of the gaming balls (launching, circulation), a presentation control board G120 that receives presentation control commands from the main control board G100 and is responsible for overall control of the execution of presentations by the presentation means, a power supply board G130 that generates and supplies the power supply voltage required for the gaming machine GMB from an external power source, a gaming ball etc. lending device connection terminal board G140 that is connected to the gaming ball etc. lending device, a decorative relay board G150 on which components related to the presentation means are mounted or connected, a front frame relay board G160, an upper decorative board G170, and a decorative board G180.

[0471] (3.2.1 Main control board) The main control board G100 includes a main control unit G101 and a system reset circuit G103. The main control unit G101 is a microprocessor including a CPU (Central Processing Unit), a ROM (Read Only Memory), and an RWM (Read / Write Memory). The ROM stores control programs for controlling game operations as well as various data required for game operation control. The RWM functions as a work area and buffer memory. The CPU controls game operations by executing control programs stored in the ROM.

[0472] The system reset circuit G103 detects when the power is turned on, when the power is turned off, or when there is a power abnormality, and outputs a system reset signal to reset the main control unit G101. Although not shown in the figure, the main control unit G101 also includes a CTC (Counter Timer Circuit) for implementing periodic interrupts, a constant-period pulse output creation function (bit rate generator), and a time measurement function, an interrupt controller circuit that performs interrupt enable / disable functions such as timer interrupts that issue interrupt signals, a watchdog timer (WDT) circuit that monitors for abnormal operation of the control program, an IAT (Inhibit Running Outside Designated Area) circuit that monitors whether the program is being executed correctly within a pre-set address range, and a counter circuit (random number generation circuit) for generating random numbers within a certain range (hard random number values) in a hardware manner.

[0473] The counter circuit includes a random number generating circuit that generates random numbers, and a sampling circuit that samples random numbers from the random number generating circuit at a predetermined timing, and functions as a 16-bit counter as a whole. The main control unit G101 sends instructions to the sampling circuit according to the processing state, thereby obtaining the number indicated by the random number generating circuit as a random number for jackpot determination (0 to 65535), and uses the random number for jackpot determination in the jackpot lottery. Note that the random number for jackpot determination is obtained by adding a software random number generated by appropriate software processing and a hard random number to prevent cheating such as aiming for a jackpot.

[0474] The main control board G100 is connected to a special symbol 1 start port switch G41a that detects the entry of a game ball into the special symbol 1 start port G41, a special symbol 2 start port switch G43a that detects the entry of a game ball into the special symbol 2 start port G43, a normal symbol start port switch G47a that detects the passage of a game ball into the normal symbol start port G47, a prize port switch G53a that detects the entry of a game ball into the prize port G53, and a large prize port switch G49a that detects the entry of a game ball into the large prize port G49. The detection signals output from these are input to the main control unit G101. Therefore, the main control unit G101 can grasp which prize port the game ball entered (passed) based on the detection signals from each switch.

[0475] In addition, the main control board G100 is connected to a large prize opening solenoid G51b that operates the special electric role G51 (movable piece G51a) that opens and closes the large prize opening G49, and a normal electric role solenoid G45b that operates the normal electric role G45 (movable piece G45a) that opens and closes the special symbol 2 start opening G43. The main control unit G101 outputs a control signal for controlling these solenoids.

[0476] The game board G9 is also provided with a magnetic sensor G67 for detecting magnetism, a radio wave sensor G69 for detecting radio waves, and a vibration sensor G71 for detecting vibrations, and these sensors are connected to the main control board G100. Signals from these sensors are input to the main control unit G101.

[0477] In addition, the main display G63 is connected to the main control board G100. The main control unit G101 outputs a control signal for turning on and displaying the main display G63.

[0478] The main control board G100 is connected to the frame control board G110 so that they can communicate with each other. The main control board G100 (main control unit G101) mainly transmits control commands including information about winning balls and launch control signals indicating whether or not game balls can be launched to the frame control board G110. The main control board G100 also receives a door open signal indicating the opening of the front frame G7, an RWM clear signal for clearing the RWM, a power supply abnormality signal indicating a power supply abnormality, and a frame communication confirmation signal for confirming communication from the frame control board G110. Furthermore, the main control board G100 receives drive power (DC35VA, DC12VA, DC5VA, backup power) from the frame control board G110.

[0479] The main control board G100 transmits various performance control commands, including information on the special symbol variable display game and information on errors, to the performance control board G120. However, in order to prevent fraud such as cheating, the main control board G100 only transmits signals to the performance control board G120, and is configured for one-way communication in which it cannot receive signals from the performance control board G120.

[0480] (3.2.2 Frame control board) The frame control board G110 is equipped with a frame control unit G111, an RWM clear switch G112a, a game ball count clear switch G112b, a ball removal switch G112c, an error release switch G112d, a performance indicator G113, a system reset circuit G114, a power supply abnormality signal generating circuit G115, a launch control circuit G116 and a backup power supply generating circuit G117.

[0481] The frame control unit G111 is a microprocessor equipped with a CPU, a ROM, and a RWM. The ROM stores control programs for managing the number of game balls, controlling the launching device G31 and the lifting device G33, and various data required for these controls. The RWM functions as a work area and a buffer memory. The CPU executes the control programs stored in the ROM to manage the number of game balls, control the launching device G31 and the lifting device G33, and the like.

[0482] The RWM clear switch G112a, the game ball count clear switch G112b, the ball removal switch G112c, and the error reset switch G112d are push button type switches. If the RWM clear switch G112a is pressed when the power is turned on, the frame control unit G111 clears the RWM and sends an RWM clear signal to the main control board G100. The main control unit G101 that receives the RWM clear signal clears a predetermined area of ​​the RWM.

[0483] If the game ball count clear switch G112b is pressed when the power is turned on, the frame control unit G111 clears the game ball count that it manages. When the game ball count is cleared, 0 is displayed on the game ball count display G21.

[0484] When the ball removal switch G112c is pressed when the power is turned on, the frame control unit G111 performs a ball removal process to discharge the game balls enclosed in the gaming machine GMB to the outside. Specifically, the frame control unit G111 drives the lifting motor G33a on the condition that the lifting inlet switch G33f described later detects the game balls.

[0485] If the error reset switch G112d is pressed when a specific error occurs, the frame control unit G111 resets the specific error that has occurred.

[0486] The performance indicator G113 is composed of, for example, a 6-digit 8-segment (7-segment + 1-dot) indicator. The performance indicator G113 is controlled by the frame control unit G111, and displays game performance information calculated based on game results over a predetermined period (for example, every 6000 games). The game performance information includes continuous role ratio, role ratio, base, etc. The continuous role ratio is the ratio of the number of prize balls that have won the large prize opening G49 to the total number of prize balls. The role ratio is the ratio of the number of prize balls that have won the special pattern 2 start opening G43 and the number of prize balls that have won the large prize opening G49 to the total number of prize balls. The base is the ratio of the total number of prize balls to the number of game balls that have been shot out. In addition, the performance display G113 can switch and display the game performance information for each predetermined period (each section).

[0487] The system reset circuit G114 detects when the power is turned on, when the power is turned off, or when there is a power abnormality, and outputs a system reset signal to reset the frame control unit G111.

[0488] The power supply abnormality signal generating circuit G115 monitors voltage drops of the drive power supply (5V DC voltage (DC5VA), 12V DC voltage (DC12VA)) supplied from the power supply board G130, and outputs a power supply abnormality signal to the main control unit G101 when the voltage falls below a predetermined threshold. The power supply abnormality signal generating circuit G115 may also monitor voltage drops of 24V AC voltage (AC24V).

[0489] The launch control circuit G116 controls the launch of game balls from the launch device G31 by controlling the drive of the launch device G31 (ball feed solenoid G31a, launch solenoid G31b).

[0490] The backup power generation circuit G117 generates a backup power (VBB) to be supplied to the RWM of the main control unit G101 and the frame control unit G111 when the power is cut off. The RWM of the main control unit G101 and the frame control unit G111 that receives the backup power (VBB) can hold (back up) the stored data for a certain period of time even when the power is cut off.

[0491] A door opening sensor G73 provided on the inner frame G5 is connected to the frame control board G110. When the door opening sensor G73 detects at least one of the fact that the front frame G7 is opened relative to the inner frame G5 and the fact that the inner frame G5 is opened relative to the outer frame G3, it outputs a door opening signal to the main control board G100 via the frame control board G110.

[0492] The circulation mechanism G30 provided in the inner frame G5 is provided with a lifting motor G33a, an out ball switch G33b, a foul ball switch G33c, an excess position detection switch G33d, an insufficient position detection switch G33e, a lifting inlet switch G33f, a lifting outlet switch G33g, and a lifting position detection switch G33h, which are connected to the frame control board G110.

[0493] The circulation mechanism G30 is formed with a pre-lifting path along which game balls discharged from the game area G37 are guided, a lifting path along which game balls that have passed through the pre-lifting path are lifted, and a post-lifting path along which game balls lifted up by the lifting path are guided to the launching device G31. In the circulation mechanism G30, the game ball discharged from the game area G37 is guided to the bottom end of the lifting path through the pre-lifting path. The game ball guided to the bottom end of the lifting path is lifted upward in the lifting path by the lifting device G33. Then, the game ball that reaches the top end of the lifting path is sent to the post-lifting path and then guided to the launching device G31 through the post-lifting path.

[0494] The lifting motor G33a is controlled by the frame control unit G111 and rotates a lifting part, which is, for example, a spiral member, arranged in the lifting path. The rotated lifting part guides the game balls that have reached the downstream end of the pre-lifting path to the lifting path, and lifts the game balls that are retained in the lifting path upward. In addition, it sends the game balls from the top end of the lifting path to the post-lifting path.

[0495] The out ball switch G33b, the foul ball switch G33c, the excessive position detection switch G33d, the insufficient position detection switch G33e, the lifting inlet switch G33f, and the lifting outlet switch G33g are switches that detect game balls, and when a game ball is detected, they output a detection signal to the frame control board G110 (frame control unit G111).

[0496] The out ball switch G33b is disposed upstream of the pre-lifting path and detects a game ball (out ball) that is discharged from the game area G37 and guided to the pre-lifting path. The foul ball switch G33c is arranged on a foul ball junction path connected between the positions where the out ball switch G33b and the excess position detection switch G33d are respectively arranged on the pre-lifting path, and detects game balls among those launched from the launching device G31 that do not reach the playing area G37 and are returned to the pre-lifting path through the foul ball junction path.

[0497] The excessive position detection switch G33d and the insufficient position detection switch G33e are disposed downstream of the out ball switch G33b on the pre-lift path at a predetermined distance, and detect game balls remaining in the pre-lift path. The excessive position detection switch G33d is disposed upstream of the insufficient position detection switch G33e on the pre-lift path. Then, when the power is turned on, if the over-position detection switch G33d does not detect any game balls and the under-position detection switch G33e detects game balls, that is, if there are game balls at the position where the under-position detection switch G33e is located and there are no game balls at the position where the over-position detection switch G33d is located, the frame control unit G111 de...

Claims

[Claim 1] A CPU means for generating first information specifying an image presentation by the display device and second information specifying an audio presentation; A transfer means for transferring the first information and the second information to the first circuit and the second circuit via a predetermined transmission path, A gaming machine, characterized in that the transmission path for the first information and / or the transmission path for the second information is configured so that one transmission circuit can be selected from a plurality of options.

Images