Imaging device, imaging system and moving device

Abstract

To provide a technique advantageous for improving N / S ratio.SOLUTION: A photoelectric conversion device includes: a photoelectric conversion element; a first node to which charge from the photoelectric conversion element is supplied; an amplification transistor for outputting a signal according to the voltage at the first node; a first transistor for opening / closing a path between a second node not included in a path from the photoelectric conversion element to the first node and the first node; and a second transistor for opening / closing a path between the second node and a third node, wherein a second capacitance added to the second node by conducting the second transistor is larger than a first capacitance added to the first node by conducting the first transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an imaging device, an imaging system, and a moving object. [Background technology]

[0002] Patent Document 1 discloses a configuration having a first capacitance-added transistor, one end of which is connected to a floating diffusion section (hereinafter, FD section) and the other end of which is connected to a reset transistor, in order to expand the dynamic range of an imaging device. Patent Document 1 also discloses a configuration having a second capacitance-added transistor between the reset transistor and the first capacitance-added transistor. Patent Document 1 further discloses a configuration in which an intermediate voltage between a high level and a low level is applied to the reset transistor, the first capacitance-added transistor, or the second capacitance-added transistor in order to suppress the voltage amplitude of the FD section according to a high luminance signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Application No. 2019-111594 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one aspect of the present disclosure is to provide a technique that is advantageous for improving the S / N ratio.

[0005] Another object of the present disclosure is to provide a technique that is advantageous for expanding the dynamic range and improving linearity. [Means for solving the problem]

[0006] One aspect of the present disclosure relates to a photoelectric conversion device including a photoelectric conversion element, a first node to which charge is supplied from the photoelectric conversion element, an amplifying transistor that outputs a signal corresponding to a voltage of the first node, a second node not included in a path from the photoelectric conversion element to the first node, a first transistor that opens and closes a path between the first node, and a second transistor that opens and closes a path between the second node and a third node, wherein a second capacitance added to the second node by the second transistor being conductive is greater than a first capacitance added to the first node by the first transistor being conductive.

[0007] Another aspect of the present disclosure relates to a photoelectric conversion device including a photoelectric conversion element, a first node to which charge is supplied from the photoelectric conversion element, an amplifying transistor to output a signal corresponding to a voltage of the first node, a first transistor to open and close a path between the first node and a second node not included in a path from the photoelectric conversion element to the first node, a second transistor to open and close a path between the second node and a third node, and a third transistor arranged in a path between the third node and a fourth node, wherein a fixed potential is applied to a gate of the third transistor to cause the third transistor to be conductive.

[0008] Another aspect of the present disclosure relates to a photoelectric conversion device including a photoelectric conversion element, a first node to which charge is supplied from the photoelectric conversion element, an amplifying transistor that outputs a signal corresponding to a voltage of the first node, a first transistor that opens and closes a path between the first node and a second node that is not included in a path from the photoelectric conversion element to the first node, and a second transistor that opens and closes a path between the second node and a third node, and a third transistor arranged in a path between the third node and a fourth node, wherein a third capacitance added to the third node by the third transistor being conductive is greater than a second capacitance added to the second node by the second transistor being conductive. Effect of the Invention

[0009] According to an aspect of the present disclosure, there is provided a technique that is advantageous for improving the S / N ratio.

[0010] According to another aspect of the present disclosure, a technique advantageous for expanding the dynamic range and improving linearity is provided. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing the configuration of an imaging device according to first to third embodiments. [Diagram 2] FIG. 4 is an equivalent circuit diagram showing the configuration of a pixel of a comparative example. [Diagram 3] FIG. 4 is an equivalent circuit diagram showing the configurations of pixels according to another comparative example and the first embodiment. [Figure 4] FIG. 4 is a plan view showing the configuration (layout) of pixels of a comparative example, another comparative example, and the first embodiment. [Diagram 5] FIG. 2 is a diagram for explaining the first embodiment. [Figure 6] FIG. 2 is a diagram for explaining the first embodiment. [Figure 7] FIG. 2 is a diagram for explaining the first embodiment. [Figure 8] FIG. 11 is a diagram for explaining an imaging apparatus according to a second embodiment. [Figure 9] FIG. 13 is a diagram showing the configuration of a pixel according to a second embodiment. [Figure 10] FIG. 11 is a plan view showing the configuration (layout) of a pixel according to a second embodiment. [Figure 11] FIG. 11 is an equivalent circuit diagram showing the configuration of a pixel according to a third embodiment. [Figure 12] FIG. 13 is a plan view showing the configuration (layout) of a pixel according to a third embodiment. [Figure 13] FIG. 11 is a diagram for explaining an imaging device according to a third embodiment. [Figure 14] FIG. 1 is a diagram showing a configuration of a photoelectric conversion system according to an embodiment. [Figure 15] 1 is a diagram showing the configuration of a vehicle system according to an embodiment and a photoelectric conversion system mounted thereon for performing imaging; [Figure 16] 16 is a diagram showing the operation of the photoelectric conversion system of FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0013] FIG. 1 shows a schematic configuration of an imaging device 1 of the first embodiment. The imaging device 1 may include, for example, a pixel array 100, a vertical scanning circuit 101, an amplifier circuit 102, a horizontal scanning circuit 103, an output circuit 104, and a control circuit 105. The pixel array 100 may include a plurality of pixels 20 arranged to form a plurality of rows and a plurality of columns. The vertical scanning circuit 101 may be configured to select the plurality of pixels 20 on a row-by-row basis. The vertical scanning circuit 101 may be configured to drive a plurality of control lines that control the pixels 20 in each row. The vertical scanning circuit 101 may include, for example, logic circuits such as a shift register and / or an address decoder. A vertical output line 10 is provided in each column of the pixel array 100, and pixel signals from the pixels 20 may be output to the vertical output line 10 for each column. The amplifier circuit 102 may amplify the pixel signals output to each vertical output line 10, and perform correlated double sampling processing based on the signal at the time of reset and the photoelectrically converted signal. The amplifier circuit 102 may include, for example, a plurality of column amplifiers corresponding to the plurality of vertical output lines 10 of the pixel array 100, respectively. The horizontal scanning circuit 103 selects the outputs of the plurality of column amplifiers of the amplifier circuit 102 in a predetermined order and supplies them to the output circuit 104. The output circuit 104 may be composed of, for example, a differential amplifier and a buffer amplifier, and may output the pixel signal supplied from the amplifier circuit 102 to an external or internal device (for example, a processor) of the imaging device 1. The imaging device 1 may include an AD conversion unit. The pixel array 100 may be composed of a plurality of pixels 20 arranged one-dimensionally. Alternatively, the pixel array 100 may be replaced with a single pixel 20.

[0014] FIG. 2 is an equivalent circuit diagram showing a configuration of a pixel 20A of a comparative example. FIG. 2 shows three pixels 20A in one row and three columns among a plurality of pixels 20A two-dimensionally arranged in the pixel array 100 to form a plurality of rows and a plurality of columns, but the pixel array 100 may be composed of more pixels 20A. Each pixel 20A may include a photodiode (hereinafter, PD) 201 as a photoelectric conversion element, a transfer transistor 202, and a floating diffusion 203 (hereinafter, referred to as FD203 or first node n1) functioning as a charge-voltage conversion unit. Each pixel 20A may also include a reset transistor 204, an amplification transistor 205, and a selection transistor 206. A first electrode (e.g., an anode) of the PD 201 may be connected to a first voltage line (e.g., a ground line) 208. A second electrode (e.g., a cathode) of the PD 201 may be connected to the FD 203 via the transfer transistor 202. In other words, the transfer transistor 202 transfers charges from the PD 201 to the FD 203. The transfer transistor 202 can transfer charges from the PD 201 to the FD 203 when a transfer signal Φ202(n) supplied to the gate of the transfer transistor 202 from the vertical scanning circuit 101 via a transfer signal line becomes active. The transfer transistor 202 is an optional component and may be omitted.

[0015] The reset transistor 204 can reset the voltages of the FD 203 and the second electrodes (e.g., cathodes) of the PD 201 when a reset signal Φ204(n) supplied to its gate from the vertical scanning circuit 101 via a reset signal line becomes active. The amplification transistor 205 can output a signal corresponding to the voltage of the FD 203 to the vertical output line Vout. The amplification transistor 205 can configure a source follower circuit together with a current source (not shown) connected to the vertical output line Vout. The vertical output line Vout is the vertical output line 10 in FIG. 1. In FIG. 2, Vout is given a subscript such as Vout(m-1), Vout(m), and Vout(m+1) to identify the column. The selection transistor 206 electrically connects the amplification transistor 205 to the vertical output line Vout when a selection signal Φ206(n) supplied to its gate from the vertical scanning circuit 101 via a selection signal line becomes active. The selection transistor 206 is an optional component and may be omitted. In this case, the selected state and the non-selected state of the pixel 20 can be distinguished by the voltage set to the FD 203 at the time of reset.

[0016] The pixel 20A further includes a first transistor 210 in a path between the first node n1 (FD203) and the second node n2 or the reset transistor 204. The second node n2 is a node that is not included in the path from the PD201 to the first node n1. The first transistor 210 may have a first electrode (e.g., drain) connected to the first node n1 or the FD203, and a second electrode (e.g., source) connected to the second node n2 or a first electrode (e.g., drain) of the reset transistor 204. The first transistor 210 functions as a capacitance-adding transistor that adds capacitance to the first node or the FD203 (capacitance). The capacitance that is added to the first node or the FD203 (capacitance) by the first transistor 210 being conductive (ON) is called the capacitance (first capacitance) of the first transistor 210. The first transistor 210 is made conductive when a sensitivity control signal Φ210(n) supplied to the gate of the first transistor 210 from the vertical scanning circuit 101 via a sensitivity control line becomes active level. When the capacitance of the first transistor 210 is added to the first node n1 or FD203 (the capacitance of the FD203), the capacitance of the first node n1 or FD203 itself and the capacitance of the first transistor 210 function as a charge-voltage converter, so that the sensitivity of converting charge into voltage decreases.

[0017] The first transistor 210 may be arranged in parallel with the reset transistor 204, but in that case, the parasitic capacitance of the FD 203 increases even when the first transistor 210 is not conductive, and the sensitivity of converting charge into voltage decreases. Therefore, it is preferable that the first transistor 210 and the reset transistor 204 are connected in series to the FD 203.

[0018] When light is incident on the PD 201, photoelectric conversion occurs in the PD 201, and the charge generated thereby can be accumulated in a charge accumulation region of the PD 201. When a transfer signal Φ202(n) becomes active level, the transfer transistor 202 becomes conductive and transfers the charge of the PD 201 to the FD 203. The amplification transistor 205 forms a source follower circuit and can output a signal according to the voltage of the FD 203 to the vertical output line 10 via the selection transistor 206.

[0019] When the first transistor 210 is in a non-conductive state (off state), the charge transferred from the PD 201 by the transfer transistor 202 is held only by the capacitance of the FD 203. On the other hand, when the first transistor 210 is in a conductive state (on state), the charge transferred from the PD 201 by the transfer transistor 202 is held by the capacitance of the FD 203 and the capacitance of the first transistor 210. In other words, by controlling the first transistor 210, it is possible to change the capacitance for holding the charge transferred from the PD 201 by the transfer transistor 202. By simultaneously making the reset transistor 204 and the first transistor 210 conductive, it is possible to reset the voltage of the FD 203 to a voltage corresponding to the voltage of the first voltage line 209.

[0020] A common control signal is supplied from the vertical scanning circuit 101 to the pixels 20A in the same row. That is, control signals Φ202(n), Φ204(n), Φ206(n), and Φ210(n) are supplied to the transfer transistor 202, reset transistor 204, selection transistor 206, and first transistor 210 in the nth row, respectively. These transistors are turned on when the control signal is at a high level, and turned off when the control signal is at a low level. The first transistor 210 can connect the first capacitance to the FD 203 while Φ210(n) is at a high level.

[0021] Here, the first transistor 210 will be described in more detail. One electrode (source) of the first transistor 210 is connected to the FD 203. When the first transistor 210 is in a conductive state, a channel is formed in the first transistor 210, and the capacitance (MOS capacitance) of this channel is added to the capacitance of the FD 203. Furthermore, the capacitance parasitic to the other electrode (drain) of the first transistor 210, for example, the capacitance between the gate electrode and the other electrode (drain), the PN junction capacitance of the semiconductor region constituting the other electrode, and the capacitance between the surrounding wiring are added to the capacitance of the FD 203. The capacitance added to the FD 203 increases the capacitance of the charge-voltage conversion unit, and the charge that can be held in the charge-voltage conversion unit increases, and the dynamic range is expanded. Also, when the first transistor 210 is in a non-conductive state, the capacitance of the first transistor 210 is not added to the FD 203. In this case, the sensitivity of the FD 203 or the pixel 20A (for example, the amount of voltage change for one charge (charge-voltage conversion efficiency)) can be increased. Therefore, by controlling the first transistor 210, the sensitivity of the pixel 20A can be changed.

[0022] FIG. 3 is an equivalent circuit diagram showing the configuration of a pixel 20B of another comparative example and a pixel 20C of the first embodiment. The pixel 20B and the pixel 20C have the same configuration in the equivalent circuit. The pixel 20B and the pixel 20C have a configuration in which a second transistor 211 is added to the pixel 20A. The second transistor 211 is made conductive when a sensitivity control signal Φ211(n) supplied to the gate of the second transistor 211 from the vertical scanning circuit 101 via a sensitivity control line becomes active level. As described above, when the first transistor 210 is made conductive, the capacitance of the first transistor 210 (first capacitance) is added to the capacitance of the first node n1 or the FD203. In addition, when the second transistor 211 is made conductive while the first transistor 210 is in a conductive state, the capacitance of the second transistor 211 (second capacitance) is also added to the capacitance of the FD203 in addition to the capacitance of the first transistor 210. Here, the capacitance of the second transistor 211 is the capacitance added to the second node n2 when the second transistor 211 is conductive.

[0023] The pixel 20B and the pixel 20C include a PD 201 as a photoelectric conversion element, a first node n1 (FD 203) to which an electric charge is supplied from the PD 201, and an amplifier transistor 205 that outputs a signal according to the voltage of the first node n1. The pixel 20B and the pixel 20C may also include a first transistor 210 that opens and closes a path between the first node n1 and a second node n2, and a second transistor 211 that opens and closes a path between the second node n2 and a third node n3. The pixel 20B and the pixel 20C may also include a transfer transistor 202, a reset transistor 204, and a selection transistor 206.

[0024] The transfer transistor 202 can transfer charges from the PD201 to the first node n1 (FD203) when a transfer signal Φ202(n) supplied to its gate from the vertical scanning circuit 101 via a transfer signal line becomes active. The transfer transistor 202 is an optional component and may be omitted. The reset transistor 204 can reset the voltages of the first node n1 (FD203) and the second electrode of the PD201 when a reset signal Φ204(n) supplied to its gate from the vertical scanning circuit 101 via a reset signal line becomes active. The selection transistor 206 can electrically connect the amplification transistor 205 to the vertical output line Vout when a selection signal Φ206(n) supplied to its gate from the vertical scanning circuit 101 via a selection signal line becomes active. The selection transistor 206 is an optional component and may be omitted. In this case, the selected state and the non-selected state of the pixel 20 can be distinguished by the voltage set in the FD203 at the time of reset.

[0025] By providing the first transistor 210 and the second transistor 211, the capacitance of the charge-voltage conversion unit including the FD203 can be changed in three stages. That is, the capacitance of the charge-voltage conversion unit can be selected from three stages of capacitance. The capacitance of the first stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 is in a non-conductive state (i.e., the capacitance of only the FD203). The capacitance of the second stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 is in a conductive state and the second transistor 211 is in a non-conductive state (i.e., the sum of the FD203 and the first capacitance of the first transistor 210). The capacitance of the third stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 and the second transistor 211 are in a conductive state (i.e., the sum of the FD203, the first capacitance of the first transistor 210, and the second capacitance of the second transistor 211).

[0026] The configurations of pixel 20A (comparative example), pixel 20B (another comparative example), and pixel 20C will be described with reference to Fig. 4. Fig. 4(a) shows the configuration of pixel 20A, Fig. 4(b) shows the configuration of pixel 20B, and Fig. 4(c) shows the configuration of pixel 20C. Pixel 20A only has a first transistor 210 as a transistor for controlling the capacitance of the charge-voltage conversion section. On the other hand, pixel 20B and pixel 20C have a first transistor 210 and a second transistor 211 as transistors for controlling the capacitance of the charge-voltage conversion section.

[0027] The difference between the pixel 20B and the pixel 20C is the magnitude relationship of the capacitance between the first transistor 210 and the second transistor 211. In the pixel 20B, the capacitance of the first transistor 210 is larger than that of the second transistor 211, but in the pixel 20C, the capacitance of the second transistor 211 is larger than that of the first transistor 210. Here, the capacitances of the first transistor 210 and the second transistor 211 may be proportional to their gate lengths. In the pixel 20B, the gate length of the first transistor 210 is longer than that of the second transistor 211, but in the pixel 20C, the gate length of the second transistor 211 is longer than that of the first transistor 210. In the pixels 20B and 20C, the gate width of the first transistor 210 is equal to the gate width of the second transistor 211, but the gate width of the first transistor 210 and the gate width of the second transistor 211 may be different from each other.

[0028] 5 illustrates the capacitances of the FD203, the first transistor 210, and the second transistor 211 in the pixels 20A, 20B, and 20C. In the example of FIG. 5, the capacitance of the FD203 of the pixel 20A is 0.25 [F], the capacitance of the first transistor 210 is 0.75 [F], and the sum of these is 1 [F]. The capacitance of the FD203 of the pixel 20B is 0.25 [F], the capacitance of the first transistor 210 is 0.50 [F], and the sum of these is 1 [F]. Furthermore, the capacitance of the FD203 of the pixel 20C is 0.25 [F], the capacitance of the first transistor 210 is 0.25 [F], and the capacitance of the second transistor 211 is 0.50 [F], and the sum of these is [F]. 5 shows an example of a pixel 20B in which the capacitance of the first transistor 210 is larger than the capacitance of the second transistor 211, and an example of a pixel 20C in which the capacitance of the second transistor 211 is larger than the capacitance of the first transistor 210. In FIG.

[0029] FIG. 6 illustrates the gain, the number of signal charges, the capacity of the charge-voltage conversion unit, the number of noise charges of the charge-voltage conversion unit, the signal output (S), the noise output (N), and the N / S ratio in the pixels 20A, 20B, and 20C. The gain of column a is the gain of the imaging device 1 (here, the gain is [times]). The number of signal charges of column b is the number of signal charges (here, the charge is electrons) required to output a saturation signal according to the gain. Here, the saturation signal is the upper limit of the output in the captured image according to each gain. If the number of signal charges required when the gain is 1 [times] is 1000 [electrons], the number of signal charges required when the gain is 2 [times] is 500 [electrons]. The capacity of column c is the optimal capacity (here, farads [F]) of the charge-voltage conversion unit that can be selected to convert the number of signal charges shown in column b into a voltage. It is shown that if the number of signal charges is 1000 [electrons], the optimal capacity of the charge-voltage conversion unit is 1 [F].

[0030] For pixel 20A, when the gain is 2[x], the capacitance of the charge-voltage conversion unit can be 0.5[F], which is half that of the gain of 1[x], but since the capacitance of the first transistor 210 is 0.75[F] as shown in Fig. 5, it cannot be turned off. When the gain is 4[x], the capacitance of the charge-voltage conversion unit can be 0.25[F], which is 1 / 4 that of the gain of 1[x], and the first transistor 210 can be turned off.

[0031] For pixel 20B, when the gain is 2[x], the capacitance of the charge-voltage conversion unit can be 0.5[F], which is 1 / 2 the capacitance when the gain is 1[x], and since the capacitance of second transistor 211 is 0.25[F] as shown in Fig. 5, it is possible to turn off second transistor 211. When the gain is 4[x], the capacitance of the charge-voltage conversion unit can be 0.25[F], which is 1 / 4 the capacitance when the gain is 1[x], and it is possible to turn off first transistor 210.

[0032] For pixel 20C, when the gain is 2[x], the capacitance of the charge-voltage conversion unit can be 0.5[F], which is 1 / 2 the capacitance when the gain is 1[x], and since the capacitance of second transistor 211 is 0.50[F] as shown in Fig. 5, it is possible to turn off second transistor 211. When the gain is 4[x], the capacitance of the charge-voltage conversion unit can be 0.25[F], which is 1 / 4 the capacitance when the gain is 1[x], and it is possible to turn off first transistor 210.

[0033] The noise charge number in column d is the number of noise charges generated in the charge-voltage conversion unit according to the capacity of the charge-voltage conversion unit shown in column c. If the noise generated when the capacity of the charge-voltage conversion unit is 1 [F] is 100 [electrons], it can be estimated that the noise generated when the capacity of the charge-voltage conversion unit is 0.5 [F] is 50 [electrons]. Here, when the gain is 2 [times], the noise charge of pixel 20A is 100 [electrons]. On the other hand, in pixel 20B, since the first transistor 210 can be turned off, the capacity of the charge-voltage conversion unit is reduced to 0.75 [F], and the noise charge is reduced to 75 [electrons]. Furthermore, pixel 20C has a larger capacity of the second transistor 211 than pixel 20B. Therefore, in pixel 20C, the capacity of the charge-voltage conversion unit is reduced to 0.50 [F] by turning off the second transistor 211, and the noise charge is reduced to 50 [electrons].

[0034] The signal output in column e is the saturation signal output (S signal) based on the gain shown in column a and the number of signal charges shown in column b. The noise output in column f is the noise output (N signal) based on the gain shown in column a and the number of noise charges shown in column d. For example, when the gain is 4x and 8x, the capacity of the charge-to-voltage conversion section is the same, so the number of noise charges does not change, but the N signal increases.

[0035] The N / S ratio in row g is the ratio of the S signal to the N signal shown in rows e and f, respectively. A small N / S ratio indicates a smaller proportion of noise in the captured image and better image quality. Here, when the gain is 2x, the N / S ratio of pixel 20B is reduced relative to pixel 20A, and the N / S ratio of pixel 20C is further reduced relative to pixel 20B.

[0036] FIG. 7 shows the N / S ratios in the pixels 20A, 20B, and 20C shown in FIG. 6. The horizontal axis shows the gain shown in column a of FIG. 6, and the horizontal axis shows the N / S ratio shown in column g of FIG. 6. As described above, when focusing on the N / S ratio at a gain of 2 times, the pixel 20B has a smaller N / S ratio than the pixel 20A, indicating good image quality, and the pixel 20C has a smaller N / S ratio than the pixel 20B, indicating even better image quality. Note that when the gain is 4 times or more, the capacitance of the charge-voltage conversion unit is the same in the pixels 20A, 20B, and 20C, so the N / S ratio does not change.

[0037] As described above, in the first embodiment, in a configuration in which the first transistor 210, the second transistor 211, and the reset transistor 204 are connected in series to the FD 203, the capacitance of the second transistor 211 is larger than the capacitance of the first transistor 210. This makes it possible to provide good image quality with a small N / S ratio.

[0038] The capacitance (capacitance value) of the first transistor 210 and the second transistor 211 can be appropriately determined by adjusting the design of the transistor and the relative arrangement with other wirings. Among them, the capacitance due to the channel formation of the transistor (MOS capacitance) has the highest capacitance density, so adjusting the area of ​​the transistor (gate) is the most efficient. On the other hand, if the area of ​​the transistor (gate) is increased, for example, the area of ​​the PD may be reduced. If the area of ​​the PD is reduced, it may cause a decrease in sensitivity or a decrease in the amount of saturation charge that can be accumulated in the PD, resulting in a decrease in the dynamic range.

[0039] The pixel 20C in FIG. 4(c) can be understood to have a structure in which the pixel 20A in FIG. 4(a) is divided into the first transistor 210, the first transistor 211, and the second transistor 211. In the pixel 20C, the area ratio of the gate of the first transistor 210 to the gate of the second transistor 211 is approximately equal to the ratio of the gate length of the first transistor 210 to the gate length of the second transistor 211. In other words, the capacitance of the second transistor 211 being larger than the capacitance of the first transistor 210 means that the gate length of the second transistor 211 is longer than the gate length of the first transistor 210. In general, a transistor exhibits a roll-off characteristic with respect to the gate length. In accordance with this, in the pixel 20C, the threshold of the first transistor 210 having a short gate length is lower than the threshold of the second transistor 211 having a long gate length.

[0040] Here, the driving and threshold value of the first transistor 210 and the second transistor 211 will be described with reference to FIG. 8. FIG. 8 shows the driving of the first transistor 210, the second transistor 211, and the reset transistor 204 in the readout operation of the pixel signal. In operation A, the sensitivity control signals Φ210 and Φ211 are at active levels (the first and second transistors 210 and 211 are on). In addition, in operation A, the reset signal Φ204 changes to a pulse shape. This resets the FD203 and the capacitances of the first and second transistors 210 and 211. In operation B, Φ210 and Φ204 are at active levels (the first transistor 210 and the reset transistor 204 are on). In addition, in operation B, Φ211 changes to a pulse shape. This resets the FD203 and the capacitances of the first transistor 210. In operation C, Φ211 and Φ204 become active levels (the second transistor 211 and the reset transistor 204 are on). Also, in operation C, Φ210 changes to a pulse shape. This resets the FD203.

[0041] In operation A, the second transistor 211 is continuously on, but when the threshold of the second transistor 211 is high, the voltage dependency of the capacitance of the second transistor 211, which depends on the operating point of the FD 203, may become large. That is, a difference may occur between the capacitance of the second transistor 211 at low luminance when the voltage of the charge-voltage conversion unit including the FD 203 is high and the capacitance of the second transistor 211 at high luminance when the voltage of the charge-voltage conversion unit is low. In this case, the charge-voltage conversion efficiency differs depending on the luminance, which may deteriorate the linearity characteristics.

[0042] On the other hand, there is a method of lowering the threshold of the second transistor 211 by adjusting the impurity concentration implanted into the channel of the second transistor 211. When the threshold of the second transistor 211 is lowered, the voltage dependency of the capacitance of the second transistor 211 is improved, but another problem may occur. In operation B, the capacitance of the FD 203 and the first transistor 210 is reset by turning on and off the second transistor 211 with a pulse-like Φ211. When the reset is completed, the second transistor 211 is turned off. At this time, if the threshold of the second transistor 211 is low, the voltage amplitude of the FD 203 may be limited. In other words, when a large amount of charge photoelectrically converted in the PD 201 in response to a high-luminance subject is transferred to the FD 203, the voltage of the FD 203 tends to decrease by an amount corresponding to the charge. However, since the second transistor 211 operates as an amplitude limiting circuit due to its low threshold, the second transistor 211 may leave the off state and operate so that the FD 203 is maintained at a voltage determined by the off leakage of the second transistor 211. Therefore, in operation B, the voltage amplitude of the FD 203 is limited, and the dynamic range may decrease.

[0043] The second embodiment is intended to solve such problems. Fig. 9 is an equivalent circuit showing the configuration of a pixel 20D of an imaging device 1 of the second embodiment. Fig. 10 shows the configuration of the pixel 20D. It should be noted that matters not mentioned in the second embodiment may follow the first embodiment. The pixel 20D of the second embodiment has a configuration in which a third transistor 212 is added to the pixel 20C of the first embodiment.

[0044] The pixel 20D includes a PD 201 as a photoelectric conversion element, a first node n1 (FD 203) to which an electric charge is supplied from the PD 201, and an amplifying transistor 205 that outputs a signal according to the voltage of the first node n1. The pixel 20D may also include a first transistor 210 that opens and closes a path between the first node n1 and a second node n2, and a second transistor 211 that opens and closes a path between the second node n2 and a third node n3. The pixel 20D may also include a third transistor 212 that opens and closes a path between the third node n3 and a fourth node n4. The pixel 20D may also include a transfer transistor 202, a reset transistor 204, and a selection transistor 206. A fixed potential that constantly makes the third transistor 212 conductive is applied to the gate of the third transistor 212. The gate of the third transistor 212 may be connected to, for example, a second voltage line 209.

[0045] It can be understood that the pixel 20D of the second embodiment has a configuration in which the second transistor 211 in the pixel 20C of the first embodiment is divided into the second transistor 211 and the third transistor 212. Since a voltage that constantly turns on the third transistor 212 is applied to the gate of the third transistor 212, it is not necessary to consider the off characteristics of the third transistor 212. In other words, the threshold of the third transistor 212 can be sufficiently low, and the voltage dependency of the capacitance of the third transistor 212, which depends on the operating point of the FD203, can be reduced. On the other hand, the threshold of the second transistor 211 can be sufficiently high, and the voltage amplitude limit of the FD203 can be relaxed. As described above, according to the second embodiment, it is possible to achieve both improvement of the linearity characteristics in the operation A and expansion of the dynamic range in the operation B.

[0046] In the second embodiment, an example in which the third transistor 212 is added has been shown, but more transistors may be added between the first node n1 and the reset transistor 204. Even in this case, a voltage that constantly turns on a transistor having one end connected to the reset transistor 204 can be applied to the gate of the transistor.

[0047] The imaging device 1 of the third embodiment will be described below. Fig. 11 is an equivalent circuit showing the configuration of a pixel 20E of the imaging device 1 of the third embodiment. Fig. 12 shows the configuration of the pixel 20E. Note that matters not mentioned as the third embodiment may follow the first embodiment. The pixel 20E of the third embodiment has a configuration in which a third transistor 212 is added to the pixel 20C of the first embodiment.

[0048] The third transistor 212 is turned on when the sensitivity control signal Φ212(n) supplied to its gate from the vertical scanning circuit 101 via a sensitivity control line becomes active level. As described above, when the first transistor 210 is turned on, the first capacitance of the first transistor 210 is added to the capacitance of the FD203. When the second transistor 211 is also turned on while the first transistor 210 is turned on, the second capacitance of the second transistor 211 is added to the capacitance of the FD203 in addition to the first capacitance of the first transistor 210. When the third transistor 212 is also turned on while the first and second transistors 210 and 211 are turned on, the third capacitance of the third transistor 212 is added to the capacitance of the FD203 in addition to the first and second capacitances of the first and second transistors 210 and 211. Here, the third capacitance of the third transistor 212 is a capacitance added to the capacitance of the FD203 by the third transistor 212 being turned on.

[0049] The pixel 20E includes a PD 201 as a photoelectric conversion element, a first node n1 (FD 203) to which electric charges are supplied from the PD 201, and an amplifying transistor 205 that outputs a signal according to the voltage of the first node n1. The pixel 20E may also include a first transistor 210 that opens and closes a path between the first node n1 and a second node n2, and a second transistor 211 that opens and closes a path between the second node n2 and a third node n3. The pixel 20E may also include a third transistor 212 that opens and closes a path between the third node n3 and a fourth node n4. The pixel 20E may also include a transfer transistor 202, a reset transistor 204, and a selection transistor 206.

[0050] By providing the first transistor 210, the second transistor 211, and the third transistor 212, the capacitance of the charge-voltage conversion unit including the FD203 can be changed in four stages. That is, the capacitance of the charge-voltage conversion unit can be selected from four stages of capacitance. The capacitance of the first stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 is in a non-conductive state. The capacitance of the second stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 is in a conductive state and the second transistor 211 is in a non-conductive state. The capacitance of the third stage is the capacitance of the charge-voltage conversion unit when the first transistor 210 and the second transistor 211 are in a conductive state and the third transistor 212 is in a non-conductive state. The capacitance of the fourth stage is the capacitance of the charge-voltage conversion unit when the first transistor 210, the second transistor 211, and the third transistor 212 are in a conductive state. It is also possible to drive the sensitivity control signal Φ212(n) to an active level all the time, and the operation in this case is the same as that of the second embodiment.

[0051] Here, the driving and threshold of the first transistor 210 and the second transistor 211 will be described with reference to FIG. 13. FIG. 13 shows the driving of the first transistor 210, the second transistor 211, the third transistor 212, and the reset transistor 204 in the readout operation of the pixel signal. In the operation A, the sensitivity control signals Φ210, Φ211, and Φ212 are at the active level (the first, second, and third transistors 210, 211, and 212 are on). In the operation A, the reset signal Φ204 changes to a pulse shape. This resets the capacitances of the FD203 and the first, second, and third transistors 210, 211, and 212. In the operation B, Φ210, Φ212, and Φ204 are at the active level (the first and third transistors 210 and 212, and the reset transistor 204 are on). In the operation B, Φ211 changes to a pulse shape. This resets the capacitance of FD203 and the first transistor 210. In operation C, Φ211 and Φ204 become active levels (the second transistor 211 and the reset transistor 204 are on). Also, in operation C, Φ210 changes to a pulse shape. This resets FD203.

[0052] The third capacitance added to the third node n3 by the third transistor 212 being conductive is preferably larger than the second capacitance added to the second node n2 by the second transistor 211 being conductive. This is advantageous for providing good image quality with a small N / S ratio. The third capacitance added to the third node n3 by the third transistor 212 being conductive is preferably larger than the first capacitance added to the first node n1 or the FD 203 by the first transistor 210 being conductive. This is advantageous for providing good image quality with a small N / S ratio.

[0053] In one example, the gate length of the third transistor 212 may be longer than the gate length of the second transistor 212, in which case the gate width of the third transistor 212 may or may not be equal to the gate width of the second transistor 212. In one example, the gate length of the third transistor 212 may be longer than the gate length of the first transistor 210, in which case the gate width of the third transistor 212 may or may not be equal to the gate width of the first transistor 210.

[0054] The threshold of the third transistor 212 can be set sufficiently low, and the threshold of the second transistor 211 can be set sufficiently high. For example, the threshold of the third transistor 212 can be set lower than the threshold of the second transistor 211. Such a configuration is advantageous for improving the linearity characteristics and the dynamic range, as described in relation to the second embodiment.

[0055] In order to increase the capacitance of the first transistor 210 and the third transistor 212, the areas of the second transistor 211 and the reset transistor 204 may be made smaller than the areas of the first transistor 210 and the third transistor 212. The areas of the second transistor 211 and the reset transistor 204 may be, for example, the same.

[0056] As illustrated in Figure 12, the first transistor 210 and the second transistor 211 may be disposed in a rectangular portion of an active region that includes a rectangular portion. Alternatively, as illustrated in Figure 12, the first transistor 210, the second transistor 211, and the third transistor 211 may be disposed in a rectangular portion of an active region that includes a rectangular portion. Alternatively, as illustrated in Figure 12, the first transistor 210, the second transistor 211, the third transistor 211, and the reset transistor 204 may be disposed in a rectangular portion of an active region that includes a rectangular portion.

[0057] As illustrated in Fig. 12, the PD201 as a photoelectric conversion element may have a polygonal shape, and the channel length directions of the first transistor 210, the second transistor 211, and the third transistor 212 may be parallel to one side of the polygon of the PD201. Alternatively, as illustrated in Fig. 12, the channel length directions of the first transistor 210, the second transistor 211, the third transistor 211, and the reset transistor 204 may be parallel to one side of the polygon of the PD201. In the example of Fig. 12, the channel length directions of the first transistor 210, the second transistor 211, the third transistor 211, and the reset transistor 204 are horizontal on the paper.

[0058] Hereinafter, an example of a photoelectric conversion system using the photoelectric conversion device of each of the above embodiments will be described.

[0059] Fig. 14 is a block diagram showing a configuration of a photoelectric conversion system 1200 according to this embodiment. The photoelectric conversion system 1200 of this embodiment includes a photoelectric conversion device 1215. Here, the photoelectric conversion device 1215 can be any of the photoelectric conversion devices described in the above embodiments. The photoelectric conversion system 1200 can be used as, for example, an imaging system. Specific examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera. Fig. 14 shows an example of a digital still camera as the photoelectric conversion system 1200.

[0060] 14 includes a photoelectric conversion device 1215, a lens 1213 that forms an optical image of a subject on the photoelectric conversion device 1215, an aperture 1214 that varies the amount of light passing through the lens 1213, and a barrier 1212 that protects the lens 1213. The lens 1213 and the aperture 1214 form an optical system that focuses light on the photoelectric conversion device 1215.

[0061] The photoelectric conversion system 1200 includes a signal processing unit 1216 that processes an output signal output from a photoelectric conversion device 1215. The signal processing unit 1216 performs signal processing operations to perform various corrections and compression on an input signal as necessary and output the signal. The photoelectric conversion system 1200 further includes a buffer memory unit 1206 for temporarily storing image data, and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. The photoelectric conversion system 1200 further includes a recording medium 1211 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading out the imaging data on the recording medium 1211. The recording medium 1211 may be built in the photoelectric conversion system 1200 or may be removable. In addition, communication between the recording medium control I / F unit 1210 and the recording medium 1211 and communication from the external I / F unit 1209 may be performed wirelessly.

[0062] Furthermore, the photoelectric conversion system 1200 has an overall control / calculation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1217 that outputs various timing signals to the photoelectric conversion device 1215 and the signal processing unit 1216. Here, the timing signals and the like may be input from the outside, and the photoelectric conversion system 1200 may have at least the photoelectric conversion device 1215 and the signal processing unit 1216 that processes the output signal output from the photoelectric conversion device 1215. As described in the fourth embodiment, the timing generation unit 1217 may be mounted on the photoelectric conversion device. The overall control / calculation unit 1208 and the timing generation unit 1217 may be configured to implement a part or all of the control functions of the photoelectric conversion device 1215.

[0063] The photoelectric conversion device 1215 outputs the image signal to the signal processing unit 1216. The signal processing unit 1216 performs a predetermined signal processing on the image signal output from the photoelectric conversion device 1215 and outputs image data. The signal processing unit 1216 generates an image using the image signal. The signal processing unit 1216 may perform distance measurement calculation on the signal output from the photoelectric conversion device 1215. The signal processing unit 1216 and the timing generating unit 1217 may be mounted on the photoelectric conversion device. That is, the signal processing unit 1216 and the timing generating unit 1217 may be provided on a substrate on which pixels are arranged, or may be provided on a different substrate. By configuring an imaging system using the photoelectric conversion device of each of the above-mentioned embodiments, an imaging system capable of acquiring a better quality image can be realized.

[0064] The photoelectric conversion system and the moving body of this embodiment will be described with reference to Fig. 15 and Fig. 16. Fig. 15 is a schematic diagram showing a configuration example of the photoelectric conversion system and the moving body according to this embodiment. Fig. 16 is a flow diagram showing the operation of the photoelectric conversion system according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0065] FIG. 15 shows an example of a vehicle system and a photoelectric conversion system mounted thereon for capturing images. The photoelectric conversion system 1301 includes a photoelectric conversion device 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the photoelectric conversion device 1302. The photoelectric conversion device 1302 converts the optical image of the subject formed by the optical system 1314 into an electric signal. The photoelectric conversion device 1302 is any of the photoelectric conversion devices according to the above-mentioned embodiments. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric conversion device 1302. The function of the image preprocessing unit 1315 may be incorporated in the photoelectric conversion device 1302. The photoelectric conversion system 1301 is provided with at least two sets of an optical system 1314 , a photoelectric conversion device 1302 , and an image pre-processing unit 1315 , and the output from each set of image pre-processing units 1315 is input to the integrated circuit 1303 .

[0066] The integrated circuit 1303 is an integrated circuit for use in an imaging system, and includes an image processing unit 1304 including a memory 1305, an optical distance measuring unit 1306, a distance measuring calculation unit 1307, an object recognition unit 1308, and an abnormality detection unit 1309. The image processing unit 1304 performs image processing such as development processing and defect correction on the output signal of the image pre-processing unit 1315. The memory 1305 temporarily stores the captured image and stores the defective positions of the captured pixels. The optical distance measuring unit 1306 performs focusing and distance measurement of the subject. The distance measuring calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric conversion devices 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the abnormality detection unit 1309 detects an abnormality in the photoelectric conversion device 1302, it notifies the main control unit 1313 of the abnormality.

[0067] The integrated circuit 1303 may be realized by dedicated hardware, a software module, or a combination of these. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or a combination of these.

[0068] The main control unit 1313 supervises and controls the operations of the photoelectric conversion system 1301, the vehicle sensor 1310, the control unit 1320, etc. It is also possible to adopt a method in which the main control unit 1313 is not provided, and the photoelectric conversion system 1301, the vehicle sensor 1310, and the control unit 1320 each have their own communication interface and transmit and receive control signals via a communication network (for example, CAN standard).

[0069] The integrated circuit 1303 has a function of receiving a control signal from the main control unit 1313 or transmitting a control signal or a set value to the photoelectric conversion device 1302 by its own control unit.

[0070] The photoelectric conversion system 1301 is connected to a vehicle sensor 1310, and can detect the vehicle's driving state, such as vehicle speed, yaw rate, and steering angle, as well as the state of the environment outside the vehicle, other vehicles, and obstacles. The vehicle sensor 1310 is also a distance information acquisition means for acquiring distance information to an object. The photoelectric conversion system 1301 is also connected to a driving assistance control unit 1311 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310. This allows for avoidance control when a collision is estimated, and activation of a safety device in the event of a collision.

[0071] The photoelectric conversion system 1301 is also connected to an alarm device 1312 that issues an alarm to the driver based on the result of the determination by the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 1313 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1312 warns the user by sounding an alarm, displaying alarm information on a display screen such as a car navigation system or a meter panel, vibrating a seat belt or steering wheel, etc.

[0072] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0073] 201: photodiode (PD), 202: transfer transistor, 203: floating diffusion (FD), 204: reset transistor, 205: amplification transistor, 210: first transistor, 211: second transistor, 212: third transistor, n1: first node, n2: second node, n3: third node

Claims

1. A photoelectric conversion element; a first node to which charges are supplied from the photoelectric conversion element; an amplifying transistor that outputs a signal corresponding to the voltage of the first node; a first transistor that opens and closes a path between a second node that is not included in a path from the photoelectric conversion element to the first node and the first node; a second transistor that opens and closes a path between the second node and a third node; a second capacitance added to the second node by the second transistor being conductive is greater than a first capacitance added to the first node by the first transistor being conductive; A photoelectric conversion device comprising:

2. the second capacitance is greater than the capacitance of the first node when the first transistor is not conducting; 2. The photoelectric conversion device according to claim 1.

3. The gate length of the second transistor is longer than the gate length of the first transistor.

3. The photoelectric conversion device according to claim 1 or 2.

4. The gate width of the second transistor is equal to the gate width of the first transistor.

4. The photoelectric conversion device according to claim 3.

5. further comprising a reset transistor that resets the potential of the first node; the reset transistor opens and closes a path between the third node and a predetermined voltage line; 5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. A photoelectric conversion element; a first node to which charges are supplied from the photoelectric conversion element; an amplifying transistor that outputs a signal corresponding to the voltage of the first node; a first transistor that opens and closes a path between the first node and a second node that is not included in a path from the photoelectric conversion element to the first node; a second transistor for opening and closing a path between the second node and a third node; a third transistor disposed in a path between the third node and a fourth node; A fixed potential is applied to a gate of the third transistor to make the third transistor conductive. A photoelectric conversion device comprising:

7. A photoelectric conversion element; a first node to which charges are supplied from the photoelectric conversion element; an amplifying transistor that outputs a signal corresponding to the voltage of the first node; a first transistor that opens and closes a path between the first node and a second node that is not included in a path from the photoelectric conversion element to the first node; a second transistor for opening and closing a path between the second node and a third node; a third transistor disposed in a path between the third node and a fourth node; a third capacitance added to the third node by the third transistor being conductive is greater than a second capacitance added to the second node by the second transistor being conductive; A photoelectric conversion device comprising:

8. a third capacitance added to the third node by the third transistor being conductive is greater than a first capacitance added to the first node by the first transistor being conductive; 8. The photoelectric conversion device according to claim 7.

9. a gate length of the third transistor is longer than a gate length of the second transistor; 9. The photoelectric conversion device according to claim 7 or 8.

10. the gate width of the third transistor is equal to the gate width of the second transistor; 10. The photoelectric conversion device according to claim 9.

11. a gate length of the third transistor is longer than a gate length of the first transistor; 11. The photoelectric conversion device according to claim 7,

12. the gate width of the third transistor is equal to the gate width of the first transistor; The photoelectric conversion device according to claim 11 .

13. further comprising a reset transistor that resets the potential of the first node; the reset transistor opens and closes a path between the fourth node and a predetermined voltage line; 13. The photoelectric conversion device according to claim 6, wherein the first and second electrodes are arranged in a first direction.

14. a channel length direction of the first transistor and the second transistor is parallel to one side of the photoelectric conversion element; 14. The photoelectric conversion device according to claim 1,

15. the first transistor and the second transistor are disposed in a rectangular portion of an active area that includes the rectangular portion; 15. The photoelectric conversion device according to claim 14.

16. a channel length direction of the first transistor, the second transistor, and the third transistor is parallel to one side of a photoelectric conversion element; 14. The photoelectric conversion device according to claim 6,

17. the first transistor, the second transistor, and the third transistor are disposed in a rectangular portion of an active area that includes the rectangular portion; 17. The photoelectric conversion device according to claim 16.

18. a transfer transistor that transfers charges from the photoelectric conversion element to the first node; 18. The photoelectric conversion device according to claim 1,

19. The photoelectric conversion device according to any one of claims 1 to 18, a signal processing unit that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

20. The photoelectric conversion device according to any one of claims 1 to 18, a distance information acquisition means for acquiring distance information to an object from distance measurement information based on a signal from the photoelectric conversion device, A moving body further comprising a control means for controlling the moving body based on the distance information.

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