Synthetic current compensation in switched power converter

Abstract

To reduce output capacitance while satisfying a higher transient requirement.SOLUTION: A power controller 103 comprises a control loop configured to control timing of pulsed signals that activate phases of a coupled inductor voltage regulator based on a current demand of a load circuit and comprises a transient detection circuit configured to determine predicted current through a compensation inductor of the coupled inductor voltage regulator based on a state of the phases and operating parameters of the coupled inductor voltage regulator. The transient detection circuit is configured to detect a transient in the current demand of the load circuit based on variability in phase-to-phase overlap of the pulsed signals. Responsive to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that alters the timing of the pulsed signals based on the predicted current through the compensation inductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to voltage regulators and, more particularly, to current emulation in multi-phase switched power converter topologies. [Background technology]

[0002] Power-hungry applications such as cloud computing and artificial intelligence drive the need for powerful microprocessors. These processors may have stringent transient requirements for high current slew rates, for example, greater than 3000A / μs. To design a power supply to meet the required power requirements, a multi-phase buck converter design can be utilized. To meet the power requirements, the board design may lead to high density board structures, so adding more capacitors with limited real space available for the board design is not a viable solution to meet these transient requirements.

[0003] To reduce output capacitance while meeting higher transient requirements, a power supply based on a transformer-inductor voltage regulator (TLVR) buck converter topology can be used. Due to the nature of this circuit, the inductor current slew rate during a load transient is much higher compared to a normal voltage regulator buck converter topology. However, accurate capture and reporting of the current sense signal during a transient load transition may lag behind the actual current level. Because current is used for control, the interaction between the controller device and the delayed current feedback may result in undesirable ring-back issues. Summary of the Invention

[0004] According to one aspect of the disclosure, a power controller includes a control loop configured to control timing of a pulse signal that activates a phase of a coupled inductor voltage regulator based on a current demand of a load circuit, and a transient detection circuit configured to determine a predicted current through a compensation inductor of the coupled inductor voltage regulator based on a state and an operating parameter of the phase of the coupled inductor voltage regulator. The transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in the phase overlap of the pulse signal. In response to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that varies the timing of the pulse signal based on the predicted current through the compensation inductor.

[0005] According to another aspect of the disclosure, a method includes determining, by a control loop, timing of pulse signals activating phases of a coupled inductor voltage regulator based on a current demand of a load circuit, and determining, by a transient detection circuit, a predicted current through a compensation inductor of the coupled inductor voltage regulator based on states and operating parameters of the phases of the coupled inductor voltage regulator. The method also includes monitoring in the transient detection circuit a variability in phase overlap of the pulse signals to detect a transient condition in the current demand of the load circuit, and applying, by the transient detection circuit, a correction to the control loop that varies the timing of the pulse signal based on the predicted current through the compensation inductor during at least a portion of the transient condition.

[0006] According to yet another aspect of the present disclosure, an apparatus includes one or more computer readable storage media and program instructions stored on the one or more computer readable storage media. These program instructions executable by a processing system for directing the processing system to at least determine a predicted current through a compensation inductor of a coupled inductor voltage regulator based on a state of a phase of the coupled inductor voltage regulator and an operating parameter of the coupled inductor voltage regulator, and to detect a transient in a current demand of a load circuit supplied by the coupled inductor voltage regulator based on a variability in phase overlap of a pulse signal. These program instructions further direct the processing system, in response to detecting the transient, to apply a correction to a control loop that varies a timing of the pulse signal based on the predicted current through the compensation inductor.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are more fully described below in the Detailed Description. It should be understood that this Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief description of the drawings]

[0008] Many aspects of the present disclosure can be better understood with reference to the following drawings. Although several implementations are described in connection with these drawings, the disclosure is not limited to the implementations disclosed herein. On the contrary, it is intended to cover all alternatives, modifications, and equivalents.

[0009] [Figure 1] FIG. 1 is a schematic diagram illustrating a multi-phase power converter according to an embodiment.

[0010] [Diagram 2] 1 illustrates a number of waveforms showing current and voltage responses during a load circuit power change in accordance with an example.

[0011] [Diagram 3] 13 illustrates the effect of reporting power stage current in various timing scenarios, according to one embodiment.

[0012] [Figure 4] FIG. 2 is a schematic block diagram illustrating emulated current generation according to one embodiment.

[0013] [Diagram 5] 1 illustrates a block diagram showing a method for calculating a current rate according to one embodiment.

[0014] [Figure 6] FIG. 1 illustrates a block diagram showing phase-wise counters for calculating emulated currents according to one embodiment.

[0015] [Figure 7] 4 illustrates a timing diagram showing counter operation according to one embodiment.

[0016] [Figure 8] 4 illustrates a timing diagram showing counter operation according to one embodiment.

[0017] [Figure 9] 4 illustrates a waveform response to an increase in load current according to one embodiment.

[0018] [Figure 10] 4 illustrates a waveform response to a decrease in load current according to one embodiment.

[0019] [Figure 11] 4 is a flow chart illustrating a method for transient detection according to one embodiment.

[0020] [Figure 12]1 illustrates a control loop according to one embodiment.

[0021] [Figure 13] 4 is a flow chart illustrating a method for adjusting pulse signal timing according to one embodiment.

[0022] [Figure 14] 1 illustrates an example implementation of a control system according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] 1 illustrates a schematic diagram of a multi-phase power converter 100 according to one embodiment. In particular, the multi-phase power converter 100 is arranged as a transformer-inductor voltage regulator (TLVR) step-down converter. An input voltage 110 is provided to an input node 111 that is coupled to a number of power stages 120. A first power stage 121 receives the voltage provided by the input voltage 110 and generates an output current i in response to pulse width modulation (PWM) control of one or more power switches via a PWM control signal (PWM1) from a controller 103. hp1 The second power stage 122 also receives the voltage provided by the input voltage 110 and generates an output current i in response to PWM control of one or more power switches of the second power stage 122 via a PWM control signal (PWM2) from the control circuit. hp2 Also shown is an Nth power stage 123 coupled to an input node 111 to receive a voltage provided by an input voltage 110 and generating an output current i in response to PWM control (PWMN) of one or more power switches of the Nth power stage 123. phN Generate.

[0024] 2, first and second graphs 200, 210 illustrate current transitions of the output current 113 supplied to the load circuit 114 according to one example. As shown in graph 200, the steady current undergoes a step-up change in response to an increasing demand for current from the load circuit 114. This is illustrated by waveform 201 illustrating the change in actual current in response to the increasing current demand. Graph 210 shows a step-down change in the current supplied to the load circuit 114 in response to a decreasing demand for current. A pair of reported current waveforms 202, 212 associated with actual current waveforms 210, 211, respectively, illustrate that in one example, the change in reported current is slower than the actual current due to the manner in which the reported current is calculated. Between the first steady state portion of waveforms 210, 211 and the higher and lower current value steady state portions of waveforms 210, 211, respectively, the transient response of the reported current waveforms 202, 212 attempts to adapt to changes in the actual current delivered to the load 114. As a result, first and second ring-back events 222, 223 may be seen in graph 220 illustrating output voltage waveform 221. Ring-back events 222, 223 are undesirable, and embodiments of the present disclosure describe improvements to the transient response in the reported current to reduce or eliminate the disadvantages described with reference to FIG.

[0025] Returning to Figure 1, the output current i ph1 ~i phN is fed to a number of coupled inductors 130. In particular, the output current i ph1 is provided to the first coupled inductor 131, and an output current i ph2 is provided to a second coupled inductor 132, producing an output current i phN is provided to the Nth coupled inductor 133. Each of the coupled inductors 131 to 133 has a respective output current i ph1 ~i phNThe phase 120 includes a primary winding configured to receive a current from the output of the phase 120 and a secondary winding. The primary winding is coupled to a common output node 112, which is also coupled to an output capacitor 115 and a load circuit 114. The secondary windings are coupled together in series with an external compensation inductor 134. The external compensation inductor 134 couples current changes in one of the phases 120 (e.g., power stage 121) to the rest of the phases 120 (e.g., power stages 122, 123). In this manner, the voltage droop of the output voltage is small.

[0026] A summer 102 calculates the actual current (e.g., i ph1 , i ph2 , i phN etc.) to produce a single current value i sum-ACT The current value i sum-ACT is the current i ph1 , i ph2 , i phN 1 to the same common output node 112, producing an output current 113 that is supplied to a load circuit 114. In the circuit illustrated in FIG. 1, no physical hardware is utilized to measure the actual current. Such hardware could occupy valuable real estate on a printed circuit board (PCB) supporting multi-phase power converter 100. Instead, multi-phase power converter 100 generates emulated currents (e.g., CSP1, CSP2, CSPN, etc.) in each of the respective power stages 121-123, which are summed within controller 103 (as illustrated by current summer 101) to produce a sum current signal i that is used by controller 103 to generate PWM control signals PWM1, PWM2, PWMN, etc. sum Each emulated current generated by each power stage 121-123 is generated as an output current of the respective power stage 121-123 and is supplied to the respective power stage 121-123 in a real current (e.g., i ph1 , i ph2 , i phN etc.).

[0027] 3, power stage current phases and the effect of reporting power stage currents in various timing scenarios are illustrated according to one embodiment. A power stage current reporting block 300 illustrates the relationship between example current waveforms (1001-1003) seen through the primary windings of coupled inductors 131-133, which are seen in response to corresponding PWM signals 304 sent to the respective power stages 121-123. During an ON pulse of the PWM signal 304, current portion 301 illustrates the increase in current through the primary windings. Reporting the current during the rising current portion 301 is emulated within the power stages.

[0028] Each power stage 121-123 is designed to have a Toff1 time and a Toff2 time. In a single system arrangement such as the multi-phase power converter 100, the Toff1 and Toff2 times of all included power stages may be selected to be similar or substantially similar. However, one or more of the power stages 121-123 may have separate Toff1 and / or Toff2 times. In one embodiment, the Toff1 and Toff2 times are initiated in response to a falling edge of a pulse of the PWM signal 304. During the Toff1 time, current ramps through the primary windings of the respective coupled inductors 131-133 and is also emulated within the power stages. Beginning at Toff1, the emulation of ramping current is terminated and the actual sensed current is reported to the controller 103. In response to reaching Toff2, the DC value of the current in the power stage is updated while the actual current is reported to the controller 103.

[0029] FIG. 3 illustrates example current reports 310 in response to different off-times 305 of a PWM signal 304. A PWM signal 311 is illustrated corresponding to a first example case where the PWM signal 311 has a sufficiently fast off-time 305 such that the off-time (Toff) 305 between successive PWM pulses is shorter than the Toff1 time. During the first PWM pulse cycle corresponding to the first pulse and the first Toff time, the reported power stage current 315 accurately reflects the actual inductor current 314 as seen by the respective primary winding. However, subsequent PWM cycles cause the reported power stage current 315 to deviate from the actual inductor current 314. As shown during the second PWM cycle, the shape of the reported power stage current 315 matches the shape of the actual inductor current 314. For example, the rising portions of the currents 314, 315 have the same or similar increasing slopes, and the falling portions of the currents 314, 315 have the same or similar decreasing slopes. However, due to the Toff time being shorter than the Toff2 time, the DC value of the current in the power stage cannot be reset or updated.

[0030] In the second illustrated case example, the PWM signal 312 is shown to have a Toff time 305 that is longer than the Toff1 time but shorter than the Toff2 time. As shown, the slopes of the rising portions of the actual inductor current 316 and the reported power stage current 317 are similar to the slopes of the falling portions corresponding to the Toff1 time. The decreasing current portions corresponding to the portions between the Toff1 and Toff2 times also have matching slopes. However, in response to the actual current being reported after the Toff1 time, the DC value of the reported power stage current 317 matches the DC value of the actual inductor current 316. Unfortunately, the DC value of the reported power stage current 317 is not updated as is done in response to reaching the Toff2 time. Thus, the start of each PWM cycle, which is initiated with the rising edge of the PWM pulse, involves starting the reported power stage current 317 from a DC value that does not match the corresponding DC value of the actual inductor current 316.

[0031] In a third illustrated example, the PWM signal 313 is shown to have a Toff time 305 that is greater than the Toff2 time. As shown, the slopes of the rising and falling edges of the actual inductor current 318 and the reported power stage current 319 match across a PWM cycle. Also as shown, in response to reaching and exceeding the Toff2 time, the DC value of the current in the power stage is updated to substantially represent the actual inductor current 318 in each PWM cycle.

[0032] The embodiments of the present disclosure compensate for the difference between the actual current seen by the external compensation inductor 134 and the emulated current reported to the controller 103 from the multiple power stages 120 .

[0033] FIG. 4 is a schematic block diagram illustrating a digitally emulated current generator 400 according to an example. In one embodiment, the digitally emulated current generator 400 is implemented by the controller 103. The generator 400 includes an arithmetic logic unit (ALU) 410 that receives a number of system parameters 420. The system parameters 420 include a value (Vin) of an input voltage (e.g., input voltage 110), a value (Vout) of an output voltage (e.g., output voltage at output node 112), an inductance value (Lc) of the external compensation inductor 134, a body diode voltage value (Vdiode) of the low-side FET of the power stages 121-123, a Vdroop adjustment value (Vdroop) used to account for the measurement accuracy of Vdroop in the controller 103 due to bandwidth or offset conditions, and a power supply voltage (Vpower) that is used to adjust the power supply voltage (Vpower) to the power supply 103. tune ), and a conversion factor (Conv), which may include one or more of the clock periods on which the controller 103 is operating. fact), a digital-to-analog (DAC) conversion scale, and a current to voltage conversion ratio. The values ​​of Lc, Vdiode, and the conversion coefficients may be obtained from a memory, such as a non-volatile memory, in the controller 103. Additional system parameters may be obtained from inputs to the controller 103, indicating the number (K) of power stages 121-123 that are currently on in a HIGH state (e.g., by controlling a PWM signal HIGH), the number (M) of phases that the PWM is actively switching, and the number (N) of phases available to the system.

[0034] In one embodiment, the compensation rate 421 is calculated based on the system parameters 420 using the following formula: TIFF2025032065000002.tif573

[0035] In another embodiment, the compensation rate 421 is calculated based on the system parameters 420 using the following formula: TIFF2025032065000003.tif572

[0036] 5 illustrates a block diagram showing a method 500 for calculating a rate based on Equation 2, according to one embodiment. A first multiplier 501 receives the K value and the Vin value and multiplies them together. The multiplication product is provided to a first subtractor 502.

[0037] The N value is provided to a second multiplier 503, which also receives a Vout input and generates a product of the N input and the Vout input and provides the product to a first adder 504. The N value is also provided to a second subtractor 505. The M value is provided to a second subtractor 505. M is subtracted from N in the second subtractor 505 and the difference is output to a second adder 506. The adder 506 adds the Vdiode input to the difference NM and provides the sum to the first adder 504. The first adder 504 sums the product N×Vout and the product (NM)×Vdiode and provides it to the first subtractor 502 to be subtracted from the product K×Vin. The resulting difference is provided to a third multiplier 507 and multiplied by a quotient based on a conversion factor divided by the inductance of the external compensation inductor 134. The final product obtained by multiplier 507 is output as the generated Rate in Equation 2.

[0038] Returning to FIG. 4, the calculated rate 421, along with inputs for a first off-time Toff1 422 and a second off-time Toff2 423, are provided to a current calculation block 411 having counters dedicated to each power stage 121-123 for digitally emulating the currents generated in response to the PWM signals PWM1-PWMN. As shown in FIG. 6, the current calculation block 411 includes internal counters 600, 601, 602 and external counters 603, 604, 605 for determining emulated current values ​​for individual phases (e.g., Phase 1, Phase 2, Phase N, etc.) corresponding to each power stage 121-123. FIG. 7 illustrates an example operation of the internal counter 600 and external counter 603 for Phase 1 corresponding to the operation of the power stage 121. 6 and 7, at the beginning of a PWM signal cycle beginning with the rising edge 700 of the PWM pulse 701, the value of the internal counter 600 is copied to the external counter 603 and the counters 600, 603 start incrementing or decrementing based on the rate 421. The external counter 603 increments or decrements until the end of the first off-time Toff1 422, while the internal counter 600 continues to increment or decrement until the end of the second off-time Toff2 423. As shown in FIG. 6, the external counter 603 exports its value as the emulated CSP1 value. The Phase 2 to Phase N external counters 604-605 similarly export their respective phase (e.g., Phase 2 to Phase N) values ​​for further processing by the digitally emulated current generator 400.

[0039] As shown in Figure 4, the emulated CSP1-CSPN values ​​are provided to summer 412, which combines the emulated currents into emulated current output 425. Figure 8 shows waveforms of an example implementation of the calculation of the emulated currents and their sum based on PWM signals 800, 801, 802. A clock signal 803 provides timing for the PWM signals 800-802 as well as the output of the calculation by digital ALU 410 (e.g., rate 421 output as shown), external counters 603-605, and summer 412 (e.g., emulated sum current output 425).

[0040] Each of the external counters 603-605 starts counting the value of the rate signal 421 with the rising edge of the pulse of the respective PWM signal 800-802 and stops counting at the end of the respective Toff1 time 804-806. The first external counter 603 counts three times by three, one time by five, two times by three, one time by five, and two more times by three. The second external counter 604 counts one time by five, two times by three, one time by five, three times by three, and two times by -1. The third external counter 605 counts one time by five, three times by three, and five times by -1. The sum of the counter values ​​during each clock cycle is illustrated in the summed emulated current output 425.

[0041] Returning to FIG. 4, a digital-to-analog converter (DAC) 413 converts the digital summed emulated current output 425 into an analog compensation signal I CE 2, the transient response attempts to adapt to changes in the actual current delivered to the load 114. During such a transient event, the analog compensation signal I CEIncorporating analog compensation signal 426 into the feedback control loop improves current response and reduces ringback during such transient conditions by compensating the current reported by power stages 121-123. However, incorporation of analog compensation signal 426 outside of transient events is not necessary. Thus, embodiments of the present disclosure contemplate detecting load current transients in order to apply compensation that is determined during the transient period. Outside of the transient period, compensation signal 426 is not provided to the feedback control loop.

[0042] Therefore, as shown in Fig. 4, the controller 103 also includes a transient detector block 414 configured to identify a transient in the load current in order to switch the application of the compensation signal 426 to the control loop. Figs. 9 and 10 illustrate waveforms 900, 1000 illustrating load current transient conditions according to an embodiment. Fig. 11 illustrates an implementation of transient detection using a flow chart of a procedure 1100 for determining a load current transient and controlling the activation of a compensation enable signal according to an embodiment.

[0043] 9-11, the load current 910, 1010 starts in a steady mode and transitions to a higher or lower load current at a respective transition event 921, 1021. During the steady mode, the overlap time t OL1922, 1022 may be similar or vary as the controller 103 generating signals 912-914, 1012-1014 operates the multi-phase power converter 100 to generate the desired load current. For example, the overlap times between successive PWM signals in FIG. 9 (PWM1 signal 912 and PWM2 signal 913, PWM2 signal 913 and PWMN signal 914, or PWMN signal 914 and PWM1 signal 912) may be similar or vary, as may the PWM signals in FIG. 10 (PWM1 signal 1012 and PWM2 signal 1013, PWM2 signal 1013 and PWMN signal 1014, or PWMN signal 1014 and PWM1 signal 1012). In an attempt to maintain equal degrees of separation between the operation of the power stages 121-123 to optimize the current ripple of the output voltage, the controller 103 may tend to equalize the overlap times between successive PWM signals.

[0044] In response to a load current transient in which the load current 910, 1010 changes due to a step-up transition 921 or a step-down transition 1021, the overlap time of successive PWM signals 912-914, 1012-1014 changes accordingly. As shown in FIG. 9, the step-up transition 921 increases the load current demand and the overlap time t OL2 10, the step-up transition 1021 increases the load current demand and increases the overlap time tOL2 between successive signals (eg, PWM1 signal 1012 and PWM2 signal 1013).

[0045] Overlap time t OL2 The overlap time t OL1 The increase or decrease in t is determined in the first block 1101 of the procedure 1100 by determining a first overlap time (e.g., t OL1 In a second block 1102, a second overlap time (e.g., t OL2If the correction enable signal (EMU_ENABLE) is not activated (block 1103), the subsequent overlap time t OL2 is the previous overlap time t OL1 (block 1104) to determine the overlap time t OL1 and OL2 It is determined whether the difference between the overlap time t and is large enough to indicate that a load current transient has occurred. OL1 and OL2 The difference between them is the overlap time threshold t OL_TH For example, if the absolute value of the overlap time difference meets or exceeds the threshold, the presence of a load current transient condition may be indicated. If so, the correction enable signal is activated in block 1105 and procedure 1100 returns to block 1101 to repeat another round of checking the overlap time. Enabling the correction enable signal (EMU_ENABLE 915, 1015) is illustrated in transitions 924, 1024 of Figures 9 and 10. If the absolute value of the overlap time difference does not meet or exceed the threshold, procedure 1100 returns to block 1101 to repeat another round of checking the overlap time.

[0046] If the correction enable signal (EMU_ENABLE) is activated (block 1103), the overlap time t OL1 and OL2 The difference between this and the steady state condition threshold t SS_TH In one embodiment, the steady state condition threshold is less than the overlap time threshold, and the overlap time t is less than or equal to the steady state condition threshold. OL1 and OL2 The absolute value of the difference between t and t indicates that a load current transient period does not exist. When the steady state condition threshold is reached after the load current transient period, the load current transient period ends. In block 1106, the overlap time t OL1 and OL2 The absolute difference between the steady-state condition threshold t SS_THIf the steady state condition is not met, the compensation enable signal is not changed and procedure 1100 returns to block 1101 for another round of overlap time checking. If the steady state condition is met, the compensation enable signal is deactivated in block 1107 and procedure 1100 returns to block 1101 for another round of overlap time checking.

[0047] In an alternative embodiment, a transient event may be determined by measuring the on-time (Ton) of the PWM signals 912-914, or may be inferred without sensing the DC current based on a sudden dramatic change in the PWM output, thereby keeping the output voltage regulated.

[0048] 12 illustrates a feedback control loop 1200 for generating a PWM control signal according to one embodiment. comp 1201 is generated based on the sum of three signal paths in control loop 1200. In control loop 1200, an error amplifier 1202 subtracts the sensed output voltage from the output voltage target to generate a droop voltage 1203. A first signal path in control loop 1200 includes a proportional path 1204 that receives the droop voltage 1203 and generates a proportional output 1205.

[0049] A second signal path in control loop 1200 receives the total reported current I, provided, for example, by emulated current summer 101 of FIG. sum Based on receiving 1206. sum 1206, if a load current transient exists, detects the I sum 1206. For example, the analog compensation signal I CE 426 (FIG. 4) is provided to the control loop 1200 by a switch 1208 that is controlled by an emulation enable signal 427 (FIG. 4). CE 426 is I CEThe DC portion of the control loop 1200 is modified by a mixer 1209 that combines I 426 with a DC emulated current gain 1210. The product of the mixer 1209 is converted to I sum 1206 and the sum is provided to a DC load line 1211 to generate an ideal droop value 1212. A difference signal generated by summer 1213 of the difference between the droop voltage 1203 and the ideal droop value 1212 is provided to integration path 1214 which generates an error voltage, V comp The set point of signal 1201 is adjusted to produce an integrated output 1215 that drives the output voltage error to zero.

[0050] A third signal path in the control loop 1200 is I sum 1206. When a load current transient is present, the DAC output 426 is combined in a mixer 1216 to provide correction to the AC portion of the control loop 1200. The mixer 1216 is based on I CE 426 and an AC emulated current gain 1217. The product of the mixer 1216 is output to a summer 1235 which produces a current feedback output 1218, I sum This is added to 1206.

[0051] The outputs of the three signal paths (e.g., proportional output 1205, integral output 1215, and current feedback output 1218) are combined in a summer 1219 to generate a raw voltage compensation signal 1220, which is scaled by a scaler 1221 to generate a scaled voltage compensation signal 1201. The compensation ramp signal V RAMP 1222 has a slope proportional to the number of phases or power stages 121-123 and the switching frequency setting. RAMP 1222 signal and V COMPIn response to detecting the crossing with the 1201 signal, the controller 103 issues a new clock pulse in the clock signal 1223. Based on the clock signal 1223, a phase manager 1261 in the controller 103 generates a corresponding PWM signal 1262 (e.g., PWM1-PWMN) for controlling the power stages 121-123.

[0052] FIG. 13 is a flow chart illustrating a method 1300 for adjusting the timing of a pulse signal, according to one embodiment. Method 1300 may incorporate some or all of procedure 1100 of FIG. 11 in one embodiment. Method 1300 begins with step 1301 of establishing or controlling the timing of a pulse signal that activates a phase of a coupled inductor voltage regulator according to a current demand of a load circuit. For example, PWM control signal 1262 generated with the aid of control loop 1200 of FIG. 12 is used to control power stages 121-123 to generate output voltage 112. In step 1302, a predicted current through a compensation inductor of the coupled inductor voltage regulator is determined based on the state and operating parameters of the phases of the coupled inductor voltage regulator. For example, digitally emulated current generator 400 generates current rate 421 and generates emulated current output 426 using per-phase counters 411. In step 1303, the variation in the overlap between the phases of the pulse signal is monitored to detect transient conditions in the current demand of the load circuit. As shown in FIGS. 9 and 10, the overlap time T off1 and T off2 is used to detect the start and end conditions of transients in the load current demand.

[0053] If the transient entry condition is met in step 1304, a correction to the control loop is enabled in step 1306, which changes the timing of the pulse signal based on the predicted current through the compensation inductor. The procedure 1300 then returns to step 1301 for another iterative cycle. If the transient entry condition is not met in step 1304, a transient exit condition is tested in step 1305. If the transient exit condition is met, the correction to the control loop is deactivated in step 1307, and the procedure 1300 returns to step 1301 for another iterative cycle. If the transient exit condition is not met in step 1305, the procedure 1300 returns to step 1303 to continue monitoring for the transient exit condition. The activating and deactivating of the correction is determined based on, for example, detection of a transient period in the load current facilitated by procedure 1100 of FIG.

[0054] FIG. 14 illustrates an example implementation of a control system that may implement any of the control schemes described herein. FIG. 14 includes a control system 1401. The control system 1401 represents any system or collection of systems in which the various operational techniques, architectures, scenarios, and processes disclosed herein may be implemented. For example, the control system 1401 may be used to implement the controller or control portion of the multi-phase power converter 100 of FIG. 1, the digitally emulated current generator 400 of FIG. 4, the activating correction enable signal of FIG. 11, the feedback loop control of FIG. 14, or any of the control, transient detection, or transient correction of any of the figures herein.

[0055] The control system 1401 may be implemented as a single apparatus, system, or device, or may be implemented in a distributed manner as multiple apparatus, systems, or devices. The control system 1401 includes, but is not limited to, a processing system 1402, a storage system 1403, software 1405, a communication interface system 1407, and a user interface system 1408. The processing system 1402 is operatively coupled to the storage system 1403, the communication interface system 1407, and the user interface system 1408.

[0056] Processing system 1402 loads and executes software 1405 from storage system 1403. When executed by processing system 1402 to control the power system affecting specified load regulation, transient detection, and activating / enabling of correction enable signals, software 1405 directs processing system 1402 to operate as described herein for at least the various processes, operating scenarios, and sequences described in the above implementations. Control system 1401 may optionally include additional devices, features, or functionality not described for the sake of brevity.

[0057] The processing system 1402 may include processing circuitry that retrieves and executes the software 1405 from the storage system 1403. The processing system 1402 may be implemented within a single processing device, but may also be distributed across multiple processing devices or subsystems that cooperate in executing program instructions. Examples of processing systems 1402 include general purpose central processing units, application specific processors, graphics processing units, programmable logic devices, field programmable logic devices, application specific integrated circuit devices, digital signal processors, and discrete logic, as well as any other types of processing devices and supporting circuitry, combinations, or variations thereof.

[0058] Storage system 1403 may include any tangible computer-readable storage medium that is readable by processing system 1402 and may store software 1405. Storage system 1403 may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, control programs, program modules, or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, flash memory, virtual and non-virtual memory, magnetic storage media, magnetic storage devices, or any other suitable storage media. In any case, the computer-readable storage media is not a propagating signal. In addition to computer-readable storage media, in some implementations storage system 1403 may also include computer-readable communication media to which at least a portion of software 1405 may be communicated internally or externally. Storage system 1403 may be implemented as a single storage device, but may also be implemented across multiple storage devices or subsystems that are coexistent or distributed among one another. Storage system 1403 may include additional elements, such as a controller, that may be in communication with processing system 1402 or possibly other systems.

[0059] The software 1405 may be implemented as program instructions that, among other functions, when executed by the processing system 1402, may direct the processing system 1402 to operate as described with respect to the various operational scenarios, sequences, and processes illustrated herein. For example, the software 1405 may include program instructions including the power control environment 1420 to implement the operations 1100, 1300 illustrated in FIGS. 11, 13, or other operations described herein. In particular, the program instructions may include various components or modules that cooperate or otherwise interact to perform the various processes and operational scenarios described herein. The various components or modules may be implemented with compiled or interpreted instructions, or some other variation or combination of instructions. The software 1405 may include additional processes, programs, or components, such as operating system software (e.g., 1421) or other application software (e.g., 1422), in addition to or including the power control environment 1420. The software 1405 may also include firmware or some other form of machine-readable processing instructions executable by the processing system 1402 .

[0060] When loaded and executed on the processing system 1402, the software 1405 may transform an entire suitable apparatus, system, or device (of which the control system 1401 is representative) from a general-purpose computing system to a special-purpose computing system that is customized to control a power system to affect load regulation, transient detection, feedback control loop correction operations, among other control operations. Indeed, the encoded software 1405 on the storage system 1403 may transform the physical structure of the storage system 1403. For example, if the computer-readable storage medium is implemented as a semiconductor-based memory, the software 1405 may transform the physical state of the semiconductor memory, for example, by transforming the state of the transistors, capacitors, or other discrete circuit elements that make up the semiconductor memory when the program instructions are encoded therein. Similar transformations may be performed for solid-state, magnetic, or optical media. Other transformations of physical media are possible without departing from the scope of this description, and the foregoing examples are provided only to facilitate the description herein.

[0061] In one example implementation, software 1405 includes a control process power control environment 1420, including an operating system 1421 and applications 1422, at least some of which represent the computing techniques, algorithms, architectures, scenarios, and processes described with reference to the included figures. Software 1405 may also use parameters 1410 stored by storage system 1403. Parameters 1410 include system parameters 420, which may represent any programmable registers, software defined parameters, status indicators, user controlled feature settings, or adjustment parameters described herein.

[0062] The application 1422 may implement a power control application 1423, including an overlap detection service 1424, a current emulation service 1425, and a PWM service 1426. One or more software or firmware modules may perform the functions of these services, and such modules may provide shared or distributed functionality. The overlap detection service 1424 is configured to monitor timing overlaps between pulse signals associated with voltage conversion phases that supply current to a load circuit. The current emulation service 1424 determines a current emulation signal from the parameters 1410.

[0063] From the monitored timing between the pulse signals, the overlap detection service 1424 is configured to monitor variations in the overlap between phases of the pulse signals to detect transient conditions in the current demand of the load circuit. If a transient entry condition is met based on the monitored variability, a correction to the control loop that varies the timing of the pulse signal based on a predicted current through the compensation inductor is enabled. If a transient exit condition is met, a correction to the control loop that varies the timing of the pulse signal based on a predicted current through the compensation inductor is disabled.

[0064] The current emulation service 1425 is configured to determine a counter rate based on the system parameters 420 and the power stage parameters. The current emulation service 1425 may also be configured to generate an emulated current compensation signal. The PWM service 1426 may control various external circuits that mitigate or correct various undershoot or overshoot conditions and enhance transient response to the power system. For example, based on at least an indication of a transient event condition, the PWM service 1426 is configured to generate a PWM control signal based on the emulated current compensation signal to improve transient response.

[0065] The communication interface system 1407 may include communication connections and devices that enable communication with various circuit elements, such as discrete circuit elements, transistors, interface logic, A / D or D / A conversion units, or electrical components, via a communication link or communication network (not shown). Examples of connections and devices that enable communication may include logic interfaces, off-chip communication elements, signal drivers, signal receivers, transceivers, network interface controllers, and other communication circuit elements. The connections and devices may communicate via a communication medium to exchange communications with other computing systems or networks of systems, such as metal, glass, air, or other suitable communication medium. Communication between the control system 1401 and other elements or systems (not shown) via the communication interface system 1407 may be via data links, control links, communication links, or communication networks according to various communication protocols, combinations of protocols, or variations thereof. For example, the control system 1401 may transfer the control signal transmission over a digital communication link including an Ethernet interface, a serial interface, a serial peripheral interface (SPI) link, an Inter-Integrated Circuit (I2C) interface, a Universal Serial Bus (USB) interface, a UART interface, discrete signal transmission, or a wireless interface.

[0066] The user interface system 1408 may include interface elements for receiving user or operator programmed settings for operation of the power control system, such as for changing parameters 1410. The user interface system 1408 may also provide feedback to the user or operator regarding the current settings held in parameters 1410. In some examples, the user interface system 1408 receives and transfers various information via the communication interface system 1407. The user interface system 1408 may include individual user interface elements, including software interfaces, such as terminal interfaces, command line interfaces, or application programming interfaces (APIs). The user interface system 1408 may also include physical user interfaces, such as a keyboard, mouse, voice input device, or touch screen input device, for receiving input from a user. The user interface system 1408 may include, for example, visualization / status interfaces, user command controls, and telemetry, such as user controls, start / stop controls, telemetry, operational mode control interfaces, visualization interfaces, and system characteristic calibration controls. Output devices, such as a display, speakers, a web interface, a terminal interface, and other types of output devices, may also be included in the user interface system 1408. The user interface system 1408 may also include associated user interface software executable by the processing system 1402 to support the various user input and output devices described above.

[0067] The techniques described in this disclosure may also be embodied or encoded in an article of manufacture that includes a non-transitory computer-readable storage medium. Exemplary non-transitory computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, flash memory, solid-state drive, hard disk, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagated signal. In some examples, a non-transitory storage medium may store data that may change over time (e.g., in RAM or cache).

[0068] The functional block diagrams, operational scenarios and sequences, and flow charts provided in the figures represent example systems, environments, and methodologies for implementing novel aspects of the present disclosure. For ease of explanation, the methods included herein may be in the form of functional diagrams, operational scenarios or sequences, or flow charts, and may be described as a series of acts, but it should be understood and appreciated that such methods are not limited by the order of acts, since some acts may be performed in different orders and / or simultaneously with other acts according to the acts shown and described herein. For example, those skilled in the art will understand and appreciate that a method may be represented as a series of interrelated states or events, such as a state diagram. Also, not all acts illustrated in a methodology are necessarily required for a novel implementation.

[0069] The various circuit elements and interconnection architectures described herein are used according to the above description. However, it should be understood that the disclosure herein and its enhancements are not limited to these circuit elements and interconnection architectures. Therefore, the descriptions and figures included herein show specific implementations to teach those skilled in the art how to make and use the best options. For the purpose of teaching the inventive principles, some conventional aspects have been simplified or omitted. Those skilled in the art will understand variations of these implementations that fall within the scope of the present disclosure. Those skilled in the art will also understand that the features described above can be combined in various ways to form multiple implementations.

[0070] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A by a control signal generated by device A, where the intervening component C does not change the functional relationship between device A and device B.

[0071] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuring may be accomplished by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination of these.

[0072] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to refer to an interconnection between or at the ends of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0073] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, e.g., by an end user and / or a third party.

[0074] Although particular transistors are described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no modification to the circuit. Other types of transistors may also be used, such as bipolar junction transistors (BJT). Devices may also be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). References to transistor features such as gate, source, or drain are not intended to exclude any suitable transistor technology. For example, features such as source, drain, and gate are typically used to refer to FETs, while emitter, collector, and base are typically used to refer to BJTs. Such features may be used interchangeably herein. For example, references to the gate of a transistor may refer to either the gate of a FET or the base of a BJT, and vice versa. In some examples, a control terminal may refer to either the gate of a FET or the base of a BJT. Any other suitable transistor technology may also be used. Any such transistor may be used as a switch, with the gate or base, or other equivalent feature, acting as a switch select input that may be driven to connect the source and drain (or possibly the emitter and collector).

[0075] As used herein, a field effect transistor (FET) is "on" (or the switch is closed) means that the FET's conduction channel is present and drain current can flow through the FET. As used herein, a FET is "off" (or the switch is open) means that the conduction channel is not present and drain current cannot flow through the FET. However, when a FET is off, current may flow through the transistor's body diode.

[0076] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to the replacement of the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise indicated. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0077] Use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within ±11 percent of that parameter.

[0078] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. 1. A power controller comprising: a control loop configured to control timing of a pulse signal that activates a phase of a coupled inductor voltage regulator based on a current demand of a load circuit; a transient detection circuit configured to determine an expected current through a compensation inductor of the coupled inductor voltage regulator based on a state and an operating parameter of the phase of the coupled inductor voltage regulator; Including, the transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in phase overlap of the pulse signal; and in response to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that varies the timing of the pulse signal based on the predicted current through the compensation inductor. Power controller.

2. 2. The power controller of claim 1, wherein the transient detection circuit comprises: enabling the correction to the control loop based on the variability of the overlap indicating an increase in the overlap above a first threshold; disabling the correction to the control loop based on the variability of the overlap exhibiting a decrease below a second threshold after exceeding the first threshold. a power controller configured to:

3. 2. The power controller of claim 1, wherein the transient detection circuit comprises: enabling the correction to the control loop based on the variability of the overlap indicating a decrease in the overlap below a first threshold; disabling the correction to the control loop based on the variability of the overlap exhibiting an increase above a second threshold after falling below the first threshold. a power controller configured to:

4. 2. The power controller of claim 1, wherein the correction to the control loop includes one or more of a first correction to an AC portion of the control loop and a second correction to a DC portion of the control loop.

5. 2. The power controller of claim 1, wherein the transient detection circuit comprises: determining the operating parameters of the coupled inductor voltage regulator based on at least an inductance of the compensation inductor; determining the state of the phase based at least on an amount of the phase present and a state of activating the phase; It is configured as follows: Power controller.

6. 2. The power controller of claim 1 , wherein the correction to the control loop includes a scaled combined rate of change of predicted current supplied by each phase determined based at least in part on the operating parameters and the predicted current through the compensation inductor.

7. 2. The power controller of claim 1, wherein the correction to the control loop includes a load current adjustment for the control loop corresponding to a difference between a reported current demand for the load circuit and a scaled version of the predicted current through the compensation inductor.

8. 2. The power controller of claim 1, comprising a set of programmable registers defining at least a start and end threshold for the transient.

9. 1. A method comprising: determining by a control loop the timing of a pulse signal that activates a phase of an associated inductor voltage regulator based on a current demand of a load circuit; determining, by a transient detection circuit, a predicted current through a compensation inductor of the coupled inductor voltage regulator based on a state and an operating parameter of the phase of the coupled inductor voltage regulator; monitoring in the transient detection circuitry a variability in phase overlap of the pulsed signal to detect a transient condition in the current demand of the load circuit; applying, during at least a portion of the transient condition, a correction to the control loop that varies the timing of the pulse signal based on the predicted current through the compensation inductor; A method comprising:

10. 10. The method of claim 9 further comprising: enabling, by the transient detection circuit, the correction to the control loop based on the variability of the overlap indicating an increase in the overlap above a first threshold; disabling the correction to the control loop based on the variability of the overlap exhibiting a decrease below a second threshold after exceeding the first threshold; A method comprising:

11. 10. The method of claim 9 further comprising: enabling, by the transient detection circuit, the correction to the control loop based on the variability of the overlap indicating a decrease in the overlap below a first threshold; disabling the correction to the control loop based on the variability of the overlap exhibiting an increase above a second threshold after being below the first threshold; The method includes:

12. 10. The method of claim 9, wherein the correction to the control loop includes one or more of a first correction to an AC portion of the control loop and a second correction to a DC portion of the control loop.

13. 10. The method of claim 9 further comprising: determining, by the transient detection circuit, the operating parameters of the coupled inductor voltage regulator based at least on an inductance of the compensation inductor and a voltage across the compensation inductor; determining, by the transient detection circuitry, the state of the phase based at least on an amount of the phase present and a state of activating the phase; A method comprising:

14. 10. The method of claim 9, wherein the correction to the control loop comprises a scaled combined rate of change of predicted current supplied by each phase determined based at least in part on the operating parameters and the predicted current through the compensation inductor.

15. 10. The method of claim 9, wherein the correction to the control loop includes a load current adjustment for the control loop corresponding to a difference between a reported current demand for the load circuit and a scaled version of the predicted current through the compensation inductor.

16. 10. The method of claim 9, further comprising providing, by the transient detection circuitry, a set of programmable registers that define at least a start and an end threshold of the transient condition.

17. An apparatus comprising: one or more computer readable storage media; program instructions stored on said one or more computer readable storage media; Including, The program instructions executable by a processing system may provide the processing system with at least: determining a predicted current through a compensation inductor of the coupled inductor voltage regulator based on a state of a phase of the coupled inductor voltage regulator and an operating parameter of the coupled inductor voltage regulator; detecting a transient in the current demand of a load circuit supplied by the coupled inductor voltage regulator based on a variability in phase overlap of a pulse signal; in response to detecting the transient, applying a correction to a control loop that varies a timing of the pulse signal based on the predicted current through the compensation inductor. Instruct them to Device.

18. 20. The apparatus of claim 17, further comprising instructions executable by the processing system, the instructions causing the processing system to perform at least: enabling the correction to the control loop based on the variability of the overlap indicating an increase in the overlap above a first threshold or a decrease in the overlap below a second threshold; disabling the correction to the control loop based on the variability of the overlap exhibiting a decrease below a third threshold after exceeding the first threshold or an increase above a fourth threshold after falling below the second threshold. The purpose of the instruction is to Device.

19. 20. The apparatus of claim 17, further comprising instructions executable by the processing system, the instructions causing the processing system to perform at least: determining the operating parameters of the coupled inductor voltage regulator based at least on an inductance of the compensation inductor and a voltage across the compensation inductor; determining the state of the phase based at least on an amount of the phase present and a state of activating the phase; The purpose of the instruction is to Device.

20. 20. The apparatus of claim 17, wherein the correction to the control loop includes a load current adjustment for the control loop corresponding to a difference between a reported current demand for the load circuit and a scaled version of the predicted current through the compensation inductor.

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