Semiconductor device

Abstract

To provide a semiconductor device that can reduce on-resistance.SOLUTION: A semiconductor of an embodiment comprises: a semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type; and a gate electrode provided in the semiconductor layer. The second semiconductor region includes first, second, and third regions. The first region is provided between the second region and the first semiconductor region. The third region is provided between the second region and the third semiconductor region. The gate electrode includes first, second, and third portions. The first portion faces the first region. The second portion faces the second region. The third portion faces the third region. The first portion includes a first material. The second portion includes a second material. The third portion includes a third material. When the first conductivity type is an n type, a work function of the first material and the third material is smaller than that of the second material. When the first conductivity type is a p type, the work function of the first material and the third material is larger than that of the second material.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In order to reduce the size or improve the performance of transistors, vertical transistors in which a gate electrode is embedded in a trench provided in a semiconductor layer are used. In vertical transistors, a reduction in on-resistance is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5798517 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region, a second electrode provided on the second surface side of the semiconductor layer, a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region, and a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, the second semiconductor region includes a first region, a second region, and a third region, the first region being provided between the second region and the first semiconductor region, and the third region being provided between the second region and the third semiconductor region; the gate electrode includes a first portion, a second portion, and a third portion, the first portion facing the first region, the second portion facing the second region, and the third portion facing the third region, the first portion including a first material, the second portion including a second material, and the third portion including a third material, wherein when the first conductivity type is n-type and the second conductivity type is p-type, a work function of the first material and a work function of the third material are smaller than a work function of the second material, and when the first conductivity type is p-type and the second conductivity type is n-type, a work function of the first material and a work function of the third material are larger than a work function of the second material. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a schematic top view of a semiconductor device according to a first embodiment; [Diagram 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4]1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 5] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 13] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 17] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 18] 3A to 3C are cross-sectional views showing an example of a manufacturing method of the semiconductor device according to the first embodiment. [Figure 19] FIG. 11 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 20] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third modified example of the first embodiment. [Figure 21] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 22] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a third modified example of the second embodiment. [Figure 23]FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 24] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Diagram 25] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 26] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 27] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment. [Figure 28] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 29] FIG. 23 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar members will be denoted by the same reference numerals, and the description of members that have already been described will be omitted as appropriate.

[0008] In the following description, n + , n, n - And, p + , p, p - When the notations are used, these notations indicate the relative high and low impurity concentrations in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0009] The impurity concentration of the semiconductor device can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration of the semiconductor device can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the width and depth of the impurity region of the semiconductor device can be obtained by, for example, SIMS. Distances such as the width and depth of the impurity region of the semiconductor device can also be obtained from, for example, an SCM image.

[0010] The depth of a trench, the thickness of an insulating layer, etc. of a semiconductor device can be measured on an image taken with a Transmission Electron Microscope (TEM), for example.

[0011] The materials constituting the semiconductor device can be identified by, for example, Energy Dispersive X-ray Spectroscopy (EDX).

[0012] (First embodiment) The semiconductor device of the first embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region, a second electrode provided on the second surface side of the semiconductor layer, a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region, and gate insulating layers provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region. the second semiconductor region includes a first region, a second region, and a third region, the first region being provided between the second region and the first semiconductor region, and the third region being provided between the second region and the third semiconductor region; the gate electrode includes a first portion, a second portion, and a third portion, the first portion facing the first region, the second portion facing the second region, and the third portion facing the third region, the first portion including a first material, the second portion including a second material, and the third portion including a third material, wherein when the first conductivity type is n-type and the second conductivity type is p-type, a work function of the first material and a work function of the third material are smaller than a work function of the second material, and when the first conductivity type is p-type and the second conductivity type is n-type, a work function of the first material and a work function of the third material are larger than a work function of the second material.

[0013] The semiconductor device of the first embodiment is a vertical transistor having a gate electrode embedded in a trench. The semiconductor device of the first embodiment is a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device of the first embodiment is a MOSFET 100. In this specification, a trench refers to a groove or recessed structure that the semiconductor layer itself has, and a configuration other than the semiconductor layer can be provided inside.

[0014] Hereinafter, a case will be described in which the first conductivity type is n-type and the second conductivity type is p-type, that is, an n-channel MOSFET in which electrons are carriers will be described.

[0015] Figures 1 and 2 are schematic top views of a semiconductor device according to a first embodiment. Figure 1 is a top view showing a layout pattern of electrodes and wiring of a MOSFET 100. Figure 2 is a top view showing a layout pattern of trenches of the MOSFET 100. In Figure 2, the layout pattern of electrodes and wiring is indicated by dotted lines.

[0016] Figures 3 and 4 are schematic cross-sectional views of the semiconductor device of the first embodiment. Figure 3 is a cross-section of region X shown in Figures 1 and 2. Figure 4 is a cross-section of region Y shown in Figures 1 and 2. Figure 3 shows the impurity concentration distribution of a part of the semiconductor layer.

[0017] In Figures 1 and 2, the left-right direction is defined as a first direction, and the up-down direction is defined as a second direction. Figures 3 and 4 are cross sections perpendicular to the first direction. In Figures 3 and 4, the up-down direction is defined as a third direction.

[0018] The MOSFET 100 includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0019] The silicon layer 10 is an example of a semiconductor layer. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.

[0020] The gate electrode 16 has a first portion 16a, a second portion 16b, and a third portion 16c. The gate wiring 24 includes a contact portion 24a.

[0021] The silicon layer 10 has a trench 30, n + Drain region 32, n - a p-type drift region 34, a p-type body region 36, + Source region 38, p +The mold contact area 40 is included.

[0022] The drift region 34 is an example of a first semiconductor region, the body region 36 is an example of a second semiconductor region, and the source region 38 is an example of a third semiconductor region.

[0023] The body region 36 includes a first region 36a, a second region 36b, and a third region 36c.

[0024] The silicon layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon layer 10 has a first surface ("F1" in FIG. 3) and a second surface ("F2" in FIG. 3). The second surface F2 faces the first surface F1.

[0025] The first direction and the second direction are parallel to the first face F1. The second direction is a direction intersecting the first direction. The second direction is a direction perpendicular to the first direction. The third direction is a direction perpendicular to the first face F1. The third direction is a direction perpendicular to the first direction and the second direction. The third direction is a direction from the source electrode 12 to the drain electrode 14.

[0026] Hereinafter, the term "depth" refers to the depth based on the first face F1, that is, the distance in the third direction based on the first face F1.

[0027] The silicon layer 10 is made of single crystal silicon (Si). The surface of the silicon layer 10 is inclined at an angle of 0 to 8 degrees with respect to the (100) plane, for example.

[0028] n + A n-type drain region 32 is provided in the silicon layer 10. The drain region 32 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the drain region 32 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0029] n - A drift region 34 of the type is provided in the silicon layer 10. The drift region 34 is provided between the drain region 32 and the first face F1. The drift region 34 is provided on the drain region 32.

[0030] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the drift region 34 is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 34 is, for example, + The epitaxially grown layer is formed on the drain region 32 of the semiconductor substrate 30 by epitaxial growth.

[0031] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 20 μm.

[0032] The p-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first face F1. When the MOSFET 100 is in an on-state, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0033] The body region 36 includes a first region 36a, a second region 36b, and a third region 36c. The first region 36a is provided between the second region 36b and the drift region 34. The third region 36c is provided between the second region 36b and the source region 38.

[0034] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0035] The p-type impurity concentration of the second region 36b is higher than the p-type impurity concentration of the first region 36a, and is higher than the p-type impurity concentration of the third region 36c.

[0036] 3, the p-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Px. Position Px is in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0037] n + A source region 38 of the type is provided in the silicon layer 10. The source region 38 is provided between the body region 36 and the first face F1.

[0038] The source region 38 contains an n-type impurity. The n-type impurity is, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the source region 38 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0039] p + A mold contact region 40 is provided in the silicon layer 10. The contact region 40 is provided between the body region 36 and the first face F1.

[0040] The contact region 40 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the contact region 40 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the contact region 40 is higher than the p-type impurity concentration of the body region 36.

[0041] The trench 30 exists in the silicon layer 10. The trench 30 is located on the side of the first face F1 of the silicon layer 10. The trench 30 is a groove formed in the silicon layer 10.

[0042] The trench 30 penetrates the source region 38 and the body region 36, and reaches the drift region 34. The depth of the trench 30 is, for example, not less than 0.5 μm and not more than 5 μm.

[0043] The trenches 30 extend in a first direction on the first face F1 as shown in Fig. 2. The trenches 30 are repeatedly arranged at a constant pitch in the second direction.

[0044] The gate electrode 16 is provided in the silicon layer 10. The gate electrode 16 is provided in a trench 30. The gate electrode 16 is sandwiched between body regions 36 in a second direction. The gate electrode 16 extends in a first direction.

[0045] The gate electrode 16 has a first portion 16a, a second portion 16b, and a third portion 16c. The second portion 16b is provided between the first portion 16a and the third portion 16c. The first portion 16a is provided on the second face F2 side with respect to the second portion 16b. The third portion 16c is provided on the first face F1 side with respect to the second portion 16b.

[0046] The second portion 16b contacts the first portion 16a and the third portion 16c. The first portion 16a, the second portion 16b, and the third portion 16c are electrically connected to each other.

[0047] The first portion 16a faces the first region 36a of the body region 36 in the second direction. The second portion 16b faces the second region 36b of the body region 36 in the second direction. The third portion 16c faces the third region 36c of the body region 36 in the second direction.

[0048] The first portion 16a includes a first material, the second portion 16b includes a second material, and the third portion 16c includes a third material.

[0049] The first portion 16a is made of, for example, a first material, the second portion 16b is made of, for example, a second material, and the third portion 16c is made of, for example, a third material.

[0050] The first material has a work function less than the work function of the second material, and the third material has a work function less than the work function of the second material.

[0051] The work function is the energy difference between the Fermi level and the vacuum level. By specifying the first material, the second material, and the third material, the work function of each material can be specified.

[0052] The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV, and the difference between the work function of the third material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0053] The first material, the second material, and the third material are n-type polycrystalline silicon containing n-type impurities. The n-type impurity concentration of the first material is higher than the n-type impurity concentration of the second material. The n-type impurity concentration of the third material is higher than the n-type impurity concentration of the second material.

[0054] In n-type polycrystalline silicon, the higher the n-type impurity concentration, the smaller the energy difference between the Fermi level and the bottom of the conduction band, and the smaller the work function.

[0055] The length in the third direction of the second portion 16b (d1 in FIG. 3) is, for example, 20% to 70% of the length in the third direction between the drift region 34 and the source region 38 (d2 in FIG. 3).

[0056] As shown in FIG. 3, a position Px where the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum faces the second portion 16b in, for example, the second direction.

[0057] A gate insulating layer 18 is disposed within the trench 30. The gate insulating layer 18 is disposed between the gate electrode 16 and the silicon layer 10.

[0058] The gate insulating layer 18 is provided between the gate electrode 16 and the body region 36. The gate insulating layer 18 is provided between the gate electrode 16 and the drift region 34. The gate insulating layer 18 is provided between the gate electrode 16 and the source region 38. The gate insulating layer 18 is, for example, silicon oxide.

[0059] The interlayer insulating layer 20 is provided on the silicon layer 10. The interlayer insulating layer 20 is provided between the gate electrode 16 and the source electrode 12. The interlayer insulating layer 20 has a function of electrically isolating the gate electrode 16 and the source electrode 12 from each other.

[0060] The interlayer insulating layer 20 is, for example, silicon oxide.

[0061] The source electrode 12 is provided on the first face F1 side of the silicon layer 10. The source electrode 12 is provided on the first face F1 of the silicon layer 10.

[0062] The source electrode 12 is electrically connected to the source region 38 and the contact region 40. The source electrode 12 contacts the source region 38 and the contact region 40, for example.

[0063] The source electrode 12 is, for example, a region to which a bonding wire is connected when the MOSFET 100 is mounted.

[0064] The source electrode 12 is a metal electrode and has, for example, a laminated structure of titanium (Ti) and aluminum (Al).

[0065] The drain electrode 14 is provided on the second face F2 side of the silicon layer 10. The drain electrode 14 is provided on the second face F2 of the silicon layer 10. The drain electrode 14 is electrically connected to the drain region 32. The drain electrode 14 contacts the drain region 32, for example.

[0066] The drain electrode 14 is a metal electrode and has a laminated structure of a material selected from, for example, titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), and gold (Au).

[0067] The gate electrode pad 22 is provided on the first face F1 side of the silicon layer 10. The gate electrode pad 22 is provided on the first face F1 of the silicon layer 10.

[0068] The gate electrode pad 22 is electrically connected to the gate electrode 16. When the MOSFET 100 is mounted, the gate electrode pad 22 serves as a region to which, for example, a bonding wire is connected.

[0069] The gate electrode pad 22 is a metal electrode. The gate electrode pad 22 has a laminated structure of, for example, titanium (Ti) and aluminum (Al). The material of the gate electrode pad 22 is the same as the material of the source electrode 12, for example.

[0070] 1, the gate wiring 24 is provided at an end of the source electrode 12. The gate wiring 24 is electrically connected to the gate electrode 16.

[0071] The gate wiring 24 is a metal wiring. The gate wiring 24 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The material of the gate wiring 24 is, for example, the same as the material of the source electrode 12 and the material of the gate electrode pad 22.

[0072] 4, the gate wiring 24 is connected to the gate electrode 16 in the region Y. A contact portion 24a of the gate wiring 24 is connected to the gate electrode 16 in the region Y. The contact portion 24a penetrates the interlayer insulating layer 20 and is connected to the gate electrode 16, for example.

[0073] The contact portion 24a contacts, for example, the third portion 16c of the gate electrode 16. The contact portion 24a is electrically and physically connected to the third portion 16c of the gate electrode 16, for example.

[0074] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described. Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are cross-sectional views showing an example of the method for manufacturing the semiconductor device of the first embodiment.

[0075] Figures 5 to 18 are cross sections of region X in Figures 1 and 2. Figures 5 to 18 are cross sections corresponding to Figure 3.

[0076] First, a silicon layer 10 is prepared (FIG. 5). The silicon layer 10 is an n + The drain region 32 and the n - The drift region 34 includes a mold.

[0077] Drift region 34 is formed over drain region 32 using, for example, an epitaxial growth process.

[0078] Next, a mask material 50 is formed on the silicon layer 10 (FIG. 6). The mask material 50 is formed by, for example, a chemical vapor deposition method (CVD method), a photolithography method, and a reactive ion etching method (RIE method). The mask material 50 is, for example, silicon nitride or silicon oxide.

[0079] Next, the mask material 50 is used as a mask to form the trench 30 (FIG. 7). The trench 30 is formed by using, for example, the RIE method.

[0080] Next, the gate insulating layer 18 is formed on the inner wall of the trench 30 (FIG. 8). The gate insulating layer 18 is formed by, for example, thermal oxidation.

[0081] Next, the trench 30 is filled with n-type first polycrystalline silicon 51 (FIG. 9). The first polycrystalline silicon 51 is formed by, for example, a CVD method.

[0082] Next, the first polycrystalline silicon 51 is etched to form the first portion 16a of the gate electrode 16 (FIG. 10). The first portion 16a is formed by using, for example, the RIE method.

[0083] Next, the trench 30 is filled with n-type second polycrystalline silicon 52 (FIG. 11). The second polycrystalline silicon 52 is formed by, for example, a CVD method. The n-type impurity concentration of the second polycrystalline silicon 52 is lower than the n-type impurity concentration of the first polycrystalline silicon 51.

[0084] Next, the second polycrystalline silicon 52 is etched to form the second portion 16b of the gate electrode 16 (FIG. 12). The second portion 16b is formed by using, for example, the RIE method.

[0085] Next, the trench 30 is filled with n-type third polycrystalline silicon 53 (FIG. 13). The third polycrystalline silicon 53 is formed by, for example, a CVD method. The n-type impurity concentration of the third polycrystalline silicon 53 is higher than the n-type impurity concentration of the second polycrystalline silicon 52.

[0086] Next, the third polycrystalline silicon 53 is etched to form the third portion 16c of the gate electrode 16 (FIG. 14). The third portion 16c is formed by using, for example, the RIE method.

[0087] Next, the mask material 50 is removed (FIG. 15). The mask material 50 is removed by using, for example, a wet etching method.

[0088] Next, the silicon layer 10 is provided with a p-type body region 36 and a n + Then, a source region 38 of the body region 36 is formed (FIG. 16). The body region 36 and the source region 38 are formed by using an ion implantation method.

[0089] Next, an interlayer insulating layer 20 having an opening is formed on the silicon layer 10 (FIG. 17). The interlayer insulating layer 20 is formed by using, for example, a CVD method, a photolithography method, and an RIE method.

[0090] Next, the silicon layer 10 is + A mold contact region 40 is formed. The contact region 40 is formed, for example, by ion implantation using the interlayer insulating layer 20 having an opening as a mask material.

[0091] Next, the opening of the interlayer insulating layer 20 is expanded laterally, and n + The source region 38 of the mold is exposed (FIG. 18). The opening in the interlayer insulating layer 20 is widened laterally, for example by using a wet etching method.

[0092] Thereafter, the source electrode 12, the gate electrode pad 22, the gate wiring 24, and the drain electrode 14 are formed using a known manufacturing method.

[0093] By the above manufacturing method, the MOSFET 100 of the first embodiment is manufactured.

[0094] The operation and effects of the semiconductor device of the first embodiment will be described below.

[0095] In order to reduce the size or improve the performance of transistors, vertical transistors in which a gate electrode is embedded in a trench provided in a semiconductor layer are used. In vertical transistors, a reduction in on-resistance is required.

[0096] Fig. 19 is a schematic cross-sectional view of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a MOSFET 900. Fig. 19 is a view corresponding to Fig. 3 of the first embodiment.

[0097] The MOSFET 900 differs from the MOSFET 100 of the first embodiment in that the gate electrode 16 does not include the first portion 16a, the second portion 16b, and the third portion 16c.

[0098] The on-resistance of MOSFET 900 includes the channel resistance and the resistance of drift region 34. For example, in a MOSFET used particularly for low-voltage applications, the drift region 34 is thin, and therefore the resistance of drift region 34 is low. Therefore, in a MOSFET used particularly for low-voltage applications, the proportion of channel resistance in the on-resistance is large.

[0099] One possible way to reduce the channel resistance of the MOSFET 900 is, for example, to lower the threshold voltage of the MOSFET 900. By lowering the threshold voltage of the MOSFET 900, the electron density of the inversion layer increases when the MOSFET 900 is in the on state, thereby reducing the channel resistance.

[0100] However, if the threshold voltage of the MOSFET 900 is reduced, problems arise because the MOSFET 900 may unexpectedly turn on when it is in the off state, or the leakage current may increase when the MOSFET 900 is in the off state.

[0101] In the MOSFET 100 of the first embodiment, the gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The work function of the first material included in the first portion 16a is smaller than the work function of the second material included in the second portion 16b. The work function of the third material included in the third portion 16c is smaller than the work function of the second material included in the second portion 16b.

[0102] Since the work function of the first material is smaller than that of the second material, the threshold voltage of the MOSFET formed by the first portion 16a, the gate insulating layer 18, and the first region 36a becomes lower than the threshold voltage of the MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode becomes lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0103] Similarly, since the work function of the third material is smaller than that of the second material, the threshold voltage of a MOSFET formed by the third portion 16c, the gate insulating layer 18, and the third region 36c becomes lower than the threshold voltage of a MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of a MOSFET having the third portion 16c as its gate electrode becomes lower than the threshold voltage of a MOSFET having the second portion 16b as its gate electrode.

[0104] In the MOSFET 100 of the first embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode and the threshold voltage of the MOSFET having the third portion 16c as the gate electrode are lowered, so that the channel resistance of the channel formed in the first region 36a and the channel resistance of the channel formed in the third region 36c are lowered. Therefore, the on-resistance of the MOSFET 100 is reduced.

[0105] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 100 can be kept high.

[0106] 3, consider a case where the p-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has a maximum peak in the second region 36b. In this case, it is preferable that the position Px where the p-type impurity concentration is maximum faces the second portion 16b in the second direction. By having the position Px where the p-type impurity concentration is maximum face the second portion 16b, it is possible to further increase the threshold voltage of a MOSFET having the second portion 16b as the gate electrode.

[0107] From the viewpoint of reducing the on-resistance of the MOSFET 100, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0108] Similarly, from the viewpoint of reducing the on-resistance of MOSFET 100, the difference between the work function of the third material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0109] The length in the third direction of the second portion 16b (d1 in FIG. 3) is, for example, preferably 20% to 70% of the length in the third direction between the drift region 34 and the source region 38 (d2 in FIG. 3), more preferably 30% to 60%, and even more preferably 40% to 50%. By exceeding the lower limit, the decrease in the threshold voltage can be suppressed. Also, by falling below the upper limit, the on-resistance is further reduced.

[0110] As described above, the MOSFET 100 of the first embodiment can reduce the on-resistance.

[0111] (First Modification) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the second material is p-type polycrystalline silicon.

[0112] In the MOSFET of the first modification of the first embodiment, the second material contained in the second portion 16b of the gate electrode 16 is p-type polycrystalline silicon, and the first material contained in the first portion 16a of the gate electrode 16 and the third material contained in the third portion 16c of the gate electrode 16 are n-type polycrystalline silicon.

[0113] By using p-type polycrystalline silicon as the second material, the work function of the second material becomes larger than that of the second material being n-type polycrystalline silicon, and therefore the difference between the work function of the first material and the work function of the second material, and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 100 of the first embodiment.

[0114] Therefore, according to the MOSFET of the first modification of the first embodiment, it is possible to reduce the on-resistance more than, for example, the MOSFET 100 of the first embodiment.

[0115] (Second Modification) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the first material, the second material, or the third material is a metal or a metal semiconductor compound.

[0116] In the MOSFET of the second modification of the first embodiment, at least one of the first material contained in the first portion 16a of the gate electrode 16, the second material contained in the second portion 16b of the gate electrode 16, and the third material contained in the third portion 16c of the gate electrode 16 is a metal or a metal semiconductor compound. All of the first material, the second material, and the third material may be a metal or a metal semiconductor compound.

[0117] By using at least one of the first material, the second material, and the third material as a metal or a metal semiconductor compound, for example, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 100 of the first embodiment. In addition, for example, the electrical resistance of the gate electrode 16 can be reduced, enabling the MOSFET to operate at high speed.

[0118] According to the MOSFET of the second modification of the first embodiment, for example, it is possible to reduce the on-resistance more than that of the MOSFET 100 of the first embodiment. Also, for example, the MOSFET can operate at high speed.

[0119] (Third Modification) The semiconductor device according to the third modification of the first embodiment differs from the semiconductor device according to the first embodiment in that a field plate electrode is provided.

[0120] Fig. 20 is a schematic cross-sectional view of a semiconductor device according to a third modified example of the first embodiment, which corresponds to Fig. 3 of the first embodiment.

[0121] The MOSFET 101 of the third modified example of the first embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, a gate wiring 24, a field plate electrode 26, and a field plate insulating layer 28.

[0122] The field plate electrode 26 is provided in the trench 30. The field plate electrode 26 is provided between the gate electrode 16 and the second face F2 in the third direction. The field plate electrode 26 extends in the first direction.

[0123] The field plate electrode 26 has a function of changing the electric field distribution in the drift region 34 when the MOSFET 101 is in an off state, thereby improving the breakdown voltage of the MOSFET 101.

[0124] The field plate electrode 26 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0125] The field plate insulating layer 28 is provided between the field plate electrode 26 and the silicon layer 10. The field plate insulating layer 28 is provided between the field plate electrode 26 and the drift region 34. The field plate insulating layer 28 is provided between the field plate electrode 26 and the gate electrode 16. The field plate insulating layer 28 is, for example, silicon oxide.

[0126] The thickness of the field plate insulating layer 28 is, for example, greater than the thickness of the gate insulating layer 18 .

[0127] The MOSFET 101 of the third modified example of the first embodiment includes the field plate electrode 26, which improves, for example, the breakdown voltage. Furthermore, the MOSFET 101 of the third modified example of the first embodiment includes the field plate electrode 26, which can reduce, for example, the impurity concentration of the drift region 34. Therefore, for example, the resistance of the drift region 34 can be reduced, and the on-resistance can be reduced.

[0128] According to the MOSFET 101 of the third modification of the first embodiment, for example, it is possible to improve the breakdown voltage as compared with the MOSFET 100 of the first embodiment. Also, for example, it is possible to reduce the on-resistance as compared with the MOSFET 100 of the first embodiment.

[0129] As described above, according to the first embodiment and its modifications, a semiconductor device capable of reducing the on-resistance can be realized.

[0130] Second embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the first conductivity type is p-type, the second conductivity type is n-type, and the work function of the first material and the work function of the third material are greater than the work function of the second material. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0131] Hereinafter, a case will be described in which the first conductivity type is p-type and the second conductivity type is n-type, that is, a p-channel MOSFET in which holes are carriers will be described.

[0132] Fig. 21 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 3 of the first embodiment, and shows the impurity concentration distribution in a part of a semiconductor layer.

[0133] The MOSFET 200 includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0134] The silicon layer 10 is an example of a semiconductor layer. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.

[0135] The gate electrode 16 has a first portion 16a, a second portion 16b, and a third portion 16c. The gate wiring 24 includes a contact portion 24a.

[0136] The silicon layer 10 includes a trench 30, a p + Drain region 32, p - a n-type drift region 34, a n-type body region 36, + Source region 38, n + The mold contact area 40 is included.

[0137] The drift region 34 is an example of a first semiconductor region, the body region 36 is an example of a second semiconductor region, and the source region 38 is an example of a third semiconductor region.

[0138] The body region 36 includes a first region 36a, a second region 36b, and a third region 36c.

[0139] p + The drain region 32 contains a p-type impurity. The p-type impurity is, for example, boron (B). The concentration of the p-type impurity in the drain region 32 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0140] p - The drift region 34 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the drift region 34 is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The following is the result.

[0141] The n-type body region 36 includes a first region 36a, a second region 36b, and a third region 36c.

[0142] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0143] The n-type impurity concentration of the second region 36b is higher than the n-type impurity concentration of the first region 36a, and is higher than the n-type impurity concentration of the third region 36c.

[0144] 21, the n-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Py. Position Py is in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0145] p + The source region 38 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the source region 38 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0146] n + The contact region 40 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the contact region 40 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The n-type impurity concentration of the contact region 40 is higher than the n-type impurity concentration of the body region 36.

[0147] The gate electrode 16 has a first portion 16a, a second portion 16b, and a third portion 16c. The first portion 16a includes a first material. The second portion 16b includes a second material. The third portion 16c includes a third material.

[0148] The work function of the first material is greater than the work function of the second material. The work function of the third material is greater than the work function of the second material.

[0149] The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV, and the difference between the work function of the third material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0150] The first material, the second material, and the third material are p-type polycrystalline silicon containing p-type impurities. The p-type impurity concentration of the first material is higher than the p-type impurity concentration of the second material. The p-type impurity concentration of the third material is higher than the p-type impurity concentration of the second material.

[0151] In p-type polycrystalline silicon, the higher the p-type impurity concentration, the smaller the energy difference between the Fermi level and the top of the valence band, and the larger the work function.

[0152] The length in the third direction of the second portion 16b (d1 in FIG. 21) is, for example, 20% to 70% of the length in the third direction between the drift region 34 and the source region 38 (d2 in FIG. 21).

[0153] As shown in FIG. 21, a position Py at which the n-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum faces the second portion 16b in, for example, the second direction.

[0154] In the MOSFET 200 of the second embodiment, the gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The work function of the first material included in the first portion 16a is greater than the work function of the second material included in the second portion 16b. The work function of the third material included in the third portion 16c is greater than the work function of the second material included in the second portion 16b.

[0155] Since the work function of the first material is larger than that of the second material, the threshold voltage of the MOSFET formed by the first portion 16a, the gate insulating layer 18, and the first region 36a becomes lower than the threshold voltage of the MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode becomes lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0156] Similarly, since the work function of the third material is larger than that of the second material, the threshold voltage of a MOSFET formed by the third portion 16c, the gate insulating layer 18, and the third region 36c becomes lower than the threshold voltage of a MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of a MOSFET having the third portion 16c as its gate electrode becomes lower than the threshold voltage of a MOSFET having the second portion 16b as its gate electrode.

[0157] In the MOSFET 200 of the second embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode and the threshold voltage of the MOSFET having the third portion 16c as the gate electrode are lowered, so that the channel resistance of the channel formed in the first region 36a and the channel resistance of the channel formed in the third region 36c are lowered. Therefore, the on-resistance of the MOSFET 200 is reduced.

[0158] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 200 can be kept high.

[0159] 21, consider a case where the n-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has a maximum peak in the second region 36b. In this case, it is preferable that the position Py where the n-type impurity concentration is maximum faces the second portion 16b in the second direction. By having the position Py where the n-type impurity concentration is maximum face the second portion 16b, it is possible to further increase the threshold voltage of a MOSFET having the second portion 16b as the gate electrode.

[0160] From the viewpoint of reducing the on-resistance of the MOSFET 200, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0161] Similarly, from the viewpoint of reducing the on-resistance of MOSFET 200, the difference between the work function of the third material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0162] The length in the third direction of the second portion 16b (d1 in FIG. 21) is, for example, preferably 20% to 70% of the length in the third direction between the drift region 34 and the source region 38 (d2 in FIG. 21), more preferably 30% to 60%, and even more preferably 40% to 50%. By exceeding the lower limit, the decrease in the threshold voltage can be suppressed. Also, by falling below the upper limit, the on-resistance is further reduced.

[0163] As described above, according to the MOSFET 200 of the second embodiment, the on-resistance can be reduced.

[0164] (First Modification) The semiconductor device of the first modification of the second embodiment differs from the semiconductor device of the second embodiment in that the second material is n-type polycrystalline silicon.

[0165] In the MOSFET of the second modification of the second embodiment, the second material contained in the second portion 16b of the gate electrode 16 is n-type polycrystalline silicon, and the first material contained in the first portion 16a of the gate electrode 16 and the third material contained in the third portion 16c of the gate electrode 16 are p-type polycrystalline silicon.

[0166] By using n-type polycrystalline silicon as the second material, the work function of the second material becomes smaller than that of the second material being p-type polycrystalline silicon, and therefore the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 200 of the second embodiment.

[0167] According to the MOSFET of the first modification of the second embodiment, for example, it is possible to reduce the on-resistance more than that of the MOSFET 200 of the second embodiment.

[0168] (Second Modification) The semiconductor device of the second modification of the second embodiment differs from the semiconductor device of the second embodiment in that the first material, the second material, or the third material is a metal or a metal semiconductor compound.

[0169] In the MOSFET of the second modification of the second embodiment, at least one of the first material contained in the first portion 16a of the gate electrode 16, the second material contained in the second portion 16b of the gate electrode 16, and the third material contained in the third portion 16c of the gate electrode 16 is a metal or a metal semiconductor compound. All of the first material, the second material, and the third material may be a metal or a metal semiconductor compound.

[0170] By using at least one of the first material, the second material, and the third material as a metal or a metal semiconductor compound, for example, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 200 of the second embodiment. In addition, for example, the electrical resistance of the gate electrode 16 can be reduced, enabling the MOSFET to operate at high speed.

[0171] According to the MOSFET of the second modification of the second embodiment, for example, it is possible to reduce the on-resistance more than that of the MOSFET 200 of the second embodiment. Also, for example, the MOSFET can operate at high speed.

[0172] (Third Modification) The semiconductor device according to the third modification of the second embodiment differs from the semiconductor device according to the second embodiment in that a field plate electrode is provided.

[0173] Fig. 22 is a schematic cross-sectional view of a semiconductor device according to a third modified example of the second embodiment, which corresponds to Fig. 21 of the second embodiment.

[0174] A MOSFET 201 according to the third modified example of the second embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, a gate wiring 24, a field plate electrode 26, and a field plate insulating layer 28.

[0175] The field plate electrode 26 is provided in the trench 30. The field plate electrode 26 is provided between the gate electrode 16 and the second face F2 in the third direction. The field plate electrode 26 extends in the first direction.

[0176] The field plate electrode 26 has a function of changing the electric field distribution in the drift region 34 when the MOSFET 201 is in an off state, thereby improving the breakdown voltage of the MOSFET 201 .

[0177] The field plate electrode 26 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0178] The field plate insulating layer 28 is provided between the field plate electrode 26 and the silicon layer 10. The field plate insulating layer 28 is provided between the field plate electrode 26 and the drift region 34. The field plate insulating layer 28 is provided between the field plate electrode 26 and the gate electrode 16. The field plate insulating layer 28 is, for example, silicon oxide.

[0179] The thickness of the field plate insulating layer 28 is, for example, greater than the thickness of the gate insulating layer 18 .

[0180] The MOSFET 201 of the third modified example of the second embodiment includes the field plate electrode 26, which improves, for example, the breakdown voltage. Furthermore, the MOSFET 201 of the third modified example of the second embodiment includes the field plate electrode 26, which can reduce, for example, the impurity concentration of the drift region 34. Therefore, for example, the resistance of the drift region 34 can be reduced, and the on-resistance can be reduced.

[0181] According to the MOSFET 201 of the third modification of the second embodiment, for example, it is possible to improve the breakdown voltage as compared with the MOSFET 200 of the second embodiment. Also, for example, it is possible to reduce the on-resistance as compared with the MOSFET 200 of the second embodiment.

[0182] As described above, according to the second embodiment and its modification, a semiconductor device capable of reducing the on-resistance can be realized.

[0183] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that a first insulating film is provided between the first portion and the second portion, and a second insulating film is provided between the second portion and the third portion. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0184] Figures 23 and 24 are schematic cross-sectional views of a semiconductor device according to a third embodiment. Figure 23 corresponds to Figures 3 and 4 of the first embodiment. Figure 23 shows the impurity concentration distribution of a part of a semiconductor layer.

[0185] The MOSFET 300 of the third embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, a gate wiring 24, a first insulating film 61, and a second insulating film 62.

[0186] The first material, the second material, and the third material are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0187] The first insulating film 61 is provided between the first portion 16a and the second portion 16b. The first insulating film 61 includes, for example, an oxide, a nitride, or an oxynitride. The first insulating film 61 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0188] The thickness of the first insulating film 61 is, for example, thinner than the thickness of the gate insulating layer 18.

[0189] The first insulating film 61 has a function of suppressing, for example, the diffusion of impurities between the first portion 16a and the second portion 16b. The first insulating film 61 suppresses, for example, the diffusion of impurities between the first portion 16a and the second portion 16b, which causes the work function of the first material and the work function of the second material to deviate from the desired values.

[0190] The second insulating film 62 is provided between the third portion 16c and the second portion 16b. The second insulating film 62 includes, for example, an oxide, a nitride, or an oxynitride. The second insulating film 62 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0191] The thickness of the second insulating film 62 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0192] The second insulating film 62 has a function of suppressing, for example, the diffusion of impurities between the third portion 16c and the second portion 16b. The second insulating film 62 suppresses, for example, the diffusion of impurities between the third portion 16c and the second portion 16b, which causes the work function of the third material and the work function of the second material to deviate from the desired values.

[0193] 24, the gate wiring 24 is connected to the gate electrode 16 in the region Y. A contact portion 24a of the gate wiring 24 is connected to the gate electrode 16 in the region Y.

[0194] The contact portion 24a penetrates the interlayer insulating layer 20, the third portion 16c, the second insulating film 62, the second portion 16b, and the first insulating film 61, and reaches the first portion 16a.

[0195] The contact portion 24a contacts, for example, the third portion 16c, the second portion 16b, and the first portion 16a of the gate electrode 16. The contact portion 24a is electrically and physically connected, for example, to the third portion 16c, the second portion 16b, and the first portion 16a of the gate electrode 16. The contact portion 24a electrically connects the first portion 16a, the second portion 16b, and the third portion 16c.

[0196] As described above, according to the third embodiment, like the first embodiment, a semiconductor device capable of reducing the on-resistance can be realized.

[0197] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the second embodiment in that a first insulating film is provided between the first portion and the second portion, and a second insulating film is provided between the second portion and the third portion. The semiconductor device of the fourth embodiment also differs from the semiconductor device of the third embodiment in that the first conductive type is p-type, the second conductive type is n-type, and the work function of the first material and the work function of the third material are greater than the work function of the second material. Hereinafter, some of the contents that overlap with the second or third embodiment may be omitted.

[0198] Fig. 25 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment, which corresponds to Fig. 21 of the second embodiment, and shows the impurity concentration distribution in a part of a semiconductor layer.

[0199] The MOSFET 400 of the fourth embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, a gate wiring 24, a first insulating film 61, and a second insulating film 62.

[0200] The first material, the second material, and the third material are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0201] The first insulating film 61 is provided between the first portion 16a and the second portion 16b. The first insulating film 61 includes, for example, an oxide, a nitride, or an oxynitride. The first insulating film 61 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0202] The thickness of the first insulating film 61 is, for example, thinner than the thickness of the gate insulating layer 18.

[0203] The first insulating film 61 has a function of suppressing, for example, the diffusion of impurities between the first portion 16a and the second portion 16b. The first insulating film 61 suppresses, for example, the diffusion of impurities between the first portion 16a and the second portion 16b, which causes the work function of the first material and the work function of the second material to deviate from the desired values.

[0204] The second insulating film 62 is provided between the third portion 16c and the second portion 16b. The second insulating film 62 includes, for example, an oxide, a nitride, or an oxynitride. The second insulating film 62 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0205] The thickness of the second insulating film 62 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0206] The second insulating film 62 has a function of suppressing, for example, the diffusion of impurities between the third portion 16c and the second portion 16b. The second insulating film 62 suppresses, for example, the diffusion of impurities between the third portion 16c and the second portion 16b, which causes the work function of the third material and the work function of the second material to deviate from the desired values.

[0207] The first portion 16a, the second portion 16b, and the third portion 16c are electrically connected to each other via a contact portion (not shown).

[0208] As described above, according to the fourth embodiment, like the second embodiment, a semiconductor device capable of reducing the on-resistance can be realized.

[0209] Fifth embodiment A semiconductor device of a fifth embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including an n-type first semiconductor region, a p-type second semiconductor region provided between the first semiconductor region and the first surface, and an n-type third semiconductor region provided between the second semiconductor region and the first surface, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region, a second electrode provided on the second surface side of the semiconductor layer, a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region, and gate insulating layers provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region. The second semiconductor region includes a first region and a second region, the first region being provided between the second region and the first semiconductor region or between the second region and the third semiconductor region, the gate electrode includes a first portion and a second portion, the first portion faces the first region and the second portion faces the second region, the first portion includes a first material and the second portion includes a second material, the first material is n-type polycrystalline silicon, and a work function of the first material is smaller than a work function of the second material.

[0210] The semiconductor device of the fifth embodiment differs from the semiconductor device of the first embodiment in that the gate electrode does not include the third portion. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0211] Fig. 26 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment, which corresponds to Fig. 3 of the first embodiment, and shows the impurity concentration distribution in a part of a semiconductor layer.

[0212] The MOSFET 500 of the fifth embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0213] The gate electrode 16 has a first portion 16a and a second portion 16b.

[0214] The silicon layer 10 has a trench 30, n + Drain region 32, n - a p-type drift region 34, a p-type body region 36, + Source region 38, p + The mold contact area 40 is included.

[0215] The p-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first face F1. When the MOSFET 500 is in an on-state, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0216] The body region 36 includes a first region 36a and a second region 36b. The first region 36a is provided between the second region 36b and the drift region 34.

[0217] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm-3 The following is the result.

[0218] The p-type impurity concentration of the second region 36b is higher than the p-type impurity concentration of the first region 36a.

[0219] 26, the p-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Px. Position Px is in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0220] The gate electrode 16 has a first portion 16a and a second portion 16b. The first portion 16a is provided on the second face F2 side with respect to the second portion 16b.

[0221] The second portion 16b contacts the first portion 16a. The first portion 16a and the second portion 16b are electrically connected to each other.

[0222] The first portion 16a faces a first region 36a of the body region 36 in the second direction. The second portion 16b faces a second region 36b of the body region 36 in the second direction.

[0223] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is made of, for example, the first material. The second portion 16b is made of, for example, the second material.

[0224] The work function of the first material is smaller than the work function of the second material, and the difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0225] The first material and the second material are n-type polycrystalline silicon containing n-type impurities, and the n-type impurity concentration of the first material is higher than the n-type impurity concentration of the second material.

[0226] As shown in FIG. 26, a position Px at which the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum faces the second portion 16b in, for example, the second direction.

[0227] In the MOSFET 500 of the fifth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is smaller than the work function of the second material included in the second portion 16b.

[0228] Since the work function of the first material is smaller than that of the second material, the threshold voltage of the MOSFET constituted by the first portion 16a, the gate insulating layer 18, and the first region 36a is lower than the threshold voltage of the MOSFET constituted by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode is lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0229] In the MOSFET 500 of the fifth embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode is lowered, and thus the channel resistance of the channel formed in the first region 36a is lowered, thereby reducing the on-resistance of the MOSFET 500.

[0230] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 500 can be kept high.

[0231] For example, as shown in FIG. 26, by positioning Px where the p-type impurity concentration is maximum facing the second portion 16b, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode can be further increased.

[0232] From the viewpoint of reducing the on-resistance of the MOSFET 500, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0233] As described above, according to the MOSFET 500 of the fifth embodiment, the on-resistance can be reduced.

[0234] (First Modification) The semiconductor device of the first modification of the fifth embodiment differs from the semiconductor device of the fifth embodiment in that the second material is p-type polycrystalline silicon.

[0235] In the MOSFET of the first modification of the fifth embodiment, the second material contained in the second portion 16b of the gate electrode 16 is p-type polycrystalline silicon, and the first material contained in the first portion 16a of the gate electrode 16 is n-type polycrystalline silicon.

[0236] By using p-type polycrystalline silicon as the second material, the work function of the second material becomes larger than that of the second material using n-type polycrystalline silicon, and therefore the difference between the work function of the first material and the work function of the second material can be made larger than that of the MOSFET 500 of the fifth embodiment.

[0237] According to the MOSFET of the first modification of the fifth embodiment, for example, it is possible to reduce the on-resistance more than that of the MOSFET 500 of the fifth embodiment.

[0238] (Second Modification) The semiconductor device of the second modification of the fifth embodiment differs from the semiconductor device of the fifth embodiment in that the first region of the second semiconductor region is provided between the second region and the third semiconductor region.

[0239] Fig. 27 is a schematic cross-sectional view of a semiconductor device according to a second modification of the fifth embodiment. Fig. 27 corresponds to Fig. 26 of the fifth embodiment. Fig. 27 shows an impurity concentration distribution in a part of a semiconductor layer. The semiconductor device according to the second modification of the fifth embodiment is a MOSFET 501.

[0240] The p-type body region 36 includes a first region 36a and a second region 36b. The first region 36a is provided between the second region 36b and the source region 38.

[0241] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0242] The p-type impurity concentration of the second region 36b is higher than the p-type impurity concentration of the first region 36a.

[0243] 27, the p-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Px. Position Px is in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0244] The gate electrode 16 has a first portion 16a and a second portion 16b. The first portion 16a is provided on the first face F1 side relative to the second portion 16b.

[0245] The second portion 16b contacts the first portion 16a. The first portion 16a and the second portion 16b are electrically connected to each other.

[0246] The first portion 16a faces a first region 36a of the body region 36 in the second direction. The second portion 16b faces a second region 36b of the body region 36 in the second direction.

[0247] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is made of, for example, the first material. The second portion 16b is made of, for example, the second material.

[0248] The work function of the first material is smaller than the work function of the second material, and the difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0249] The first material and the second material are n-type polycrystalline silicon containing n-type impurities, and the n-type impurity concentration of the first material is higher than the n-type impurity concentration of the second material.

[0250] As shown in FIG. 27, a position Px at which the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum faces the second portion 16b in, for example, the second direction.

[0251] In a MOSFET 501 according to a second modification of the fifth embodiment, a gate electrode 16 includes a first portion 16a and a second portion 16b. A work function of a first material included in the first portion 16a is smaller than a work function of a second material included in the second portion 16b.

[0252] Since the work function of the first material is smaller than that of the second material, the threshold voltage of the MOSFET formed by the first portion 16a, the gate insulating layer 18, and the first region 36a becomes lower than the threshold voltage of the MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode becomes lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0253] In the MOSFET 501 according to the second modification of the fifth embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode is lowered, and thus the channel resistance of the channel formed in the first region 36a is lowered, thereby reducing the on-resistance of the MOSFET 501.

[0254] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 501 can be kept high.

[0255] For example, as shown in FIG. 27, by arranging the position Px where the p-type impurity concentration is maximum facing the second portion 16b, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode can be further increased.

[0256] From the viewpoint of reducing the on-resistance of the MOSFET 501, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0257] According to the MOSFET 501 of the second modification of the fifth embodiment, the on-resistance can be reduced, similarly to the MOSFET 500 of the fifth embodiment.

[0258] As described above, according to the fifth embodiment and its modifications, a semiconductor device capable of reducing the on-resistance can be realized.

[0259] Sixth embodiment A semiconductor device of a sixth embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a p-type first semiconductor region, an n-type second semiconductor region provided between the first semiconductor region and the first surface, and a p-type third semiconductor region provided between the second semiconductor region and the first surface, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region, a second electrode provided on the second surface side of the semiconductor layer, and a gate electrode provided in the semiconductor layer and opposite to the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, wherein the second semiconductor region includes a first region and a second region, and the first region is provided between the second region and the first semiconductor region or between the second region and the third semiconductor region, the gate electrode includes a first portion and a second portion, the first portion faces the first region and the second portion faces the second region, the first portion includes a first material, and the second portion includes a second material, and a work function of the first material is greater than a work function of the second material.

[0260] The semiconductor device of the sixth embodiment differs from the semiconductor device of the second embodiment in that the gate electrode does not include the third portion. In the following, some of the contents that overlap with the second embodiment may be omitted.

[0261] Fig. 28 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment, which corresponds to Fig. 21 of the second embodiment, and shows the impurity concentration distribution in a part of a semiconductor layer.

[0262] The MOSFET 600 of the sixth embodiment includes a silicon layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24.

[0263] The gate electrode 16 has a first portion 16a and a second portion 16b.

[0264] The silicon layer 10 includes a trench 30, a p + Drain region 32, p - a n-type drift region 34, a n-type body region 36, + Source region 38, n + The mold contact area 40 is included.

[0265] The n-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first face F1. When the MOSFET 600 is in an on-state, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0266] The body region 36 includes a first region 36a and a second region 36b. The first region 36a is provided between the second region 36b and the drift region 34.

[0267] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0268] The n-type impurity concentration of the second region 36b is higher than the n-type impurity concentration of the first region 36a.

[0269] 28, the n-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Py. Position Py is in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0270] The gate electrode 16 has a first portion 16a and a second portion 16b. The first portion 16a is provided on the second face F2 side with respect to the second portion 16b.

[0271] The second portion 16b contacts the first portion 16a. The first portion 16a and the second portion 16b are electrically connected to each other.

[0272] The first portion 16a faces a first region 36a of the body region 36 in the second direction. The second portion 16b faces a second region 36b of the body region 36 in the second direction.

[0273] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is made of, for example, the first material. The second portion 16b is made of, for example, the second material.

[0274] The work function of the first material is larger than the work function of the second material, and the difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0275] The first material and the second material are p-type polycrystalline silicon containing p-type impurities, and the p-type impurity concentration of the first material is higher than the p-type impurity concentration of the second material.

[0276] As shown in FIG. 28, a position Py at which the n-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 is maximum faces the second portion 16b in, for example, the second direction.

[0277] In the MOSFET 600 of the sixth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is greater than the work function of the second material included in the second portion 16b.

[0278] Since the work function of the first material is larger than that of the second material, the threshold voltage of the MOSFET formed by the first portion 16a, the gate insulating layer 18, and the first region 36a becomes lower than the threshold voltage of the MOSFET formed by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode becomes lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0279] In the MOSFET 600 of the sixth embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode is lowered, and thus the channel resistance of the channel formed in the first region 36a is lowered, thereby reducing the on-resistance of the MOSFET 600.

[0280] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 600 can be kept high.

[0281] For example, as shown in FIG. 28, by position Py where the n-type impurity concentration is maximum facing second portion 16b, the threshold voltage of the MOSFET having second portion 16b as the gate electrode can be further increased.

[0282] From the viewpoint of reducing the on-resistance of the MOSFET 600, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0283] As described above, according to the MOSFET 600 of the sixth embodiment, the on-resistance can be reduced.

[0284] (First Modification) The semiconductor device of the first modified example of the sixth embodiment differs from the semiconductor device of the sixth embodiment in that the second material is n-type polycrystalline silicon.

[0285] In the MOSFET of the first modification of the sixth embodiment, the second material contained in the second portion 16b of the gate electrode 16 is n-type polycrystalline silicon, and the first material contained in the first portion 16a of the gate electrode 16 is p-type polycrystalline silicon.

[0286] By using n-type polycrystalline silicon as the second material, the work function of the second material is smaller than that of the second material being p-type polycrystalline silicon, and therefore the difference between the work function of the first material and the work function of the second material can be made larger than that of the MOSFET 600 of the sixth embodiment.

[0287] According to the MOSFET of the first modified example of the sixth embodiment, for example, it is possible to reduce the on-resistance more than that of the MOSFET 600 of the sixth embodiment.

[0288] (Second Modification) The semiconductor device of the second modification of the sixth embodiment differs from the semiconductor device of the sixth embodiment in that the first region of the second semiconductor region is provided between the second region and the third semiconductor region.

[0289] Fig. 29 is a schematic cross-sectional view of a semiconductor device according to a second modification of the sixth embodiment. Fig. 29 corresponds to Fig. 28 of the sixth embodiment. Fig. 29 shows an impurity concentration distribution in a part of a semiconductor layer. The semiconductor device according to the second modification of the sixth embodiment is a MOSFET 601.

[0290] The n-type body region 36 includes a first region 36a and a second region 36b. The first region 36a is provided between the second region 36b and the source region 38.

[0291] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0292] The n-type impurity concentration of the second region 36b is higher than the n-type impurity concentration of the first region 36a.

[0293] 29, the n-type impurity concentration in the depth direction of the region of the body region 36 along the gate insulating layer 18 is maximum at position Py. Position Py is in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region of the body region 36 along the gate insulating layer 18 has a maximum peak in the second region 36b.

[0294] The gate electrode 16 has a first portion 16a and a second portion 16b. The first portion 16a is provided on the first face F1 side relative to the second portion 16b.

[0295] The second portion 16b contacts the first portion 16a. The first portion 16a and the second portion 16b are electrically connected to each other.

[0296] The first portion 16a faces a first region 36a of the body region 36 in the second direction. The second portion 16b faces a second region 36b of the body region 36 in the second direction.

[0297] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is made of, for example, the first material. The second portion 16b is made of, for example, the second material.

[0298] The work function of the first material is larger than the work function of the second material, and the difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0299] The first material and the second material are p-type polycrystalline silicon containing p-type impurities, and the p-type impurity concentration of the first material is higher than the p-type impurity concentration of the second material.

[0300] As shown in FIG. 29, a position Py at which the n-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum faces the second portion 16b in, for example, the second direction.

[0301] In a MOSFET 601 according to a second modification of the sixth embodiment, a gate electrode 16 includes a first portion 16a and a second portion 16b. A work function of a first material included in the first portion 16a is larger than a work function of a second material included in the second portion 16b.

[0302] Since the work function of the first material is larger than that of the second material, the threshold voltage of the MOSFET constituted by the first portion 16a, the gate insulating layer 18, and the first region 36a is lower than the threshold voltage of the MOSFET constituted by the second portion 16b, the gate insulating layer 18, and the second region 36b. In other words, the threshold voltage of the MOSFET having the first portion 16a as its gate electrode is lower than the threshold voltage of the MOSFET having the second portion 16b as its gate electrode.

[0303] In the MOSFET 601 according to the second modification of the sixth embodiment, the threshold voltage of the MOSFET having the first portion 16a as the gate electrode is lowered, and thus the channel resistance of the channel formed in the first region 36a is lowered, thereby reducing the on-resistance of the MOSFET 601.

[0304] On the other hand, the threshold voltage of the MOSFET having the second portion 16b as the gate electrode is kept relatively high, so that the threshold voltage of the MOSFET 601 can be kept high.

[0305] For example, as shown in FIG. 29, by position Py where the n-type impurity concentration is maximum facing second portion 16b, the threshold voltage of the MOSFET having second portion 16b as the gate electrode can be further increased.

[0306] From the viewpoint of reducing the on-resistance of the MOSFET 601, the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0307] According to the MOSFET 601 of the second modification of the sixth embodiment, the on-resistance can be reduced, similarly to the MOSFET 600 of the sixth embodiment.

[0308] As described above, according to the sixth embodiment and its modifications, a semiconductor device capable of reducing the on-resistance can be realized.

[0309] While the first to sixth embodiments have been described above with reference to examples in which the semiconductor device is a MOSFET, the semiconductor device may also be an IGBT (Insulated Gate Bipolar Transistor).

[0310] Furthermore, in the first to sixth embodiments, silicon has been used as an example of the material for the semiconductor layer, but other materials such as silicon carbide (SiC) and gallium nitride (GaN) can also be used for the semiconductor layer.

[0311] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0312] 10 Silicon layer (semiconductor layer) 12 source electrode (first electrode) 14 Drain electrode (second electrode) 16 Gate electrode 16a First Part 16b Second Part 16c Third Part 18 Gate insulating layer 34 drift region (first semiconductor region) 36 Body region (second semiconductor region) 36a First Area 36b Second Area 36c The third area 38 source region (third semiconductor region) 61 First insulating film 62 Second insulating film 100 MOSFET (semiconductor device) 101 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 201 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 500 MOSFET (semiconductor device) 501 MOSFET (semiconductor device) 600 MOSFET (semiconductor device) 601 MOSFET (semiconductor device) F1 First Side F2 Second Face Px position Py position

Claims

1. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface; A semiconductor layer comprising: a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode provided on the second surface side of the semiconductor layer; a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region; Equipped with the second semiconductor region includes a first region, a second region, and a third region, the first region being provided between the second region and the first semiconductor region, and the third region being provided between the second region and the third semiconductor region; the gate electrode includes a first portion, a second portion, and a third portion, the first portion facing the first region, the second portion facing the second region, the third portion facing the third region, the first portion including a first material, the second portion including a second material, and the third portion including a third material; When the first conductivity type is n-type and the second conductivity type is p-type, the work function of the first material and the work function of the third material are smaller than the work function of the second material; A semiconductor device, wherein when the first conductivity type is p-type and the second conductivity type is n-type, a work function of the first material and a work function of the third material are greater than a work function of the second material.

2. 2. The semiconductor device according to claim 1, wherein in a cross section parallel to a direction from the first electrode to the second electrode and including the gate electrode and the semiconductor layer, a position where a second conductivity type impurity concentration is maximum in a region along the gate insulating layer of the second semiconductor region faces the second portion.

3. 2. The semiconductor device according to claim 1, wherein said first material, said second material, and said third material are polycrystalline silicon.

4. 4. The semiconductor device according to claim 3, wherein the first material, the second material, and the third material are of the same conductivity type, and an impurity concentration of the first material and an impurity concentration of the third material are different from an impurity concentration of the second material.

5. 4. The semiconductor device according to claim 3, wherein the conductivity type of said first material and the conductivity type of said third material are different from the conductivity type of said second material.

6. 2. The semiconductor device according to claim 1, further comprising a first insulating film provided between said first portion and said second portion, and a second insulating film provided between said second portion and said third portion.

7. 7. The semiconductor device according to claim 6, wherein said first portion, said second portion, and said third portion are electrically connected to each other.

8. 2. The semiconductor device according to claim 1, wherein a length of the second portion in a direction from the first electrode to the second electrode is 20% or more and 70% or less of a length in the direction between the first semiconductor region and the third semiconductor region.

9. A difference between a work function of the first material and a work function of the second material is 0.2 eV or more; 2. The semiconductor device according to claim 1, wherein a difference between a work function of said third material and a work function of said second material is 0.2 eV or more.

10. 2. The semiconductor device according to claim 1, wherein said semiconductor layer is a silicon layer.

11. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of n-type; a p-type second semiconductor region provided between the first semiconductor region and the first surface; an n-type third semiconductor region provided between the second semiconductor region and the first surface; A semiconductor layer comprising: a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode provided on the second surface side of the semiconductor layer; a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region; Equipped with the second semiconductor region includes a first region and a second region, and the first region is provided between the second region and the first semiconductor region or between the second region and the third semiconductor region; the gate electrode includes a first portion and a second portion, the first portion facing the first region and the second portion facing the second region, the first portion including a first material, and the second portion including a second material; the first material is n-type polycrystalline silicon; A semiconductor device, wherein the first material has a work function smaller than a work function of the second material.

12. 12. The semiconductor device according to claim 11, wherein in a cross section parallel to a direction from the first electrode to the second electrode and including the gate electrode and the semiconductor layer, a position where a p-type impurity concentration is maximum in a region along the gate insulating layer of the second semiconductor region faces the second portion.

13. 12. The semiconductor device of claim 11, wherein the second material is polycrystalline silicon.

14. 14. The semiconductor device according to claim 13, wherein the second material is n-type polycrystalline silicon.

15. 14. The semiconductor device according to claim 13, wherein the second material is p-type polycrystalline silicon.

16. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of p-type; an n-type second semiconductor region provided between the first semiconductor region and the first surface; a p-type third semiconductor region provided between the second semiconductor region and the first surface; A semiconductor layer comprising: a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode provided on the second surface side of the semiconductor layer; a gate electrode provided in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region; Equipped with the second semiconductor region includes a first region and a second region, and the first region is provided between the second region and the first semiconductor region or between the second region and the third semiconductor region; the gate electrode includes a first portion and a second portion, the first portion facing the first region and the second portion facing the second region, the first portion including a first material, and the second portion including a second material; A semiconductor device, wherein the first material has a work function greater than a work function of the second material.

17. 17. The semiconductor device according to claim 16, wherein in a cross section parallel to a direction from the first electrode to the second electrode and including the gate electrode and the semiconductor layer, a position where an n-type impurity concentration is maximum in a region along the gate insulating layer of the second semiconductor region faces the second portion.

18. 17. The semiconductor device of claim 16, wherein the first material and the second material are polycrystalline silicon.

19. 20. The semiconductor device according to claim 18, wherein the first material and the second material are of the same conductivity type, and the impurity concentration of the second material is different from the impurity concentration of the first material.

20. 20. The semiconductor device of claim 18, wherein the second material has a different conductivity type than the first material.

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