Semiconductor device and manufacturing method

Abstract

To reduce an inrush current due to a surge.SOLUTION: External connection wiring has a coil part 40 which is provided by deformation of a wiring member and extends in a first direction. The coil part 40 is provided with one or more pairs of first slits orthogonal in a first direction and second slits orthogonal in the first direction alternately along the first direction. The coil part 40 includes an inter-first slit region between a first slit and a second slit adjacent in the first direction and an inter-second slit region between a second slit and a first slit adjacent in the first direction. A first apex part provided at the center part of the inter-first slit region protrudes in a third direction orthogonal to a principal surface of the wiring member, and a second apex part provided at the center part of the inter-second slit region protrudes in an opposite direction in the third direction to the principal surface.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method. [Background technology]

[0002] A semiconductor device is equipped with various electronic components, such as a semiconductor chip that performs a switching operation and a control circuit that controls the switching operation of the semiconductor chip. As a related technique, there has been proposed an electrostatic protection circuit that includes an inductor having one end connected to a signal terminal and a Schottky barrier diode having a cathode connected to the other end of the inductor and an anode connected to ground (see, for example, Patent Document 1).

[0003] Furthermore, a substrate for an oscillator circuit has been proposed in which a trimming portion for adjusting the oscillation frequency is formed in a coil portion constituting an oscillator circuit among conductor patterns on an insulating substrate, a groove is formed in the trimming portion, and a slit is provided inside the trimming portion (see, for example, Patent Document 2).

[0004] Also, a semiconductor device has been proposed in which a conductive member is connected to the second surface of a cooling member, and a high potential side terminal portion and a low potential side terminal portion are selectively connected to the first surface of the cooling member and the conductive member, respectively (see, for example, Patent Document 3).

[0005] Also, an ESD protection device has been proposed that has a semiconductor substrate, a semiconductor substrate on which first and second input / output electrodes that are conductive to an ESD (Electro-Static Discharge) protection circuit for a high-frequency line are formed, and a redistribution layer that has first and second terminal electrodes connected to each of the input / output electrodes (see, for example, Patent Document 4).

[0006] In addition, a semiconductor device has been proposed in which an electrostatic protection circuit is formed on a semiconductor chip separate from the main semiconductor chip, an electrostatic protection chip is mounted on one main surface of a lead frame on which the main semiconductor chip is mounted, and a conductive connection is made between the bonding pads of the main semiconductor chip and the external pins of the lead frame by wiring members via the electrostatic protection chip (see, for example, Patent Document 5).

[0007] Also, an antenna device has been proposed that is formed by punching out a plate-like body having bent portions successively joined at joints, and then bending the bent portions 90 degrees from the punched body (see, for example, Patent Document 6).

[0008] Also, an inductor component has been proposed in which a first conductor pattern and a second conductor pattern are arranged in a helical shape via a through-hole conductor, and an inductor is formed by the first conductor pattern, the second conductor pattern, and the through-hole conductor (see, for example, Patent Document 7). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2005-117000 A [Patent Document 2] Japanese Patent Application Publication No. 9-270570 [Patent Document 3] JP 2017-50336 A [Patent Document 4] JP 2014-33207 A [Patent Document 5] Japanese Patent Application Publication No. 6-140564 [Patent Document 6] JP 2005-341091 A [Patent Document 7] JP 2017-220502 A Summary of the Invention [Problem to be solved by the invention]

[0010] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that are capable of reducing an inrush current caused by a surge. [Means for solving the problem]

[0011] According to one aspect of the invention, there is provided an electronic component, and an external connection wiring made of a plate-like wiring member having one end connected to the electronic component and another end opposite to the one end, the external connection wiring being provided by deformation of the wiring member, and having a coil portion extending in a first direction from the one end to the other end of the wiring member, and a flat plate portion provided on the one end side and the other end side of the coil portion, the coil portion being a side surface of the main surface of the wiring member, the first side surface being located in a second direction perpendicular to the first direction, and a second side surface being located in a direction opposite to the second direction, a first slit extending from the first side surface of the wiring member in a direction opposite to the second direction and perpendicular to the first direction, a second slit extending from a second side surface in the second direction and perpendicular to the first direction, the first slits and the second slits being arranged alternately in one or more pairs along the first direction, the coil portion including a first inter-slit region between the first slit and the second slit adjacent thereto in the first direction, and a second inter-slit region between the second slit and the first slit adjacent thereto in the first direction, a first apex provided in a central portion of the first inter-slit region with respect to the second direction protruding in a third direction perpendicular to the main surface, and a second apex provided in a central portion of the second inter-slit region with respect to the second direction protruding in a direction opposite to the third direction with respect to the main surface.

[0012] According to one aspect of the invention, a manufacturing method is provided in which a wiring member that is plate-shaped and extends in a first direction is provided with one or more pairs of first slits extending in the opposite direction to the second direction from a first side surface of the wiring member that is located in a second direction perpendicular to the first direction among the side surfaces facing the main surface, and second slits extending in the second direction from a second side surface of the wiring member that is located in the opposite direction to the second direction among the side surfaces facing the main surface, and orthogonal to the first direction, alternately arranged along the first direction, and a central portion of a first inter-slit region between the first slit and the second slit adjacent to the first direction in the second direction is protruded in a third direction perpendicular to the main surface, and a central portion of a second inter-slit region between the second slit and the first slit adjacent to the first direction in the second direction is protruded in the opposite direction to the third direction with respect to the main surface, thereby forming a coil portion by the first inter-slit region and the second inter-slit region in the wiring member.

[0013] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. Effect of the Invention

[0014] According to the disclosed technique, inrush current due to a surge can be reduced, and damage to electronic components in a semiconductor device can be prevented. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating a comparative example of a semiconductor module. [Diagram 2] 1 is a plan view of a semiconductor module according to an embodiment; [Diagram 3] 3A to 3C are a plan view, a front view, and a side view of a coil portion. [Figure 4] FIG. [Diagram 5] 5A to 5C are diagrams showing a manufacturing process of the coil portion. [Figure 6]11A and 11B are diagrams showing examples of dies used in molding the coil portion. [Figure 7] 4 is a cross-sectional view showing an example of the arrangement of a coil portion relative to a case. FIG. [Figure 8] 11 is a diagram for explaining input and output of a signal via a TEMP terminal. FIG. [Figure 9] FIG. 13 is a diagram showing a current value when a surge is applied. [Figure 10] 13A to 13C are a plan view, a front view, and a side view showing a modified example of the coil portion. [Figure 11] FIG. 13 is a perspective view showing a modified example of the coil portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the XY surface facing upward (+Z direction) in the semiconductor device shown in the figure. Similarly, "up" refers to the upward (+Z direction) direction in the semiconductor device shown in the figure. The terms "back surface" and "lower surface" refer to the XY surface facing downward (-Z direction) in the semiconductor device shown in the figure. Similarly, "lower" refers to the downward (-Z direction) direction in the semiconductor device shown in the figure. The same directionality is used in other figures as necessary. The terms "front surface", "upper surface", "upper", "back surface", "lower surface", "lower", and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of ​​the present invention. For example, "upper" and "lower" do not necessarily mean a vertical direction relative to the ground. In other words, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0017] First, a comparative example of a semiconductor module included in a semiconductor device will be described with reference to FIG. 1, and then a semiconductor module included in a semiconductor device according to an embodiment will be described with reference to FIG.

[0018] Fig. 1 is a diagram showing a comparative example of a semiconductor module, showing a plan view of a semiconductor module 2 included in a semiconductor device 1 (see Fig. 8) seen from above (in the -Z direction).

[0019] The semiconductor module 2 is attached to the front surface of a cooling substrate (not shown). The semiconductor module 2 includes a cubic case 10. The periphery of the case 10 in a plan view is surrounded by a sidewall, and the inside of the sidewall forms a storage area 11 for storing various components.

[0020] The storage area 11 is sealed by a sealing member (not shown). The sealing member may be a thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenol resin, a maleimide resin, or a polyester resin. An epoxy resin is preferable. Furthermore, a filler may be added to the sealing member. The filler is a ceramic having insulating properties and high thermal conductivity.

[0021] Such a case 10 includes a plurality of lead frames, which will be described later, and is integrally molded from a thermoplastic resin. Examples of such resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin.

[0022] An opening is provided at the bottom of the case 10. A heat sink (not shown) is provided on the back side of the bottom of the case 10. The heat sink covers the opening of the case 10. An insulating substrate 20 is provided in the opening on the heat sink. Therefore, the front surface of the insulating substrate 20 is sealed with a sealing member. The insulating substrate 20 may be made of ceramics or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride. Examples of insulating resins include paper phenol substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates.

[0023] Wiring boards 21a-21d are formed on the front surface of insulating substrate 20. Wiring boards 21a-21d are made of a metal with excellent conductivity. Such metal is, for example, copper, aluminum, or an alloy containing at least one of these as a main component. Furthermore, the surfaces of wiring boards 21a-21d may be plated. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The plated wiring boards 21a-21d have improved corrosion resistance.

[0024] Semiconductor chips 22a-22c and 23a-23c are arranged on the front surface of wiring board 21a. Semiconductor chips 22d and 23d are arranged on the front surface of wiring board 21b. Semiconductor chips 22e and 23e are arranged on the front surface of wiring board 21c. Semiconductor chips 22f and 23f are arranged on the front surface of wiring board 21d.

[0025] The semiconductor chips 22a to 22e include switching elements. The switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The semiconductor chips 23a to 23e include diode elements. As the diode elements, for example, SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes may be used as FWDs (Free Wheeling Diodes).

[0026] In the bottom region of the case 10, a flat bottom surface 12 is provided in a region excluding the opening. The bottom surface 12 is located, for example, higher than the front surface of the insulating substrate 20. A plurality of lead frames including lead frames 13a and 13b are provided on the front surface of the bottom surface 12. These lead frames are made of a material having excellent electrical conductivity. Such a material is, for example, copper, aluminum, or an alloy containing at least one of these. It is also possible to plate each lead frame with a material having excellent corrosion resistance.

[0027] One end of the lead frame 13a extends outward (in the +Y direction) from the case 10. The other end of the lead frame 13a enters the case 10 from the one end side and extends along the long side of the insulating substrate 20 to the short side (in the +X direction) of the case 10. Such a lead frame 13a is connected to a COM terminal (common terminal). In addition, control ICs (Integrated Circuits) 31a to 31c, 32 are arranged on the front surface of the lead frame 13a on the side of the long side of the insulating substrate 20. Electrodes formed on the front surfaces of the control ICs 31a to 31c, 32 are connected to the lead frame 13a via bonding wires 14a to 14d, respectively.

[0028] One end of the lead frame 13b extends outward (in the +Y direction) from the case 10. The other end of the lead frame 13b enters the case 10 from the one end side and extends to a side portion of the wiring board 21d of the insulating substrate 20. Such a lead frame 13b is connected to a TEMP terminal. Also, a temperature sensing electrode formed on the front surface of the control IC 32 is connected to the lead frame 13b via a bonding wire 14e. The TEMP terminal is an output terminal for a temperature sensing signal, and a voltage signal corresponding to the temperature of the control IC 32 is transmitted to the TEMP terminal via the bonding wire 14e and the lead frame 13b, and is output from the TEMP terminal to the outside.

[0029] In the above-mentioned semiconductor module 2, the semiconductor chips 22a, 23a and the semiconductor chips 22d, 23d constitute an inverter circuit for one phase. The semiconductor chips 22a, 23a constitute an upper arm portion of a half-bridge circuit, and the semiconductor chips 22d, 23d constitute a lower arm portion of the half-bridge circuit. The semiconductor chips 22b, 23b and the semiconductor chips 22e, 23e also constitute an inverter circuit for one phase. The semiconductor chips 22b, 23b constitute an upper arm portion of the half-bridge circuit, and the semiconductor chips 22e, 23e constitute a lower arm portion of the half-bridge circuit. The semiconductor chips 22c, 23c and the semiconductor chips 22f, 23f also constitute an inverter circuit for one phase. The semiconductor chips 22c, 23c constitute an upper arm portion of the half-bridge circuit, and the semiconductor chips 22f, 23f constitute a lower arm portion of the half-bridge circuit.

[0030] The control electrode formed on the front surface of the control IC 31a and the gate electrode formed on the front surface of the semiconductor chip 22a are connected via a bonding wire 15a. The control electrode formed on the front surface of the control IC 31b and the gate electrode formed on the front surface of the semiconductor chip 22b are connected via a bonding wire 15b. The control electrode formed on the front surface of the control IC 31c and the gate electrode formed on the front surface of the semiconductor chip 22c are connected via a bonding wire 15c. The control ICs 31a to 31c are gate driver ICs for the upper arm, and output gate control signals to the gate electrodes of the semiconductor chips 22a to 22c, respectively, to control the switching operations of the semiconductor chips 22a to 22c.

[0031] A control electrode formed on the front surface of the control IC 32 and gate electrodes formed on the front surfaces of the semiconductor chips 22d-22f are connected via bonding wires 15d-15f, respectively. The control IC 32 is a gate driver IC for the lower arm, and outputs gate control signals to the gate electrodes of the semiconductor chips 22d-22f to control the switching operations of the semiconductor chips 22d-22f.

[0032] The semiconductor module 2 thus configured constitutes, for example, an IPM (Intelligent Power Module) in which a switching element and a control circuit are housed in one package. The combination of the semiconductor chip 22a including the switching element and the semiconductor chip 23a including the diode element may be realized as one chip as an RC (Reverse Conducting)-IGBT. Similarly, the combination of the semiconductor chips 22b and 23b, the combination of the semiconductor chips 22c and 23c, the combination of the semiconductor chips 22d and 23d, the combination of the semiconductor chips 22e and 23e, and the combination of the semiconductor chips 22f and 23f may also be realized as an RC-IGBT.

[0033] Incidentally, the control ICs 31a to 31c, 32 in the semiconductor module 2 may be destroyed by the influence of a high-frequency surge from the outside. In order to prevent such destruction, for example, a method of disposing a protection element device such as a Zener diode or a bypass capacitor between the external terminal and the control IC is considered. While this method is expected to be effective in suppressing overvoltage caused by a high-frequency surge, it is insufficient in suppressing overcurrent. In the control ICs 31a to 31c, 32, a latch-up destruction occurs due to an inrush current of a high-frequency surge flowing into an internal parasitic transistor, but the above method cannot deal with such a problem. In addition, when a protection element device is added or the withstand voltage of the control IC is improved, the chip size of the control IC increases, which is a problem in that the semiconductor module 2 becomes large.

[0034] Fig. 2 is a plan view of a semiconductor module according to an embodiment, in which components common to Fig. 1 are denoted by the same reference numerals. The semiconductor module 2a according to the present embodiment differs from the comparative example of FIG. 1 in that a coil portion 40 is provided in a region 13b1 (see FIG. 1) of the lead frame 13b. The lead frame 13b is formed so that the width in the region 13b1 is wider than that in FIG. 1. The region 13b1 of the lead frame 13b is then deformed by cutting and folding to form the coil portion 40.

[0035] In the semiconductor module 2 of the comparative example, the temperature sense signal in the control IC 32 flows as a voltage in the lead frame 13b, and this voltage is output from the TEMP terminal. Since the signal line of the temperature sense signal is intended to output a voltage, the control IC 32 has a characteristic that it is weak against application of high-frequency overcurrent compared to the other control ICs 31a to 31c. In other words, when a large current is injected from the outside into the TEMP terminal, a clamp voltage is generated in the protection element inside the control IC 32, and the parts that are weak against the breakdown voltage are destroyed.

[0036] Therefore, in the semiconductor module 2a, the coil section 40 is provided on the lead frame 13b through which the voltage signal for temperature sensing flows. This makes it possible to delay the rise of the current when a high-frequency surge is applied from the TEMP terminal, and as a result, the peak of the current is reduced. This suppresses the current applied to the control IC 32, and reduces the possibility of the control IC 32 being destroyed.

[0037] Next, the configuration of the coil section will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a plan view, a front view, and a side view of the coil section. Fig. 4 is a perspective view of the coil section. Note that Fig. 3 shows a plan view, a front view, and a side view with the extension direction of lead frame 13b (the direction of arrow A) as the front.

[0038] In the region of the coil portion 40 of the lead frame 13b, when viewed from the front (looking in the direction of the arrow A (first direction)), multiple sets of slits 41a perpendicular to the lead frame 13b from the right direction (downward in the plan view of FIG. 3) (extending in the second direction) and slits 41b perpendicular to the lead frame 13b from the left direction (upward in the plan view of FIG. 3) (extending in the opposite direction to the second direction) are alternately provided. That is, the slits 41a reach the right end of the lead frame 13b in the width direction but do not reach the left end. On the other hand, the slits 41b reach the left end of the lead frame 13b in the width direction but do not reach the right end. Adjacent slits are formed at equal intervals.

[0039] When viewed from the front, the inter-slit region 42a between the slit 41a and the adjacent slit 41b is bent so that the center in the width direction protrudes upward (in the third direction) relative to the main surface of the lead frame 13b to form an apex. On the other hand, when viewed from the front, the inter-slit region 42b between the slit 41b and the adjacent slit 41a is bent so that the center in the width direction protrudes downward (in the direction opposite to the third direction) relative to the main surface of the lead frame 13b to form an apex.

[0040] However, in the width direction region of the coil portion 40 of the lead frame 13b, an end region 43a where the slits 41a are not provided and an end region 43b where the slits 41b are not provided are maintained flush with the main surface of the lead frame 13b, and only the remaining central region 43c protrudes upward or downward. In the plan view of Fig. 3, bending lines protruding upward or diagonally upward with respect to the main surface of the lead frame 13b are indicated by dashed lines, and bending lines protruding downward or diagonally downward with dotted lines.

[0041] As a result, inter-slit regions 42a protruding upward and inter-slit regions 42b protruding downward appear alternately on the main surface of lead frame 13b, and adjacent inter-slit regions are connected by end region 43a or end region 43b. As a result, a coil having a rectangular (diamond) cross section is formed by inter-slit regions 42a protruding upward and inter-slit regions 42b protruding downward.

[0042] The slits 41a and 41b are formed to have a constant width. This prevents adjacent inter-slit regions sandwiching the slit from contacting each other. Specifically, the inter-slit region 42a and the next inter-slit region 42b adjacent in the direction of arrow A are spaced apart by the width of the slit 41b in the end region 43a. The inter-slit region 42b and the next inter-slit region 42a adjacent in the direction of arrow A are spaced apart by the width of the slit 41a in the end region 43b.

[0043] Such a coil increases the inductance component of the lead frame 13b. Therefore, when a high-frequency surge is applied from the TEMP terminal, the rise of the current flowing through the control IC 32 via the lead frame 13b is delayed, and the peak of the current is reduced. As a result, the current applied to the control IC 32 is suppressed, and the possibility of the control IC 32 being destroyed can be reduced.

[0044] Next, a method for manufacturing the coil portion 40 will be described with reference to FIGS. Fig. 5 is a diagram showing a manufacturing process of the coil portion, and Fig. 6 is a diagram showing an example of a mold used in molding the coil portion.

[0045] First, a 0.4 mm thick conductive plate is pressed using a mold to cut out lead frame 13b (step S1). At this time, multiple frames including lead frames 13a and 13b are actually formed while being connected by tie bars. Furthermore, the width W of the region of lead frame 13b where coil portion 40 is formed is made wider than the width of region 13b1 in the comparative example shown in FIG. 1. For example, width W is expanded from 2 mm to 6 mm. However, in the regions of lead frame 13b other than the region where coil portion 40 is formed, the width may remain at 2 mm as in the comparative example.

[0046] Next, the slits 41a and 41b are cut in the lead frame 13b in the region of the coil portion 40 (step S2). For example, a pair of dies 51a and 51b as shown in Fig. 6 is used. The opposing surfaces of the dies 51a and 51b are provided with blades corresponding to the shapes of the slits 41a and 41b, and the lead frame 13b is sandwiched between the dies 51a and 51b from above and below to form the slits 41a and 41b.

[0047] Next, the inter-slit regions 42a and 42b are folded (step S3). For example, a pair of dies 52a and 52b as shown in Fig. 6 is used. The upper die 52a has a downwardly facing protrusion at a position corresponding to the inter-slit region 42b, and the lower die 52b has an upwardly facing protrusion at a position corresponding to the inter-slit region 42a. Then, the lead frame 13b with the slits formed therein is sandwiched from above and below by the dies 52a and 52b and pressed.

[0048] The cross-sectional shape of the protrusion of the die 52a viewed from the front (viewed from the direction of arrow A) forms an isosceles triangle with the apex facing upward, and the cross-sectional shape of the protrusion of the die 52b viewed from the front forms an isosceles triangle with the apex facing downward. Therefore, by pressing, the protrusion of the die 52a folds the inter-slit region 42b downward, and the protrusion of the die 52b folds the inter-slit region 42a upward. As a result, the central region 43c of the coil portion 40 in the lead frame 13b is folded in an accordion-like shape so that adjacent inter-slit regions protrude in opposite directions from the main surface, forming a coil.

[0049] As described above, the coil can be formed by a simple manufacturing method of cutting and folding a flat conductive plate. Therefore, the circuit components for suppressing overcurrent can be added at low cost. In addition, since the circuit components for suppressing overcurrent can be arranged inside the semiconductor module 2a, it is not necessary to provide a space for arranging such circuit components outside the semiconductor module 2a, and the increase in size of the entire semiconductor device 1 can be suppressed. Furthermore, since the coil can be formed by only expanding the width of the coil formation area in the existing lead frame, the increase in size of the semiconductor module 2a can be suppressed. It is also possible to form the coil by utilizing the free space of the semiconductor module 2a, and in this case, the coil can be formed without increasing the size of the semiconductor module 2a, and the destruction of the control IC 32 can be prevented.

[0050] The winding direction of the coil in the coil portion 40 may be opposite to that in the examples of FIGS. 3 to 6. The winding direction of the coil can be changed by changing the order of forming the slits 41a formed from the right side of the lead frame 13b (the downward direction in the plan view of FIG. 3) and the slits 41b formed from the left side of the lead frame 13b with respect to the direction of the arrow A. That is, in the examples of FIGS. 3 to 6, the slits 41a are formed first with respect to the direction of the arrow A, and then the slits 41b are formed. However, the winding direction of the coil may be reversed by forming the slits 41b first with respect to the direction of the arrow A, and then forming the slits 41a.

[0051] Fig. 7 is a cross-sectional view showing an example of the arrangement of the coil portion relative to the case, showing a cross-sectional view taken along dashed line BB (BB cross-sectional view) and a cross-sectional view taken along dashed line CC (CC cross-sectional view) in Fig. 3.

[0052] The lead frame 13b is disposed on the front surface of the bottom surface 12 of the case 10. The inter-slit region 42b of the coil portion 40 protrudes downward from the main surface of the lead frame 13b. Therefore, a recess 16 having a size and shape capable of accommodating at least the inter-slit region 42b is formed below the coil portion 40 in the case 10. In the example of FIG. 7, the side of the recess 16 in the BB cross section is vertical, but the side of the recess 16 may also be inclined in accordance with the inclination of the inter-slit region 42b. By forming such a recess 16 in the case 10 and arranging the lead frame 13b so that the inter-slit region 42b is accommodated in the recess 16, it becomes possible to arrange the lead frame 13b on which the coil portion 40 is formed on the front surface of the bottom surface 12 having the same height as the comparative example of FIG. 1 without deforming the three-dimensional shape of the coil portion 40.

[0053] FIG. 8 is a diagram for explaining input and output of signals via the TEMP terminal. As described above, the TEMP terminal is an external output terminal for outputting, as a voltage, the temperature sense signal in the control IC 32. In order to output such a voltage signal, the control IC 32 has a circuit configuration as shown in FIG.

[0054] The control IC32 includes an operational amplifier A1. A constant reference voltage REF is input to the non-inverting input terminal of the operational amplifier A1. A temperature signal corresponding to a temperature detected by a temperature sensor (not shown) included in the control IC32 is input to the inverting input terminal of the operational amplifier A1 via a resistor R1a. A resistor R1b is connected between the output terminal and the inverting input terminal of the operational amplifier A1 to form a negative feedback circuit. With this configuration, a differential amplifier is formed that amplifies the difference between the reference voltage REF and the voltage of the temperature signal with an amplification factor corresponding to the ratio of the resistors R1a and R1b, and a voltage corresponding to the temperature of the control IC32 is output from the operational amplifier A1.

[0055] The output terminal of the operational amplifier A1 is connected to the anode of the diode D1a and the cathode of the diode D1b. The power supply voltage VDD is applied to the cathode of the diode D1a, and the anode of the diode D1b is connected to the COM terminal and ground. A connection point 32a between the anode of the diode D1a and the cathode of the diode D1b is connected to the TEMP terminal via the lead frame 13b.

[0056] Furthermore, the semiconductor device 1 includes a control MPU (Micro Processing Unit) 3. The MPU 3 includes an input terminal 3a, to which a temperature sense signal output from a TEMP terminal is input via a resistor R2. One end of a capacitor C2 is connected between the resistor R2 and the input terminal 3a, and the other end of the capacitor C2 is connected to ground. The resistor R2 and the capacitor C2 limit the inrush current.

[0057] Here, diodes D1a and D1b are a protection circuit to protect control IC32 from surge input from the TEMP terminal. However, when a large current is input from the TEMP terminal due to a high-frequency surge, a clamp voltage is generated in diode D1b. The gate of the transistor included in operational amplifier A1 has a low breakdown voltage and may be destroyed by the clamp voltage.

[0058] To address this problem, in this embodiment, a coil L1 is inserted in the path between the connection point 32a and the TEMP terminal. The coil L1 corresponds to the coil unit 40 described above. When a high-frequency surge is applied to the TEMP terminal from the outside, the inductance of the coil L1 slows down the rise of the input current and the peak of the current applied to the operational amplifier A1 is reduced, thereby reducing the possibility of the operational amplifier A1 being destroyed. Therefore, the possibility of the control IC 32 being destroyed by a high-frequency surge can be reduced, and the reliability of the semiconductor device 1 can be improved.

[0059] Next, an example of a coil design will be described. For example, Type 2 of the ESD test standard of JEDEC (Joint Electron Device Engineering Council) assumes an inrush current of 1.33A / 2nsec when 2000V is applied. Therefore, assume that an inrush current of 1.33A / 2nsec is applied to the TEMP terminal from an HBM (Human Body Model) power supply with an internal resistance of 1.5kΩ and an internal capacitance of 100pF. The latch-up tolerance of the control IC32 is set to 500μA, and a synthetic impedance is designed so that the input current to the control IC32 does not exceed 500μA when the above inrush current is applied. If the internal resistance of the control IC32 is 300Ω, Z=(R2+ω2L2) 1 / 2 To meet this requirement, an inductance of 950nH or more is required.

[0060] 4, the length of coil portion 40 is L1, the length of one turn of the coil in the longitudinal direction of coil portion 40 (=the distance between two slits) is L2, and the width of the coil is L3. Furthermore, the width of lead frame 13b on which coil portion 40 is formed is W, and the length of one side of the coil when the cross section is a square is D. This D is regarded as the diameter of the coil.

[0061] As an example, we will assume that W = 6 mm, D = 2 mm, L1 = 15 mm, and a coil with n = 20 turns will be formed. In this case, L2 = 0.75 mm. Also, taking into account the width of the slit, L3 = 0.3 mm. The inductance is K × μ0 × π × (D / 2) 2 ×n 2 / L1. K (Nagaoka coefficient) = 0.92, and μ0 is the vacuum permeability. Considering the inductance of 10 nH of the lead frame 13b before the coil is formed, an inductance of 970 nH can be ensured by forming the coil portion 40 with the above dimensions.

[0062] Fig. 9 is a diagram showing the current value when a surge is applied. Fig. 9 shows the relationship between the inductance and the surge current value when a surge of 2000V is applied. If the coil section 40 is not formed (as in the comparative example of Fig. 1), the surge current would exceed the latch-up resistance of the control IC 32, which is 500μA, but by forming the coil section 40 with the number of turns n=20 as described above and ensuring an inductance of 970nH, the surge current can be suppressed below the latch-up resistance.

[0063] In the above embodiment, the coil portion 40 has a rectangular (diamond) cross-sectional shape, but the cross-sectional shape of the coil portion 40 may be another polygonal shape such as a hexagon. Also, it is preferable that the cross-sectional shape of the coil portion 40 is a circle as shown in the following Figures 10 and 11.

[0064] Fig. 10 is a plan view, a front view, and a side view showing a modified example of the coil section, and Fig. 11 is a perspective view showing a modified example of the coil section. In Fig. 10 and Fig. 11, components common to Fig. 3 and Fig. 4 are denoted by the same reference numerals.

[0065] In the modified example shown in FIG. 10 and FIG. 11, the coil portion 40 in the above embodiment is modified to a coil portion 40a. The coil portion 40a is different from the coil portion 40 in that the cross section is formed to be circular. That is, in the coil portion 40a, the inter-slit region 42a is curved upward with respect to the main surface of the lead frame 13b and is formed to form a semicircle protruding upward. The inter-slit region 42b is curved downward with respect to the main surface of the lead frame 13b and is formed to form a semicircle protruding downward. Due to the curved shape of the inter-slit regions 42a and 42b, the cross section of the coil portion 40 is circular.

[0066] However, end regions 43a, 43b in the inter-slit regions 42a, 42b are maintained to be flush with the main surface of the lead frame 13b, similar to the coil portion 40. The end regions 43a, 43b connect adjacent inter-slit regions, thereby forming a helical coil in the coil portion 40a.

[0067] The length L1 of the coil portion 40a, the length L2 of one coil turn, the width L3 of the coil, the width W of the lead frame 13b, the diameter D of the coil, and the number of turns n of the coil are the same as those of the coil portion 40. Then, by forming a spiral coil, the cross-sectional area is increased compared to the coil portion 40, and the inductance is increased. Therefore, the inrush current due to a high-frequency surge can be more reliably reduced, and the possibility of the control IC 32 being destroyed can be reduced.

[0068] Incidentally, such coil portion 40a may also be formed by the manufacturing method described with reference to Figures 5 and 6. However, in the case of forming coil portion 40a, the cross-sectional shape of the convex portion included in die 52a shown in Figure 6 as viewed from the front (as viewed from the direction of arrow A) may be a semicircular shape facing upward, and the cross-sectional shape of the convex portion of die 52b as viewed from the front may be a semicircular shape facing downward. [Explanation of symbols]

[0069] 1 Semiconductor device 2,2a Semiconductor Module 3. MPU 3a Input terminal 10 Cases 11 Storage area 12 Bottom 13a, 13b Lead frame 13a1 area 14a~14e,15a~15f Bonding wire 16 Recess 20 Insulating substrate 21a~21d Wiring board 22a-22f, 23a-23f Semiconductor chips 31a~31c,32 Control IC 32a Connection point 40,40a Coil section 41a, 41b Slit 42a, 42b Area between slits 43a,43b End area 43c central area 51a, 51b, 52a, 52b Mold A1 Op Amp C2 Capacitor D1a, D1b Diode L1 coil R1a,R1b,R2 resistance REF Reference voltage VDD Power supply voltage

Claims

1. Electronic components, an external connection wiring formed of a plate-shaped wiring member having one end connected to the electronic component and another end opposite to the one end; having the external connection wiring is provided by deformation of the wiring member, and includes a coil portion extending in a first direction from the one end to the other end of the wiring member, and a flat plate portion provided on the one end side and the other end side of the coil portion, The coil portion includes: a first side surface located in a second direction perpendicular to the first direction and a second side surface located in a direction opposite to the second direction, the first side surface being a side surface of the wiring member; a first slit extending from the first side surface of the wiring member in a direction opposite to the second direction and perpendicular to the first direction; a second slit extending in the second direction from the second side surface of the wiring member and perpendicular to the first direction; having one or more pairs of the first slits and the second slits are alternately provided along the first direction, the coil portion includes a first inter-slit region between the first slit and the second slit adjacent thereto in the first direction, and a second inter-slit region between the second slit and the first slit adjacent thereto in the first direction, a first apex provided in a central portion of the first inter-slit region with respect to the second direction protrudes in a third direction perpendicular to the main surface, and a second apex provided in a central portion of the second inter-slit region with respect to the second direction protrudes in a direction opposite to the third direction with respect to the main surface; Semiconductor device.

2. Further comprising a semiconductor chip for performing a switching operation, The electronic component includes a control circuit that controls a switching operation of the semiconductor chip. The semiconductor device according to claim 1 .

3. The other end is an output terminal that outputs a voltage indicating a measurement value of the temperature of the electronic component. The semiconductor device according to claim 1 .

4. The first inter-slit region is folded at the first apex, and the second inter-slit region is folded at the second apex. The semiconductor device according to claim 1 .

5. The first inter-slit region has a shape curved in the third direction, and the second inter-slit region has a shape curved in a direction opposite to the third direction. The semiconductor device according to claim 1 .

6. a case that houses the electronic component, the one end of the wiring member, and the coil portion, and from which the other end of the wiring member extends outward; The case is a flat surface on which the coil portion and the flat plate portion are disposed; a recess formed in a region of the flat surface where the coil portion is provided, the recess accommodating a portion of the coil portion protruding toward an opposite side of the flat surface from the front surface; having The semiconductor device according to claim 1 .

7. a first slit extending in an opposite direction to the second direction from a first side surface of a side surface of the wiring member that is located in a second direction perpendicular to the first direction and perpendicular to the first direction, and a second slit extending in the second direction from a second side surface of the side surface of the wiring member that is located in the opposite direction to the second direction and perpendicular to the first direction, are alternately formed along the first direction, in one or more pairs; a central portion in the second direction in a first inter-slit region between the first slit and the second slit adjacent in the first direction is protruded in a third direction perpendicular to the main surface, and a central portion in the second direction in a second inter-slit region between the second slit and the first slit adjacent in the first direction is protruded in a direction opposite to the third direction with respect to the main surface, thereby forming a coil portion by the first inter-slit region and the second inter-slit region in the wiring member. Manufacturing method.

8. In the step of forming the coil portion, the first inter-slit region is bent at a center portion in the second direction so as to be convex toward the third direction side, and the second inter-slit region is bent at a center portion in the second direction so as to be convex toward a direction opposite to the third direction. The method of claim 7.

9. In the step of forming the coil portion, the first inter-slit region is curved in the third direction, and the second inter-slit region is curved in a direction opposite to the third direction. The method of claim 7.

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