Semiconductor device

Abstract

To provide a semiconductor device capable of size reduction.SOLUTION: A semiconductor device includes a source electrode 12 provided on a substrate 10, a gate electrode 14 provided in a loop shape on the substrate while surrounding the source electrode, a drain electrode 16 provided on the substrate while surrounding the gate electrode in a first direction, a direction opposite to the first direction, and a second direction that is orthogonal to the first direction, and a gate wire 23 having a first end connected to only one place of the gate electrode and a second end connected to a first gate bus bar, and provided on the substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known that a plurality of unit FETs each having a source, gate and drain electrode are arranged in the direction in which the electrodes are arranged (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A Summary of the Invention [Problem to be solved by the invention]

[0004] When multiple unit FETs are arranged, it is difficult to miniaturize the semiconductor device, and the design may become difficult when trying to miniaturize the semiconductor device.

[0005] The present disclosure has been made in consideration of the above problems, and aims to achieve miniaturization. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a source electrode provided on a substrate; a gate electrode surrounding the source electrode and provided in a loop shape on the substrate; a drain electrode provided on the substrate and surrounding the gate electrode from a first direction, a direction opposite to the first direction, and a second direction perpendicular to the first direction; and a gate wiring provided on the substrate, the first end of which is connected to only one point on the gate electrode and the second end of which is connected to a first gate bus bar. Effect of the Invention

[0007] According to the present disclosure, miniaturization is possible. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 3 is a plan view of the semiconductor device according to the first comparative example. [Figure 4] FIG. 4 is a plan view of a semiconductor device according to a second comparative example. [Diagram 5] FIG. 5 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 6] FIG. 6 is a plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 7] FIG. 7 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 9] FIG. 9 is a plan view of a semiconductor device according to a second modification of the second embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device in accordance with a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including a source electrode provided on a substrate, a gate electrode surrounding the source electrode and provided on the substrate in a loop shape, a drain electrode provided on the substrate and surrounding the gate electrode from a first direction, a direction opposite to the first direction, and a second direction perpendicular to the first direction, and a gate wiring provided on the substrate, the first end of which is connected to only one point on the gate electrode and the second end of which is connected to a first gate bus bar. This allows the semiconductor device to be easily designed and miniaturized. (2) In the above (1), the drain electrode may surround the gate electrode only from the first direction, a direction opposite to the first direction, and the second direction. (3) In the above (2), the first end of the gate wiring may be connected within a range having a width that is half the width in the first direction of a portion of the gate electrode that is not surrounded by the drain electrode from the direction opposite to the second direction, centered on a center point in the first direction. This makes it possible to effectively bring the gate widths of two FETs connected in parallel closer to each other, making the design easier. (4) In the above (1), the drain electrode may surround the gate electrode from the direction opposite to the second direction, thereby making it possible to increase the effective gate width and thus to reduce the size. (5) In any one of the above (1) to (4), the width of the source electrode in the second direction may be three times or less and one-third or more of the width of the source electrode in the first direction, thereby improving heat dissipation. (6) In any one of the above (1) to (5), a metal layer may be provided under the substrate and electrically connected to the source electrode through a via hole penetrating the substrate, thereby enabling miniaturization. (7) In any one of the above (1) to (6), the substrate may have an active region in which a semiconductor layer in the substrate is activated, and a region of the drain electrode surrounding the gate electrode from the first direction, the direction opposite to the first direction, and the second direction may be provided on the active region, thereby enabling miniaturization. (8) In any one of (1) to (7) above, the semiconductor device may further include a FET group including a plurality of unit FETs arranged in the first direction, each of which includes the source electrode, the gate electrode, and the drain electrode, and adjacent unit FETs sharing the drain electrode, and a drain bus bar sandwiching a first FET group among the FET groups between the first gate bus bar and connected to the drain electrodes of the plurality of unit FETs in the first FET group, the first gate bus bar being connected to gate wirings of the plurality of unit FETs in the first FET group. This facilitates the design of a semiconductor device with a large gate width. (9) In the above (8), the semiconductor device may further include a second FET group included in the FET group, the drain bus bar being sandwiched between the first FET group and the second FET group, and a second gate bus bar sandwiching the second FET group between the drain bus bar and connected to gate wirings of a plurality of unit FETs in the second FET group. This makes it easier to design a semiconductor device with a large gate width. (10) In the above item (9), the width of the drain bus bar in the second direction may be greater than the width in the first direction of the drain electrode shared by unit FETs adjacent in the first direction. This allows the current density of the drain bus bar to be close to the current density of the drain electrode, thereby enabling miniaturization. (11) In the above (9) or (10), a gate pad electrically connected to the first gate bus bar and the second gate bus bar, and a drain pad sandwiching the first FET group and the second FET group between the gate pad and the drain pad and electrically connected to the drain bus bar may be provided. This allows the gate pad and drain pad to be efficiently arranged, making it possible to reduce the size. (12) In any one of (9) to (11) above, the semiconductor device may include a plurality of units, each of which includes the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar, and which are arranged in the second direction. This allows the unit FETs to be arranged efficiently, thereby making it possible to reduce the size.

[0010] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] Fig. 1 is a plan view of the semiconductor device in Example 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. The thickness direction of the substrate 10 is the Z direction, the direction in which the drain electrode 16c and the gate bus bar 24 sandwich the source electrode 12 is the X direction, and the direction in which the drain electrodes 16a and 16b sandwich the source electrode 12 is the Y direction.

[0012] 1 and 2, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, a region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region 13. A region of the semiconductor layer 10b that is activated but not inactivated is an active region 11.

[0013] A source electrode 12, a gate electrode 14, a drain electrode 16, a gate wiring 23, a gate bus bar 24, and a drain bus bar 26 are provided on a substrate 10. A unit FET 35 includes a source electrode 12, a gate electrode 14, and a drain electrode 16.

[0014] The planar shape of the source electrode 12 is a substantial rectangle having sides extending in the X and Y directions. A gate electrode 14 is provided in a loop shape to surround the source electrode 12. The gate electrode 14 includes gate electrodes 14a to 14d. The gate electrodes 14a and 14b extend in the X direction and sandwich the source electrode 12 in the Y direction. The gate electrodes 14c and 14d extend in the Y direction and sandwich the source electrode 12 in the X direction.

[0015] The drain electrode 16 surrounds the gate electrode 14 from the + direction (first direction) in the Y direction, the - direction (opposite to the first direction) in the Y direction, and the - direction (second direction perpendicular to the first direction) in the X direction. The drain electrode 16 includes drain electrodes 16a to 16c. The drain electrodes 16a to 16c and the source electrode 12 sandwich the gate electrodes 14a to 14c, respectively. The source electrode 12, the gate electrodes 14a to 14c, and the drain electrodes 16a to 16c are provided on the active region 11 of the substrate 10.

[0016] The unit FET 35 has unit FETs 35a to 35c. The unit FET 35a has a source electrode 12, a gate electrode 14a, and a drain electrode 16a. The unit FET 35b has a source electrode 12, a gate electrode 14b, and a drain electrode 16b. The unit FET 35c has a source electrode 12, a gate electrode 14c, and a drain electrode 16c.

[0017] The gate electrode 14d is provided on the inactive region 13 of the substrate 10. The gate bus bar 24 is provided in a region on the inactive region 13 of the substrate 10 that is provided in the X direction of the gate electrode 14d, and extends in the Y direction. The gate wiring 23 is provided on the inactive region 13, and electrically connects and shorts the gate electrode 14d and the gate bus bar 24.

[0018] Drain bus bar 26 includes drain electrode 16c and drain electrode 16 provided on inactive region 13, and extends in the Y direction. Gate bus bar 24 and drain bus bar 26 sandwich unit FET 35 in the X direction.

[0019] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. As a result, the metal layer 28 is electrically connected to the source electrode 12 via the via hole 20, and is short-circuited. A reference potential such as a ground potential is supplied to the metal layer 28.

[0020] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FET 35 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a, and an aluminum gallium nitride barrier layer provided on the gallium nitride channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS).

[0021] The source electrode 12 and the drain electrode 16 include an ohmic contact layer 37 and a low resistance layer 38. The gate wiring 23 and the gate bus bar 24 include a gate metal layer 39 and a low resistance layer 38. The ohmic contact layer 37 is a metal layer that makes ohmic contact with the semiconductor layer 10b, and is, for example, a titanium film and an aluminum film from the substrate 10 side. The low resistance layer 38 is a metal layer having a lower resistivity than an ohmic contact layer such as a gold layer. The gate electrode 14 and the gate metal layer 39 are metal films, and are, for example, a nickel film and a gold film from the substrate 10 side. An insulating layer may be provided so as to cover the source electrode 12, the gate electrode 14, the drain electrode 16, the gate wiring 23, and the gate bus bar 24. The insulating layer is, for example, an inorganic insulating film such as a silicon nitride layer, or an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer. 2, the widths of the ohmic contact layer 37 and the gate metal layer 39 are greater than the width of the low resistance layer 38, but the widths of the ohmic contact layer 37 and the gate metal layer 39 may be the same as the width of the low resistance layer 38. Also, the low resistance layer 38 does not necessarily have to be provided.

[0022] [Comparative Example 1] 3 is a plan view of a semiconductor device according to Comparative Example 1. As shown in FIG. 3, in a semiconductor device 110 according to Comparative Example 1, gate electrodes 14c, 14d and a drain electrode 16c are not provided. Gate electrodes 14a and 14b are directly connected to a gate bus bar 24. Drain electrodes 16a and 16b are directly connected to a drain bus bar 26. The drain bus bar 26 is provided on an inactive region 13. In Comparative Example 1, two unit FETs 35a and 35b are provided for one source electrode 12. The other configurations are the same as those of Example 1.

[0023] [Comparative Example 2] FIG. 4 is a plan view of a semiconductor device according to Comparative Example 2. As shown in FIG. 4, in the semiconductor device 112 according to Comparative Example 2, a gate electrode 14c is provided that connects the negative end of the gate electrode 14a in the X direction to the negative end of the gate electrode 14b in the X direction. A drain electrode 16c is provided that connects the negative end of the drain electrode 16a in the X direction to the negative end of the drain electrode 16b in the X direction. The drain electrode 16c is provided on the active region 11. As a result, three unit FETs 35a to 35c are provided for one source electrode 12. Therefore, the gate width of the unit FET 35 can be made larger than that of Comparative Example 1. The output of one source electrode 12 can be increased, making it possible to achieve high output. Considering the same output power, the semiconductor device can be made smaller. The other configurations are the same as those of Example 1, and description thereof will be omitted.

[0024] When a high-frequency signal is supplied from the negative end of the gate bus bar 24 in the Y direction as indicated by the arrow 50c, one of the branched signals passes through the gate bus bar 24 and then flows through the gate electrode 14a as indicated by the arrow 50a. The other branched signal flows through the gate electrodes 14b and 14c as indicated by the arrow 50b. The signal flowing through the arrow 50a and the signal flowing through the arrow 50b join at a point 52 where the electrical lengths of the arrows 50a and 50b are the same, that is, at a point where the gate electrodes 14a and 14c contact each other. For this reason, the unit FET 35 can be effectively regarded as a FET in which two FETs, a first FET having the unit FET 35a and a second FET having the unit FETs 35b and 35c, are connected in parallel. The first FET and the second FET have different effective gate widths up to the point 52. In this case, when designing a high-frequency transistor by arranging a plurality of unit FETs 35, it is necessary to take into account FETs having effectively different gate widths, which makes the design difficult.

[0025] [Description of Example 1] According to the first embodiment, as shown in FIG. 1, the first end of the gate wiring 23 is connected only to a portion 51 (one portion) of the gate electrode 14, and the second end of the gate wiring 23 is connected to the gate bus bar 24. As a result, one of the high-frequency signals that has passed through the gate wiring 23 and is branched at the portion 51 passes through a part of the gate electrode 14d and the gate electrode 14a as indicated by an arrow 50a, and reaches a portion 52 in the gate electrode 14c. The other branched signal passes through a part of the gate electrode 14d and the gate electrode 14b as indicated by an arrow 50b, and reaches a portion 52 in the gate electrode 14c. The portion 52 where the electrical length of the arrow 50a is the same as that of the arrow 50b is approximately the center of the gate electrode 14c. As a result, the unit FET 35 can be effectively regarded as a FET in which two FETs, a first FET having the unit FET 35a and a portion of the unit FET 35c, and a second FET having the unit FET 35b and a portion of the unit FET 35c are connected in parallel. Compared to Comparative Example 2, the effective gate widths of the first FET and the second FET can be made closer to each other. Therefore, when designing a high-frequency transistor by arranging a plurality of unit FETs 35, the design becomes easier. In this way, in Example 1, the semiconductor device 100, which is easy to design, can be miniaturized.

[0026] In the first embodiment, the drain electrode 16 does not surround the gate electrode 14 from the + direction in the X direction (the opposite direction to the second direction). That is, the drain electrode 16 surrounds the gate electrode 14 only from the + direction in the Y direction, the - direction in the Y direction, and the - direction in the X direction. In this way, the drain electrode 16 does not need to be provided between the source electrode 12 and the gate bus bar 24.

[0027] In FIG. 1, the portion 54 is a portion of the gate electrode 14 that is not surrounded by the drain electrode 16 from the positive direction in the X direction. The width of the portion 54 in the Y direction is W1. The center point of the portion 54 in the Y direction is the center point 53. The range 55 is a range having a width W2 that is 1 / 2 the width W1 of the portion 54 in the Y direction, centered on the center point 53. At this time, the first end of the gate wiring 23 is connected within the range 55. This allows the effective gate widths of the two FETs that are effectively connected in parallel among the unit FETs 35 to be closer to each other. Therefore, when designing a high-frequency transistor by arranging a plurality of unit FETs 35, the design becomes easier. The width W2 of the range 55 can be 1 / 3 or 1 / 4 of the width W1.

[0028] The metal layer 28 is provided under the substrate 10 and is electrically connected to the source electrode 12 through a via hole 20 penetrating the substrate 10. This allows a reference potential to be supplied to the source electrode 12. When one via hole 20 is provided in the source electrode 12, the effective gate width of the unit FET 35 per one via hole 20 can be increased, thereby enabling miniaturization.

[0029] The region of the drain electrode 16 surrounding the gate electrode 14 from the positive and negative directions in the Y direction and the negative direction in the X direction is provided on the active region 11. This allows the drain electrode 16c to function as the drain electrode of the unit FET 35c, thereby enabling miniaturization.

[0030] [Modification 1 of Example 1] FIG. 5 is a plan view of a semiconductor device according to Modification 1 of Example 1. As shown in FIG. 5, in a semiconductor device 101 according to Modification 1 of Example 1, FET groups 36a and 36b are arranged in the X direction. The FET groups 36a and 36b include a plurality of unit FETs 35 arranged in the Y direction. The unit FETs 35 adjacent to each other in the Y direction share a drain electrode 16. The FET groups 36a and 36b share a drain bus bar 26 and are provided in mirror symmetry with respect to the drain bus bar 26 in the X direction. The gate electrodes 14 of the plurality of unit FETs 35 in the FET group 36a are electrically connected to and short-circuited with the gate bus bar 24a. The gate electrodes 14 of the plurality of unit FETs 35 in the FET group 36b are electrically connected to and short-circuited with the gate bus bar 24b. The gate bus bar 24a and the drain bus bar 26 sandwich the FET group 36a in the X direction, and the gate bus bar 24b and the drain bus bar 26 sandwich the FET group 36b in the X direction.

[0031] The gate bus bars 24a, 24b and the drain bus bar 26 extend in the Y direction. The gate pad 25 and the drain pad 27 are arranged to sandwich the FET groups 36a and 36b in the Y direction. The gate bus bars 24a and 24b are electrically connected to and short-circuited with the gate pad 25 at their negative ends in the Y direction. The drain bus bar 26 is electrically connected to and short-circuited with the drain pad 27 at their positive end in the Y direction. The number of unit FETs 35 included in each of the FET groups 36a and 36b may be two, three, five or more. The other configurations are the same as those in the first embodiment, and description thereof will be omitted.

[0032] As in the first modification of the first embodiment, the FET group 36a (first FET group) has a plurality of unit FETs 35 arranged in the Y direction, and the drain electrodes 16 of adjacent unit FETs 35 are shared. The gate electrodes 14 of the plurality of unit FETs 35 in the FET group 36a are electrically connected to the gate bus bar 24a (first gate bus bar). The drain electrodes 16 of the unit FETs 35 in the FET group 36a are connected to the drain bus bar 26. The drain bus bar 26 and the gate bus bar 24a sandwich the FET group 36a. With this structure, the unit FETs 35 can be arranged in the Y direction, and the gate width in the semiconductor device 101 can be increased. Since the unit FETs 35 having approximately the same characteristics are arranged, it is easy to design the semiconductor device 101 having a large gate width.

[0033] The FET groups 36a and 36b (second FET group) sandwich the drain bus bar 26. The drain bus bar 26 and the gate bus bar 24b (second gate bus bar) sandwich the FET group 36b. This allows the unit FETs 35 to be arranged in the Y direction, making it possible to increase the gate width in the semiconductor device 101. Since unit FETs 35 with approximately the same characteristics are arranged, it becomes easier to design the semiconductor device 101 with a large gate width.

[0034] The gate pad 25 to which the gate bus bars 24a and 24b are connected and the drain pad 27 to which the drain bus bar 26 is connected are provided to sandwich the FET groups 36a and 36b. This allows a gate potential to be supplied from the gate pad 25 to the gate electrodes 14 of the FET groups 36a and 36b via the gate bus bars 24a and 24b. A drain potential can be supplied from the drain pad 27 to the drain electrodes 16 of the FET groups 36a and 36b via the drain bus bar 26. In this way, the gate pad 25 and the drain pad 27 can be efficiently arranged, making it possible to reduce the size.

[0035] A current larger than that of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction flows through the drain bus bar 26. By making the current density of the drain bus bar 26 and the current density of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction approximately equal, the size of the semiconductor device 101 can be reduced. Therefore, as shown in FIG. 5, the width W3 in the X direction of the drain bus bar 26 is made larger than the width W4 in the Y direction of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction. This makes it possible to make the current density of the drain bus bar 26 and the current density of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction closer to each other. This makes it possible to reduce the size of the semiconductor device 101. The width W3 can be set to 1.5 times or more, or to 2 times or more, the width W4. From the viewpoint of not making the current density of the drain bus bar 26 too small, the width W3 can be set to 10 times or less the width W4.

[0036] The width of the source electrode 12 in the X direction is, for example, 0.1 μm to 200 μm, for example, 50 μm. The width of the source electrode 12 in the Y direction is, for example, 0.1 μm to 200 μm, for example, 50 μm. The gate length of the gate electrode 14 is, for example, 0.05 μm to 5 μm. The width W3 of the drain bus bar 26 in the X direction is, for example, 10 μm to 200 μm, for example, 50 μm. The width W4 of the drain electrode 16 in the Y direction shared by the unit FETs 35 adjacent in the Y direction is, for example, 10 μm to 100 μm, for example, 25 μm. The width of the drain electrode 16c in the X direction is, for example, 5 μm to 50 μm, for example, 12 μm. The distance in the X direction between the gate electrode 14d and the gate bus bars 24a and 24b is, for example, 0.1 μm to 100 μm, for example, 5 μm. The width in the X direction of the gate bus bars 24a and 24b is, for example, 0.05 μm to 500 μm, for example, 30 μm. The width in the Y direction of the gate wiring 23 is, for example, 0.05 μm to 500 μm, for example, 1.0 μm.

[0037] [Modification 2 of Example 1] 6 is a plan view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 6, in a semiconductor device 102 according to Modification 2 of Example 1, a plurality of units 34 each having FET groups 36a, 36b, gate bus bars 24a, 24b, and drain bus bars 26 are arranged in the X direction. A gate pad 25 is provided for each unit 34, and a drain pad 27 is provided for each unit 34. The gate pads 25 of the plurality of units 34 may be provided in a connected state. The drain pads 27 of the plurality of units 34 may be provided in a connected state. The number of units 34 may be two, three, five or more. The other configurations are the same as those of Modification 1 of Example 1, and description thereof will be omitted.

[0038] As in the second modification of the first embodiment, by arranging the units 34 in the X direction, the multiple unit FETs 35 can be arranged efficiently, thereby enabling miniaturization.

[0039] [Example 2] FIG. 7 is a plan view of a semiconductor device according to a second embodiment. As shown in FIG. 7, in a semiconductor device 103 according to the second embodiment, the drain electrode 16 includes a drain electrode 16d in addition to the drain electrodes 16a to 16c. The drain electrode 16d is provided between the gate electrode 14d and the gate bus bar 24. The drain electrode 16d is provided on the active region 11. The unit FET 35d includes a source electrode 12, a gate electrode 14d, and a drain electrode 16d. The drain electrode 16d is divided into two in the Y direction. A region 32 in which the drain electrode 16d is not provided is provided between the divided drain electrodes 16d. The region 32 extends in the X direction. The gate wiring 23 is provided in the region 32 and does not overlap the drain electrode 16d. The gate wiring 23 is provided on the inactive region 13. The other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

[0040] According to the second embodiment, the drain electrode 16 surrounds the gate electrode 14 from the positive direction in the X direction. This makes it possible to increase the effective gate width of the unit FETs 35 sharing one source electrode 12, as compared with FIG. 1 of the first embodiment. This allows the semiconductor device 103 to be made more compact. To achieve this compactness, the width of the region 32 in the Y direction can be set to 1 / 2 or less of the width of the gate electrode 14d in the Y direction.

[0041] As in the first embodiment, the first end of the gate wiring 23 is connected to only one point on the gate electrode 14. This allows the unit FET 35 to be regarded as a FET in which a first FET and a second FET having approximately the same effective gate width are connected in parallel. This makes it easier to design a high-frequency transistor by arranging a plurality of unit FETs 35 in a row. In addition, the effective gate width can be made larger than that of the second comparative example, allowing for miniaturization.

[0042] In the second embodiment, regardless of the position of the portion 51 where the gate wiring 23 is connected to the gate electrode 14, the effective gate width of the FET extending from the portion 51 to the portion 52 via the gate electrode 14a is substantially the same as that of the FET extending from the portion 51 to the portion 52 via the gate electrode 14b. This makes the design easier.

[0043] [Modification 1 of Example 2] FIG. 8 is a plan view of a semiconductor device according to Modification 1 of Example 2. As shown in FIG. 8, in a semiconductor device 104 according to Modification 1 of Example 2, the width Wx in the X direction and the width Wy in the Y direction of the source electrode 12 are substantially the same. The planar shape of the source electrode 12 is substantially square. This allows the effective gate width of the unit FET 35 to be maximized when the planar area of ​​the source electrode 12 is the same. In addition, heat can be diffused isotropically. This improves heat dissipation. The other configurations are the same as those of Example 2, and description thereof will be omitted.

[0044] From the viewpoint of increasing the effective gate width and from the viewpoint of heat dissipation, the width W3 can be set to 3 times or less and 1 / 3 times or more, 2 times or less and 1 / 2 times or more, or 1.5 times or less and 1 / 1.5 times or more of the width W4. In the first embodiment and its modified examples, the width W3 can be set to 3 times or less and 1 / 3 times or more, 2 times or less and 1 / 2 times or more, or 1.5 times or less and 1 / 1.5 times or more of the width W4.

[0045] [Modification 2 of Example 2] Fig. 9 is a plan view of a semiconductor device according to Modification 2 of Example 2. As shown in Fig. 9, in a semiconductor device 105 according to Modification 2 of Example 2, the unit FET 35 is the unit FET 35 of Example 2. The number of unit FETs 35 included in each of the FET groups 36a and 36b may be two, three, or five or more. The other configurations are the same as those of Modification 1 of Example 1, and description thereof will be omitted.

[0046] As in Modification 2 of Example 2, unit FETs 35 having drain electrodes 16d may be arranged in the Y direction. This allows the gate width to be increased in the semiconductor device 105. The width W3 in the X direction of the drain bus bar 26 is greater than the width W4 in the Y direction of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction. This allows a larger current to flow through the drain bus bar 26 than through the drain electrodes 16 of the unit FETs 35.

[0047] [Modification 3 of Example 2] 10 is a plan view of a semiconductor device according to Modification 3 of Example 2. As shown in FIG. 10, in a semiconductor device 106 according to Modification 3 of Example 2, the unit FET 35 is the unit FET 35 of Example 2. The number of units 34 may be two, three, or five or more. The other configurations are the same as those of Modification 2 of Example 1, and a description thereof will be omitted. As in Modification 3 of Example 2, the units 34 may be arranged in the X direction.

[0048] [Example 3] FIG. 11 is a plan view of a semiconductor device according to a third embodiment. As shown in FIG. 11, in the semiconductor device 107, an insulating frame 61 made of ceramics or the like is mounted on a base 60 made of a metal such as copper. An input terminal 62 and an output terminal 63 are provided on the frame 61. Chips 40, 44 and a semiconductor chip 48 are mounted on the base 60. The semiconductor chip 48 is, for example, the semiconductor device 102 in FIG. 6 of the modified example 2 of the first embodiment or the semiconductor device 105 in FIG. 9 of the modified example 3 of the second embodiment. The chip 40 includes a dielectric layer 41, a conductor pattern 42 provided on the dielectric layer 41, and a conductor pattern (not shown) provided under the dielectric layer 41. The chip 44 includes a dielectric layer 45, a conductor pattern 46 provided on the dielectric layer 45, and a conductor pattern (not shown) provided under the dielectric layer 45. The conductor patterns 42, 46, the input terminal 62, and the output terminal 63 are metal layers such as gold layers. A gate pad 25 and a drain pad 27 are provided on the semiconductor chip 48. In FIG. 11, the units 34 and the like are omitted.

[0049] The bonding wire 65 electrically connects the input terminal 62 and the conductor pattern 42. The bonding wire 66 electrically connects the conductor pattern 42 and the gate pad 25. The bonding wire 67 electrically connects the drain pad 27 and the conductor pattern 46. The bonding wire 68 electrically connects the conductor pattern 46 and the output terminal 63.

[0050] The conductor pattern 42 sandwiching the dielectric layer 41 and the conductor pattern below the dielectric layer 41 function as a shunt-connected capacitor. Bonding wires 65 and 66 and chip 40 form an input matching circuit. The conductor pattern 46 sandwiching the dielectric layer 45 and the conductor pattern below the dielectric layer 45 function as a shunt-connected capacitor. Bonding wires 67 and 68 and chip 44 form an output matching circuit.

[0051] A high frequency signal inputted from input terminal 62 is inputted to semiconductor chip 48 via chip 40. The high frequency signal amplified in semiconductor chip 48 is outputted from output terminal 63 via chip 44. As shown in FIG. 6 of modified example 2 of embodiment 1 and FIG. 10 of modified example 3 of embodiment 2, gate pad 25 and drain pad 27 are provided on the long side of substrate 10. This allows bonding wires 66 and 67 to be easily bonded to gate pad 25 and drain pad 27. As in embodiment 3, the semiconductor devices of embodiments 1 and 2 and their modified examples may be configured such that a semiconductor chip is mounted in a package.

[0052] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0053] 10, 10a Board 10b Semiconductor layer 11 Active area 12 Source electrode 13 Inactive area 14, 14a, 14b, 14c, 14d Gate electrode 16, 16a, 16b, 16c, 16d Drain electrodes 20 Beer Hall 23 Gate wiring 24, 24a, 24b Gate busbar 25 Gate Pad 26 Drain busbar 27 Drain Pad 28, 28a metal layer 32 areas 34 units 35, 35a, 35b, 35c, 35d Unit FET 36a, 36b FET group 37 Ohmic contact layer 38 Low resistance layer 39 Gate metal layer 40, 44 chips 41, 45 Dielectric layer 42, 46 Conductor pattern 48 Semiconductor Chips 50a, 50b, 50c Arrows 51, 52 locations 53 Center point 54 parts 55 range 60 base 61 Frame 62 Input terminal 63 Output terminal 65, 66, 67, 68 Bonding wire 100, 101, 102, 103, 104, 105, 105, 106, 107, 110, 112 Semiconductor device

Claims

1. A source electrode provided on the substrate; a gate electrode provided on the substrate in a loop shape to surround the source electrode; a drain electrode provided on the substrate and surrounding the gate electrode from a first direction, a direction opposite to the first direction, and a second direction perpendicular to the first direction; a gate wiring provided on the substrate, the gate wiring having a first end connected to only one portion of the gate electrode and a second end connected to a first gate bus bar; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the drain electrode surrounds the gate electrode only from the first direction, a direction opposite to the first direction, and the second direction.

3. 3. The semiconductor device according to claim 2, wherein a first end of the gate wiring is connected within a range having a width that is half the width in the first direction of a portion of the gate electrode that is not surrounded by the drain electrode from the opposite direction to the second direction, the range being centered on a center point in the first direction.

4. The semiconductor device according to claim 1 , wherein the drain electrode surrounds the gate electrode in a direction opposite to the second direction.

5. 5 . The semiconductor device according to claim 1 , wherein the width of the source electrode in the second direction is equal to or smaller than three times and equal to or larger than one-third of the width of the source electrode in the first direction.

6. 5. The semiconductor device according to claim 1, further comprising a metal layer provided under the substrate and electrically connected to the source electrode through a via hole penetrating the substrate.

7. the substrate has an active region in which a semiconductor layer in the substrate is activated; 5. The semiconductor device according to claim 1, wherein a region of the drain electrode surrounding the gate electrode from the first direction, the direction opposite to the first direction, and the second direction is provided on the active region.

8. a FET group including a plurality of unit FETs arranged in the first direction, each of the unit FETs including the source electrode, the gate electrode, and the drain electrode, the drain electrode being shared between adjacent unit FETs; a drain bus bar that sandwiches a first FET group among the FET group between the first gate bus bar and the drain electrodes of a plurality of unit FETs in the first FET group are connected to the drain bus bar; Equipped with The semiconductor device according to claim 1 , wherein the first gate bus bar is connected to gate wirings of a plurality of unit FETs in the first FET group.

9. a second FET group included in the FET group, the second FET group sandwiching the drain bus bar with the first FET group; a second gate bus bar that sandwiches the second FET group between the drain bus bar and the second gate bus bar and is connected to gate wirings of a plurality of unit FETs in the second FET group; The semiconductor device according to claim 8 .

10. The semiconductor device according to claim 9 , wherein a width of the drain bus bar in the second direction is larger than a width in the first direction of the drain electrode shared by unit FETs adjacent in the first direction.

11. a gate pad to which the first gate bus bar and the second gate bus bar are electrically connected; a drain pad sandwiching the first FET group and the second FET group between the gate pad and the drain pad and electrically connected to the drain bus bar; The semiconductor device according to claim 9 .

12. 10. The semiconductor device according to claim 9, comprising a plurality of units arranged in the second direction, each of which comprises the first group of FETs, the second group of FETs, the drain bus bar, the first gate bus bar, and the second gate bus bar.

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