Memory device

Abstract

To provide a memory device that specifies initialization data of memory cell data to perform batch initialization or a memory device that partially masks an initialization area of memory cell data to perform batch initialization.SOLUTION: There is provided a memory device including: a control circuit that receives an initialization mode signal sent from an initialization control circuit and generates an internal clock and a write control signal; an IO (Input / Output) input circuit that applies a low level to a True side or a Bar side of a bit line according to the initialization data sent from the initialization control circuit; and a selection circuit that simultaneously selects a plurality of word lines and a plurality of bit lines. The initialization data is written simultaneously to memory cells connected to the selected word line and bit line.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to storage devices, such as static random access memories (SRAMs). [Background technology]

[0002] A technology for initializing data in a memory cell has been developed. Patent Document 1 discloses a technology for initializing data in a memory cell at a relatively high speed while suppressing an increase in area. When a reset signal is set to a high level, a control circuit of the semiconductor device sets the first transistor to an off state, the multiple word lines to a selected state, the precharge circuit to an off state, the write column switch to an on state, and the read column switch to an off state. The write circuit sets the first bit line to a low level and the second bit line to a high level, thereby initializing the multiple memory cells. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2023-88805 Summary of the Invention [Problem to be solved by the invention]

[0004] The initialization described in Patent Document 1 shortens the initialization time by initializing all memory cell regions at the same time. However, since the data at the time of initialization is fixed inside the SRAM, initialization can only be performed with 0 or 1. Also, only all memory cell regions can be initialized. Therefore, there is a problem that it is not possible to perform batch initialization of ECC (Error Checking and Correction) memory or memory having an area where important data is stored.

[0005] Therefore, an object of the present disclosure is to provide a storage device that specifies initialization data for memory cell data and initializes the data all at once, or a storage device that masks part of an initialization region for memory cell data and initializes the data all at once.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a storage device initializes an arbitrary area with arbitrary data. Effect of the Invention

[0008] According to the embodiment, it is possible to provide a storage device which specifies initialization data for memory cell data and performs collective initialization, or a storage device which performs collective initialization by partially masking an initialization region for memory cell data. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a schematic diagram showing a state of batch initialization of a storage device. [Diagram 2] FIG. 11 is a schematic diagram showing an example of a state in which a Hamming code of a storage device is masked. [Diagram 3] FIG. 11 is a schematic diagram showing another example of a state in which the Hamming code of the storage device is masked. [Figure 4] FIG. 13 is a schematic diagram showing a case where initialization in the word direction of a storage device is restricted. [Diagram 5] FIG. 13 is a schematic diagram showing a case where bit-wise initialization of a storage device is restricted. [Figure 6] 1 is a schematic diagram of a circuit of a memory device according to an embodiment; [Figure 7] 13 is a diagram illustrating a memory device according to an embodiment in which a circuit for lowering a voltage level is added to a word line driver. [Figure 8] 4 is a timing chart of the storage device according to the embodiment. [Figure 9]1 is a block diagram of a storage device according to an embodiment in which an ECC circuit is added; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in terms of hardware, by a CPU (Central Processing Unit), memory, and other circuits, and in terms of software, by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on the hardware, or a combination of these. In addition, in each drawing, the same elements are given the same symbols, and duplicate explanations are omitted as necessary.

[0011] (Description of Storage Device According to an Embodiment) FIG. 1 is a schematic diagram showing a state of a collective initialization of a memory device. FIG. 2 is a schematic diagram showing an example of a state in which the Hamming code of a memory device is masked. FIG. 3 is a schematic diagram showing another example of a state in which the Hamming code of a memory device is masked. FIG. 4 is a schematic diagram showing a case in which word-wise initialization of a memory device is restricted. FIG. 5 is a schematic diagram showing a case in which bit-wise initialization of a memory device is restricted. FIG. 6 is a schematic diagram of a circuit of a memory device according to an embodiment. The memory device according to the embodiment will be described with reference to FIGS. 1 to 6. The memory device 600 is, for example, an SRAM (Static Random Access Memory).

[0012] As shown in Figure 1, SRAM macros to which ECC is not applied can be initialized all at once. All values ​​in the memory area are set to 0. On the other hand, it is desirable for SRAM macros to which ECC is applied not to have all values ​​be 0, as shown in Figures 2 and 3, for example. For example, from the viewpoint of functional safety, it is desirable to put a value of 1 in the Hamming codes of adjacent bit lines as shown in Figure 2. It is also desirable to put a value of 1 in the Hamming codes at different codes as shown in Figure 3.

[0013] Also, there are cases where it is desired to restrict initialization in the word line direction, as shown in Fig. 4. Furthermore, there are cases where it is desired to restrict initialization in the bit line direction, as shown in Fig. 5. The storage device disclosed herein is a storage device that specifies initialization data for memory cell data and performs batch initialization, or a storage device that performs batch initialization by partially masking an initialization region for memory cell data, and can achieve these states in a batch.

[0014] As shown in FIG. 6, the memory device 600 according to the embodiment includes an initialization control circuit (not shown), a write / read internal clock generation circuit 601, a write control circuit 602, an internal clock generation circuit 603, a row address decoder and initialization time word multiple simultaneous selection circuit 604, a col address decoder and initialization time column switch multiple simultaneous selection circuit 605, an internal clock generation circuit 607, a bit write mask circuit 608, and a write circuit 609.

[0015] The initialization control circuit transmits an initialization mode signal that transitions the memory device to an initialization mode. The initialization mode is a state in which initialization is performed. The initialization control circuit also transmits initialization data of 0 or 1 to be written to the memory device 600. The initialization data is data that initializes the memory device. The initialization control circuit may also transmit an initialization address area mask signal that masks the area to be initialized. The initialization control circuit may also transmit an initialization data mask signal that masks the data to be initialized.

[0016] The write control circuit 602, the internal clock generation circuit 603, and the internal clock generation circuit 607 are collectively referred to as a control circuit. The internal clock generation circuit 603 receives a clock signal and an initialization mode signal from the write / read internal clock generation circuit 601, and generates an internal clock for initialization. The internal clock generation circuit 607 receives a clock signal and an initialization mode signal from the write / read internal clock generation circuit 601, and generates an internal clock for initialization. The write control circuit 602 generates a write control signal that enables the enable signal of the write circuit during initialization, making it possible to write.

[0017] The row address decoder and initialization multiple word simultaneous selection circuit 604 is also called a word line selection circuit 604. The word line selection circuit 604 has a function of a normal row address decoder. Furthermore, the word line selection circuit 604 can limit the initialization in the word line direction by taking in initialization area information input and selecting a word line with any variation.

[0018] As shown in the table in Figure 6, for example, when the initialization mode signal INITM is 1 and the address input A is 000, all word lines are selected. When the initialization mode signal is 1 and the address input A is 001, the even word lines are selected. When the address input A is 010, the odd word lines are selected. When the address input A is 011, the lower half word lines are selected. When the address input A is 100, the upper half word lines are selected. In this way, multiple word lines can be selected simultaneously during initialization.

[0019] The Col address decoder and initialization-time column switch multiple simultaneous selection circuit 605 is also called a bit line selection circuit 605. The bit line selection circuit 605 has a column address decoder function. Furthermore, the bit line selection circuit 605 takes in initialization area information input and selects column switches with any variation, thereby restricting the initialization in the bit line direction on a column-by-column basis.

[0020] The word line selection circuit 604 and the bit line selection circuit 605 are collectively referred to as a selection circuit. In this manner, the selection circuit masks the initialization of a part of the address area based on an initialization address area mask signal input from the initialization control circuit. The word line selection circuit 604 is connected to a word driver section 700. The bit line selection circuit 605 is connected to a column selector and precharge section 610.

[0021] The BitWrite mask circuit 608 has a function of disabling data input and restricting input in the bit line direction during normal operation. The normal operation is when the memory device 600 is used as a memory device. Furthermore, the BitWrite mask circuit 608 has a function of disabling data input and restricting input in the bit line direction during initialization as well.

[0022] The Write circuit 609 has a function of inputting data of 0 or 1 under normal circumstances. Furthermore, the Write circuit 609 has a function of inputting data of 0 or 1 during initialization. The BitWrite mask circuit 608 and the Write circuit 609 are collectively referred to as an IO input circuit. In this way, the IO input circuit masks the IO input of a part of the memory cells according to the initialization data mask signal input from the initialization control circuit.

[0023] The internal clock generation circuit 607 and the IO input circuit are collectively referred to as a write buffer and sense amplifier unit 606. The write buffer and sense amplifier unit 606 is connected to a column selector and precharge unit 610. The column selector and precharge unit 610 has a BT (Bit True) line and a BB (Bit Bar) line connected to the memory cells. Normally, a high level is applied to the true side and the bar side of the bit line. Initialization is performed by applying a low level to the true side or the bar side of the bit line.

[0024] With the above configuration, it is possible to provide a storage device which specifies initialization data for memory cell data and performs collective initialization, or a storage device which performs collective initialization by partially masking an initialization region for memory cell data.

[0025] (Description of a Word Driver Unit of a Storage Device According to an Embodiment) Fig. 7 is a diagram in which a circuit for lowering a voltage level is added to a word line driver of a memory device according to an embodiment. A word driver unit of the memory device according to an embodiment will be described with reference to Fig. 7. The word driver unit 700 is a circuit for driving a word line.

[0026] As shown in FIG. 7, the word driver section 700 includes a wiring 701 connected to the word line selection circuit 604 , a word line driver circuit 702 , and a level lowering circuit 703 .

[0027] The wiring 701 is connected to a plurality of word line driver circuits 702. The wiring 701 raises the voltages of a plurality of word lines in response to a signal generated by the word line selection circuit 604 at the time of initialization.

[0028] The word line driver circuits 702 are connected to one level lowering circuit 703. The level lowering circuit 703 is a complementary transistor having an N-channel transistor and a P-channel transistor. The gate of the level lowering circuit 703 is connected to a reset write signal, and the output is connected to a power supply line of the word driver circuit. Since a through current flows during initialization restriction in the bit line direction, the level lowering circuit 703 turns off the P-channel transistor and turns on the N-channel transistor during initialization. Therefore, the level lowering circuit 703 can lower the high level potential of the word line at the time of rising. As a result, the level lowering circuit 703 suppresses the peak current and the charge / discharge current, and reduces the power consumption of the memory device 600.

[0029] (Description of Timing Chart of Storage Device According to the Embodiment) 8 is a timing chart of the storage device according to the embodiment. The timing chart of the storage device according to the embodiment will be described with reference to FIGS.

[0030] 6 and 8, INITM is an initialization mode signal. When the initialization mode signal becomes high level, initialization is performed. When the initialization mode signal INITM becomes high, the write control signal WTRSTE of the write control circuit 602 becomes high. Also, when the initialization mode signal INITM becomes high, the internal clock CPIO of the internal clock generation circuit 607 becomes high.

[0031] Then, LLHL data is input to the BT (Bit True) line in response to the initialization data input DIN (0010).HHLH data is input to the BB (Bit Bar) line in response to the initialization data input DIN (0010).

[0032] In response to the initialization mode signal, a plurality of word lines are selected in a High state, and data (0010) is input to the memory cells in response to the initialization data input DIN (0010).

[0033] With the above configuration, a plurality of word lines are selected, and selected initialization data is input to the memory cells.

[0034] (Description of a Storage Device Adding an ECC (Error Checking and Correction) Circuit According to an Embodiment) Fig. 9 is a block diagram of a storage device according to an embodiment to which an ECC circuit has been added. The storage device to which an ECC circuit according to an embodiment has been added will be described with reference to Fig. 9. The ECC circuit is an error detection / correction circuit.

[0035] The memory device 900 to which an ECC circuit has been added comprises a system control circuit 901 , an ECC circuit 902 , and a memory device 903 .

[0036] The MBIST (Memory Built In Self Test) circuit 904 is a test circuit that tests a memory before shipment. For example, the MBIST circuit outputs initialization data MDIN when initializing a storage device 900 with an added ECC circuit before shipment.

[0037] The system control circuit 901 includes an initialization control circuit. In a memory test after shipment, the system control circuit 901 outputs an initialization mode signal INITM, initialization data CDIN, an initialization address area mask signal CA, and an initialization data mask signal CBWN.

[0038] The ECC circuit 902 is connected to the system control circuit 901. The ECC circuit is also connected to the memory device 903. That is, the ECC circuit 902 is disposed between the system control circuit 901 and the memory device 903. The ECC circuit receives initialization data and transmits an error detection / correction code EDIN.

[0039] The storage device 903 is, for example, an SRAM macro. The storage device 903 receives initialization data including a Hamming code output from an ECC during initialization in a memory test after shipment, and is initialized all at once according to the data DIN.

[0040] The initialization flow of the memory device 900 to which an ECC circuit has been added is as follows. First, the system control circuit 901 outputs initialization data including a bit designation signal to the ECC circuit. The system control circuit 901 also outputs an address signal designating an initialization area to the memory device 903. Next, the ECC circuit 902 receives the initialization data and generates a Hamming code. Next, the memory device 903 receives the initialization data including the Hamming code from the ECC circuit 902, and receives an address signal designating an initialization area from the system control circuit 901. Next, the system control circuit 901 outputs an initialization mode signal to the memory device 903. Finally, the memory device 903 performs initialization processing of the designated area.

[0041] The above configuration makes it possible to handle the case where an ECC circuit is added to perform initialization using initialization data including a Hamming code.

[0042] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0043] 600 memory device, 601 internal clock generation circuit for write / read, 602 write control circuit, 603 internal clock generation circuit, 604 multiple simultaneous word selection circuit at initialization, 605 multiple simultaneous column switch selection circuit at initialization, 606 write buffer, sense amplifier section, 607 internal clock generation circuit, 608 BitWrite mask circuit, 609 Write circuit, 610 column selector, precharge section, 700 word driver section, 701 wiring, 702 word line driver circuit, 703 level lowering circuit, 900 memory device with ECC circuit added, 901 system control circuit, 902 ECC circuit, 903 memory device

Claims

1. a control circuit that receives an initialization mode signal transmitted from the initialization control circuit and generates an internal clock and a write control signal; an IO (Input / Output) input circuit that applies a low level to a true side or a bar side of a bit line in response to initialization data transmitted from the initialization control circuit; a selection circuit for simultaneously selecting a plurality of word lines and a plurality of bit lines; A storage device that simultaneously writes the initialization data into memory cells connected to the selected word line and bit line.

2. the initialization control circuit generates an initialization address area mask signal for masking an area to be initialized; 2. The storage device according to claim 1, wherein the selection circuit masks the initialization of a part of an address area based on the initialization address area mask signal input from the initialization control circuit.

3. the initialization control circuit generates an initialization data mask signal for masking data to be initialized; 2. The storage device according to claim 1, wherein said IO input circuit masks IO inputs of some of said memory cells in response to said initialization data mask signal input from said initialization control circuit.

4. 2. The memory device according to claim 1, wherein a word driver section connected to said selection circuit lowers a high level potential of said selected word lines.

5. an error detection / correction circuit disposed between the initialization control circuit and the storage device according to claim 1; the initialization mode signal, the initialization data, an initialization data mask signal for masking data to be initialized, and an initialization address area mask signal for masking an area to be initialized, all of which are transmitted from the initialization control circuit; A storage device that retrieves the error detection / correction code transmitted from the error detection / correction circuit and collectively initializes the data in the memory cells.

6. 2. The storage device of claim 1, wherein the storage device is a static random access memory (SRAM) macro.

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