Information processing system

Abstract

To provide an information processing system configured to start executing updated firmware earlier than the case where the updated firmware stored in a recording unit is transferred to a main memory via a nonvolatile memory.SOLUTION: A sub processor 46 in an information processing system 10 is configured to: cause a first direct memory access control unit 50 to transfer at least a part of updated firmware 80A stored in a recording unit 20 to a main memory 48 from the recording unit 20; cause the first direct memory access control unit 50 or a second direct memory access control unit 52 to transfer the updated firmware 80A from the recording unit 20 to a nonvolatile memory 60; and start, when the updated firmware 80A is completely transferred to the main memory 48, executing the update firmware 80A transferred to the main memory 48 before the updated firmware 80A is completely transferred to the nonvolatile memory 60.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an information processing system. [Background technology]

[0002] For example, Patent Document 1 discloses an information processing device comprising: a storage means for storing firmware including a basic part for a device to operate alone and an application part other than the basic part; an extraction means for extracting the basic part of new firmware when updating the firmware stored in the storage means with new firmware; an update means for updating the basic part of the firmware with the basic part extracted by the extraction means before the application part; and an execution means for executing a process to validate the basic part updated by the update means. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-232100 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure aims to provide an information processing system that accelerates the start of execution of updated firmware compared to a case in which updated firmware stored in a recording unit is transferred to a main memory via a non-volatile memory. [Means for solving the problem]

[0005] An information processing system of a first aspect comprises a main memory, a non-volatile memory, a processor that executes pre-update firmware stored in the main memory, a first direct memory access control unit controlled by the processor, and a second direct memory access control unit controlled by the processor, wherein the processor causes the first direct memory access control unit to transfer at least a portion of the updated firmware stored in a recording unit from the recording unit to the main memory, and causes the first direct memory access control unit or the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory, and when the transfer of the updated firmware to the main memory is completed, starts executing the updated firmware transferred to the main memory before the transfer of the updated firmware to the non-volatile memory is completed.

[0006] A second aspect of the information processing system is an information processing system described in the first aspect, in which the processor transfers at least a portion of the updated firmware to a memory area in the main memory in which the pre-update firmware executed by the processor is stored, and in parallel with having the first direct memory access control unit transfer the entire updated firmware from the recording unit to the main memory, the processor causes the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory.

[0007] A third aspect of the information processing system is an information processing system described in the first aspect, in which the processor causes the first direct memory access control unit to transfer a portion of the updated firmware to the main memory, and causes the second direct memory access control unit to transfer another portion of the updated firmware to the main memory, and then transfers the updated firmware from the recording unit to the non-volatile memory.

[0008] A fourth aspect of the information processing system is an information processing system described in the third aspect, in which the processor transfers at least a portion of the updated firmware to a memory area in the main memory in which the pre-update firmware executed by the processor is stored.

[0009] A fifth aspect of the information processing system is an information processing system as described in the first aspect, in which, when the processor determines that it is unable to control the second direct memory access control unit, the processor causes the first direct memory access control unit to transfer all of the updated firmware from the recording unit to the main memory, and then further causes the updated firmware to be transferred from the recording unit to the non-volatile memory.

[0010] A sixth aspect of the information processing system is an information processing system described in the fifth aspect, wherein the processor transfers the updated firmware from the recording unit to the non-volatile memory in parallel with execution of the updated firmware transferred to the main memory. Effect of the Invention

[0011] According to the information processing system of the first aspect, it is possible to speed up the start of execution of the updated firmware compared to a case in which the updated firmware stored in the recording unit is transferred to the main memory via the non-volatile memory.

[0012] According to the information processing system of the second aspect, it is possible to execute the updated firmware without stopping the processor.

[0013] According to the information processing system according to the third aspect, it is possible to speed up the start of execution of the updated firmware, compared to a case in which the entire updated firmware is transferred by the first direct memory access controller.

[0014] According to the information processing system of the fourth aspect, it is possible to execute the updated firmware without stopping the processor.

[0015] According to the information processing system of the fifth aspect, the transfer of the updated firmware can be completed more quickly, compared to a case in which the processor waits until it can control the second direct memory access control unit.

[0016] According to the information processing system of the sixth aspect, the transfer of the updated firmware to the non-volatile memory can be completed more quickly compared to a case in which the transfer of the updated firmware to the non-volatile memory is not performed until the processor finishes executing the updated firmware. [Brief description of the drawings]

[0017] [Figure 1] 1 is a block diagram illustrating a configuration of an information processing system according to a first embodiment of the present disclosure. [Diagram 2] 4 is a timing chart illustrating an operation when the information processing system according to the first embodiment of the present disclosure is started in a normal boot mode. [Diagram 3] 3 is a sequence diagram illustrating an operation of the information processing system according to the first embodiment of the present disclosure. FIG. [Figure 4] 4 is a timing chart illustrating an operation when the information processing system according to the first embodiment of the present disclosure updates firmware. [Diagram 5] FIG. 1 is a block diagram illustrating a configuration of an information processing system according to a comparative example of the present disclosure. [Figure 6] FIG. 11 is a sequence diagram illustrating an operation of an information processing system according to a comparative example of the present disclosure. [Figure 7] 11 is a timing chart illustrating an operation when an information processing system according to a comparative example of the present disclosure updates firmware. [Figure 8] 13 is a diagram illustrating an operation of an information processing system according to a second embodiment of the present disclosure for updating firmware stored in a main memory. FIG. [Figure 9] 8, and is a diagram illustrating an operation of the information processing system according to the second embodiment of the present disclosure updating firmware stored in the main memory. [Figure 10] 13 is a timing chart illustrating an operation when an information processing system according to a third embodiment of the present disclosure updates firmware. [Figure 11] 13 is a timing chart illustrating an operation when an information processing system according to a fourth embodiment of the present disclosure updates firmware. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

[0019] [First embodiment] (Information Processing System) FIG. 1 is a diagram showing an example of an information processing system 10 according to the present embodiment. The information processing system 10 according to the present embodiment is applied to computer-controlled devices such as image forming devices, industrial devices, and communication devices. As shown in FIG. 1, the information processing system 10 shown in the present embodiment includes a recording unit 20, a main control unit 30, a sub-processor 46, and a non-volatile memory 60. Each component of the information processing system 10 shown in FIG. 1 is supplied with power from a power source (not shown).

[0020] (Recording Section 20) The recording unit 20 is a device that records the updated firmware 80A. The recording unit 20 may be any device that can record the updated firmware 80A, but as an example, a DRAM (Dynamic Random Access Memory) is used. The recording unit 20 is also connected to a main control unit 30 (described later) via a channel 24.

[0021] (Main control unit 30) The main control unit 30 has a first interface (I / F) 32, a second interface 34, and a main processor 36.

[0022] The first interface 32 is connected to the recording unit 20 via a channel 24. The second interface 34 is connected to a sub-control unit 40 (described later) via a channel 26. The main processor 36 is, for example, a CPU (Central Processing Unit), and is connected to the first interface 32 and the second interface 34 via a bus 38. The main processor 36 executes a program stored in a memory (not shown) of the main control unit 30.

[0023] (Sub-control unit 40) The sub-control unit 40 has a first interface 42, a second interface 44, a sub-processor 46, a main memory 48, a first direct memory access control unit 50, and a second direct memory access control unit 52. The sub-control unit 40 further has a hash calculation unit 54.

[0024] The first interface 42 is connected to the main control unit 30 via the channel 26. The second interface 44 is connected to the non-volatile memory 60 via the channel 28. The sub-processor 46 is, for example, a CPU, and is connected to the first interface 42, the second interface 44, and the main memory 48 via the bus 38. The sub-processor 46 executes a program stored in the main memory 48. The sub-processor 46 in this embodiment is an example of a "processor" in the present disclosure.

[0025] The main memory 48 is, for example, a volatile storage device such as a static random access memory (SRAM), and is connected to each component of the sub-controller 40 via the bus 38. The main memory 48 is a device in which data is temporarily stored while the sub-processor 46 is running. Furthermore, the main memory 48 stores firmware when the sub-processor 46 is started up, as described below, and the sub-processor 46 executes the firmware stored in the main memory 48. Note that the main memory 48 according to this embodiment is configured such that stored data is lost when the supply of power from a power source (not shown) is stopped, for example, when the information processing system 10 is shut down.

[0026] The first direct memory access control unit 50 is connected to the main memory 48, the first interface 42, and the second interface 44 via the bus 38. The first direct memory access control unit 50 is a so-called DMAC (Direct Memory Access Controller), and can access the updated firmware 80A stored in the recording unit 20 via the channel 26 and the main control unit 30. The first direct memory access control unit 50 can also access the non-volatile memory 60 via the channel 28. The first direct memory access control unit 50 according to this embodiment can read data stored in the main memory 48 and the non-volatile memory 60 and write data to the main memory 48 and the non-volatile memory 60, regardless of the state of the sub-processor 46.

[0027] The second direct memory access control unit 52 has the same configuration as the first direct memory access control unit 50. That is, the second direct memory access control unit 52 can read data stored in the main memory 48 and the non-volatile memory 60 and write data to the main memory 48 and the non-volatile memory 60 regardless of the state of the sub-processor 46.

[0028] The hash calculation unit 54 is connected to the sub-processor 46, the first direct memory access control unit 50, and the second direct memory access control unit 52 via the bus 38. In addition, the hash calculation unit 54 has a calculation function of outputting a hash value, which is a calculation result that is uniquely determined for the input data, when the hash calculation unit 54 receives data.

[0029] (Non-volatile memory 60) The non-volatile memory 60 is, for example, a storage device such as a flash memory, and is connected to the sub-control unit 40 via the channel 28. The non-volatile memory 60 is a device in which firmware executed by the sub-processor 46 is stored, and when the sub-processor 46 starts up as described below, the pre-update firmware 80B stored in the non-volatile memory 60 is executed. Note that the non-volatile memory 60 according to this embodiment has a function of retaining stored data even when the supply of power from a power source (not shown) is stopped, for example, when the information processing system 10 is shut down.

[0030] In the information processing system 10 according to this embodiment, the main control unit 30 and the sub-control unit 40 are capable of executing control operations separately. The main control unit 30 and the sub-control unit 40 may be incorporated in the same device or in separate devices, so long as they are connected via a channel 26 as shown in Fig. 1. Furthermore, the channels 24, 26, and 28 may communicate with each other in any manner, so long as each component is capable of communicating with each other as shown in Fig. 1.

[0031] In this embodiment, the main control unit 30 is capable of providing updated firmware 80A for the sub-control unit 40. More specifically, when the main processor 36 receives an instruction from the sub-processor 46 of the sub-control unit 40, it transfers the updated firmware 80A stored in the recording unit 20 to the sub-control unit 40. Also, when the main processor 36 receives an instruction from the first direct memory access control unit 50 or the second direct memory access control unit 52, it transfers the updated firmware 80A stored in the recording unit 20 to the sub-control unit 40.

[0032] Next, a specific operation of the sub-control unit 40 according to this embodiment will be described.

[0033] (Normal boot mode operation) 2 is a diagram showing a process of a normal boot mode in which the sub-control unit 40 executes firmware stored in the non-volatile memory 60 in this embodiment. In the normal boot mode as shown in FIG. 2, the sub-processor 46 transfers the firmware from the non-volatile memory 60 to the main memory 48 in sequence N1. In addition, the sub-processor 46 transfers the firmware stored in the main memory 48 to the hash calculation unit 54 in sequence N2. In addition, the hash calculation unit 54 calculates a hash value and compares it with a previously calculated hash value to check the reliability of the data. Then, the sub-processor 46 executes the firmware stored in the main memory 48 when it is confirmed that the reliability of the firmware stored in the main memory 48 is ensured based on the hash value.

[0034] The above-mentioned normal boot mode is executed when the firmware is stored in the non-volatile memory 60. In other words, when a process for updating firmware is performed, the completion of the process indicates a state in which the updated firmware is stored in the non-volatile memory 60.

[0035] (Firmware update mode operation) Next, the operation of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60 in this embodiment will be described with reference to Figures 3 and 4. Figure 3 is a sequence diagram of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60 in this embodiment. Figure 3 is a sequence diagram of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60, following Figure 3. Figure 4 is a timing chart that explains the processes of the first direct memory access control unit 50 and the second direct memory access control unit 52.

[0036] In the information processing system 10 according to this embodiment, as shown in FIG. 3, the first direct memory access control unit 50 and the second direct memory access control unit 52 each perform an operation of transferring the updated firmware 80A in parallel.

[0037] In the following description, there are cases where one configuration requests two different configurations to issue the same instruction substantially simultaneously, or where two different configurations request one configuration to issue the same instruction substantially simultaneously. In these cases, the symbols A and B are added to the end of the sequence names in the following description and drawings to indicate that the two processes are started substantially simultaneously. Note that "substantially simultaneously" includes the start of each process within an allowable time when the operating speed of the information processing system 10 is taken into consideration.

[0038] In the following timing charts, the horizontal size of the rectangles showing the processing contents indicates the relative length of the processing time required for the processing contents. For example, in Fig. 4, it is shown that the processing performed from sequence F5A to sequence F8 requires more processing time than the processing performed from sequence F5B to sequence F14.

[0039] 3, in sequence F1, the sub-processor 46 checks the usage status of the first direct memory access control unit 50 and the second direct memory access control unit 52. Specifically, it checks whether the first direct memory access control unit 50 and the second direct memory access control unit 52 are on standby (not executing another process).

[0040] Next, in sequence F2A, the sub-processor 46 transmits an instruction to transfer the updated firmware 80A to the first direct memory access control unit 50. In addition, in sequence F2B, the sub-processor 46 transmits an instruction to transfer the updated firmware 80A to the second direct memory access control unit 52.

[0041] Next, in sequence F3A, the first direct memory access control unit 50 requests transmission of the updated firmware 80A stored in the recording unit 20. Also, in sequence F3B, the second direct memory access control unit 52 requests transmission of the updated firmware 80A stored in the recording unit 20.

[0042] Next, in sequence F4A, the recording unit 20 transmits the updated firmware 80A to the first direct memory access control unit 50. In addition, the recording unit 20 transmits the updated firmware 80A to the second direct memory access control unit 52 in sequence F4B.

[0043] Next, in sequence F5A, the first direct memory access control unit 50 starts transmitting the updated firmware 80A to the main memory 48. Also, in sequence F5B, the second direct memory access control unit 52 starts transmitting the updated firmware 80A to the non-volatile memory 60.

[0044] In the information processing system 10 according to the present embodiment, the main memory 48 and the nonvolatile memory 60 have different write speeds. In other words, the main memory 48 and the nonvolatile memory 60 require different times from when an instruction to store the same data is received until the storage is completed. Specifically, the main memory 48, which is an SRAM, has a higher write speed than the nonvolatile memory 60, which is a flash memory.

[0045] For this reason, when the main memory 48 and the non-volatile memory 60 receive data at the same time, the timing at which each sequence is completed differs, as shown in Figures 3 and 4. Specifically, as shown in Figures 3 and 4, the write process to the main memory 48 is completed before the write process to the non-volatile memory 60.

[0046] 3, when the main memory 48 has completed receiving the updated firmware 80A, in sequence F8, the main memory 48 notifies the first direct memory access control unit 50 that the transfer has been completed. Note that, in sequence F8, the second direct memory access control unit 52 continues to transmit the updated firmware 80A to the non-volatile memory 60, as shown in FIG. 3 and FIG. 4.

[0047] Next, in sequence F9, the first direct memory access control unit 50 causes the hash calculation unit 54 to calculate a hash value for the updated firmware 80A stored in the main memory 48. Then, the first direct memory access control unit 50 compares a predetermined hash value with the calculated hash value to confirm the reliability of the updated firmware 80A transmitted to the main memory 48 as data.

[0048] Next, in sequence F10, the first direct memory access control unit 50 notifies the sub-processor 46 that the transfer of the updated firmware 80A to the main memory 48 has been completed.

[0049] Next, the sub-processor 46 reads the updated firmware 80A from the main memory 48 in sequence F11.

[0050] Next, the main memory 48 transmits the updated firmware 80A to the sub-processor 46 in sequence F12.

[0051] Next, in sequence F13, the sub-processor 46 starts executing the updated firmware 80A. Thereafter, the sub-processor 46 executes the updated firmware 80A.

[0052] 3, in this embodiment, after the updated firmware 80A is executed in sequence F13, the transmission of the updated firmware 80A to the non-volatile memory 60 is completed. Then, when the non-volatile memory 60 has completed receiving the updated firmware 80A, in sequence F14, the non-volatile memory 60 notifies the second direct memory access control unit 52 that the transfer has been completed.

[0053] Next, in sequence F15, the second direct memory access control unit 52 causes the hash calculation unit 54 to calculate a hash value for the updated firmware 80A stored in the nonvolatile memory 60. Then, the second direct memory access control unit 52 compares a predetermined hash value with the calculated hash value to confirm the reliability of the pre-update firmware 80B transmitted to the nonvolatile memory 60 as data.

[0054] Next, in sequence F16, the second direct memory access control unit 52 notifies the sub-processor 46 that the transfer of the updated firmware 80A to the non-volatile memory 60 has been completed.

[0055] By executing the above procedure, the sub-control unit 40 completes the transfer of the updated firmware 80A to the non-volatile memory 60. When the sub-processor 46 is started from the next time onwards, the sub-processor 46 transfers the updated firmware 80A stored in the non-volatile memory 60 to the main memory 48 as shown in FIG. 2, and then executes the updated firmware 80A.

[0056] (Information Processing System 110 of Comparative Example) FIG. 5 shows an information processing system 110 according to a comparative example of the present embodiment. The difference between the information processing system 110 according to the comparative example and the information processing system 10 according to the comparative example is the number of direct memory access control units, as shown in FIG. 1 and FIG. 5. Specifically, the information processing system 10 according to the present embodiment includes two direct memory access control units, whereas the information processing system 110 according to the comparative example includes one direct memory access control unit, the first direct memory access control unit 50. The other configurations are the same as those of the information processing system 10 according to the present embodiment. In the following description, the same components in the information processing system 110 according to the comparative example and the information processing system 10 according to the present embodiment will be described with the same reference numerals.

[0057] (Operation in Firmware Update Mode by Information Processing System 110 in Comparative Example) Next, the operation of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60 in this embodiment will be described with reference to Figures 6 and 7. Figure 6 is a sequence diagram of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60 in this embodiment. Figure 6 is a sequence diagram of the firmware update mode in which the sub-control unit 40 updates firmware stored in the non-volatile memory 60, following Figure 6. Figure 7 is a timing chart that explains the process of the first direct memory access control unit 50.

[0058] 6, in sequence F101, the sub processor 46 checks the usage state of the first direct memory access control unit 50. Specifically, it checks whether the first direct memory access control unit 50 is in standby (not executing another process).

[0059] Next, in sequence F102, the sub-processor 46 sends an instruction to the first direct memory access control unit 50 to transfer the updated firmware 80A.

[0060] Next, in sequence F103, the first direct memory access control unit 50 requests the recording unit 20 to transmit the updated firmware 80A stored therein.

[0061] Next, in sequence F104, the recording unit 20 transmits the updated firmware 80A to the first direct memory access control unit 50.

[0062] Next, the first direct memory access control unit 50 starts transmitting the updated firmware 80A to the non-volatile memory 60 in sequence F105.

[0063] Next, as shown in FIG. 6, when the nonvolatile memory 60 has completed receiving the updated firmware 80A, in sequence F107, the nonvolatile memory 60 notifies the first direct memory access control unit 50 that the transfer has been completed.

[0064] Next, in sequence F108, the first direct memory access control unit 50 causes the hash calculation unit 54 to calculate a hash value for the updated firmware 80A stored in the nonvolatile memory 60. Then, the first direct memory access control unit 50 compares a predetermined hash value with the calculated hash value to confirm the reliability of the updated firmware 80A transmitted to the nonvolatile memory 60 as data.

[0065] Next, the first direct memory access control unit 50 starts transmitting the updated firmware 80A to the main memory 48 in sequence F109.

[0066] Next, when the main memory 48 has completed receiving the updated firmware 80A, in sequence F111, the main memory 48 notifies the first direct memory access control unit 50 that the transfer has been completed.

[0067] Next, in sequence F112, the first direct memory access control unit 50 causes the hash calculation unit 54 to calculate a hash value for the updated firmware 80A stored in the main memory 48. Then, the first direct memory access control unit 50 compares a predetermined hash value with the calculated hash value to confirm the reliability of the updated firmware 80A transmitted to the main memory 48 as data.

[0068] Next, in sequence F113, the first direct memory access control unit 50 notifies the sub-processor 46 that the transfer of the updated firmware 80A to the main memory 48 has been completed.

[0069] Next, the sub-processor 46 reads the updated firmware 80A from the main memory 48 in sequence F114.

[0070] Next, the main memory 48 transmits the updated firmware 80A to the sub-processor 46 in sequence F115.

[0071] Next, in sequence F116, the sub-processor 46 starts executing the updated firmware 80A. Thereafter, the sub-processor 46 executes the updated firmware 80A.

[0072] By executing the above procedure, the information processing system 110 according to the comparative example also completes the transfer of the updated firmware 80A to the non-volatile memory 60 by the sub-control unit 40. When the sub-processor 46 is started from the next time onwards, the sub-processor 46 transfers the updated firmware 80A stored in the non-volatile memory 60 to the main memory 48 as shown in FIG. 2, and then executes the updated firmware 80A.

[0073] Here, as shown in FIGS. 3 to 7, the time required from the start of transfer of the updated firmware 80A until the updated firmware 80A is stored in the main memory 48 differs between this embodiment and the comparative example.

[0074] (Action and effect) In other words, according to the information processing system 10 of this embodiment, the execution of the updated firmware 80A can be started earlier than when the updated firmware 80A stored in the recording unit 20 is transferred to the main memory 48 via the non-volatile memory 60.

[0075] [Second embodiment] Next, an information processing system 10 according to a second embodiment of the present disclosure will be described with reference to Fig. 8 and Fig. 9. Note that the configuration of the information processing system 10 according to this embodiment is similar to the configuration of the information processing system 10 according to the first embodiment, and a description of the specific configuration will be omitted.

[0076] (Operation of the information processing system 10 in the firmware update mode according to the second embodiment) 8 and 9, in the information processing system 10 according to the present embodiment, a storage area to which the updated firmware 80A is transferred to the main memory 48 is specified. More specifically, in the information processing system 10 according to the present embodiment, in sequence F5A in the first embodiment, the first direct memory access control unit 50 transfers the firmware 80A to the storage area in the main memory 48 in which the pre-update firmware 80B is stored.

[0077] That is, in the information processing system 10 according to this embodiment, when the first direct memory access control unit 50 completes the transfer of the updated firmware 80A, the sub-processor 46 executes the updated firmware 80A.

[0078] (Action and effect) According to the information processing system 10 of the present embodiment, the updated firmware 80A can be executed without stopping the processor. In other words, in the information processing system 10 of the present embodiment, the updated firmware 80A is executed without restarting the processor, so that the timing of executing the updated firmware 80A can be further accelerated compared to the information processing system 10 of the first embodiment.

[0079] [Third embodiment] Next, an information processing system 10 according to a third embodiment of the present disclosure will be described with reference to FIG. 10. The configuration of the information processing system 10 according to this embodiment is the same as that of the information processing system 10 according to the first embodiment, and a detailed description of the configuration will be omitted. As shown in FIG. 10, in the firmware update mode, the same sequences as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and a detailed description will be omitted. In the information processing system 10 according to this embodiment, the updated firmware 80A can be divided into a basic portion for the sub-processor 46 to operate independently and an application portion other than the basic portion.

[0080] (Operation of the Information Processing System 10 in the Firmware Update Mode According to the Third Embodiment) 10 is a timing chart for explaining the processes of the first direct memory access control unit 50 and the second direct memory access control unit 52 in the firmware update mode of this embodiment. In the information processing system 10 according to this embodiment, the sequence F5A in which the information processing system 10 according to the first embodiment transfers the updated firmware 80A to the main memory 48 is further divided into a sequence F205A1 and a sequence F205A2. More specifically, the sequence F205A1 is a sequence in which the basic part of the updated firmware 80A is transferred, and the sequence F205A2 is a sequence in which the application part of the updated firmware 80A is transferred.

[0081] 10, in the information processing system 10 according to the present embodiment, the first direct memory access control unit 50 executes the sequence F205A1, and the second direct memory access control unit 52 executes the sequence F205A2. In other words, in the information processing system 10 according to the present embodiment, the second direct memory access control unit 52 executes the sequence F205A2 before executing the sequence F5B. That is, in the information processing system 10 according to the present embodiment, the sub-processor 46 causes the second direct memory access control unit 52 to transfer the updated firmware 80A to the main memory 48. Then, the sub-processor 46 further causes the second direct memory access control unit 52 to transfer the updated firmware 80A from the recording unit 20 to the non-volatile memory 60.

[0082] In this embodiment, the first direct memory access control unit 50 transfers the updated firmware 80A to a storage area in the main memory 48 where the pre-update firmware 80B is stored in sequence F205A1, similar to the second embodiment. In addition, the second direct memory access control unit 52 transfers the updated firmware 80A to a storage area in the main memory 48 where the pre-update firmware 80B is stored in sequence F205A2, similar to the second embodiment. In addition, the sub-processor 46 according to this embodiment executes the updated firmware 80A immediately after completing sequence F205A1 in which a basic part of the updated firmware 80A is transferred, without waiting for completion of sequence F205A2.

[0083] (Action and effect) According to the information processing system 10 of this embodiment, it is possible to start execution of the updated firmware 80A earlier than when the entire updated firmware 80A is transferred by the first direct memory access control unit 50. Furthermore, in the information processing system 10 of this embodiment, it is possible to execute the updated firmware 80A without stopping the processor. In other words, in the information processing system 10 of this embodiment, since the updated firmware 80A is executed without restarting the processor, it is possible to further accelerate the timing of execution of the updated firmware 80A compared to the information processing systems 10 of the first and second embodiments.

[0084] [Fourth embodiment] Next, an information processing system 10 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 11. Note that the configuration of the information processing system 10 according to this embodiment is similar to the configuration of the information processing system 10 according to the first embodiment, and a description of the specific configuration will be omitted.

[0085] (Operation of the Information Processing System 10 in the Firmware Update Mode According to the Fourth Embodiment) In this embodiment, in sequence F1 in the first embodiment, it is determined that the second direct memory access control unit 52 is executing another process and cannot transfer the updated firmware 80A. Then, in this embodiment, as shown in Fig. 11, the sub-processor 46 causes the first direct memory access control unit 50 to execute sequences F305A and F9, similarly to the first embodiment.

[0086] 11, in this embodiment, when the first direct memory access control unit 50 completes execution of sequence F9, the sub-processor 46 causes the first direct memory access control unit 50 to execute sequence F305B to transmit the updated firmware 80A to the non-volatile memory 60. In addition, when the sub-processor 46 completes execution of sequence F9, the sub-processor 46 causes the first direct memory access control unit 50 to execute sequence F315 to cause the hash calculation unit 54 to calculate a hash value for the updated firmware 80A stored in the non-volatile memory 60. In other words, in this embodiment, when the first direct memory access control unit 50 completes execution of sequence F9, the sub-processor 46 causes the first direct memory access control unit 50 to execute processes similar to sequences F5B and F15.

[0087] (Action and effect) According to the information processing system 10 of this embodiment, it is possible to complete the transfer of the updated firmware 80A earlier than when the sub-processor 46 waits until it can control the second direct memory access control unit 52. In other words, in this embodiment, even if it is determined that it is not possible to control either the first direct memory access control unit 50 or the second direct memory access control unit 52 at the time of sequence F1, it is possible to update the firmware.

[0088] (Modification) In this embodiment as well, when the second direct memory access control unit 52 becomes controllable while the first direct memory access control unit 50 is executing sequence F5A or sequence F9, the second direct memory access control unit 52 may be caused to execute sequence F5B, as in the other embodiments. In other words, in this embodiment as well, the updated firmware 80A may be transferred from the recording unit 20 to the non-volatile memory 60 in parallel with the execution of the updated firmware 80A transferred to the main memory 48.

[0089] Even in this modified example, the transfer of the updated firmware 80A to the non-volatile memory 60 can be completed more quickly compared to a case in which the transfer of the updated firmware 80A to the non-volatile memory 60 is not performed until the processor finishes executing the updated firmware 80A.

[0090] The above describes an embodiment of the present disclosure with reference to the attached drawings. However, it is clear that a person with ordinary knowledge in the technical field to which the present disclosure pertains can conceive of various modifications or applications within the scope of the technical ideas described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0091] Furthermore, preferred aspects of the present disclosure will be described below.

[0092] (((1))) A main memory; A non-volatile memory; A processor that executes pre-update firmware stored in the main memory; a first direct memory access control unit controlled by the processor; a second direct memory access control unit controlled by the processor; Equipped with the processor causes the first direct memory access control unit to transfer at least a portion of the updated firmware stored in a recording unit from the recording unit to the main memory, and causes the first direct memory access control unit or the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory, and when the transfer of the updated firmware to the main memory is completed, starts execution of the updated firmware that was transferred to the main memory before the transfer of the updated firmware to the non-volatile memory is completed. Information processing system.

[0093] (((2))) the processor causes the first direct memory access control unit to transfer the entire updated firmware from the recording unit to the main memory while transferring at least a portion of the updated firmware to a storage area in the main memory in which the pre-update firmware executed by the processor is stored, and causes the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory in parallel with the first direct memory access control unit transferring the entire updated firmware from the recording unit to the main memory; (((1))) is an information processing system.

[0094] (((3))) the processor causes the first direct memory access control unit to transfer a portion of the updated firmware to the main memory, and causes the second direct memory access control unit to transfer another portion of the updated firmware to the main memory, and then causes the processor to transfer the updated firmware from the recording unit to the non-volatile memory; (((1))) is an information processing system.

[0095] (((4))) The processor transfers at least a portion of the updated firmware to a storage area in the main memory in which the pre-update firmware executed by the processor is stored. (((3))) is an information processing system.

[0096] (((5))) when it is determined that the processor cannot control the second direct memory access control unit, the processor causes the first direct memory access control unit to transfer the entire updated firmware from the recording unit to the main memory, and then causes the first direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory. (((1))) is an information processing system.

[0097] (((6))) the processor transfers the updated firmware from the recording unit to the non-volatile memory in parallel with execution of the updated firmware transferred to the main memory; (((5))) is an information processing system.

[0098] According to the information processing system of (((1))), it is possible to speed up the start of execution of the updated firmware compared to a case in which the updated firmware stored in the recording unit is transferred to the main memory via a non-volatile memory. According to the information processing system of (((2))), updated firmware can be executed without stopping the processor. According to the information processing system of (((3))), it is possible to speed up the start of execution of the updated firmware, compared to a case in which the entire updated firmware is transferred by the second direct memory access control unit. According to the information processing system of (((4))), updated firmware can be executed without stopping the processor. According to the information processing system of (((5))), the transfer of the updated firmware can be completed more quickly than in the case where the processor waits until it can control the second direct memory access control unit. According to the information processing system of (((6))), the transfer of the updated firmware to the non-volatile memory can be completed more quickly than in a case where the transfer of the updated firmware to the non-volatile memory is not performed until the processor finishes executing the updated firmware. [Explanation of symbols]

[0099] 10. Information Processing Systems 20 Recording Section 24 Channels 26 Channels 28 Channels 30 Main control unit 32 First Interface 34 Second Interface 36 Main Processor 38 Bus 40 Sub-control section 42 First Interface 44 Second Interface 46 Sub-processor (an example of a processor) 48 Main memory 50 First direct memory access control unit 52 Second direct memory access control unit 54 Hash calculation unit 60 Non-volatile memory 80A Updated Firmware 80B Pre-update firmware 110 Information Processing Systems

Claims

1. A main memory; A non-volatile memory; A processor that executes the pre-update firmware stored in the main memory; a first direct memory access control unit controlled by the processor; a second direct memory access control unit controlled by the processor; Equipped with the processor causes the first direct memory access control unit to transfer at least a portion of the updated firmware stored in a recording unit from the recording unit to the main memory, and causes the first direct memory access control unit or the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory, and when the transfer of the updated firmware to the main memory is completed, starts execution of the updated firmware that was transferred to the main memory before the transfer of the updated firmware to the non-volatile memory is completed. Information processing system.

2. the processor causes the first direct memory access control unit to transfer the entire updated firmware from the recording unit to the main memory while transferring at least a portion of the updated firmware to a storage area in the main memory in which the pre-update firmware executed by the processor is stored, and causes the second direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory in parallel with the first direct memory access control unit transferring the entire updated firmware from the recording unit to the main memory; The information processing system according to claim 1 .

3. the processor causes the first direct memory access control unit to transfer a portion of the updated firmware to the main memory, and causes the second direct memory access control unit to transfer another portion of the updated firmware to the main memory, and then causes the processor to transfer the updated firmware from the recording unit to the non-volatile memory; The information processing system according to claim 1 .

4. The processor transfers at least a portion of the updated firmware to a storage area in the main memory in which the pre-update firmware executed by the processor is stored. The information processing system according to claim 3 .

5. when it is determined that the second direct memory access control unit cannot be controlled, the processor causes the first direct memory access control unit to transfer the entire updated firmware from the recording unit to the main memory, and then causes the first direct memory access control unit to transfer the updated firmware from the recording unit to the non-volatile memory. The information processing system according to claim 1 .

6. the processor transfers the updated firmware from the recording unit to the non-volatile memory in parallel with execution of the updated firmware transferred to the main memory; The information processing system according to claim 5 .

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