Wiring board, stacked wiring board and method for manufacturing wiring board

Abstract

To suppress diffusion of noise from a semiconductor element.SOLUTION: A wiring board has a first wiring structure, and a second wiring structure. The first wiring structure has a mounting surface of a semiconductor element and a rear face opposite to the mounting surface. The second wiring structure is formed on the rear face of the first wiring structure. The second wiring structure has a reinforced insulating layer, a cavity, an electronic component, and a filler resin layer. The reinforced insulating layer is formed on the rear face of the first wiring structure. The cavity is formed by notching the reinforced insulating layer in a direction of the rear face of the first wiring structure. The electronic component is positioned in the cavity. The filler resin layer is made to fill the cavity, and coats the electronic component.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring board, a multilayer wiring board, and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, for example, a laminated wiring board is known in which an intermediate board having fine wiring is laminated on a main board. In such a laminated wiring board, a semiconductor element is mounted on the intermediate board, and electronic components such as a capacitor may be mounted on the main board around the intermediate board. The electronic components mounted on the main board have a function of reducing noise generated from the semiconductor element mounted on the intermediate board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-144207 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the above-mentioned laminated wiring board has a problem that noise from the semiconductor element may diffuse. Specifically, since the semiconductor element mounted on the intermediate board and the electronic component mounted on the main board are connected via the wiring of the intermediate board and the wiring of the main board, the length of the wiring between the semiconductor element and the electronic component becomes large, and the inductance of the wiring increases. As a result, the noise from the semiconductor element is not sufficiently reduced in the electronic component, and there is a risk that it will diffuse around the semiconductor element.

[0005] The disclosed technology has been made in consideration of the above, and aims to provide a wiring board, a stacked wiring board, and a method for manufacturing a wiring board that can suppress the diffusion of noise from semiconductor elements. [Means for solving the problem]

[0006] In one embodiment, the wiring board disclosed in the present application has a first wiring structure and a second wiring structure. The first wiring structure has a mounting surface for a semiconductor element and a back surface opposite to the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure has a reinforcing insulating layer, a cavity, an electronic component, and a filling resin layer. The reinforcing insulating layer is formed on the back surface of the first wiring structure. The cavity is formed by cutting the reinforcing insulating layer toward the back surface of the first wiring structure. The electronic component is located in the cavity. The filling resin layer fills the cavity and covers the electronic component. Effect of the Invention

[0007] According to one aspect of the wiring board disclosed in the present application, it is possible to suppress the diffusion of noise from a semiconductor element. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a structure of a substrate according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a configuration of a first wiring board according to the embodiment. [Diagram 3] FIG. 3 is a flow diagram showing a method for manufacturing the first wiring board according to the embodiment. [Figure 4] FIG. 4 is a diagram showing a specific example of a glass support. [Diagram 5] FIG. 5 is a diagram showing a specific example of the seed layer forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of a resist layer forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of the electrode pad forming step. [Figure 8] FIG. 8 illustrates a specific example of the resist layer removing step. [Figure 9] FIG. 9 is a diagram showing a specific example of the seed layer removing step. [Figure 10] FIG. 10 is a diagram showing a specific example of the insulating layer forming step. [Figure 11] FIG. 11 is a diagram showing a specific example of the seed layer forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of a resist layer forming step. [Figure 13] FIG. 13 is a diagram showing a specific example of an electrolytic copper plating process. [Figure 14] FIG. 14 is a diagram showing a specific example of the resist layer removing step. [Figure 15] FIG. 15 is a diagram showing a specific example of the seed layer removing step. [Figure 16] FIG. 16 is a diagram showing a specific example of the solder application step. [Figure 17] FIG. 17 is a diagram showing a specific example of the adhesive layer forming step. [Figure 18] FIG. 18 is a flow diagram showing a method for manufacturing a substrate according to an embodiment. [Figure 19] FIG. 19 is a diagram showing a specific example of the first wiring board mounting step. [Figure 20] FIG. 20 is a diagram showing a specific example of the glass support peeling step. [Figure 21] FIG. 21 is a diagram illustrating a configuration example of a semiconductor device. [Figure 22] FIG. 22 is a flow diagram showing a method of forming a second wiring structure according to an embodiment. [Diagram 23] FIG. 23 is a diagram showing a specific example of the reinforcing insulating layer forming step. [Figure 24] FIG. 24 is a diagram showing an example of a via hole forming step. [Diagram 25] FIG. 25 is a diagram showing a specific example of the seed layer forming step. [Figure 26] FIG. 26 is a diagram showing a specific example of a resist layer forming step. [Figure 27] FIG. 27 is a diagram showing a specific example of an electrolytic copper plating process. [Figure 28] FIG. 28 illustrates a specific example of the resist layer removing step. [Figure 29] FIG. 29 is a diagram showing a specific example of the seed layer removing step. [Diagram 30] FIG. 30 is a diagram showing a specific example of the cavity forming step. [Diagram 31] FIG. 31 is a diagram showing a specific example of an electronic component placement process. [Diagram 32] FIG. 32 is a diagram showing a specific example of an electronic component embedding step. [Diagram 33] FIG. 33 is a diagram showing an example of a via hole forming step. [Diagram 34] FIG. 34 is a diagram showing a configuration of a first wiring substrate according to the first modification of the embodiment. [Diagram 35] FIG. 35 is a diagram showing a specific example of a cavity forming step. [Diagram 36] FIG. 36 is a diagram showing a specific example of an electronic component placement process. [Figure 37] FIG. 37 is a diagram showing a configuration of a first wiring board according to the second modification of the embodiment. [Figure 38] FIG. 38 is a diagram showing a configuration of a first wiring board according to the third modification of the embodiment. [Figure 39] FIG. 39 is a diagram showing a specific example of a cavity forming step. [Diagram 40] FIG. 40 is a diagram showing a specific example of an electronic component placement process. [Diagram 41] FIG. 41 is a diagram showing a configuration of a first wiring board according to the fourth modification of the embodiment. [Diagram 42] FIG. 42 is a diagram showing a specific example of the recess forming step. [Diagram 43] FIG. 43 is a diagram showing a specific example of an electronic component placement process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of a wiring board, a multilayer wiring board, and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to the embodiments.

[0010] (Embodiment) FIG. 1 is a diagram showing the structure of a substrate according to an embodiment. FIG. 1 shows a schematic cross section of the substrate according to the embodiment. The substrate shown in FIG. 1 is a laminated type wiring substrate in which a first wiring substrate 100 is laminated on a second wiring substrate 200. In the following description, the direction from the second wiring substrate 200 to the first wiring substrate 100 in FIG. 1 is considered to be up, and the direction from the first wiring substrate 100 to the second wiring substrate 200 is considered to be down. However, the first wiring substrate 100 and the second wiring substrate 200 may be manufactured and used, for example, upside down, or in any position.

[0011] The first wiring substrate 100 is an intermediate substrate having a first wiring structure 110 in which a plurality of thin film layers are laminated, and a second wiring structure 120 serving as a base layer. An electrode pad 111 is formed on an upper surface 110a of the first wiring structure 110. The electrode pad 111 is formed of a conductor such as copper, and serves as a connection terminal when a semiconductor element is bonded to the first wiring substrate 100. That is, when a semiconductor element is bonded to the first wiring substrate 100, the semiconductor element is mounted on the upper surface 110a of the first wiring structure 110, and the electrode pad 111 and the electrode of the semiconductor element are bonded by solder. An electrode pad 121 is formed on a lower surface of the second wiring structure 120. The electrode pad 121 is formed of a conductor such as copper, and serves as a connection terminal when the first wiring substrate 100 is bonded to the second wiring substrate 200. Moreover, electrode pad 121 is connected to the wiring of first wiring structure 110 through a wiring layer and a via in second wiring structure 120.

[0012] The second wiring board 200 is a main board having a core layer 210, a build-up layer 220 laminated on the upper surface of the core layer 210, and a build-up layer 230 laminated on the lower surface of the core layer 210. An electrode pad 221 is formed on the upper surface of the build-up layer 220, and an electrode pad 231 is formed on the lower surface of the build-up layer 230. The electrode pad 221 is formed of a conductor such as copper, and serves as a connection terminal when the second wiring board 200 is joined to the first wiring board 100. The electrode pad 231 is formed of a conductor such as copper, and serves as a connection terminal when the second wiring board 200 is joined to an external component such as a motherboard. In addition, wiring that electrically connects the electrode pad 221 and the electrode pad 231 is formed inside the core layer 210, inside the build-up layer 220, and inside the build-up layer 230.

[0013] First wiring board 100 is mounted on second wiring board 200. That is, electrode pad 121, which is a connection terminal of first wiring board 100, and electrode pad 221, which is a connection terminal of second wiring board 200, are joined by solder 201. Then, adhesive layer 101 is formed between the lower surface of first wiring board 100 (i.e., the lower surface of second wiring structure 120) and the upper surface of second wiring board 200. Adhesive layer 101 bonds first wiring board 100 and second wiring board 200 together while covering a portion of the side surface of first wiring board 100.

[0014] The first wiring board 100 and the second wiring board 200 bonded by the adhesive layer 101 and the solder 201 in this manner are manufactured separately. The first wiring board 100 is manufactured on a support made of, for example, glass. That is, the first wiring structure 110 is formed on the glass support with the upper surface 110a of the first wiring structure 110 facing the glass support, and the second wiring structure 120 is laminated on the lower surface 110b of the first wiring structure 110, thereby manufacturing the first wiring board 100. Then, when the first wiring board 100 and the second wiring board 200 manufactured on the glass support are bonded by the adhesive layer 101 and the solder 201, the glass support is peeled off from the first wiring board 100.

[0015] Here, the configuration of an intermediate structure formed in the process of manufacturing first wiring substrate 100 will be described with reference to FIG. 2. FIG. 2 is a diagram showing the configuration of first wiring substrate 100 according to an embodiment. The intermediate structure of first wiring substrate 100 shown in FIG. 2 has glass support 300, first wiring structure 110 formed above glass support 300, and second wiring structure 120 laminated on lower surface 110b of first wiring structure 110. First wiring structure 110 and second wiring structure 120 are formed upside down on glass support 300. Electronic component 130 is embedded in second wiring structure 120.

[0016] The glass support 300 is a support having a flat upper surface, and a release layer 301 is formed on the upper surface. For example, a silicone-based or acrylic-based adhesive material is used as the release layer 301. The glass support 300 is peeled off from the release layer 301 to obtain the first wiring board 100. The glass support 300 is peeled off from the release layer 301 after the first wiring board 100 and the second wiring board 200, which are fabricated on the glass support 300, are joined by an adhesive layer 101 and a solder 201. Note that a support other than the glass support 300 may be used, and the material of such a support may be metal, silicon, ceramic, or the like.

[0017] The first wiring structure 110 is a structure having a thickness of, for example, about 30 to 50 μm, including a first thin film layer 112, a second thin film layer 113, a third thin film layer 114, and a fourth thin film layer 115. Here, the first wiring structure 110 is formed by laminating four thin film layers on the upper surface of the glass support 300, but the number of thin film layers laminated on the upper surface of the glass support 300 does not have to be four. The first to fourth thin film layers 112 to 115 are thin film layers formed by forming a wiring layer 116 including fine wiring on an insulating layer 110c. The wiring layers 116 of the first to fourth thin film layers 112 to 115 are connected by vias 117 penetrating the insulating layer 110c. The vias 117 are formed in a truncated cone shape with a diameter on the electrode pad 111 side smaller than that on the electrode pad 121 side.

[0018] The insulating layers 110c of the first to fourth thin film layers 112 to 115 are formed using, for example, a photosensitive insulating resin. When the fine wiring layers 116 are formed above the respective insulating layers 110c, a resist is formed on the upper surface of the insulating layers 110c, and patterning and electrolytic copper plating are performed.

[0019] An electrode pad 111 is embedded in the first thin film layer 112, which is the bottom layer. The electrode pad 111 is formed of a conductor such as copper, and is used as a connection terminal when a semiconductor element is bonded to the first wiring board 100. A surface (lower surface) of the first thin film layer 112 located on the upper surface side of the glass support 300 forms an upper surface 110a of the first wiring structure 110, which is a mounting surface for a semiconductor element, and the electrode pad 111 is exposed from the first thin film layer 112 on the upper surface 110a of the first wiring structure 110. The electrode pad 111 is connected to the wiring layer 116 of the second thin film layer 113 by a via 117 penetrating the insulating layer 110c of the first thin film layer 112.

[0020] The second wiring structure 120 is a structure having a thickness of, for example, about 50 to 100 μm, including a reinforcing insulating layer 123 and a filled resin layer 124. The reinforcing insulating layer 123 is formed by impregnating a reinforcing member such as glass fiber with an insulating resin. By including the reinforcing member in the reinforcing insulating layer 123, the rigidity of the second wiring structure 120 becomes greater than the rigidity of the first wiring structure 110, and the strength of the first wiring board 100 is improved. The insulating resin impregnated in the reinforcing member of the reinforcing insulating layer 123 is a resin that hardens by thermosetting, such as an epoxy resin or a polyimide resin. A wiring layer 125 is formed on the surface of the reinforcing insulating layer 123. The wiring layer 125 is connected to the wiring of the first wiring structure 110 by a via 126 that penetrates the reinforcing insulating layer 123. The via 126 is formed in a truncated cone shape with a diameter on the electrode pad 111 side smaller than that on the electrode pad 121 side. The electronic component 130 is embedded in the reinforcing insulating layer 123. A cavity for accommodating the electronic component 130 is formed in the reinforcing insulating layer 123.

[0021] The filled resin layer 124 is a layer formed continuously with the filled resin 135 filled in the cavity in the electronic component embedding step described later. The electrode pad 121 and the wiring 127 are formed on the surface of the filled resin layer 124. The electrode pad 121 is formed of a conductor such as copper, and serves as a connection terminal when the first wiring board 100 is joined to the second wiring board 200. The wiring 127 is formed of a conductor such as copper, and serves as a transmission wiring for transmitting an input / output signal of the electronic component 130. The vias 122 and 128 are formed in the filled resin layer 124 after the electronic component embedding step, and the electrode pad 121 or the wiring 127 on the surface of the filled resin layer 124 is connected to the wiring layer 125 on the surface of the reinforcing insulating layer 123 or the electrode 131 of the electronic component 130. The vias 122 and 128 are formed in a truncated cone shape with a diameter on the electrode pad 111 side smaller than that on the electrode pad 121 side. Filling resin layer 124 may be formed using the same reinforcing material and insulating resin as reinforcing insulating layer 123.

[0022] Electronic component 130 is, for example, a capacitor or other such electronic component, and has a function of reducing noise generated from a semiconductor element mounted on upper surface 110a of first wiring structure 110. Electronic component 130 is embedded in reinforcing insulating layer 123. That is, electronic component 130 is embedded in second wiring structure 120 by filling resin 135 around electronic component 130.

[0023] Thus, in the embodiment, since the electronic component 130 is embedded in the second wiring structure 120, the semiconductor element mounted on the upper surface 110a of the first wiring structure 110 and the electronic component 130 are connected only through the wiring of the first wiring board 100, which is the relay board. That is, the semiconductor element and the electronic component 130 are connected through the electrode pads 111, the wiring layer 116, the vias 117, the wiring layer 125, the vias 126, the wiring 127, and the vias 128 of the first wiring board 100. As a result, compared to a structure in which the semiconductor element and the electronic component mounted on the main board are connected through the wiring of the relay board and the wiring of the main board, the length of the wiring between the semiconductor element and the electronic component 130 can be made smaller, and the inductance of the wiring can be reduced. As a result, the noise from the semiconductor element can be efficiently reduced in the electronic component 130, and the diffusion of the noise from the semiconductor element can be suppressed.

[0024] Moreover, in the embodiment, electronic component 130 is embedded in second wiring structure 120 including a reinforcing member. This makes it possible to improve resistance to stress applied to electronic component 130, thereby reducing the possibility of damage to electronic component 130.

[0025] Moreover, in the embodiment, the thickness of second wiring structure 120 is equal to or greater than that of first wiring structure 110. Therefore, restrictions on the component size of electronic component 130 embedded in second wiring structure 120 can be reduced.

[0026] Moreover, in the embodiment, first wiring structure 110 is formed on glass support 300 with upper surface 110a, which is the mounting surface for semiconductor elements, facing glass support 300. This increases the strength of first wiring substrate 100, and improves the handleability of first wiring substrate 100.

[0027] 2 is peeled off from first wiring substrate 100 after first wiring substrate 100 and second wiring substrate 200 are joined, the timing of peeling off glass substrate 300 is not limited thereto. For example, glass substrate 300 may be peeled off at the stage where first wiring substrate 100 is formed on glass substrate 300 shown in FIG.

[0028] Next, a method for manufacturing the first wiring substrate 100 shown in Fig. 2 will be specifically described with reference to a flow diagram shown in Fig. 3. Fig. 3 is a flow diagram showing the method for manufacturing the first wiring substrate 100 according to the embodiment.

[0029] First, a glass support 300 is prepared as a support for manufacturing the first wiring substrate 100 (step S101). Specifically, as shown in FIG. 4, for example, a release layer 301 is formed on the flat upper surface of the glass support 300. FIG. 4 is a diagram showing a specific example of the glass support 300. Note that a support other than the glass support 300 may be used, and the material of such a support may be metal, silicon, ceramic, or the like.

[0030] Then, as shown in Fig. 5, a seed layer 302 is formed on the upper surface of the release layer 301 of the glass support 300 by, for example, sputtering copper (step S102). Fig. 5 is a diagram showing a specific example of the seed layer formation step.

[0031] Then, as shown in Fig. 6, a resist layer 151 having an opening 151a is formed on the seed layer 302 (step S103). The resist layer 151 is formed using, for example, a dry film resist, and the opening 151a can be formed by, for example, photolithography or laser processing. Fig. 6 is a diagram showing a specific example of the resist layer formation step.

[0032] After the resist layer 151 is formed, the electrode pads 111 are formed by electrolytic copper plating in which power is supplied from the seed layer 302 (step S104). Specifically, as shown in Fig. 7, for example, the electrode pads 111 are formed on the seed layer 302 exposed in the openings 151a of the resist layer 151. Fig. 7 is a diagram showing a specific example of the electrode pad formation step.

[0033] Next, the resist layer 151 is removed (step S105), for example, as shown in Fig. 8. Fig. 8 is a diagram showing a specific example of the resist layer removing step. To remove the resist layer 151, for example, caustic soda or an amine-based alkaline stripping liquid is used.

[0034] After the resist layer 151 is removed, unnecessary portions of the seed layer 302 are removed by flash etching (step S106). Specifically, the seed layer 302 exposed without contacting the electrode pad 111 is dissolved by an etching solution that dissolves the seed layer 302, and the peeling layer 301 is exposed except for the portion that contacts the electrode pad 111, as shown in FIG. 9. FIG. 9 is a diagram showing a specific example of the seed layer removal step. Note that the seed layer 302 in contact with the electrode pad 111 remains even after the flash etching, but is not shown in FIG. 9.

[0035] When the seed layer 302 is removed, the first wiring structure 110 is formed on the peeling layer 301. First, the insulating layer 110c of the first thin film layer 112 is formed on the peeling layer 301 so as to cover the electrode pad 111 (step S107). The insulating layer 110c is formed using a photosensitive insulating resin, and a via hole is formed by photolithography. Specifically, as shown in FIG. 10, for example, a via hole 112a is formed in the insulating layer 110c of the first thin film layer 112 at a position corresponding to the electrode pad 111, exposing the upper surface of the electrode pad 111. FIG. 10 is a diagram showing a specific example of the insulating layer formation step. The surface (lower surface) of the first thin film layer 112 located on the upper surface side of the glass support 300 forms the upper surface 110a of the first wiring structure 110, which is the mounting surface of the semiconductor element, and the electrode pad 111 is exposed from the first thin film layer 112 on the upper surface 110a of the first wiring structure 110.

[0036] Then, a seed layer is formed on the surface of the insulating layer 110c of the first thin film layer 112 by, for example, copper sputtering (step S108). That is, as shown in Fig. 11, for example, a seed layer 112b is formed to cover the surface of the electrode pad 111 exposed in the via hole 112a and the surface of the insulating layer 110c of the first thin film layer 112 including the inner wall of the via hole 112a. Fig. 11 is a diagram showing a specific example of the seed layer formation step.

[0037] After the seed layer 112b is formed, a resist layer for forming the wiring layer 116 of the first thin film layer 112 is formed on the seed layer 112b (step S109). That is, for example, as shown in Fig. 12, a resist layer 152 having openings in areas where wiring patterns of fine wiring are to be formed is formed on the seed layer 112b by patterning using exposure and development. Fig. 12 is a diagram showing a specific example of the resist layer formation step.

[0038] After the resist layer 152 is formed, the wiring layer 116 and vias 117 of the first thin film layer 112 are formed on the seed layer 112b exposed from the openings of the resist layer 152, for example, by electrolytic copper plating fed from the seed layer 112b (step S110). Specifically, for example, as shown in Fig. 13, the via holes 112a are filled with electrolytic copper to form the vias 117, and the wiring layer 116 having fine wiring is formed. Fig. 13 is a diagram showing a specific example of the electrolytic copper plating process.

[0039] When the wiring layer 116 and the vias 117 of the first thin film layer 112 are formed by electrolytic copper plating, the resist layer 152 is removed (step S111), for example, as shown in Fig. 14. Fig. 14 is a diagram showing a specific example of the resist layer removing step. To remove the resist layer 152, for example, caustic soda or an amine-based alkaline stripping solution is used.

[0040] After the resist layer 152 is removed, unnecessary portions of the seed layer 112b are removed by flash etching (step S112), and the first thin film layer 112 of the first wiring structure 110 is completed. That is, as shown in FIG. 15, for example, the seed layer 112b is removed except for the portions in contact with the wiring layer 116 and the vias 117, and the first thin film layer 112 having the insulating layer 110c, the wiring layer 116, and the vias 117 is laminated on the peeling layer 301. FIG. 15 is a diagram showing a specific example of the seed layer removal step. Note that the seed layer 112b in contact with the wiring layer 116 and the vias 117 remains even after the flash etching, but is not shown in FIG. 15.

[0041] Since multiple thin film layers may be laminated to form first wiring structure 110, whether the process is to end or not is determined depending on whether the lamination of the thin film layers is completed (step S113). If the lamination of the thin film layers is not completed (step S113 No), the same process as the formation of first thin film layer 112 described above is repeated to form second thin film layer 113 and onward.

[0042] On the other hand, if the lamination of the thin film layers is complete (Yes in step S113), this means that first wiring structure 110 is completed, and second wiring structure 120 is formed on lower surface 110b of first wiring structure 110 (step S114). That is, reinforcing insulating layer 123 and filled resin layer 124 are laminated in order on lower surface 110b of first wiring structure 110, forming second wiring structure 120 having wiring layer 125, electrode pads 121, and wiring 127, and in which electronic component 130 is embedded. The process of forming second wiring structure 120 will be described in detail later.

[0043] 2 is obtained. That is, an intermediate structure is formed in which first wiring structure 110 and second wiring structure 120 are formed on glass support 300. First wiring structure 110 and second wiring structure 120 constitute first wiring substrate 100.

[0044] Next, in order to bond first wiring board 100 to second wiring board 200, solder 201 is applied to electrode pads 121 of first wiring board 100 (step S115), for example, as shown in Fig. 16. Fig. 16 is a diagram showing a specific example of the solder application step.

[0045] When the solder 201 is applied to the electrode pads 121 of the first wiring substrate 100, an adhesive layer 101 that covers the electrode pads 121 and the solder 201 is formed on the lower surface of the second wiring structure 120 where the electrode pads 121 are located (step S116), as shown in Fig. 16. Fig. 17 is a diagram showing a specific example of the adhesive layer formation step.

[0046] Next, a method for manufacturing the substrate shown in Fig. 1 will be specifically described with reference to a flow chart shown in Fig. 18. Fig. 18 is a flow chart showing a method for manufacturing a substrate according to an embodiment.

[0047] First, first wiring board 100 fabricated on glass support 300 is mounted on second wiring board 200 via adhesive layer 101 (step S121). Specifically, as shown in Fig. 19, first wiring board 100 and second wiring board 200 are bonded by adhesive layer 101 such that electrode pad 121 of first wiring board 100 and electrode pad 221 of second wiring board 200 are connected via solder 201. Fig. 19 is a diagram showing a specific example of the first wiring board mounting step.

[0048] When first wiring board 100 and second wiring board 200 are joined by adhesive layer 101 and solder 201, glass support 300 is peeled off from peeling layer 301 of first wiring board 100 (step S122), for example, as shown in Fig. 20. Fig. 20 is a diagram showing a specific example of the glass support peeling step.

[0049] Then, release layer 301 is removed (step S123), thereby completing the laminated wiring board in which first wiring board 100 and second wiring board 200 shown in FIG. 1 are laminated.

[0050] The laminated wiring board shown in FIG. 1 can be used for a semiconductor device mounting a semiconductor element such as a semiconductor chip. Specifically, for example, as shown in FIG. 21, a semiconductor chip 400 is mounted on an upper surface 110a of a first wiring board 100. FIG. 21 is a diagram showing a configuration example of a semiconductor device. An electrode 410 of the semiconductor chip 400 and an electrode pad 111 of the first wiring board 100 are joined by solder 401. Then, the joint between the electrode 410 and the electrode pad 111 is sealed by an underfill resin 402. As a result, a semiconductor device is obtained in which the semiconductor chip 400 is mounted on the first wiring board 100, which is an intermediate board, via the underfill resin 402.

[0051] In such a semiconductor device, the electronic component 130 is embedded in the second wiring structure 120. Therefore, the semiconductor chip 400 mounted on the upper surface 110a of the first wiring structure 110 and the electronic component 130 are connected only through the wiring of the first wiring substrate 100, which is an intermediate substrate. That is, the semiconductor chip 400 and the electronic component 130 are connected through the electrode pads 111, the wiring layer 116, the vias 117, the wiring layer 125, the vias 126, the wiring 127, and the vias 128 of the first wiring substrate 100. As a result, the length of the wiring between the semiconductor chip 400 and the electronic component 130 can be reduced, and the inductance of the wiring can be reduced, compared to a structure in which the semiconductor chip 400 and the electronic component mounted on the main substrate are connected through the wiring of the intermediate substrate and the wiring of the main substrate. As a result, the noise from the semiconductor chip 400 can be efficiently reduced in the electronic component 130, and the diffusion of the noise from the semiconductor chip 400 can be suppressed.

[0052] Next, a process of forming second wiring structure 120 of first wiring substrate 100 will be specifically described with reference to a flow diagram shown in Fig. 22. Fig. 22 is a flow diagram showing a method of forming second wiring structure 120 according to the embodiment. The process of forming second wiring structure 120 shown in Fig. 22 corresponds to step S114 in Fig. 3.

[0053] First, a reinforcing insulating layer 123 covering the outermost wiring layer 116 of first wiring structure 110 is formed on lower surface 110b of first wiring structure 110 (step S131). That is, as shown in Fig. 23 for example, reinforcing insulating layer 123 in an uncured state is laminated on lower surface 110b of first wiring structure 110, and wiring layer 116 is covered by reinforcing insulating layer 123. Reinforcing insulating layer 123 formed on lower surface 110b of first wiring structure 110 is thermally cured. Fig. 23 is a diagram showing a specific example of the reinforcing insulating layer forming step.

[0054] Then, a via hole is formed in reinforcing insulating layer 123 (step S132). Specifically, as shown in FIG. 24, for example, via hole 123a is formed which penetrates reinforcing insulating layer 123 and exposes the surface of wiring layer 116, which is the outermost layer of first wiring structure 110. FIG. 24 is a diagram showing an example of a via hole forming step. Via hole 123a can be formed by laser processing, for example. Residue (smear) of insulating resin generated by laser processing is removed by desmearing.

[0055] After the via holes 123a are formed, a seed layer is formed on the surface of the reinforcing insulating layer 123 by, for example, copper sputtering (step S133). That is, as shown in Fig. 25, for example, a seed layer 123b is formed to cover the surface of the wiring layer 116 exposed in the via holes 123a and the surface of the reinforcing insulating layer 123 including the inner wall of the via holes 123a. Fig. 25 is a diagram showing a specific example of the seed layer formation step.

[0056] After the seed layer 123b is formed, a resist layer for forming the wiring layer 125 is formed on the seed layer 123b (step S134). That is, for example, as shown in Fig. 26, a resist layer 161 having openings in portions where wiring patterns are to be formed is formed on the seed layer 123b by patterning using exposure and development. Fig. 26 is a diagram showing a specific example of the resist layer formation step.

[0057] When the resist layer 161 is formed, the wiring layer 125 and the vias 126 are formed on the seed layer 123b exposed from the openings of the resist layer 161 by, for example, electrolytic copper plating in which power is supplied from the seed layer 123b (step S135). Specifically, as shown in FIG. 27, for example, the via holes 123a are filled with electrolytic copper plating to form the vias 126, and the wiring layer 125 having a predetermined wiring pattern is formed. FIG. 27 is a diagram showing a specific example of the electrolytic copper plating process. The wiring layer 125 and the vias 126 are not arranged in the area of ​​the reinforcing insulating layer 123 where the electronic component 130 is to be accommodated. In the example of FIG. 27, the electronic component 130 is to be accommodated in the area near the center of the reinforcing insulating layer 123, so the wiring layer 125 and the vias 126 are not arranged in this area.

[0058] After the wiring layer 125 and the vias 126 are formed by electrolytic copper plating, the resist layer 161 is removed (step S136), for example, as shown in Fig. 28. Fig. 28 is a diagram showing a specific example of the resist layer removing step. To remove the resist layer 161, for example, caustic soda or an amine-based alkaline stripping solution is used.

[0059] After the resist layer 161 is removed, unnecessary portions of the seed layer 123b are removed by flash etching (step S137). Specifically, the seed layer 123b exposed without contacting the wiring layer 125 and the vias 126 is removed, and the reinforcing insulating layer 123 is exposed except for the portions contacting the wiring layer 125 and the vias 126, as shown in FIG. 29. FIG. 29 is a diagram showing a specific example of the seed layer removal step. Note that the seed layer 123b in contact with the wiring layer 125 and the vias 126 remains even after the flash etching, but is not shown in FIG. 29.

[0060] When the seed layer 123b is removed, a cavity is formed in a region of the reinforcing insulating layer 123 where the electronic component 130 is to be accommodated (step S138). Specifically, as shown in FIG. 30, the reinforcing insulating layer 123 is cut toward the lower surface 110b of the first wiring structure 110 to form the cavity 170. FIG. 30 is a diagram showing a specific example of the cavity formation step. The cavity formation step can be achieved by performing laser processing using, for example, a CO2 laser. The reinforcing insulating layer 123 is cut down to the lower surface 110b of the first wiring structure 110, so that the lower surface 110b of the first wiring structure 110 is exposed at the bottom of the cavity 170.

[0061] Then, electronic component 130 is placed in cavity 170 (step S139). Specifically, for example, as shown in Fig. 31, electronic component 130 is temporarily adhered onto lower surface 110b of first wiring structure 110 in cavity 170 with a semi-cured adhesive (not shown). Fig. 31 is a diagram showing a specific example of the electronic component placement step.

[0062] When electronic component 130 is placed in cavity 170, filling resin 135 is filled into cavity 170 to embed electronic component 130 (step S140). That is, for example, as shown in FIG. 32, cavity 170 is filled with filling resin 135, and filling resin layer 124 extending above electronic component 130 is formed. As a result, electronic component 130 is embedded in reinforcing insulating layer 123. FIG. 32 is a diagram showing a specific example of the electronic component embedding step. When cavity 170 is filled with filling resin 135 and filling resin layer 124 is formed, these resins are thermally cured. At the same time, the adhesive that temporarily bonds electronic component 130 is also thermally cured, and electronic component 130 is fixed onto lower surface 110b of first wiring structure 110 in cavity 170. By fixing electronic component 130 onto lower surface 110b of first wiring structure 110, heat generated from electronic component 130 is conducted through wiring layer 116 of first wiring structure 110 and efficiently dissipated to the outside of first wiring structure 110.

[0063] Then, via holes are formed in the filled resin layer 124 (step S141). Specifically, as shown in Fig. 33, for example, via hole 124a is formed which penetrates the filled resin layer 124 and exposes the wiring layer 125 on the surface of the reinforcing insulating layer 123, and via hole 124b is formed which penetrates the filled resin layer 124 and exposes the electrode 131 of the electronic component 130. Fig. 33 is a diagram showing an example of the via hole forming step. The via holes 124a and 124b can be formed by, for example, laser processing.

[0064] At the positions where the via holes 124a, 124b are formed, the electrode pads 121 and the wiring 127 are formed on the surface of the filled resin layer 124 (step S142). The electrode pads 121 and the wiring 127 are formed, for example, by SAP (Semi Additive Process). Vias 122, 128 are formed together with the electrode pads 121 and the wiring 127, and the electrode pads 121 or the wiring 127 on the surface of the filled resin layer 124 are connected to the wiring layer 125 on the surface of the reinforcing insulating layer 123 or the electrodes 131 of the electronic components 130. This completes the second wiring structure 120 in which the electronic components 130 are embedded.

[0065] Next, various modified examples of the embodiment will be described with reference to Figures 34 to 43. In the various modified examples described below, the same parts as those in the embodiment will be denoted by the same reference numerals, and duplicated explanations may be omitted.

[0066] 34 is a diagram showing a configuration of a first wiring board 100 according to Modification 1 of the embodiment. In first wiring board 100 according to Modification 1, the fixing manner of electronic component 130 embedded in reinforcing insulating layer 123 is different from that of the above-described embodiment.

[0067] Specifically, in Modification 1, the cavity of reinforcing insulating layer 123 does not extend all the way to lower surface 110b of first wiring structure 110, and the bottom surface of the cavity is formed by reinforcing insulating layer 123. Electronic component 130 is fixed onto reinforcing insulating layer 123 that forms the bottom surface of the cavity.

[0068] In the first modification, electronic component 130 is fixed onto reinforcing insulating layer 123 that forms the bottom surface of the cavity, so that reinforcing insulating layer 123 can be interposed between electronic component 130 and lower surface 110b of first wiring structure 110. This makes it possible to further improve the resistance of electronic component 130 to stress applied thereto, and further reduce the possibility of damage to electronic component 130.

[0069] Next, a method for manufacturing first wiring board 100 according to Modification 1 of the embodiment will be specifically described with reference to Figs. 35 and 36. In the method for manufacturing first wiring board 100 according to Modification 1, the cavity forming step (step S138 in Fig. 22) and the electronic component placement step (step S139 in Fig. 22) in the process of forming second wiring structure 120 are different from those of the embodiment. Fig. 35 is a diagram showing a specific example of the cavity forming step. Fig. 36 is a diagram showing a specific example of the electronic component placement step.

[0070] When seed layer 123b is removed, a cavity is formed in a region of reinforcing insulating layer 123 where electronic component 130 is to be accommodated. Specifically, as shown in Fig. 35, reinforcing insulating layer 123 is cut out to a position that does not reach lower surface 110b of first wiring structure 110, to form cavity 170. The bottom surface of cavity 170 is formed by reinforcing insulating layer 123.

[0071] Then, electronic component 130 is placed in cavity 170. Specifically, for example, as shown in FIG. 36, electronic component 130 is temporarily bonded onto reinforcing insulating layer 123 located on the bottom surface of cavity 170 by a semi-cured adhesive (not shown). Then, in a later electronic component embedding step, the adhesive for temporarily bonding electronic component 130 is also thermally cured at the same time as filling resin layer 124 is thermally cured, and electronic component 130 is fixed onto reinforcing insulating layer 123 located on the bottom surface of cavity 170. By fixing electronic component 130 onto reinforcing insulating layer 123 located on the bottom surface of cavity 170, reinforcing insulating layer 123 is interposed between electronic component 130 and lower surface 110b of first wiring structure 110, and resistance to stress applied to electronic component 130 is further improved. Thereafter, steps from step 140 in FIG. 22 onwards are performed, and first wiring board 100 of modified example 1 is completed.

[0072] 37 is a diagram showing a configuration of first wiring board 100 according to Modification 2 of the embodiment. First wiring board 100 according to Modification 2 of the embodiment differs from Modification 1 in that a plurality of electronic components 130 are embedded in second wiring structure 120.

[0073] Specifically, in Modification 2, a plurality of cavities 170 are formed in reinforcing insulating layer 123 of second wiring structure 120, and a plurality of electronic components 130 are located in each of the cavities 170. Then, filled resin layer 124 of second wiring structure 120 fills the plurality of cavities 170 and covers the plurality of electronic components 130. In this way, the plurality of electronic components 130 are embedded in second wiring structure 120.

[0074] Thus, in variant example 2, multiple electronic components 130 are embedded in the second wiring structure 120, so that noise from the semiconductor element can be efficiently reduced in the multiple electronic components 130, thereby further suppressing the diffusion of noise from the semiconductor element.

[0075] 38 is a diagram showing a configuration of a first wiring board 100 according to Modification 3 of the embodiment. In first wiring board 100 according to Modification 3, the fixing manner of electronic component 130 embedded in reinforcing insulating layer 123 is different from that of the above-described embodiment.

[0076] Specifically, in Modification 3, pad 118 is formed on wiring layer 116, which is the outermost layer of first wiring structure 110, and the cavity of reinforcing insulating layer 123 reaches pad 118. Pad 118 can be formed by using a resist having an opening corresponding to the shape of pad 118 when forming wiring layer 116. Electronic component 130 is then fixed onto pad 118 exposed from the bottom surface of the cavity of reinforcing insulating layer 123.

[0077] In variant example 3, electronic component 130 is fixed onto pad 118 of wiring layer 116, so that heat generated from electronic component 130 is conducted through wiring layer 116 of first wiring structure 110 and efficiently dissipated to the outside of first wiring structure 110.

[0078] Next, a method for manufacturing first wiring substrate 100 according to Modification 3 of the embodiment will be specifically described with reference to Figs. 39 and 40. In the method for manufacturing first wiring substrate 100 according to Modification 3, the cavity forming step (step S138 in Fig. 22) and the electronic component placement step (step S139 in Fig. 22) in the step of forming second wiring structure 120 are different from those of the embodiment. Fig. 39 is a diagram showing a specific example of the cavity forming step. Fig. 40 is a diagram showing a specific example of the electronic component placement step. Note that in Fig. 39, pads 118 are formed on wiring layer 116, which is the outermost layer of first wiring structure 110, before the step of forming the cavity is performed.

[0079] When the seed layer 123b is removed, a cavity is formed in the area of ​​the reinforcing insulating layer 123 where the electronic component 130 is to be accommodated. Specifically, as shown in FIG. 39, the reinforcing insulating layer 123 is cut out up to the pad 118 to form the cavity 170. The cavity forming step can be realized by performing laser processing using, for example, a CO2 laser. In the laser processing, the pad 118 functions as a stop layer for the laser light, so that the cavity 170 having a flat bottom surface is obtained. The pad 118 is exposed at the bottom surface of the cavity 170. The pad 118 has a planar shape (e.g., a rectangle) that is larger in size than the planar shape of the bottom surface of the cavity 170. Therefore, the side surface of the pad 118 is located outside the side surface of the cavity 170.

[0080] Then, electronic component 130 is placed in cavity 170. Specifically, for example, as shown in FIG. 40, electronic component 130 is temporarily attached to pad 118 located on the bottom surface of cavity 170 by a semi-cured adhesive (not shown). Then, in a later electronic component embedding step, the adhesive for temporarily attaching electronic component 130 is thermally cured at the same time as filling resin layer 124 is thermally cured, and electronic component 130 is fixed onto pad 118 located on the bottom surface of cavity 170. By fixing electronic component 130 onto pad 118 of wiring layer 116, heat generated from electronic component 130 is conducted through wiring layer 116 of first wiring structure 110 and efficiently dissipated to the outside of first wiring structure 110. Thereafter, the steps from step 140 in FIG. 22 onwards are performed, and first wiring board 100 of modification 3 is completed.

[0081] 41 is a diagram showing a configuration of a first wiring board 100 according to Modification 4 of the embodiment. In first wiring board 100 according to Modification 4, the structure of the cavity in reinforcing insulating layer 123 and the structure of filled resin layer 124 are different from those in the above-described embodiment.

[0082] Specifically, in the fourth modification, the side surface of the cavity of the reinforcing insulating layer 123 has a recess 171 at a position adjacent to the bottom surface of the cavity. A part of the filled resin layer 124 is stored in the recess 171 of the cavity.

[0083] In the fourth modification, a portion of the filled resin layer 124 is stored in the recess 171 of the cavity, and thus the adhesion between the filled resin layer 124 and the cavity of the reinforcing insulating layer 123 can be improved by the anchor effect.

[0084] Next, a manufacturing method for manufacturing the first wiring board 100 according to the fourth modification of the embodiment will be specifically described with reference to Figs. 42 and 43. The manufacturing method for manufacturing the first wiring board 100 according to the fourth modification differs from the third modification in that it includes a recessed portion forming step between the cavity forming step and the electronic component arranging step. Furthermore, the manufacturing method for manufacturing the first wiring board 100 according to the fourth modification differs from the third modification in the electronic component arranging step. Fig. 42 is a diagram showing a specific example of the recessed portion forming step. Fig. 43 is a diagram showing a specific example of the electronic component arranging step.

[0085] When cavity 170 reaching pad 118 is formed in reinforcing insulating layer 123 (see FIG. 39), recess 171 is formed on the side surface of cavity 170. Specifically, pad 118 is removed by etching, thereby forming recess 171 on the side surface of cavity 170, as shown in FIG. 42, for example. Underside 110b of first wiring structure 110 is exposed at the bottom surface of cavity 170.

[0086] Then, electronic component 130 is placed in cavity 170. Specifically, for example, as shown in FIG. 43, electronic component 130 is temporarily attached to lower surface 110b of first wiring structure 110 in cavity 170 by a semi-cured adhesive (not shown). Then, in a subsequent electronic component embedding step, the adhesive for temporarily attaching electronic component 130 is also thermally cured at the same time as filling resin layer 124 is thermally cured, and electronic component 130 is fixed on lower surface 110b of first wiring structure 110 in cavity 170. Also, in the electronic component embedding step, a part of filling resin layer 124 is stored in recess 171 of the cavity, so that the adhesion between filling resin layer 124 and cavity 170 of reinforcing insulating layer 123 can be improved by an anchor effect. Thereafter, the steps from step 140 in FIG. 22 onwards are performed, and first wiring board 100 of modification 4 is completed.

[0087] As described above, the wiring board (for example, first wiring board 100) according to the embodiment has a first wiring structure (for example, first wiring structure 110) and a second wiring structure (for example, second wiring structure 120). The first wiring structure has a mounting surface (for example, upper surface 110a) for mounting a semiconductor element and a back surface (for example, lower surface 110b) opposite to the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure has a reinforcing insulating layer (for example, reinforcing insulating layer 123), an electronic component (for example, electronic component 130), and a filling resin layer (for example, filling resin layer 124). The reinforcing insulating layer is formed on the back surface of the first wiring structure. The electronic component is located in a cavity (for example, cavity 170) formed by cutting out the reinforcing insulating layer toward the back surface of the first wiring structure. The filling resin layer fills the cavity and covers the electronic component. This makes it possible to suppress the diffusion of noise from the semiconductor element. [Explanation of symbols]

[0088] 100 First wiring board 110 1st wiring structure 110a top side 110b Bottom side 112 1st thin film layer 113 Second thin film layer 114 Third thin film layer 115 4th thin film layer 116 Wiring layer 120 Second wiring structure 123 Reinforced insulation layer 124 Filled resin layer 130 Electronic Components 170 Cavity 200 Second wiring board 300 Glass support

Claims

1. a first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; a second wiring structure formed on the back surface of the first wiring structure; having The second wiring structure includes: a reinforcing insulating layer formed on the back surface of the first wiring structure; a cavity formed by cutting the reinforcing insulating layer toward the rear surface of the first wiring structure; an electronic component located within the cavity; a filled resin layer that fills the cavity and covers the electronic component; A wiring board comprising:

2. The electronic component includes: The wiring board according to claim 1, characterized in that the reinforcing insulating layer is positioned within the cavity formed by cutting out the reinforcing insulating layer to the rear surface of the first wiring structure, and is fixed onto the rear surface of the first wiring structure.

3. The electronic component includes: The wiring board according to claim 1, characterized in that the wiring board is positioned within the cavity formed by cutting the reinforcing insulating layer to a position that does not reach the back surface of the first wiring structure, and is fixed onto the reinforcing insulating layer that forms the bottom surface of the cavity.

4. The second wiring structure includes: A plurality of the electronic components are included, The plurality of electronic components include the reinforcing insulating layer is cut out toward the rear surface of the first wiring structure to form a plurality of cavities, The filled resin layer is 2. The wiring board according to claim 1, wherein the cavity is filled with a resin to cover the electronic components.

5. The thickness of the second wiring structure is 2. The wiring board according to claim 1, wherein the thickness of the first wiring structure is equal to or greater than the thickness of the second wiring structure.

6. Further comprising a support, The first wiring structure includes:

2. The wiring board according to claim 1, wherein the wiring board is formed on the support body with the mounting surface facing the support body.

7. A laminated wiring board in which a wiring board is laminated on another wiring board, The wiring board includes: a first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; a second wiring structure formed on the back surface of the first wiring structure; having The second wiring structure includes: a reinforcing insulating layer formed on the back surface of the first wiring structure; a cavity formed by cutting the reinforcing insulating layer toward the rear surface of the first wiring structure; an electronic component located within the cavity; a filled resin layer that fills the cavity and covers the electronic component; A laminated wiring board comprising:

8. an electrode pad is provided on an opposite surface of the filled resin layer opposite to the first wiring structure; Another electrode pad is provided on a surface of the other wiring board, 8. The laminated wiring board according to claim 7, wherein the electrode pad and the other electrode pad are electrically connected, and the wiring board is laminated on the other wiring board.

9. forming a first wiring structure having a mounting surface for a semiconductor element and a back surface opposite to the mounting surface; forming a second wiring structure on the back surface of the first wiring structure; having The step of forming the second wiring structure includes: forming a reinforcing insulating layer on the rear surface of the first wiring structure; The reinforcing insulating layer is cut out toward the rear surface of the first wiring structure to form a cavity; Placing an electronic component in the formed cavity; Filling the cavity with a filling resin that covers the electronic components.

4. A method for manufacturing a wiring board comprising the steps of:

10. In the step of forming the first wiring structure, Prepare a support, 10. The method for manufacturing a wiring board according to claim 9, wherein the first wiring structure is formed on the support body so that the mounting surface is in contact with the support body.

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