Storage system

Abstract

To reduce power consumption in a storage system.SOLUTION: Each of a plurality of controllers of a storage system includes: a plurality of first power feeding areas of which electric power is independently controllable; and a processor which processes an input / output request and a memory which is connected to the processor, the processor and the memory being provided in each first power feeding area. Each of the plurality of controllers is configured as being switchable between a first operating mode in which all the first power feeding areas provided to the controller are made in a working state and a second operating mode in which one or some of the first power feeding areas provided to the controller are made in a stopped state and other first power feeding areas are made in the working state.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to power supply control of a storage system. [Background technology]

[0002] In a storage system that receives data I / O requests from a host computer and stores and outputs data, a processor and memory are installed in the controller for internal control. This processor and memory operate at high speeds to achieve high processing performance, and as a result, consume a lot of power. On the other hand, in a storage system, there are cases where data I / O requests from the host computer are not received regularly. Even when there are no data I / O requests from the host computer, that is, when the storage system is on standby, the controller processor continues to operate because it detects when an I / O request arrives.

[0003] Furthermore, in a storage system, if a controller stops processing due to a failure, data input / output to / from the host computer may become impossible, or data received from the host computer may be lost, so two or more controllers are provided for controller redundancy. That is, if one of two or more controllers stops processing due to a failure, the remaining controller takes over the processing, and data received from the host computer is duplicated and stored by two or more controllers, so that data input / output to / from the host computer can continue, and data received from the host computer can be prevented from being lost.

[0004] There is also a demand for reducing power consumption in such storage systems. In particular, in a storage system, even when the system is in standby mode and there is no data input / output request from the host computer, the controller processor continues to operate and continues to consume power, so there is a demand for reducing this standby power consumption as much as possible depending on the presence or absence of data input / output requests from the host computer.

[0005] In such a case, if the storage system has three or more controllers, redundancy can be maintained by keeping two of the controllers in operation, so it is conceivable that the controllers exceeding two will stop processing and be powered off. Patent Document 1 is an example of such a case.

[0006] In Patent Document 1, power is turned off on a controller-by-controller basis, so in a storage system with a maximum of two controllers, turning off the power to one of the controllers would result in a loss of redundancy, and so the method cannot be applied. In other words, if only one controller continues to operate, input and output of data to and from the host computer cannot be continued if that controller stops processing due to a fault, and data received from the host computer may be lost. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-102409 A Summary of the Invention [Problem to be solved by the invention]

[0008] The problem to be solved by the present invention is to control the power supply of processors and memories in a storage system and reduce power consumption without compromising redundancy. [Means for solving the problem]

[0009] One aspect of the present invention is a storage system that stores or outputs data in response to a data input / output request from a host device, the storage system including multiple controllers, each of which includes multiple first power supply domains that can be independently power controlled, a processor provided in each of the first power supply domains that processes the input / output requests, and a memory connected to the processor, the multiple controllers being configured to be switchable between a first operating mode in which all of the first power supply domains provided in the controller are in an operating state, and a second operating mode in which some of the first power supply domains provided in the controller are stopped and the other first power supply domains are in an operating state.

[0010] One aspect of the present invention is a storage system that stores or outputs data in response to a data input / output request from a host device, the storage system including multiple controllers, a first controller of the multiple controllers includes multiple power supply domains that can be separately power controlled, the first power supply domain of the multiple power supply domains includes a first processor and a first memory connected to the first processor, a second power supply domain of the multiple power supply domains includes a second processor and a second memory connected to the second processor, the first processor consumes more power than the second processor, a second controller of the multiple controllers includes multiple power supply domains that can be separately power controlled, and a third power supply domain of the multiple power supply domains of the second controller includes a third processor. a third processor and a third memory connected to the third processor, a fourth power supply domain of the second controller includes a fourth processor and a fourth memory connected to the fourth processor, the third processor consumes more power than the fourth processor, the storage system has a first operation mode and a second operation mode, the first operation mode puts a power supply of the first power supply domain in an operating state and a power supply of the second power supply domain in a stopped state, the power supply of the third power supply domain in an operating state and a power supply of the fourth power supply domain in a stopped state, and the second operation mode puts the power supply of the first power supply domain in a stopped state and a power supply of the second power supply domain in an operating state, the power supply of the third power supply domain in a stopped state and a power supply of the fourth power supply domain in an operating state. Effect of the Invention

[0011] One aspect of the present invention is the ability to reduce power consumption in a storage system. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 shows an example of the configuration of a storage system. [Diagram 2] FIG. 2 is a first example of a flowchart of power supply control. [Diagram 3] FIG. 3 shows an example of a first processing sequence for write request processing. [Figure 4] FIG. 4 shows an example of a first processing sequence for processing a read request. [Diagram 5] FIG. 5 is a second example of a flowchart of power supply control. [Figure 6] FIG. 6 is an example of a second processing sequence for write request processing. [Figure 7] FIG. 7 shows an example of a second processing sequence for processing a read request. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiments will be described with reference to the drawings. Note that the embodiments are merely examples for realizing the present invention, and do not limit the technical scope of the present invention, and all of the combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0014] In the following description, various types of information may be described using the expression "xxx table", but the various types of information may be expressed in a data structure other than a table. To indicate that it does not depend on the data structure, the "xxx table" may be called "xxx information". Also, in the following description, numbers are used as identification information for elements, but other types of identification information (e.g., names, identifiers) may be used.

[0015] In addition, in the following description, when describing elements of the same type without distinguishing between them, common symbols (or reference signs) may be used, and when describing elements of the same type with distinction between them, reference signs (or element IDs) may be used.

[0016] The program is executed by a processor (e.g., a CPU (Central Processing Unit)) included in the storage controller to perform a defined process using a storage resource (e.g., a main memory) and / or a communication interface device as appropriate, so the subject of the process may be the storage controller or the processor. The storage controller may also include a hardware circuit that performs some or all of the process. The computer program may be installed from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium. EXAMPLES

[0017] A first embodiment will be described with reference to Fig. 1, Fig. 2, Fig. 3, and Fig. 4. Fig. 1 is an example of the configuration of a storage system according to the first embodiment. In Fig. 1, a storage system 1 according to the first embodiment includes two controllers 110a and 110b, and eight storage devices 107a to 107h. The controllers 110a and 110b are each removable from the storage system 1. This allows easy replacement of the storage controllers.

[0018] The controller 110a includes two protocol chips 101a and 101b, one front-end switch 102a, two processors 104a and 104b, two memories 105a and 105b, and one back-end switch 106a. The back-end switch 106a is a storage device connection unit.

[0019] Similarly, the controller 110b includes two protocol chips 101c and 101d, one front-end switch 102b, two processors 104c and 104d, two memories 105c and 105d, and one back-end switch 106b. The back-end switch 106b is a storage device connection unit.

[0020] The two controllers 110a and 110b are connected by an inter-controller path 103. In Fig. 1, the inter-controller path 103 connects the front-end switch 102a of the controller 110a and the front-end switch 102b of the controller 110b.

[0021] The protocol chips 101a to 101d are each connected to a host device (not shown), perform protocol control of communications with the host device, retrieve data input / output requests from the host device, and return responses to data input / output requests to the host device.

[0022] In the storage system 1, one example of a protocol for communication with a host device is Fibre Channel. Another example is iSCSI (internet Small Computer System Interface). Yet another example is NVMe over Fabrice (Non-Volatile Memory express over Fabric).

[0023] FIG. 1 illustrates an example of a configuration in which two controllers 110a and 110b have two protocol chips 101a and 101b, and 101c and 101d, respectively. However, the number of protocol chips 101a to 101d is not limited to two per controller, and may be any number greater than or equal to one.

[0024] The front-end switch 102a connects the protocol chips 101a and 101b to the processors 104a and 104b. The front-end switch 102a sends data I / O requests received by the protocol chips 101a and 101b from a host device (not shown) to either the processor 104a or 104b, and also sends responses to the data I / O requests to the host device returned by either the processor 104a or 104b to the protocol chip 101a or 101b.

[0025] Similarly, the front-end switch 102b connects the protocol chips 101c and 101d to the processors 104c and 104d. The front-end switch 102b sends data I / O requests received by the protocol chips 101c and 101d from a host device (not shown) to either the processor 104c or 104d, and also sends responses to the data I / O requests for the host device returned by either the processor 104c or 104d to the protocol chip 101c or 101d.

[0026] Furthermore, the front-end switches 102a and 102b are connected by an inter-controller path 103. The front-end switches 102a and 102b transmit data sent from the processor 104a or 104b of the controller 110a to the processor 104c or 104d of the controller 110b, and transmit data sent from the processor 104c or 104d of the controller 110b to the processor 104a or 104b of the controller 110a.

[0027] Although FIG. 1 illustrates one front-end switch 102a and one front-end switch 102b for each of the controllers 110a and 110b, the number of front-end switches is not limited to one per controller and may be any number greater than or equal to one.

[0028] The processors 104a to 104d each share the processing of data input / output requests from a host device in the storage system 1. Although two processors 104a and 104b, and 104c and 104d are illustrated in Fig. 1 for two controllers 110a and 110b, respectively, the number of processors is not limited to two for each controller, and may be any number equal to or greater than two.

[0029] Similarly, the memories 105a to 105d store program codes to be executed by the processors 104a to 104d and data to be processed, respectively, and also temporarily store data written from a host device until the data is written to one of the storage devices 107a to 107h.

[0030] At this time, if a processor or memory belonging to any of the controllers, such as processors 104a and 104b, memories 105a and 105b of controller 110a, or processors 104c and 104d, memories 105c and 105d of controller 110b, fails, data written from the host device may be lost from that controller.

[0031] Therefore, when data is written from the host device to memory 105a or 105b of controller 110a, or memory 105c or 105d of controller 110b, a copy of the data is sent to and stored in one of the memories of the other controller. This prevents the data written from the host device from being lost as a whole even if the processor or memory of one of controllers 110a or 110b fails.

[0032] Furthermore, the memories 105a to 105d temporarily store data read from any of the storage devices 107a to 107h until the data is returned to the host device. Such memories 105a to 105d are typically volatile memories such as DRAM (Dynamic Random Access Memory). Although one memory 105a to 105d is illustrated for each of the processors 104a to 104d in FIG. 1, the number of memories per processor is not limited to one and may be any number equal to or greater than one.

[0033] The backend switches 106a and 106b connect the processors 104a to 104d and the storage devices 107a to 107h. At this time, the backend switches 106a and 106b connect the processors 104a to 104d to the storage devices 107a to 107h in accordance with a storage protocol used by the storage devices 107a to 107h for inputting and outputting data.

[0034] A typical example of a storage protocol used by the storage devices 107a to 107h is NVMe (Non-Volatile Memory express). Another example of a storage protocol used by the storage devices 107a to 107h is SAS (Serial Attached Small computer system interface).

[0035] The conversion between the storage protocol used by the storage devices 107a to 107h and the communication with the processors 104a to 104d may be performed by the backend switches 106a and 106b, or may be performed by adding a separate storage protocol processing unit (not shown). Alternatively, the processors 104a to 104d may process the storage protocol by software.

[0036] 1 illustrates two backend switches 106a and 106b, the number of backend switches 106a and 106b is not limited to two and may be any number. If the processors 104a to 104d are configured to process the storage protocol using software, the processors 104a to 104d may be directly connected to the storage devices 107a to 107h without providing the backend switches 106a and 106b.

[0037] The storage devices 107a-107h read or write data in response to a data input / output request sent from the processors 104a-104d via the backend switches 106a or 106b. A typical example of the storage devices 107a-107h is an SSD (Solid State Drive) that uses a flash memory as a storage element. Another example of the storage devices 107a-107h is an HDD (Hard Disk Drive) that uses a magnetic disk as a storage element.

[0038] The storage devices 107a to 107h may be one type of storage device, or multiple types of storage devices may be mixed. Although eight storage devices 107a to 107h are illustrated in Fig. 1, the number of storage devices 107a to 107h is not limited to eight and may be any number. Therefore, the storage devices 107a to 107h do not need to be installed in the storage system 1.

[0039] In this case, a storage system other than the host device may be connected to the protocol chips 101a to 101d, and a data read or write request may be sent from the processors 104a to 104d via the front-end switch 102a or 102b from the protocol chips 101a to 101d to the other connected storage system, so that the data may be read or written.

[0040] 1, the controller 110a includes a power supply area 120a, power supply areas 121a and 121b, and a power supply area 122a. The power supply area 120a includes protocol chips 101a and 101b and a front-end switch 102a, and is controlled by a power supply control unit 130a to turn on or off the power. The protocol chips 101a and 101b are connected to a host device and communicate with the host device, so that the power supply control unit 130a controls the power supply to turn on or off depending on whether or not the host device is communicating with the protocol chips, and controls the power supply not to stop when the host device is communicating with the protocol chips. Note that the power supply area in this embodiment is an area where the power supply can be independently controlled to be turned on or off, and at least two or more power supplies are provided in the controller.

[0041] Various electronic devices constituting the controller, such as a processor and memory, are provided in one of the power supply domains, and the supply and stop of their operating power is controlled on a power supply domain basis. A power supply domain is not limited to being defined as a physically defined partition, but may be defined as a group of electronic devices whose supply of operating power is controlled collectively on and off. In either definition, the electronic devices in the controller belong exclusively to one of the power supply domains, and power is supplied or stopped based on the power supply domain unit. The number of electronic devices provided in a power supply domain is arbitrary and may be one or more.

[0042] A specific embodiment of the multiple power supply areas is, for example, a so-called electronic circuit board, on which multiple independent power wirings are installed, each electronic component is connected to one of the power wirings, and each independent power wiring has a power terminal that can be connected / disconnected independently. In such an embodiment, for example, the power terminals may be regarded as a power control unit. Note that when the power supply areas are constructed in the manner described in the specific embodiment, each power supply area is defined as a configuration that cannot be removed from the controller.

[0043] The power supply domain 121a includes a processor 104a and a memory 105a, and is controlled by a power supply control unit 131a so that the power supply is turned on or off. Similarly, the power supply domain 121b includes a processor 104b and a memory 105b, and is controlled by a power supply control unit 131b so that the power supply is turned on or off. The power supply domain 122a includes a backend switch 106a, and is controlled by a power supply control unit 132a so that the power supply is turned on or off.

[0044] Similarly, the controller 110b includes a power domain 120b, power domains 121c and 121d, and a power domain 122b. The controller 110b is configured so that each power domain cannot be removed from the controller 110a. The power domain 120b includes protocol chips 101c and 101d and a front-end switch 102b, and is controlled by a power control unit 130b to turn on or off the power.

[0045] The power supply domain 121c includes a processor 104c and a memory 105c, and is controlled by a power supply control unit 131c to turn on or off the power supply. Similarly, the power supply domain 121d includes a processor 104d and a memory 105d, and is controlled by a power supply control unit 131d to turn on or off the power supply. The power supply domain 122b includes a back-end switch 106b, and is controlled by a power supply control unit 132b to turn on or off the power supply.

[0046] The storage system 1 of the first embodiment has a plurality of operation modes including a first operation mode and a second operation mode. In the first operation mode, the power supplies of all power supply domains are in an operating state, and in the second operation mode, the power supplies of some of the power supply domains are in an operating state and the power supplies of the other some of the power supply domains are in a stopped state.

[0047] In the first embodiment, when the system is started up, the power supplies of all the power supply domains 120a, 120b, 121a to 121d, 122a, and 122b are turned on and all the processors 104a to 104d are made to perform processing. This is the first operation mode.

[0048] Thereafter, depending on the frequency of I / O requests from the host device, the controller 110a stops the processing of one of the processors 104a or 104b, and the power supply of the power supply domain 121a or 121b to which the stopped processor belongs is stopped. The controller 110b also stops the processing of one of the processors 104c or 104d, and the power supply of one of the power supply domains 121c or 121d to which the stopped processor belongs is stopped. This is the second operation mode. Therefore, when the storage system 1 operates in the second operation mode, some of the multiple processors included in the controller are stopped, and the power supply of the power supply domain to which the stopped processor belongs is stopped. Note that in order to process I / O requests, at least one processor in the controller continues to operate, and the power supply of the power supply domain to which the continuously operating processor belongs is in an operating state.

[0049] Further thereafter, depending on the frequency of input / output from the host device, the stopped power domain 121a or 121b, and power domain 121c or 121d are put back into operation, and the stopped processor 104a or 104b, and processor 104c or 104d are restarted. This is the first operation mode. In other words, the storage system 1 changes from the first operation mode to the second operation mode, and then changes back to the first operation mode. This will be explained with reference to FIG. 2. FIG. 2 is a flowchart of an example of power supply control.

[0050] 201: When the storage system 1 is started up, the power supplies of all the power supply domains 120a, 120b, 121a to 121d, 122a, and 122b are in operation.

[0051] 202: After that, the storage system 1 observes the frequency of I / O requests from the host device.

[0052] 203: If the condition that the frequency is equal to or less than a preset value (threshold) in a preset period is not satisfied (203: NO), the flow returns to step 202. Therefore, the observation of the frequency of input / output requests shown in steps 202 and 203 and the judgment of the observation result are periodically performed.

[0053] 204: If the frequency is equal to or lower than the predetermined value for a predetermined period of time (203: YES), the storage system 1 decides to stop power to the power domains 121a and 121c (stop processing of the processors 104a and 104c). That is, when the storage system 1 in this embodiment is started up, it starts operating in the first operation mode. Next, when the storage system 1 detects that the frequency of I / O requests is lower than an arbitrarily determined standard while operating in the first operation mode, it decides to transition to the second operation mode.

[0054] 205: Next, the processor 104a hands over the process to the processor 104b, and the processor 104c hands over the process to the processor 104d.

[0055] 206: Next, the processors 104a and 104c stop their processing.

[0056] 207: Furthermore, the power supply control unit 131a stops the power supply to the power supply domain 121a, and the power supply control unit 131c stops the power supply to the power supply domain 121c. Therefore, in step 203, the power supply to the processor 104a and the memory 105a installed in the power supply domain 121a is stopped, and the power supply to the processor 104c and the memory 105c installed in the power supply domain 121c is stopped.

[0057] 208: After the storage system 1 transitions to the second operation mode, it subsequently observes the frequency of I / O requests from the host device.

[0058] 209: If the frequency is smaller than a preset value (threshold) in a preset period (209: NO), the flow returns to 208. Therefore, the observation of the frequency of input / output requests shown in steps 208 and 209 and the judgment of the observation result are periodically performed. Note that the preset period in this step may be the same as or different from the preset period in step 203.

[0059] The predetermined value in this step is not particularly specified to be larger or smaller than the predetermined value in step 203. However, if the predetermined value in step 203 is larger than the predetermined value in this step, even if the condition in step 203 is satisfied (203: YES), steps 204 to 207 are executed, and the power supply to the power supply domains 121a and 121c is stopped, the frequency of I / O requests from the host device in this step 209 may become larger than the predetermined value in this step, and the flow may not return to step 208 but may immediately proceed to the next step 210.

[0060] Therefore, it is desirable to set the predetermined value in step 203 smaller than the predetermined value in step 209. That is, by appropriately setting the predetermined value (203) related to switching from the first mode to the second mode and the predetermined value (208) related to switching from the second mode to the first mode, it is possible to prevent unnecessary switching operations from being performed.

[0061] 210: If the frequency is equal to or greater than the predetermined value in the predetermined period (209: YES), the power supply control unit 131a operates the power supply in the power supply domain 121a, and the power supply control unit 131c operates the power supply in the power supply domain 121c. Thus, in step 210, power supply to the processor 104a and memory 105a installed in the power supply domain 121a is started, and power supply to the processor 104c and memory 105c installed in the power supply domain 121c is started.

[0062] 211: Furthermore, the processors 104a and 104c resume their respective processing.

[0063] 212: Thereafter, processor 104b reallocates processing for the I / O request to processor 104a, and processor 104d reallocates processing to processor 104c.

[0064] The observation of the frequency of I / O requests from the host device in 202 and 208 may be performed by an operating processor among the processors 104a to 104d, or may be performed by a separate dedicated processor for observation. As a method of observation, for example, a function such as a timer counter for measuring time may be provided in the processors 104a to 104d or the dedicated processor for observation, and the observation may be realized by using the time measurement function to count whether an I / O request arrives from the host device within a certain period of time.

[0065] The object of observation may be other values ​​related to the frequency of I / O requests from the host device, in addition to observing the frequency of I / O requests from the host device. For example, the frequency of I / O requests from the host device may be substituted by a processor operation rate defined as the ratio of the time spent in an operating processor among the processors 104a to 104d to the time spent processing I / O requests from the host device or garbage collection related to the I / O requests, to the time spent waiting for I / O requests from the host device, or the time spent in the storage system 1 or the storage devices 107a to 107d for self-inspection and repair processing, or rebuild processing in the case of a RAID (Redundant Array of Independent Disks) configuration.

[0066] In the following description, when the frequency of I / O requests from a host device is substituted with a separately defined processor operating rate or the like, the frequency of I / O requests from the host device is to be read as the separately defined processor operating rate or the like.

[0067] The decision to shut down power to power domains 121a and 121c of 204 may be made by any one or more of processors 104a to 104d communicating with each other to exchange or tally up the observation results of the frequency of I / O requests from each host device, or a separate dedicated processor may be provided for the decision processing and tally up the observation results of the frequency of I / O requests from the host devices.

[0068] When the processors 104a to 104d are connected to each other, or when a dedicated processor for the decision process is provided, the observation results of the frequency of I / O requests from the host device may be communicated between the processors 104a to 104d and the host device by providing a communication means via the front-end switch 102a or 102b or the back-end switch 106a or 106b, or by providing a dedicated communication signal line. Alternatively, when a dedicated processor for observing the frequency of I / O requests from the host device is provided, the processor may also perform the decision process.

[0069] Next, an example of processing a write request from a host device will be described. Fig. 3 shows a sequence diagram of an example of write request processing. Note that the following will be an example of the operation when a write request from a host device is sent to controller 110a. However, the operation shown below can also be applied when controller 110b receives a write request from a host device by changing the relationship between the protocol switch, processor, memory, front-end switch, and back-end switch.

[0070] 301: The protocol chip 101a sends a write request received from the host device to the memory 105a of the processor 104a.

[0071] 302: The processor 104a retrieves the write request and write data from the host device from the memory 105a.

[0072] 303: The processor 104a sends the write data to the memory 105c of the processor 104c for duplication.

[0073] 304: The processor 104a sends a notification instruction of the completion of the write request to the host device to the protocol chip 101a. Upon receiving the notification instruction of the completion of the write request to the host device, the protocol chip 101a notifies the host device of the completion of the write request.

[0074] 305: The processor 104a sends a write command to the storage device 107a.

[0075] 306: The storage device 107a sends a request for write data to the processor 104a.

[0076] 307: The processor 104a retrieves the write data from the memory 105a. This retrieval may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically retrieves the write data from the memory 105a in response to a write data request from the storage device 107a. Alternatively, this may be performed by software executed by the processor 104a.

[0077] 308: The processor 104a returns the write data to the storage device 107a. This return may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically returns the write data retrieved from the memory 105a in response to a write data request from the storage device 107a. Alternatively, this may be performed by software executed by the processor 104a.

[0078] 309: The storage device 107a notifies the processor 104a that the write data has been received and that the data has been stored.

[0079] 310-318: Steps 310-318 will be described by replacing the processor 104a with the processor 104b, the processor 104c with the processor 104d, the memory 105a with the memory 105b, and the memory 105c with the memory 105d in steps 301-309.

[0080] Next, when a write request from the host device is sent to the controller 110a and it is decided that the controllers 110a and 110b will transition from the first operation mode to the second operation mode, the processes executed for both the controllers 110a and 110b will be explained in 319 to 336. Note that the processor and memory to be stopped are not limited to the examples shown below, and may be the other processor and memory in each controller. 319-322: These steps are similar to steps 301-304.

[0081] 323: Any one of the processors decides to stop the processor 104a and the memory 105a. That is, it is decided to stop the power supply to the power supply domain 121a. That is, 323 indicates that the controller 110a transitions from the first operation mode to the second mode, and at that time, it is decided that the processor 104a and the memory 105a are stopped.

[0082] 324: Any one of the processors decides to stop the processor 104c and the memory 105c. That is, it is decided to stop the power supply to the power supply domain 121c. That is, 324 indicates that the controller 110b transitions from the first operation mode to the second mode, and at that time, it is decided that the processor 104c and the memory 105c are stopped.

[0083] 325: The processor 104a retrieves the write data from the memory 105a in order to take over the write data.

[0084] 326: The processor 104a sends the write data to the memory 105b of the processor 104b for write data transfer.

[0085] 327: The processor 104c retrieves the write data from the memory 105c in order to take over the write data.

[0086] 328: The processor 104c sends the write data to the memory 105d of the processor 104d for takeover of the write data.

[0087] 329: The processor 104a and the memory 105a are shut down. That is, the power supply control unit 131a shuts down the power supply to the power supply domain 121a.

[0088] 330: The processor 104c and the memory 105c are stopped. That is, the power supply control unit 131c stops the power supply to the power supply domain 121c.

[0089] 331: The processor 104b checks the write data in the memory 105b taken over from the processor 104a, that is, checks the write request from the host.

[0090] 332-336: Steps 332 to 336 are similar to steps 314-318.

[0091] As a result, when all power supply domains are operating, with respect to a write request (a request to store data) from a host device, either the processor 104a or 104b of the controller 110a can receive and process the write request.

[0092] When the power supply domains 121a and 121c are stopped, that is, when the processors 104a and 104c are stopped, the processor 104a can transfer the write request received from the host to the processor 104b. Furthermore, a copy of the write data from the host device that was sent from the memory 105a of the processor 104a of the controller 110a to the memory 105c of the processor 104c of the controller 110b and stored therein can also be transferred from the memory 105c of the processor 104c to the memory 105d of the processor 104d. This makes it possible to prevent the write data from the host device from being lost even if some kind of failure occurs in the processor 104b or memory 105b that has taken over the write data from the host device in the controller 110a.

[0093] In the write request processing sequence described above, a case has been shown in which the first operation mode is switched to the second operation mode while the controller 110a is receiving a write request. Therefore, when a new write request is sent from the host device after the takeover described above is completed, the processor and memory included in the power supply domain that continues to operate execute the operations shown in 301 to 309.

[0094] Next, an example of processing a read request from a host device will be described. Fig. 4 shows a sequence diagram of an example of read request processing. In the following, an example is shown of the operation when a read request from a host device is sent to controller 110a. However, the operation shown below can also be applied when controller 110b receives a read request from a host device by changing the relationship between the protocol chip, processor, memory, front-end switch, and back-end switch.

[0095] 401: The protocol chip 101a sends a read request received from the host device to the memory 105a of the processor 104a.

[0096] 402: The processor 104a retrieves from the memory 105a a read request from the host device.

[0097] 403: The processor 104a sends a read command to the storage device 107a.

[0098] 404: The storage device 107a returns the read data to the processor 104a.

[0099] 405: The processor 104a stores the read data from the storage device 107a in the memory 105a. This storage of the read data may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically stores the read data in the memory 105a according to the read data returned from the storage device 107a. Alternatively, the storage may be performed by software executed by the processor 104a.

[0100] 406: The processor 104a retrieves the read data from the memory 105a.

[0101] 407: The processor 104a sends a read response sending instruction including read data to the host device and the read data to the protocol chip 101a. Upon receiving the read response sending instruction including read data to the host device and the read data, the protocol chip 101a sends a read response including the read data to the host device.

[0102] 408-414: Steps 408 to 414 will be described by replacing the processor 104a with the processor 104b and the memory 105a with the memory 105b in steps 401 to 407.

[0103] 415: The protocol chip 101a sends the read request received from the host to the memory 105a of the processor 104a. This step is similar to step 401.

[0104] 416: Any one of the processors decides to shut down the processor 104a and the memory 105a. That is, it is decided to shut down the power supply to the power supply domain 121a. This step is similar to step 323.

[0105] 417: One of the processors determines to stop the processor 104c and the memory 105c. That is, it is determined to stop the power supply to the power supply domain 121c. This step is similar to step 324.

[0106] 418: The processor 104a retrieves the read request from the host device from the memory 105a in order to take over the read request.

[0107] 419: The processor 104a sends the read request from the host device to the memory 105b of the processor 104b to take over the read request.

[0108] 420: The processor 104a and the memory 105a are stopped. That is, the power supply control unit 131a stops the power supply to the power supply domain 121a. This step is the same as step 329.

[0109] 421: The processor 104c and the memory 105c are stopped. That is, the power supply control unit 131c stops the power supply of the power supply domain 121c. This step is the same as step 330.

[0110] 422: The processor 104b retrieves the read request from the host device in the memory 105b, which has been taken over from the processor 104a.

[0111] 423-427: Steps 423-427 are similar to steps 410-414.

[0112] As a result, when all power supply domains are operating, any of the processors 104a and 104b of the controller 110a can receive and process a read request from a host device. When the power supply domain 121a is stopped, that is, when the processor 104a is stopped, the processor 104a can transfer the read request received from the host to the processor 104b. In the above-described read request processing sequence, a case has been shown in which the first operation mode is switched to the second operation mode while the controller 110a is receiving the read request. Therefore, when a new write request is sent from the host device after the above-described transfer is completed, the processors and memories included in the operating power supply domains perform the operations shown in 401 to 407. EXAMPLES

[0113] A second embodiment will be described with reference to Figs. 1, 5, 6, and 7. The configuration of the storage system in the second embodiment is the same as that of the storage system in the first embodiment. An example thereof is shown in Fig. 1. The description of Fig. 1 is omitted since it is the same as that of the first embodiment. However, in the second embodiment, the processors 104a and 104c consume more power than the processors 104b and 104d, and the processors 104b and 104d consume much less power than the processors 104a and 104c (for example, 1 / 10 or less). For example, the processors 104a and 104c with high power consumption can exhibit a higher processing capacity than the processors 104b and 104d with low power consumption.

[0114] The storage system of the second embodiment has a plurality of operation modes including a first operation mode and a second operation mode. In the first operation mode and the second operation mode, some power supply domains are in an operating state and some power supply domains are in a stopped state. In the first operation mode and the second operation mode, the power supply domains in an operating state are different.

[0115] In the first embodiment, all the power domains 120a, 120b, 121a to 121d, 122a, and 122b are initially in a power operating state. On the other hand, in the second embodiment, only the power domains 120a and 120b, the power domain 121a including the processor 104a and memory 105a, the power domain 121c including the processor 104c and memory 105c, and the power domains 122a and 122b are initially in a power operating state. The power domain 121b including the processor 104b and memory 105b, and the power domain 121d including the processor 104d and memory 105d are in a power-off state. This is the first operation mode.

[0116] Thereafter, depending on the frequency of I / O requests from the host, the power supply domains 121a and 121c are put into a power-off state, and the power supply domains 121b and 121d are put into a power-on state. This is the second operation mode. This makes it possible to reduce power consumption. The power supply control of this embodiment will now be described. Figure 5 shows a flowchart of an example of power supply control. 501: When the storage system 1 is started up, the power supply domains 120a, 120b, 121a, 121c, 122a, and 122b are operating, and the power supply domains 121b and 121d are stopped.

[0117] 502: After that, the storage system 1 observes the frequency of I / O requests from the host device.

[0118] 503: If the condition that the frequency is equal to or less than the predetermined value (threshold value) for the predetermined period is not satisfied (503: NO), the flow returns to step 502.

[0119] 504: If the frequency is equal to or less than a predetermined value for a predetermined period, the storage system 1 decides to switch the operating power domain from the power domains 121a and 121c to the power domains 121b and 121d. In other words, it is decided to switch the processing from the processors 104a and 104c to the processors 104b and 104d.

[0120] 505: The power supply control units 131b and 131d turn on the power supplies of the power supply domains 121b and 121d, thereby starting the processes of the processors 104b and 104d.

[0121] 506: The processor 104a hands over the process to the processor 104b, and the processor 104c hands over the process to the processor 104d.

[0122] 507: The power control units 131a and 131c stop the power supply to the power supply domains 121a and 121c, thereby stopping the processing of the processors 104a and 104c.

[0123] 508: The storage system 1 observes the frequency of I / O requests from the host device.

[0124] 509: If the condition that the frequency is equal to or greater than the preset value (threshold) for a preset period is not satisfied (509: NO), the flow returns to step 508. The preset period in this step may be the same as or different from the preset period in step 503. The preset value in this step is not particularly specified to be larger or smaller than the preset value in step 503. However, if the preset value in step 503 is larger than the preset value in this step, even if the condition in step 503 is satisfied (503: YES), steps 504 to 507 are executed, the power supply domains 121b and 121d are operated, and the power supply domains 121a and 121c are stopped, the frequency of the I / O request from the host device may be larger than the preset value in this step in this step 509, and the flow may not return to step 508 but may immediately proceed to the next step 510. For this reason, it is preferable to set the preset value in step 503 smaller than the preset value in step 509.

[0125] 510: If the frequency is equal to or greater than the predetermined value for the predetermined period (509: YES), the power supply control units 131a and 131c turn on the power supplies of the power supply domains 121a and 121c, thereby restarting the processing of the processors 104a and 104c.

[0126] 511: The processor 104b hands over the process to the processor 104a, and the processor 104d hands over the process to the processor 104c.

[0127] 512: The power control units 131b and 131d stop the power supply to the power supply domains 121b and 121d, thereby stopping the processing of the processors 104b and 104d.

[0128] The observation of the frequency of I / O requests from the host device in steps 502 and 508 may be performed by one of the processors 104a to 104d that is in operation, or may be performed by a separate processor dedicated for observation. As a method of observation, similar to that of the first embodiment, for example, the processors 104a to 104d or the processor dedicated for observation may be provided with a function such as a timer counter that measures time, and the time measurement function may be used to count whether an I / O request arrives from the host device within a certain period of time.

[0129] As for the object of observation, in addition to observing the frequency of I / O requests from the host device as in the first embodiment, other values ​​related to the frequency of I / O requests from the host device may be substituted. For example, among the processors 104a to 104d, for the processors that are in operation, a processor operating rate or the like may be defined separately as in the first embodiment. In the following description, when the frequency of I / O requests from the host device is substituted with a processor operating rate or the like that is defined separately, the frequency of I / O requests from the host device is to be read as the processor operating rate or the like that is defined separately.

[0130] The decision to switch from power domains 121a and 121c to power domains 121b and 121d in step 504 may be made by either or both of the operating processors 104a and 104c communicating with each other to exchange or compile observation results of the frequency of I / O requests from each host device, or a separate processor dedicated to the decision-making process may be provided to compile the observation results of the frequency of I / O requests from the host devices.

[0131] When the processors 104a to 104d are connected to each other, or when a dedicated processor for the decision process is provided, the observation results of the frequency of I / O requests from the host device may be communicated between the processors 104a to 104d and the host device by providing a communication means via the front-end switch 102a or 102b or the back-end switch 106a or 106b, or by providing a dedicated communication signal line. Alternatively, when a dedicated processor for observing the frequency of I / O requests from the host device is provided, the processor may also perform the decision process.

[0132] Next, an example of processing a write request from a host device will be described below. Fig. 6 shows a sequence diagram of an example of the write request processing.

[0133] 601: The protocol chip 101a sends a write request arriving from the host device to the memory 105a of the processor 104a.

[0134] 602: The processor 104a retrieves the write request and write data from the host device from the memory 105a.

[0135] 603: The processor 104a sends the write data to the memory 105c of the processor 104c for duplication.

[0136] 604: The processor 104a sends a notification instruction of the completion of the write request to the host device to the protocol chip 101a. Upon receiving the notification instruction of the completion of the write request to the host device, the protocol chip 101a notifies the host device of the completion of the write request.

[0137] 605: The processor 104a sends a write command to the storage device 107a.

[0138] 606: The storage device 107a sends a request for write data to the processor 104a.

[0139] 607: The processor 104a retrieves the write data from the memory 105a. This retrieval may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically retrieves the write data from the memory 105a in response to a write data request from the storage device 107a. Alternatively, this may be performed by software executed by the processor 104a.

[0140] 608: The processor 104a returns the write data to the storage device 107a. This return may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically returns the write data retrieved from the memory 105a in response to a write data request from the storage device 107a. Alternatively, this may be performed by software executed by the processor 104a.

[0141] 609: The storage device 107a notifies the processor 104a that the write data has been received and stored.

[0142] 610-613: Steps 610-613 are similar to steps 601-604.

[0143] 614: Any of the operating processors determines to switch the processing from the processor 104a and the memory 105a to the processor 104b and the memory 105b. That is, it is determined to switch the operating power domain from the power domain 121a to the power domain 121b.

[0144] 615: Any of the operating processors determines to switch the processing from the processor 104c and the memory 105c to the processor 104d and the memory 105d. That is, it is determined to switch the operating power domain from the power domain 121c to the power domain 121d.

[0145] 616: The processor 104b and the memory 105b start up. That is, the power supply control unit 131b operates the power supply of the power supply domain 121b.

[0146] 617: The processor 104d and the memory 105d start up. That is, the power supply control unit 131d operates the power supply of the power supply domain 121d.

[0147] 618: The processor 104a retrieves the write data from the memory 105a in order to take over the write data.

[0148] 619: The processor 104a sends the write data to the memory 105b of the processor 104b for takeover of the write data.

[0149] 620: The processor 104c retrieves the write data from the memory 105c in order to take over the write data.

[0150] 621: The processor 104c sends the write data to the memory 105d of the processor 104d for takeover of the write data.

[0151] 622: The processor 104a and the memory 105a are stopped. That is, the power supply control unit 131a stops the power supply to the power supply domain 121a.

[0152] 623: The processor 104c and the memory 105c are stopped. That is, the power supply control unit 131c stops the power supply to the power supply domain 121c.

[0153] 624: The processor 104b checks the write data in the memory 105b taken over from the processor 104a, that is, checks the write request from the host.

[0154] 625-629: Steps 625-620 are the same as steps 605-609.

[0155] The following description will be given by replacing processor 104a with processor 104b and memory 105a with memory 105b.

[0156] 630-638: Steps 630-638 will be described by replacing the processor 104a with the processor 104b, the processor 104c with the processor 104d, the memory 105a with the memory 105b, and the memory 105c with the memory 105d in steps 601-609.

[0157] As a result, when the power supplies of the power supply domains 121a and 121c are operating, the processor 104a of the controller 110a can receive and process a write request (a data storage request) from the host device. When switching from the power supply domains 121a and 121c to the power supply domains 121b and 121d, that is, when switching processing from the processors 104a and 104c to the processors 104b and 104d, the processor 104a can hand over the write request received from the host to the processor 104b.

[0158] Furthermore, a copy of the write data from the host device that was sent from memory 105a of processor 104a to memory 105c of processor 104c of controller 110b and stored therein can also be handed over from memory 105c of processor 104c to memory 105d of processor 104d. This makes it possible to prevent the write data from the host device from being lost even if some kind of failure occurs in processor 104b or memory 105b that has handed over the write data from the host device in controller 110a.

[0159] Next, an example of processing a read request from a host device will be described with reference to Fig. 7, which shows a sequence diagram of an example of the read request processing.

[0160] 701: The protocol chip 101a sends a read request received from the host device to the memory 105a of the processor 104a.

[0161] 702: The processor 104a retrieves from the memory 105a a read request from the host device.

[0162] 703: The processor 104a sends a read command to the storage device 107a.

[0163] 704: The storage device 107a returns the read data to the processor 104a.

[0164] 705: The processor 104a stores the read data from the storage device 107a in the memory 105a. This storage of the read data may be performed by providing a function in part of the hardware circuit of the processor 104a that automatically stores the read data in the memory 105a according to the read data returned from the storage device 107a. Alternatively, the storage may be performed by software executed by the processor 104a.

[0165] 706: The processor 104a retrieves the read data from the memory 105a.

[0166] 707: The processor 104a sends a read response sending instruction including the read data to the host device and the read data to the protocol chip 101a. Upon receiving the read response sending instruction including the read data to the host device and the read data, the protocol chip 101a sends a read response including the read data to the host device.

[0167] 708: The protocol chip 101a sends the read request received from the host to the memory 105a of the processor 104a. This step is the same as step 701.

[0168] 709: Any of the operating processors determines to switch the processing from the processor 104a and the memory 105a to the processor 104b and the memory 105b. That is, it is determined to switch the operating power domain from the power domain 121a to the power domain 121b. This step is similar to step 614.

[0169] 710: Any of the operating processors decides to switch the processing from the processor 104c and the memory 105c to the processor 104d and the memory 105d. That is, it decides to switch the operating power domain from the power domain 121c to the power domain 121d. This step is similar to step 615.

[0170] 711: The processor 104b and the memory 105b start up. That is, the power supply control unit 131b activates the power supply of the power supply domain 121b. This step is the same as step 616.

[0171] 712: The processor 104d and the memory 105d start up. That is, the power supply control unit 131d activates the power supply of the power supply domain 121d. This step is the same as step 617.

[0172] 713: The processor 104a retrieves the read request from the host device from the memory 105a in order to take over the read request.

[0173] 714: The processor 104a sends the read request from the host device to the memory 105b of the processor 104b to take over the read request.

[0174] 715: The processor 104a and the memory 105a are stopped. That is, the power supply control unit 131a stops the power supply to the power supply domain 121a. This step is similar to step 622.

[0175] 716: The processor 104c and the memory 105c are stopped. That is, the power supply control unit 131c stops the power supply to the power supply domain 121c. This step is similar to step 623.

[0176] 717: The processor 104b retrieves the read request from the host device in the memory 105b, which has been taken over from the processor 104a.

[0177] 718-722: Steps 718-722 will be described by replacing the processor 104a with the processor 104b and the memory 105a with the memory 105b in steps 703-707.

[0178] 723-729: Steps 723-729 will be described by replacing the processor 104a with the processor 104b and the memory 105a with the memory 105b in steps 701-707.

[0179] As a result, when the power supplies of the power domains 121a and 121c are operating, the processor 104a of the controller 110a can receive and process a read request from the host device. When switching from the power domains 121a and 121c to the power domains 121b and 121d, that is, when switching processing from the processors 104a and 104c to the processors 104b and 104d, the processor 104a can hand over the read request received from the host to the processor 104b.

[0180] The present invention is not limited to the above-mentioned embodiment, but includes various modified examples. For example, the above-mentioned embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to those including all of the configurations described. It is also possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.

[0181] In addition, the above-mentioned configurations, functions, processing units, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. In addition, the above-mentioned configurations, functions, etc. may be realized in software by a processor interpreting and executing a program that realizes each function. Information such as the program, table, file, etc. that realizes each function can be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0182] In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other. [Explanation of symbols]

[0183] 1: Storage system 101a to 101d: Protocol chip 102a, 102b: Front-end switches 103: Inter-controller path 104a to 104d: processor 105a~105a:Memory 106a, 106b: back-end switches 107a~107h: Storage device 110a, 110b: controller 120a, 120b, 121a~d, 122a, 122b: Power area 130a, 130b, 131a-d, 132a, 132b: power supply control unit

Claims

1. A storage system that stores or outputs data in response to a data input / output request from a host device, Includes multiple controllers, Each of the plurality of controllers is A plurality of first power supply regions each capable of being independently power controlled; A processor that processes the I / O request and a memory that is connected to the processor are provided in each of the first power supply domains, Each of the plurality of controllers is a first operation mode in which all the first power supply domains provided in the controller are in an active state; a second operation mode in which a part of the first power supply domains provided in the controller are stopped and the other first power supply domains are in operation.

2. 2. The storage system according to claim 1, the plurality of controllers are removably installed in the storage system; A storage system, wherein the plurality of first power supply domains of each of the plurality of controllers are configured so as not to be removable from each controller.

3. 2. The storage system according to claim 1, one of the first power supply domains of each of the plurality of controllers includes a protocol chip that is connected to the host device and controls a protocol of communication with the host device; A storage system, wherein all of the processors in each of the plurality of controllers are configured to be able to process data I / O requests from the host device and received by the protocol chip.

4. 2. The storage system according to claim 1, further comprising one or more storage devices; one of the first power supply domains of each of the plurality of controllers includes a storage device connection unit that connects a processor of the first power supply domain to the storage device; A storage system, wherein the processor of each of the first power supply areas of the plurality of first power supply areas of each controller writes data on the memory to the storage device via the storage device connection unit, and reads data from the storage device and stores it in the memory.

5. 2. The storage system according to claim 1, Each controller of the plurality of controllers adopting the first operation mode when a frequency of data input / output requests from the host device is equal to or greater than a first threshold value; The storage system employs the second operation mode when a frequency of data input / output requests from the host device is equal to or lower than a second threshold value.

6. 2. The storage system according to claim 1, the plurality of controllers includes a first controller and a second controller; When the first controller and the second controller employ the first operation mode, The first controller receives write data from the host device; a first memory of the first controller stores the write data; The first controller sends a copy of the write data to the second controller; a second memory of the second controller storing a copy of the write data; When the first controller and the second controller change from the first operation mode to the second operation mode, When the first memory is included in the first power supply domain in which power is stopped in the second operation mode, the first controller transfers the write data stored in the first memory to a third memory included in the first power supply domain in which power is operated in the second operation mode of the first controller; A storage system, wherein, in the second operating mode, when the second memory is included in a power supply domain in which power is stopped, the second controller transfers a copy of the write data stored in the second memory to a fourth memory included in the first power supply domain of the second controller in which power is in an operating state in the second operating mode.

7. 2. The storage system according to claim 1, At least one of the multiple controllers is at least one second power supply domain capable of being power-controlled independently of the first power supply domain; a protocol chip provided in the second power supply domain, connected to the host device, and controlling communication with the host device; The second power supply domain is configured to be switchable between an operating state and a stopped state, A storage system, wherein the second power domain is configured to be in the active state when the protocol chip communicates with the host device, and to be in the stopped state when the protocol chip is not communicating with the host device.

8. A storage system that stores or outputs data in response to a data input / output request from a host device, Includes multiple controllers, a first controller of the plurality of controllers includes a plurality of power supply domains that can be separately power controlled; a first power domain of the multiple power domains includes a first processor and a first memory coupled to the first processor; a second power domain of the multiple power domains includes a second processor and a second memory coupled to the second processor; the first processor consumes more power than the second processor; a second controller of the plurality of controllers includes a plurality of power supply domains that can be separately power controlled; a third power supply domain of the second controller includes a third processor and a third memory connected to the third processor; a fourth power supply domain of the second controller includes a fourth processor and a fourth memory connected to the fourth processor; the third processor consumes more power than the fourth processor; The storage system has a first operation mode and a second operation mode, the first operation mode is a state in which the power supply of the first power supply domain is in an active state and the power supply of the second power supply domain is in a stopped state, the power supply of the third power supply domain is in an active state and the power supply of the fourth power supply domain is in a stopped state; The second operating mode of the storage system includes a power supply for the first power supply domain being stopped and a power supply for the second power supply domain being operating, a power supply for the third power supply domain being stopped and a power supply for the fourth power supply domain being operating.

9. 9. The storage system according to claim 8, the first controller and the second controller are removable from the storage system; the first power supply domain and the second power supply domain of the first controller are configured to be non-detachable from the first controller; A storage system, wherein the third power supply region and the fourth power supply region of the second controller are configured so as not to be removable from the second controller.

10. 9. The storage system according to claim 8, one of the plurality of power supply domains of each of the first controller and the second controller includes a protocol chip that controls a protocol of communication with the host device; each of the first processor and the second processor is configured to process a data input / output request from the host device received by the protocol chip of the first controller; A storage system, wherein each of the third processor and the fourth processor is configured to be able to process a data input / output request from the host device that is received by the protocol chip of the second controller.

11. 9. The storage system according to claim 8, further comprising one or more storage devices; one of the plurality of power supply domains of the first controller includes a first storage device connection unit that connects to the storage device; one of the plurality of power supply domains of the second controller includes a second storage device connection section that connects to the storage device; the first processor writes data on the first memory to the storage device via the first storage device connection unit, reads data from the storage device and stores the data in the first memory; the second processor is configured to be able to write data on the second memory to the storage device and read data from the storage device and store the data in the second memory via the first storage device connection unit; the third processor writes data on the third memory to the storage device via the second storage device connection unit, reads data from the storage device and stores the data in the third memory; A storage system wherein the fourth processor writes data on the fourth memory to the storage device via the second storage device connection unit, and reads data from the storage device and stores it in the fourth memory.

12. 9. The storage system according to claim 8, When a frequency of data input / output requests from the host device is equal to or greater than a first threshold, the first controller and the second controller adopt the first operation mode; A storage system, wherein when a frequency of data input / output requests from the host device is equal to or lower than a second threshold, the first controller and the second controller adopt the second operation mode.

13. 9. The storage system according to claim 8, When the first controller and the second controller employ the first operation mode, When the first controller receives write data from the host device, the first controller stores the write data in the first memory; The first controller sends a copy of the write data to the second controller; The second controller stores a copy of the write data in the third memory; When the first controller and the second controller employ the second operation mode, When the first controller receives write data from the host device, the first controller stores the write data in the second memory; The first controller sends a copy of the write data to the second controller; The second controller stores a copy of the write data in the fourth memory; When the first controller and the second controller change from the first operation mode to the second operation mode, the first controller transfers the write data stored in the first memory to the second memory; The second controller transfers a copy of the write data stored in the third memory to the fourth memory.

Images