Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing current collapse.SOLUTION: A semiconductor device has a barrier layer having an upper surface with a nitrogen polarity, a channel layer having an upper surface with a nitrogen polarity on the barrier layer, a first cap layer having an upper surface with a nitrogen polarity on the channel layer, and a dielectric film in contact with the upper surface of the first cap layer, and the first cap layer is an aluminum nitride layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A high electron mobility transistor (HEMT) in which a channel layer is formed on a barrier layer has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2005 / 119787 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for suppressing current collapse.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing current collapse. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises a barrier layer having an upper surface with nitrogen polarity, a channel layer having an upper surface with nitrogen polarity and above the barrier layer, a first cap layer having an upper surface with nitrogen polarity and above the channel layer, and a dielectric film in contact with the upper surface of the first cap layer, wherein the first cap layer is an aluminum nitride layer. Effect of the Invention

[0007] According to the present disclosure, current collapse can be suppressed. [Brief description of the drawings]

[0008] [Figure 1]FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (part 1) showing the method for manufacturing the semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 4) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 6] 6A to 6C are cross-sectional views (part 5) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing the basic structure of the epitaxial substrate used in the experiment. [Figure 9] FIG. 9 shows an atomic force microscope image (part 1). [Figure 10] FIG. 10 shows an atomic force microscope image (part 2). [Figure 11] FIG. 11 is a diagram showing the relationship between the aluminum composition and the sheet resistance. [Figure 12] FIG. 12 is a diagram showing the relationship between the aluminum composition and the number of protrusions. [Figure 13] FIG. 13 is a diagram showing the relationship between the thickness and the sheet resistance of an aluminum nitride layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a barrier layer having an upper surface with a nitrogen polarity, a channel layer having an upper surface with a nitrogen polarity and over the barrier layer, a first cap layer having an upper surface with a nitrogen polarity and over the channel layer, and a dielectric film in contact with the upper surface of the first cap layer, wherein the first cap layer is an aluminum nitride layer.

[0011] [2] A semiconductor device according to another embodiment of the present disclosure includes a barrier layer having an upper surface with nitrogen polarity, a channel layer having an upper surface with nitrogen polarity and over the barrier layer, a first cap layer having an upper surface with nitrogen polarity and over the channel layer, and a dielectric film in contact with the upper surface of the first cap layer, wherein the ratio of aluminum among group III elements in the upper surface of the first cap layer is 52% or more.

[0012] When the first cap layer is an aluminum nitride layer or the ratio of aluminum in the group III elements on the top surface of the first cap layer is 52% or more, the first cap layer can have excellent surface morphology, which reduces electron traps present on the surface of the first cap layer and suppresses current collapse.

[0013] [3] In the structure of [1] or [2], the first cap layer may have a thickness of 0.2 nm or more and less than 2.0 nm. In this case, an increase in sheet resistance can be suppressed while suppressing current collapse.

[0014] [4] In any one of [1] to [3], a second cap layer having a nitrogen polarity on its upper surface may be provided between the channel layer and the first cap layer, and a ratio of aluminum in the group III elements in the second cap layer may be lower than a ratio of aluminum in the group III elements in the first cap layer. In this case, even if the two-dimensional electron gas is reduced by the first cap layer, the two-dimensional electron gas can be compensated by the second cap layer.

[0015] [5] In any one of [1] to [4], a gate electrode may be provided on the dielectric film. In this case, gate leakage is easily suppressed.

[0016] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, "planar view" refers to viewing an object from above.

[0017] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing a semiconductor device according to the embodiment.

[0018] As shown in FIG. 1, the semiconductor device 1 according to the embodiment mainly includes a growth substrate 10, a nitride semiconductor layer 20, a dielectric film 31, a passivation film 50, a regrown layer 41S, a regrown layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0019] The growth substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the growth substrate 10 is a SiC substrate, the upper surface of the growth substrate 10 is a carbon (C) polarity surface. When the surface of the growth substrate 10 is a C polarity surface, the nitride semiconductor layer 20 can grow as a crystal with a nitrogen (N) polarity surface as the growth surface.

[0020] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24, and a cap layer 25. The nitride semiconductor layer 20 may include a nucleation layer between the growth substrate 10 and the buffer layer 21.

[0021] The buffer layer 21 is on the growth substrate 10. The buffer layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the AlN layer is, for example, not less than 1 nm and not more than 2000 nm. The buffer layer 21 may include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer.

[0022] The barrier layer 22 is on the buffer layer 21. The barrier layer 22 is, for example, an AlGaN layer. The band gap of the barrier layer 22 is larger than the band gap of the channel layer 24. The thickness of the barrier layer 22 is, for example, 1 nm or more and 50 nm or less. The composition of the barrier layer 22 is, for example, Al Y Ga 1-Y N (0.15≦Y≦0.55). The conductivity type of the barrier layer 22 is, for example, n-type or undoped (i-type). Instead of the AlGaN layer, a scandium aluminum nitride (ScAlN), an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used. Y Ga 1-Y In the case of N, the proportion of Al in the group III elements in the barrier layer 22 is Y×100%.

[0023] The spacer layer 23 is on the barrier layer 22. The spacer layer 23 is, for example, an AlN layer. The thickness of the spacer layer 23 is, for example, in the range of 0.2 nm to 5 nm.

[0024] The channel layer 24 is on the spacer layer 23. The channel layer 24 is, for example, a GaN layer. The band gap of the channel layer 24 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 24 is, for example, 1 nm or more and 50 nm or less. Distortion occurs between the channel layer 24 and the barrier layer 22 and the spacer layer 23 due to the difference in lattice constants thereof, and this distortion induces a piezoelectric charge at the interface between the two layers. As a result, a two dimensional electron gas (2DEG) is generated in the channel layer 24 near the surface facing the barrier layer 22, and a channel region 26 is formed. The conductivity type of the channel layer 24 is, for example, n-type or undoped (i-type).

[0025] The cap layer 25 includes a second cap layer 25B and a first cap layer 25A. The second cap layer 25B is on the channel layer 24. The first cap layer 25A is on the second cap layer 25B. For example, the second cap layer 25B is an AlGaN layer, and the first cap layer 25A is an aluminum nitride (AlN) layer. The composition of the second cap layer 25B is, for example, Al X Ga 1-X For example, the thickness of the second cap layer 25B is 0.2 nm or more and 10 nm or less, and the thickness of the first cap layer 25A is 0.2 nm or more and less than 2.0 nm. X Ga 1-X In the case of N, the proportion of Al in the group III elements in the second cap layer 25B is X×100%.

[0026] On the C-polarity surface of the SiC substrate, the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, the second cap layer 25B, and the first cap layer 25A grow as crystals with the N-polarity surface as the growth surface. Therefore, the upper surface of each of the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, the second cap layer 25B, and the first cap layer 25A has N-polarity, and the lower surface of each has gallium (Ga) polarity or aluminum (Al) polarity.

[0027] A recess 40S for a source and a recess 40D for a drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. In other words, the recess 40S and the recess 40D are formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be in the channel layer 24, the spacer layer 23, or the barrier layer 22.

[0028] The dielectric film 31 is on the nitride semiconductor layer 20. The dielectric film 31 is in contact with the upper surface 29 of the first cap layer 25A. For example, the dielectric constant of the dielectric film 31 is higher than that of silicon dioxide (SiO2). The dielectric film 31 may be a high-dielectric constant film. The dielectric film 31 is, for example, a silicon nitride (SiN) film. The dielectric film 31 may be a dielectric oxide film or a dielectric oxynitride film. The dielectric oxide film or the dielectric oxynitride film may contain at least one selected from the group consisting of hafnium (Hf), lanthanum (La), and zirconium (Zr). The dielectric oxide film or the dielectric oxynitride film may contain at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric film 31 may be hafnium silicate (HfSiO x ) membrane, hafnium aluminate (HfAlO x ) film, a hafnium silicon oxynitride (HfSiON) film, or a hafnium aluminum oxynitride (HfAlON) film. The thickness of the dielectric film 31 is, for example, 1 nm or more and 30 nm or less. An opening 31S for a source and an opening 31D for a drain are formed in the dielectric film 31. The opening 31S is connected to the recess 40S, and the opening 31D is connected to the recess 40D.

[0029] The regrown layer 41S is on the channel layer 24, the spacer layer 23, or the barrier layer 22 in the recess 40S. The regrown layer 41D is on the channel layer 24, the spacer layer 23, or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as an n-type impurity. The electrical resistance of the regrown layer 41S and the regrown layer 41D is lower than the electrical resistance of the channel layer 24. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowth of an n-type GaN layer after the formation of the recess 40S and the recess 40D in the nitride semiconductor layer 20.

[0030] The source electrode 42S is on the regrown layer 41S, and the drain electrode 42D is on the regrown layer 41D. The source electrode 42S contacts the regrown layer 41S, and the drain electrode 42D contacts the regrown layer 41D. The source electrode 42S makes ohmic contact with the regrown layer 41S, and the drain electrode 42D makes ohmic contact with the regrown layer 41D.

[0031] The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 is, for example, a SiN film. The thickness of the passivation film 50 is, for example, 5 nm to 50 nm in a portion having a uniform thickness on the dielectric film 31. The passivation film 50 has an opening 50S for a source, an opening 50D for a drain, and an opening 50G for a gate. A part of the regrown layer 41S is exposed from the opening 50S, and a part of the regrown layer 41D is exposed from the opening 50D. In a plan view, the opening 50G is between the opening 50S and the opening 50D. A part of the dielectric film 31 is exposed from the opening 50G.

[0032] In a plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is located on the passivation film 50 and the dielectric film 31, and contacts the dielectric film 31 through an opening 50G.

[0033] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 7 are cross-sectional views showing the method for manufacturing the semiconductor device 1 according to the embodiment.

[0034] 2, a nitride semiconductor layer 20 is formed on a growth substrate 10 by, for example, metal organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24, a second cap layer 25B, and a first cap layer 25A are formed in this order. The first cap layer 25A is formed at a temperature of, for example, 700° C. or higher. The buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the second cap layer 25B may also be formed at the same temperature as the first cap layer 25A.

[0035] Next, as shown in FIG. 3, a dielectric film 31 is formed on the nitride semiconductor layer 20.

[0036] Next, as shown in FIG. 4, an opening 31S for a source and an opening 31D for a drain are formed in the dielectric film 31, and a recess 40S for a source and a recess 40D for a drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. In other words, the recess 40S and the recess 40D may be formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be in the channel layer 24, the spacer layer 23, or the barrier layer 22. The opening 31S, the opening 31D, the recess 40S, and the recess 40D can be formed by, for example, reactive ion etching (RIE) using a mask (not shown).

[0037] 5, a regrown layer 41S is formed on the channel layer 24, the spacer layer 23, or the barrier layer 22 in the recess 40S, and a regrown layer 41D is formed on the channel layer 24, the spacer layer 23, or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D can be formed by, for example, a physical vapor deposition (PVD) method such as an evaporation method, a sputtering method, or a molecular beam epitaxy (MBE) method, or a metalorganic chemical vapor deposition (MOCVD) method.

[0038] 6, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. In forming the source electrode 42S and the drain electrode 42D, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is first formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in an area where the metal layer is to be formed is used for film formation, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed.

[0039] 7, a passivation film 50 is formed on the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D.

[0040] Next, an opening 50G for a gate is formed in the passivation film 50 (see FIG. 1). The opening 50G can be formed by, for example, RIE using a mask (not shown).

[0041] Next, the gate electrode 43, which contacts the dielectric film 31 through the opening 50G, is formed on the passivation film 50 and the dielectric film 31 (see FIG. 1). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) having an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed.

[0042] Next, an opening 50S for a source and an opening 50D for a drain are formed in the passivation film 50 (see FIG. 1). The openings 50S and 50D can be formed by, for example, RIE using a mask (not shown).

[0043] In this manner, the semiconductor device 1 can be manufactured.

[0044] In the semiconductor device 1 of the embodiment, the upper surfaces of the barrier layer 22 and the channel layer 24 each have N polarity, which makes it easier to shorten the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D, and makes it easier to achieve low resistance.

[0045] Furthermore, since the layer in contact with the dielectric film 31, i.e., the first cap layer 25A which is the last layer formed in the nitride semiconductor layer 20, is an AlN layer, excellent surface morphology can be obtained in the nitride semiconductor layer 20. This makes it possible to reduce electron traps present on the surface of the nitride semiconductor layer 20 and suppress current collapse.

[0046] Furthermore, since the gate electrode 43 is provided on the dielectric film 31 and a MIS (metal insulator semiconductor) structure is formed, gate leakage can be easily suppressed.

[0047] It is not necessary that the first cap layer 25A is an AlN layer. Even if the first cap layer 25A is an AlGaN layer, if the ratio of Al in the group III elements is 52% or more, that is, if the Al composition is 0.52 or more, on the upper surface 29 of the first cap layer 25A, the nitride semiconductor layer 20 can have excellent surface morphology. The ratio of Al in the group III elements in the upper surface 29 may be 90% or more, that is, the Al composition may be 0.9 or more, or the ratio of Al in the group III elements may be 95% or more, that is, the Al composition may be 0.95 or more. The higher the Al composition, the higher the thermal decomposition resistance of the first cap layer 25A, and the easier it is to obtain excellent surface morphology. However, while an AlGaN layer with a high Al composition is difficult to form stably, an AlN layer has the advantage of being easy to form.

[0048] The Al composition of the nitride semiconductor layer can be measured by X-ray diffraction (XRD) or energy dispersive X-ray spectroscopy.

[0049] If the thickness of the first cap layer 25A is less than 0.2 nm, it will be less than one molecular layer, and there is a risk that the effect of suppressing current collapse by the first cap layer 25A will be difficult to obtain. If the thickness of the first cap layer 25A is 2.0 nm or more, the 2DEG in the channel region 26 will decrease, and the sheet resistance will increase. If the thickness of the first cap layer 25A is less than 2.0 nm, the sheet resistance can be kept low. The thickness of the first cap layer 25A may be 0.2 nm or more and 1.0 nm or less, 0.2 nm or more and 0.9 nm or less, or 0.2 nm or more and 0.8 nm or less. The thickness of the first cap layer 25A may be 0.3 nm or more and 1.9 nm or less, or 0.4 nm or more and 1.8 nm or less.

[0050] Furthermore, by forming the first cap layer 25A at a temperature of 700° C. or higher, it is easy to obtain excellent surface morphology in the first cap layer 25A. The formation temperature of the first cap layer 25A may be 800° C. or higher, or 900° C. or higher.

[0051] Furthermore, by providing the second cap layer 25B having a lower Al composition than the first cap layer 25A between the channel layer 24 and the first cap layer 25A, the reduction in 2DEG caused by the first cap layer 25A can be compensated for by the second cap layer 25B. Therefore, an increase in sheet resistance can be suppressed. Even if the first cap layer 25A is an AlGaN layer, if the Al composition in the second cap layer 25B is lower than the Al composition in the first cap layer 25A, the reduction in 2DEG can be compensated for by the second cap layer 25B. However, the nitride semiconductor layer 20 may not include the second cap layer 25B, and the first cap layer 25A may be in contact with the upper surface of the channel layer 24.

[0052] Here, the results of the experiment conducted by the inventor of the present application will be described. FIG. 8 is a cross-sectional view showing the basic structure of the epitaxial substrate used in the experiment. As shown in FIG. 8, the basic structure of the epitaxial substrate used in the experiment includes a growth substrate 110 and a nitride semiconductor layer 120. The growth substrate 110 is a SiC substrate whose upper surface is a C-polarity surface. The nitride semiconductor layer 120 includes a nucleation layer 127, a buffer layer 121, a barrier layer 122, a spacer layer 123, a channel layer 124, and a cap layer 125. The nucleation layer 127 is on the growth substrate 110. The buffer layer 121 is on the nucleation layer 127. The barrier layer 122 is on the buffer layer 121. The spacer layer 123 is on the barrier layer 122. The channel layer 124 is on the spacer layer 123. The cap layer 125 includes a second cap layer 125B and a first cap layer 125A. The second cap layer 125B is on the channel layer 124. The first cap layer 125A is on the second cap layer 125B. The top surface of each of the nucleation layer 127, the buffer layer 121, the barrier layer 122, the spacer layer 123, the channel layer 124, the second cap layer 125B and the first cap layer 125A has an N-polarity, and the bottom surface of each has a Ga-polarity or an Al-polarity.

[0053] (First experiment) In the first experiment, an epitaxial substrate in which the cap layer 125 does not include the second cap layer 125B and the first cap layer 125A is in contact with the upper surface of the channel layer 124 was used, and a difference in surface morphology due to a difference in the Al composition in the first cap layer 125A was confirmed. Specifically, two types of epitaxial substrates (samples No. 1 and No. 2) were produced. In sample No. 1, an AlGaN layer with an Al composition of 0.2 was formed as the first cap layer 125A, and in sample No. 2, an AlN layer with an Al composition of 1.0 was formed as the first cap layer 125A. The other configurations were the same between samples No. 1 and No. 2.

[0054] Then, the surface morphology of samples No. 1 and No. 2 was observed using an atomic force microscope (AFM). The results are shown in Figures 9 and 10. Figure 9 is a diagram showing an AFM image of sample No. 1. Figure 10 is a diagram showing an AFM image of sample No. 2. As shown in Figures 9 and 10, sample No. 2 had a surface morphology superior to that of sample No. 1.

[0055] (Second experiment) In the second experiment, epitaxial substrates with different cap layer 125 configurations were used. The first cap layer 125A was an AlN layer with a thickness of 0.25 nm, and the second cap layer 125B was an AlGaN layer or an AlN layer with a thickness of 2 nm. In condition A, the cap layer 125 did not include the first cap layer 125A, but only the second cap layer 125B. In condition B, the cap layer 125 did not include the second cap layer 125B, but only the first cap layer 125A, and the first cap layer 125A was in contact with the upper surface of the channel layer 124. In condition C, the cap layer 125 included the first cap layer 125A and the second cap layer 125B. The Al composition of the second cap layer 125B in condition C was 0.2.

[0056] Then, the sheet resistance of each epitaxial substrate was measured. The results are shown in Fig. 11. Fig. 11 is a diagram showing the relationship between the Al composition and the sheet resistance. Note that the Al composition on the horizontal axis in Fig. 11 represents the Al composition on the upper surface of the nitride semiconductor layer 120.

[0057] As shown in FIG. 11, under condition A, the sheet resistance increased as the Al composition of the second cap layer 125B increased. This is because the thickness of the second cap layer 125B was 2 nm, and the higher the Al composition, the easier it is for the 2DEG to decrease. Under conditions B and C, the sheet resistance was low even though the Al composition of the first cap layer 125A was 1.0. This is because the thickness of the first cap layer 125A was 0.25 nm, and the 2DEG is less likely to decrease.

[0058] (Third experiment) In the third experiment, the change in sheet resistance due to ultraviolet irradiation was measured. In the third experiment, two types of epitaxial substrates (samples No. 3 and No. 4) were produced. In sample No. 3, the cap layer 125 did not include the first cap layer 125A, and in sample No. 4, the cap layer 125 included the first cap layer 125A and the second cap layer 125B. The first cap layer 125A was an AlN layer with a thickness of 0.25 nm. The second cap layer 125B was an AlGaN layer with a thickness of 2 nm, and the Al composition of the second cap layer 125B was 0.2. The other configurations were the same between samples No. 3 and No. 4.

[0059] The sheet resistance of each epitaxial substrate was measured under two conditions: condition D without UV irradiation and condition E with UV irradiation. The ratio R of the sheet resistance measured under condition D to the sheet resistance measured under condition E was calculated. The results are shown in Table 1.

[0060] [Table 1]

[0061] As shown in Table 1, sample No. 4 had a smaller ratio R than sample No. 3. When the surface of the nitride semiconductor layer is irradiated with ultraviolet light, electrons captured in electron traps present on the surface of the nitride semiconductor layer are released. Therefore, a small ratio R means that there are fewer electron traps on the surface of the nitride semiconductor layer. From the results shown in Table 1, it can be said that sample No. 4, which has the first cap layer 125A, has fewer electron traps than sample No. 3, which does not have the first cap layer 125A. Therefore, sample No. 4 can suppress current collapse more effectively than sample No. 3.

[0062] (Experiment 4) In the fourth experiment, the change in sheet resistance due to ultraviolet irradiation was also measured. In the fourth experiment, two types of epitaxial substrates (samples No. 5 and No. 6) were produced. Sample No. 5 did not have a cap layer 125, and in sample No. 6, the cap layer 125 did not include the second cap layer 125B. The first cap layer 125A was an AlN layer with a thickness of 0.25 nm. The other configurations were the same between samples No. 5 and No. 6. Note that the configuration of the barrier layer 122 differed between samples No. 3 and No. 4 and samples No. 5 and No. 6.

[0063] Then, the sheet resistance of each epitaxial substrate was measured under the same two conditions as in Experiment 3. In addition, the ratio R of the sheet resistance measured under condition D to the sheet resistance measured under condition E was calculated. The results are shown in Table 2.

[0064] [Table 2]

[0065] As shown in Table 2, the ratio R of sample No. 6 was smaller than that of sample No. 5. From the results shown in Table 2, it can be said that sample No. 6 having the first cap layer 125A has fewer electron traps than sample No. 5 not having the first cap layer 125A. Therefore, sample No. 6 can suppress current collapse more effectively than sample No. 5.

[0066] (Fifth experiment) In the fifth experiment, a number of samples with different Al compositions on the top surface of the nitride semiconductor layer 120 were prepared, and the number of protrusions present on the top surface was measured from the AFM images of the top surfaces. In measuring the number of protrusions, the AFM images were binarized using an appropriate threshold value within the range of -2 nm to +2 nm with respect to the average plane of the top surface. 2 The number of protrusions per unit area was calculated. The results are shown in Fig. 12. Fig. 12 is a diagram showing the relationship between the Al composition and the number of protrusions.

[0067] As shown in FIG. 12, the number of protrusions decreased as the Al composition increased. In other words, the surface morphology improved as the Al composition increased. In particular, when the Al composition was 0.6 or more, the number of protrusions increased by 1 μm. 2 The number of protrusions per unit area was 0. Also, as mentioned above, the higher the Al composition, the fewer the electron traps. From the above, it can be said that the improvement of the surface morphology contributes to the reduction of electron traps. Also, in Figure 12, the intercept of the horizontal axis is 0.52. From this, it can be said that an Al composition of 0.52 or more is excellent in the effects of improving the surface morphology and reducing electron traps.

[0068] (Experiment 6) In the sixth experiment, an epitaxial substrate was used in which an AlGaN layer having an Al composition of 0.2 and a thickness of 3 nm was used as the second cap layer 125B, and an AlN layer was used as the first cap layer 125A. The sheet resistance was measured while changing the thickness of the first cap layer 125A. The results are shown in FIG. 13. FIG. 13 is a diagram showing the relationship between the thickness and the sheet resistance of the first cap layer 125A.

[0069] 13, the thicker the first cap layer 125A, the higher the sheet resistance. This is because the first cap layer 125A is an AlN layer, and therefore the thicker the first cap layer 125A, the smaller the 2DEG. However, when the thickness of the first cap layer 125A is in the range of 1 nm or less, the increase in sheet resistance is more gradual than when the thickness exceeds 1 nm.

[0070] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0071] 1: Semiconductor device 10, 110: growth substrate 20, 120: nitride semiconductor layer 21, 121: Buffer layer 22, 122: Barrier layer 23, 123: Spacer layer 24, 124: Channel layer 24A:Top surface 25, 125: Cap layer 25A, 125A: 1st cap layer 25B, 125B: 2nd cap layer 26: Channel region 29:Top surface 31: Dielectric film 31D, 31S, 50D, 50G, 50S: Aperture 40D, 40S: Concave 41D, 41S: Regrowth layer: Regrowth layer 42D: Drain electrode 42S: Source electrode 43: Gate electrode 50: Passivation film 127: Nucleation layer

Claims

1. a barrier layer having a nitrogen polarity on the upper surface; a channel layer having a nitrogen polarity on an upper surface thereof and on the barrier layer; a first cap layer having a nitrogen polarity on a top surface thereof and over the channel layer; a dielectric film in contact with the top surface of the first cap layer; having The first cap layer is an aluminum nitride layer.

2. a barrier layer having a nitrogen polarity on the upper surface; a channel layer having a nitrogen polarity on an upper surface thereof and on the barrier layer; a first cap layer having a nitrogen polarity on a top surface thereof and over the channel layer; a dielectric film in contact with the top surface of the first cap layer; having A semiconductor device, wherein the percentage of aluminum in group III elements in the top surface of the first cap layer is 52% or more.

3. 3. The semiconductor device according to claim 1, wherein the first cap layer has a thickness of not less than 0.2 nm and less than 2.0 nm.

4. a second cap layer having a nitrogen polarity on an upper surface between the channel layer and the first cap layer; 3. The semiconductor device according to claim 1, wherein a ratio of aluminum among the group III elements in said second cap layer is lower than a ratio of aluminum among the group III elements in said first cap layer.

5. 3. The semiconductor device according to claim 1, further comprising a gate electrode on said dielectric film.

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