Printed circuit board

Abstract

To provide a printed circuit board capable of maintaining normal functioning even when any defect occurs.SOLUTION: A printed circuit board includes a first wiring section including a plurality of first distribution lines, a first integrated circuit chip connected to one side of the first wiring section, the first integrated circuit chip configured to convert N signals (N is a natural number) into one signal, a second integrated circuit chip connected to the other side of the first wiring section, the second integrated circuit chip configured to convert one signal into N signals (N is a natural number), a wiring section 2-1 connected to the first integrated circuit chip and including a plurality of distribution lines 2-1, and a wiring section 2-2 connected to the second integrated circuit chip and including a plurality of distribution lines 2-2. When the number of the plurality of first distribution lines is X and the number of the plurality of distribution lines 2-1 is Y1, X, Y1 satisfy Y1 / N<X.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, etc., multi-chip packages including memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are used to process data that has increased exponentially. In addition, as the number of cores of CPUs and GPUs in server products increases rapidly, die splitting technology that can effectively increase the number of cores has become commonplace, and the demand for high-density circuits that connect logic semiconductors and memory semiconductors or logic semiconductors and logic semiconductors has also increased rapidly, and the demand for die-to-die interconnection that connects them to each other has increased. In order to design a substrate for die-to-die interconnection, a technology for realizing fine circuits is required, and research is ongoing to improve reliability and increase yield while realizing high-density fine circuits on a large-area substrate. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT It is one of the many objects of the present invention to provide a printed circuit board that is capable of functioning properly even when a defect occurs.

[0004] Another of the various objects of the present invention is to provide a printed circuit board having an improved yield even when fine wiring is realized.

[0005] Another one of the various objects of the present invention is to provide a printed circuit board that can improve reliability.

Means for Solving the Problems

[0006] One of several solution means proposed through the present invention is a first wiring portion including a plurality of first wirings, a first integrated circuit chip connected to one side of the first wiring portion and converting N (N is a natural number) signals into one signal, a second integrated circuit chip connected to the opposite side of the first wiring portion and converting one signal into N (N is a natural number) signals, a second - 1 wiring portion connected to the first integrated circuit chip and including a plurality of second - 1 wirings, and a second - 2 wiring portion connected to the second integrated circuit chip and including a plurality of second - 2 wirings. When the number of the plurality of first wirings is X and the number of the plurality of second - 1 wirings is Y1, it is to provide a printed circuit board in which X and Y1 satisfy Y1 / N < X.

[0007] Another one of several solution means proposed through the present invention is a first insulating portion including a plurality of first insulating layers and a plurality of cavities respectively penetrating a part of the plurality of first insulating layers, a first integrated circuit chip mounted in one of the plurality of cavities and including a multiplexer (MUX) circuit, a second integrated circuit chip mounted in one of the plurality of cavities and including a de - multiplexer (DEMUX) circuit, a second insulating portion disposed across a part of the first integrated circuit chip and a part of the second integrated circuit chip, and a first wiring portion disposed on or within the second insulating portion and connecting the first integrated circuit chip and the second integrated circuit chip. The first wiring portion includes a plurality of first wirings, and at least one of the plurality of first wirings is open, or at least two of the plurality of first wirings are short - circuited so as not to connect the first integrated circuit chip and the second integrated circuit chip. It is to provide a printed circuit board.

Effect of the Invention

[0008] Among the various advantages of the present invention, one advantage is that it provides a printed circuit board that is capable of functioning properly even when a defect occurs.

[0009] Another of the various effects of the present invention is that it is possible to provide a printed circuit board with improved yield even when fine wiring is realized.

[0010] Another advantage of the present invention, among the various advantages, is that it is possible to provide a printed circuit board that can improve reliability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a schematic plan view of a portion of a printed circuit board according to an example. [Figure 4] FIG. 13 is a plan view illustrating a schematic diagram of a modified example of a printed circuit board according to an example. [Diagram 5] FIG. 13 is a plan view illustrating a schematic diagram of a modified example of a printed circuit board according to an example. [Figure 6a] FIG. 1 is a cross-sectional view illustrating a schematic configuration of a printed circuit board according to an example. [Figure 6b] FIG. 1 is a cross-sectional view illustrating a schematic configuration of a printed circuit board according to an example. [Figure 7a] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. [Figure 7b] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. [Figure 8a] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. [Figure 8b] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. [Figure 9a] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. [Figure 9b] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. [Figure 10a] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. [Figure 10b] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to yet another example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0017] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0022] Printed Circuit Board FIG. 3 is a plan view that illustrates a schematic view of a portion of a printed circuit board according to an example, and FIG. 4 is a plan view that illustrates a schematic view of a modified example of the printed circuit board according to an example.

[0023] Referring to FIG. 3, a semiconductor package according to one example may include a first insulating part 110, a first wiring part 120 arranged on or within the first insulating part 110 and including a plurality of first wirings 121, a first integrated circuit chip 210 connected to one side of the first wiring part 120, a second integrated circuit chip 220 connected to the opposite side of the first wiring part 120, a 2-1 wiring part 130 having one side connected to the first integrated circuit chip 210 and including a plurality of 2-1 wirings 131, and a 2-2 wiring part 140 having one side connected to the second integrated circuit chip 220 and including a plurality of 2-2 wirings 141.

[0024] The printed circuit board according to an example may include a first integrated circuit chip 210 and a second integrated circuit chip 220 disposed on a first insulating part 110. Each of the first integrated circuit chip 210 and the second integrated circuit chip 220 may include an integrated circuit (IC) in which hundreds to millions of circuits are integrated into one chip.

[0025] The first integrated circuit chip 210 may include a demultiplexer (DEMUX) circuit that converts N signals (N is a natural number) into one signal, and the second integrated circuit chip 220 may include a multiplexer (MUX) circuit that converts one signal into N signals (N is a natural number). The demultiplexer circuit is a so-called demultiplexing circuit, and may mean a circuit that converts a plurality of signal paths into one signal path and transmits the signal by using a method such as time delay control. The multiplexer circuit is a so-called multiplexing circuit, and may convert one signal path into a plurality of signal paths and transmit the signal by using a method such as time delay control. In this case, the Ns presented in the N:1 ratio of the demultiplexer circuit included in the first integrated circuit chip 210 and the 1:N ratio of the multiplexer circuit included in the second integrated circuit chip 220 may not be the same.

[0026] The first integrated circuit chip 210 can transmit the signal input via the 2-1 wiring unit 130 to the first wiring unit 120 by demultiplexing. At this time, the first integrated circuit chip 210 can select each transmission signal path. That is, the integrated circuit of the first integrated circuit chip 210 can select which wiring to use among the plurality of first wirings 121, and can be set not to use a pad connected to an open wiring.

[0027] The second integrated circuit chip 220 may multiplex the signal inputted through the first wiring unit 120 and transmit it to the 2-2 wiring unit 140. In this case, the second integrated circuit chip 220 may receive the signal through a pad connected to the first wiring unit 120.

[0028] Since the first integrated circuit chip 210 and the second integrated circuit chip 220 can operate separately from the first semiconductor chip 230 and the second semiconductor chip 240, as shown in Fig. 6a, the first integrated circuit chip 210 and the second integrated circuit chip 220 can be inspected and corrected for defects before the first semiconductor chip 230 and the second semiconductor chip 240 are mounted. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 can be externally controlled to correct the defective first wiring 121 using I2C communication, but the present invention is not limited thereto, and any communication method for controlling an integrated circuit, such as SPI communication, can be used without limitation. In this case, it can be said that it is preferable to use the I2C communication method that can be controlled without using an internal clock.

[0029] The second - 1 wiring portion 130 can correspond to an input portion input to the first integrated circuit chip 210, and the first wiring portion 120 can correspond to an output portion of the first integrated circuit chip 210. Also, the first wiring portion 120 can correspond to an input portion of the second integrated circuit chip 220, and the second - 2 wiring portion 140 can correspond to an output portion of the second integrated circuit chip 220.

[0030] At this time, when the number of the plurality of first wirings 121 is X, the number of the plurality of second - 1 wirings 131 is Y1, and the number of the plurality of second - 2 wirings 141 is Y2, Y1 / N < X can be satisfied, and Y2 / N < X can be satisfied. Satisfying Y1 / N < X can mean that, based on the first integrated circuit chip 210, the number of the plurality of first wirings 121 is more than the number of input signals converted through the first integrated circuit chip 210. Satisfying Y2 / N < X can mean that, based on the second integrated circuit chip 220, the number of the plurality of first wirings 121 is more than the number of signals converted and output through the second integrated circuit chip 220. That is, in the signal transmission process of the printed circuit board input through the second - 1 wiring portion 130 and output to the second - 2 wiring portion 140 through the first wiring portion 120, it can be meant that the plurality of first wirings 121 of the first wiring portion 120 includes a number of wirings more than the number of necessary wirings. At this time, the larger number of wirings can function as dummies, and can function as so - called dummy lanes. At this time, the number of dummy lanes can correspond to X - Y1 / N, or can also correspond to X - Y2 / N.

[0031] Many defects may occur during the manufacturing process of a printed circuit board, one of which is an open phenomenon between wirings. An open is a concept including a state in which a certain wiring is broken midway or a state in which resistance is excessively high, and may mean a state in which two components cannot be electrically connected. That is, a process of patterning wiring includes a step of removing at least a part of metal constituting the wiring, and at this time, a part of the metal that should be connected by the wiring is removed, and an open defect occurs. In general, if an open occurs during wiring patterning, the corresponding printed circuit board is defective and cannot perform its function. However, since the printed circuit board according to an example realizes a number of first wirings 121 that is more than the required number, even if an open phenomenon occurs in one of the wirings, it can be used by changing it to another excess wiring. That is, a signal can be transmitted by detouring the defective wiring through lane shifting without using the defective wiring. At this time, lane shifting can be performed by immediately changing the defective lane to a dummy lane, rather than sequentially changing lanes after the lane in which the defect occurs.

[0032] FIG. 3 shows the first wiring portion 120 where no open phenomenon occurs, and FIG. 4 is a plan view showing the first wiring portion 120 where an open phenomenon has occurred. As a non-limiting specific example, the first integrated circuit chip 210 is represented as performing a 1:2 signal conversion, and the second integrated circuit chip 220 is represented as performing a 2:1 signal conversion. The number of input signals input to the first integrated circuit chip 210 and the number of output signals output via the second integrated circuit chip 220 are represented as 16. Also, the plurality of first wirings 121 of the first wiring portion 120 are represented as being 10. That is, as shown in FIGS. 3 and 4, X can correspond to 10, Y1 and Y2 can correspond to 16, and N can correspond to 2, satisfying Y1 / N < X and Y2 / N < X. However, this is merely an example, and the number of signals and wirings is not limited thereto. As shown in FIG. 3, the number of first wirings 121 required in the first wiring portion 120 is 8, but the plurality of first wirings 121 are realized as 10, and two of the first wirings 121 can correspond to dummy lanes.

[0033] Referring to FIG. 4, at least one of the first wirings 121 may be opened. By opening at least one of the first wirings 121, the first integrated circuit chip 210 and the second integrated circuit chip 220 may not be connected through the opened wiring. That is, the opened wiring cannot electrically connect the first integrated circuit chip 210 and the second integrated circuit chip 220. This is because a defect phenomenon due to an open occurs in a stage of realizing the first wiring 121 in a stage of manufacturing a printed circuit board. However, the defect can be dealt with by bypassing the opened wiring by the first integrated circuit chip 210 and the second integrated circuit chip 220 to a dummy lane without using the wiring where the defect occurs. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 can be designed by using a dummy lane without using the wiring where the defect occurs. However, the present invention is not limited thereto, and lane shifting can be performed by skipping the wiring where the defect occurs and sequentially connecting from the next wiring. In one example, the printed circuit board can detect defects that occur in the first wiring section 120 before the first semiconductor chip 230 and the second semiconductor chip 240 are mounted, and therefore it may be more advantageous to design the defective wiring to be directly bypassed to a dummy lane rather than using the first semiconductor chip 230 and the second semiconductor chip 240 to move the defective wiring one square at a time.

[0034] In this case, if the number of open wirings among the plurality of first wirings 121 is Z, Y1 / N≦XZ and Y2 / N≦XZ can be satisfied. That is, the printed circuit board can be designed by including a number of dummy lanes that is greater than the number of wirings in which defects due to opening have occurred. That is, if the dummy lanes are designed at the design stage, it can be meant that even if a certain number of defects occur, normal operation is possible through lane shift to the dummy lanes. When a wiring defect occurs in a general printed circuit board, it cannot perform its original function and is discarded, but the printed circuit board according to the example can be diverted to the dummy lanes even if a defect occurs, so that a certain level of defect is not recognized as a defect of the entire printed circuit board. That is, even if a defect occurs in a part of the first wiring part 120, the entire printed circuit board does not become defective, and it can operate as a good printed circuit board. Therefore, the yield of the printed circuit board can be improved.

[0035] Meanwhile, referring to FIG. 5, in the first wiring unit 120, at least two of the plurality of first wirings 121 may be shorted to each other. When at least two of the plurality of first wirings 121 are shorted to each other, the first integrated circuit chip 210 and the second integrated circuit chip 220 may not be able to transmit and receive electrical signals due to the shorted wiring. That is, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be shorted to each other and not be electrically connected to each other. In this case, the fact that the first integrated circuit chip 210 and the second integrated circuit chip 220 are not connected does not mean that they are not physically connected, but means that electrical signals cannot be transmitted from the first integrated circuit chip 210 to the second integrated circuit chip 220. That is, the short circuit phenomenon refers to a defect occurring during the manufacturing process of the printed circuit board. However, the printed circuit board according to an example can deal with the defect by bypassing the two wirings shorted by the first integrated circuit chip 210 and the second integrated circuit chip 220 to different dummy lanes, without using them. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be designed by using a dummy lane without using the wire in which the defect occurs. However, the present invention is not limited to this, and lane shifting may be performed by skipping the wire in which the defect occurs and sequentially connecting the next wire. Since the printed circuit board according to an example can detect a defect occurring in the first wiring unit 120 before the first semiconductor chip 230 and the second semiconductor chip 240 are mounted, it may be more advantageous to design the wire in which the defect occurs to be directly bypassed to the respective dummy lanes rather than using the first semiconductor chip 230 and the second semiconductor chip 240 to move the wire in which the defect occurs one square at a time.

[0036] As for defects due to shorts, similarly to defects due to open circuits, the number of dummy lanes can be designed to be greater than the number of wirings in which shorts have occurred. That is, if the number of wirings in which shorts have occurred is Z, then, as described above, Y1 / N≦XZ and Y2 / N≦XZ can be satisfied. In the case of a short circuit, since a short circuit occurs between at least two or more different wirings among the multiple first wirings 121, Z can be greater than 2 in the case of a short circuit. At this time, a short circuit does not occur only in one part, and two or more short circuits may occur, and a defect in which three or more first wirings 121 are shorted may occur.

[0037] In addition, wiring defects of the printed circuit board may be more diverse than those shown in FIG. 4 or FIG. 5. For example, the open defect shown in FIG. 4 and the short defect shown in FIG. 5 may occur simultaneously. As another example, wiring defects may occur in various ways, such as an increase in resistance due to impurities, or a defect in a part of the wiring due to undulation. Without being limited thereto, a defect in a via connected to the wiring may occur, or a defect occurring during connection of the first wiring unit 120 and the first integrated circuit chip 210 and / or the second integrated circuit chip 220, such as a defect occurring during soldering, may occur. That is, various defects can be overcome by changing the wiring to a dummy lane as described above, and a good printed circuit board can be provided.

[0038] The printed circuit board according to the embodiment can control defects caused by opening even before the first semiconductor chip 230 and the second semiconductor chip 240 are mounted. For example, in general printed circuit boards and packages, defects are generally controlled after all semiconductor chips are mounted, but the printed circuit board according to the embodiment can control defects even before the first semiconductor chip 230 and the second semiconductor chip 240 are mounted. Wiring defects can be inspected in a state in which the first integrated circuit chip 210 and the second integrated circuit chip 220 are mounted, and other wiring is used using the first integrated circuit chip 210 and the second integrated circuit chip 220 according to the inspection result, so that the design freedom for the semiconductor chip can be improved. That is, in general cases, a semiconductor chip equipped with a lane shift function must be used, and a separate correction step is required through the semiconductor chip, whereas the printed circuit board according to the embodiment can freely use the first wiring 121 regardless of the semiconductor chip, so that no separate power consumption is required and wiring defects of the printed circuit board can be overcome before the semiconductor chip is mounted. That is, unlike a general printed circuit board or semiconductor package, the printed circuit board according to an example can control defective wiring even if the first semiconductor chip 230 and the second semiconductor chip 240 are not mounted. That is, as shown in Figures 3 and 4, even if the first semiconductor chip 230 and the second semiconductor chip 240 are not included, the printed circuit board according to an example can complete a quality inspection and function as a printed circuit board.

[0039] In the printed circuit board according to an example, the first semiconductor chip 230 and the second semiconductor chip 240 may be electrically connected to each other, and may have a signal path connected to the 2-1 wiring unit 130, the first integrated circuit chip 210, the first wiring unit 120, the second integrated circuit chip 220, the 2-2 wiring unit 140, and the second semiconductor chip 240. The signal path may be confirmed by analyzing each layer of the completed printed circuit board one by one. That is, before the first semiconductor chip 230 and the second semiconductor chip 240 are connected, or in a state in which the first semiconductor chip 230 and the second semiconductor chip 240 are removed, it may be confirmed whether the 2-1 wiring unit 130 and the 2-2 wiring unit 140 are connected to each other by removing one by one from the upper layer based on the first wiring unit 120 connected to the first integrated circuit chip 210 and the second integrated circuit chip 220, and by repeating this, it may be confirmed that the signal path is formed. However, the present invention is not limited to this, and any other method for analyzing the signal path may be used without limitation.

[0040] 3 and 4 mainly illustrate the wiring connection between the first integrated circuit chip 210 and the second integrated circuit chip 220, with the first wiring unit 120 of the printed circuit board at the center. Since the arrangement of the first integrated circuit chip 210 and the second integrated circuit chip 220 within the printed circuit board and the arrangement relationship between the first wiring unit 120, the 2-1 wiring unit 130, and the 2-2 wiring unit 140 may vary, the arrangement relationship will be described in detail below with reference to cross-sectional views.

[0041] 6a and 6b are schematic plan views of a printed circuit board according to an example.

[0042] The first insulating part 110 may include a plurality of first insulating layers 111, and each of the first insulating layers 111 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, and / or glass fabric) together with such a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 111 may be an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), but is not limited thereto, and may be Ajinomoto Build-up Film (ABF), Photo Imageable Dielectric (PID), FR-4, Bismaleimide Triazine (BT), etc. However, it is not limited thereto, and other polymeric materials having excellent rigidity may be used as necessary. The first insulating layer 111 may include an insulating layer corresponding to a core layer.

[0043] The first wiring unit 120 disposed on or within the first insulating unit 110 may include a plurality of first wirings 121 and a plurality of first vias 122. Each of the plurality of first wirings 121 and the plurality of first vias 122 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first wirings 121 may include, but are not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included.

[0044] Each of the first wiring 121 and the first via can perform various functions according to the design of the corresponding layer. For example, it can include a ground pattern / via, a power pattern / via, a signal pattern / via, etc. Here, the signal pattern can include a pattern / via for transmitting various signals, such as a data signal, other than the ground pattern / via, the power pattern / via, etc. These patterns can each include a line pattern, a plane pattern, and / or a pad pattern.

[0045] Each of the first vias 122 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of the via hole. The microvias may be arranged in a stacked type and / or a staggered type.

[0046] The first wiring 121 and the first via 122 may be formed integrally with each other, but are not limited thereto. The first wiring 121 and / or the first via 122 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive method, but are not limited thereto, and any method that can form a circuit on a printed circuit board can be used without limitation.

[0047] The 2-1 wiring unit 130 and the 2-2 wiring unit 140 may also be disposed on or within the first insulating unit 110, and may include a 2-1 wiring 131 and a 2-1 via 132, and a 2-2 wiring 141 and a 2-2 via 142, respectively. The 2-1 wiring unit 130 and the 2-2 wiring unit 140 may be coupled to the first integrated circuit chip 210 and the second integrated circuit chip 220, respectively. In addition, the 2-1 wiring unit 130 and the 2-2 wiring unit 140 may be coupled to the first semiconductor chip 230 and the second semiconductor chip 240 on the opposite side, respectively.

[0048] The 2-1 wiring 131 and the 2-2 wiring 141 included in the 2-1 wiring section 130 and the 2-2 wiring section 140 may have the same characteristics as the first wiring 121, respectively, but are not necessarily limited to this and may be configured differently. Similarly, the 2-1 via 132 and the 2-2 via 142 may have the same characteristics as the first via 122, respectively.

[0049] Meanwhile, the printed circuit board according to an example may further include a third wiring unit 150 disposed on or within the first insulating unit 110. The third wiring unit 150 may be connected to the first integrated circuit chip 210 and the second integrated circuit chip 220, and may also be connected to the first semiconductor chip 230 and the second semiconductor chip 240. The third wiring unit 150 may include a third wiring 151 and a third via 152, which may have the same characteristics as the first wiring 121 and the first via 122, respectively, but are not necessarily limited thereto. The third wiring unit 150 may be distinguished from the first wiring unit 120, the 2-1 wiring unit 130, and the 2-2 wiring unit 140 in that the third wiring unit 150 is not for connecting any two of the first semiconductor chip 230, the second semiconductor chip 240, the first integrated circuit chip 210, and the second integrated circuit chip 220.

[0050] The first integrated circuit chip 210 and the second integrated circuit chip 220 may each include a body 211, 221 and pads 212, 222. An integrated circuit may be implemented inside the body 211, 221, and may be mounted on a printed circuit board via the pads 212, 222. The features of the first integrated circuit chip 210 and the second integrated circuit chip 220 can be applied to the above-mentioned description, so a duplicate description will be omitted.

[0051] Meanwhile, the printed circuit board according to an example may include a connecting member 300 for connecting the first integrated circuit chip 210 to the first wiring unit 120, the 2-1 wiring unit 130, and the third wiring unit 150, respectively, or for connecting the second integrated circuit chip 220 to the first wiring unit 120, the 2-2 wiring unit 140, and the third wiring unit 150, respectively. The connecting member 300 may be formed of a conductive material, for example, solder, but the material of the connecting member 300 is not particularly limited thereto. The connecting method of the connecting member 300 is not limited thereto, and may be formed of a land, a ball, a pin, or the like. The connecting member 300 may be formed in a multi-layer or single layer. When formed in a multi-layer, it may include copper pillars and solder, and when formed in a single layer, it may include solder made of tin-silver or copper, but is not limited thereto. The number, intervals, arrangement, etc. of the connecting members 300 are not particularly limited, and can be easily modified by a person of ordinary skill in the art according to design requirements.

[0052] On the other hand, the first integrated circuit chip 210 and the second integrated circuit chip 220 can be used without restrictions as long as they include the above-mentioned circuits, and can have other functions in addition to the above, and can also realize functions such as a controller, processor, memory, etc. like other semiconductor chips.

[0053] Referring to FIG. 6 b , the printed circuit board according to an example may further include a first semiconductor chip 230 and a second semiconductor chip 240 .

[0054] Each of the first semiconductor chip 230 and the second semiconductor chip 240 may be an integrated circuit (IC) in which hundreds to millions of circuits are integrated in one chip. Each of these may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, specifically, an application processor (AP: Application Processor), but is not limited thereto, and may be a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC) memory controller (MC: Memory Controller) chip, or a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable and programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM), and it goes without saying that these may be arranged in combination with each other.

[0055] The first semiconductor chip 230 and the second semiconductor chip 240 may each be composed of a body 231, 241 and pads 232, 242, and the surface on which the pads 232, 242 for connection to a wiring portion of a printed circuit board are arranged is an active surface, and the opposite surface is an inactive surface. Each of the first semiconductor chip 230 and the second semiconductor chip 240 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material for the bodies 231, 241. Various circuits may be formed in the bodies 231, 241 of the first semiconductor chip 230 and the second semiconductor chip 240.

[0056] The first semiconductor chip 230 may be connected to the 2-1 wiring portion 130 and the third wiring portion 150 via connecting members 300, respectively, and the second semiconductor chip 240 may be connected to the 2-2 wiring portion 140 and the third wiring portion 150 via connecting members 300, respectively.

[0057] The wiring parts of the printed circuit board according to an embodiment are connected to each other at the shortest distance, and the signal paths can be connected at the shortest distance. In particular, the 2-1 wiring part 130 and the 2-2 wiring part 140 are preferably realized at the shortest distance. That is, the first semiconductor chip 230 and the first integrated circuit chip 210 are preferably connected at the shortest distance, and the second integrated circuit chip 220 and the second semiconductor chip 240 are preferably connected at the shortest distance, but are not necessarily limited thereto. Since the first integrated circuit chip 210 and the second integrated circuit chip 220 are used to correct defects occurring in the first wiring part 120, the first semiconductor chip 230 and the first integrated circuit chip 210 and the second semiconductor chip 240 and the second integrated circuit chip 220 are connected at the shortest distance, thereby reducing the defect rate.

[0058] Meanwhile, the printed circuit board according to an example is not limited to the configuration shown in Figures 6a and 6b. In particular, other insulating layers and wiring layers may be further included under the first insulating part 110, and although Figures 6a and 6b may only show the upper side of the printed circuit board, the printed circuit board may further include other general configurations of the printed circuit board. For example, the printed circuit board according to an example may further include a solder resist layer. That is, the printed circuit board may further include configurations that can be utilized by a person having ordinary skill in the art.

[0059] 7a and 7b are cross-sectional views that diagrammatically show a printed circuit board according to another example.

[0060] 7a and 7b, the first insulating unit 110 may further include a cavity C penetrating at least a portion of the plurality of first insulating layers 111. Although the cavity C is shown penetrating at least a portion of the plurality of first insulating layers 111, the cavity C is not limited thereto and may penetrating only a portion of any one of the insulating layers. As a method for forming the cavity C, a known cavity forming method may be used, and it goes without saying that the shape of the cavity C may also be various since there are various methods for forming the cavity C.

[0061] Meanwhile, among the configurations other than the cavity C, the same configurations as those of the printed circuit board according to one example can also be applied to the printed circuit board according to the other example, so a duplicated description thereof will be omitted.

[0062] 8a and 8b are cross-sectional views that diagrammatically show a printed circuit board according to yet another example.

[0063] 8a and 8b, the first insulating part 110 may further include a core 112. The core 112 may include a material including inorganic filler, organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric) together with resin, and may be an insulating material such as PPG (Prepreg), RCC (Resin Coated Copper), CCL (Copper Clad Laminate), etc., but is not limited thereto. In this case, the core 112 may be thicker than the first insulating layer 111. Also, the core 112 may include a cavity C.

[0064] The first integrated circuit chip 210 and the second integrated circuit chip 220 may be mounted in the cavity C, and may be connected to each other through vias. That is, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be connected to the first wiring 121 through the first via 122. Also, the first integrated circuit chip 210 may be connected to the 2-1 via 132 and the third via 152, respectively, and the second integrated circuit chip 220 may be connected to the 2-2 via 142 and the third via 152, respectively. In this case, the first semiconductor chip 230 may be disposed directly above the first integrated circuit chip 210. In this case, it may be advantageous for the first semiconductor chip 230 and the first integrated circuit chip 210 to be connected to each other at the shortest distance. The first semiconductor chip 230 and the first integrated circuit chip 210 may be connected to each other through the 2-1 via 132. At this time, the 2-1 via 132 has a stacked via structure, thereby allowing the first semiconductor chip 230 and the first integrated circuit chip 210 to be connected in the shortest distance. The second semiconductor chip 240 and the second integrated circuit chip 220 may have the same arrangement, but are not necessarily limited thereto.

[0065] Meanwhile, among the configurations other than the arrangement and connection of the first insulating part 110 and the first integrated circuit chip 210 and the second integrated circuit chip 220, the configurations similar to those of the printed circuit board according to one example and the printed circuit board according to another example can also be applied to the printed circuit board according to the other example, and therefore, repeated explanations regarding this will be omitted.

[0066] 9a and 9b are cross-sectional views that diagrammatically show a printed circuit board according to yet another example.

[0067] 9a and 9b, the first semiconductor chip 230 may be disposed directly above the first integrated circuit chip 210 so as to overlap a portion of the first integrated circuit chip 210. In this case, the first semiconductor chip 230 and the first integrated circuit chip 210 may be connected at the shortest distance, and the 2-1 via may have a stacked via structure. The second semiconductor chip 240 and the second integrated circuit chip 220 may have the same arrangement, but are not necessarily limited thereto.

[0068] On the other hand, among the configurations other than the arrangement of the first semiconductor chip 230 and the second semiconductor chip 240, the configurations similar to those of the printed circuit board of one example, the printed circuit board of another example, and the printed circuit board of yet another example can also be applied to the printed circuit board of yet another example, so duplicate explanations regarding this will be omitted.

[0069] 10a and 10b are cross-sectional views that diagrammatically show a printed circuit board according to yet another example.

[0070] 10a and 10b, the first insulating unit 110 may be disposed on the first integrated circuit chip 210 and the second integrated circuit chip 220, and may further include a second insulating layer 113 having a cavity C. The second insulating layer 113 may include an insulating material, which may be selected from the same insulating material group as the first insulating layer 111, and may include the same insulating material as the first insulating layer 111, but is not necessarily limited thereto. In this case, the second insulating layer 113 may be disposed to be spaced apart from the first insulating layer 111, and the first wiring unit 120 realized in the first insulating unit 110 may be connected to the first integrated circuit chip 210 and the second integrated circuit chip 220 via the connecting member 300.

[0071] This means that the printed circuit board according to another example may have a so-called add-on form in which the first wiring unit 120 connecting the first integrated circuit chip 210 and the second integrated circuit chip 220 is attached as a separate structure. With respect to the first insulating unit 110 connecting the first integrated circuit chip 210 and the second integrated circuit chip 220, defects occurring in the first wiring unit 120 realized in the first insulating unit 110 can be overcome. By making such a structure possible, it is possible to deal with wiring defects occurring in a connection structure connecting semiconductor chips to each other.

[0072] At this time, the first integrated circuit chip 210 and the first semiconductor chip 230 may be directly connected via the connecting member 300, and the second integrated circuit chip 220 and the second semiconductor chip 240 may be directly connected via the connecting member 300. Since the semiconductor chip and the integrated circuit chip can be directly connected, the 2-1 wiring unit 130 and the 2-2 wiring unit 140 may be omitted, and the defect rate that may occur when connecting the semiconductor chip and the integrated circuit chip may be reduced.

[0073] 10a and 10b, the first insulating part 110 is shown as being disposed on the second insulating layer 113, but is not necessarily limited thereto, and the first insulating part 110 may also be disposed in the cavity C of the second insulating layer 113. In this case, the first integrated circuit chip 210 and the second integrated circuit chip 220 may be disposed on the second insulating layer 113, and the first semiconductor chip 230 and the second semiconductor chip 240 may be disposed in a cavity formed in the second insulating layer 113. In this case, the first insulating part 110 and the first wiring part 120 may function as a connection structure that connects the first semiconductor chip 230 and the second semiconductor chip 240.

[0074] On the other hand, among the configurations other than the arrangement of the first insulating part 110 and the connection between the semiconductor chip and the integrated circuit chip, the configurations similar to those of the printed circuit board of one example, the printed circuit board of another example, and the printed circuit board of yet another example can also be applied to the printed circuit board of yet another example, so duplicate explanations regarding this will be omitted.

[0075] In the present invention, the cross-sectional shape may refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the planar shape may refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0076] In the present invention, for convenience, terms such as "upper side, upper portion, top surface" are used to mean a direction toward a surface on which electronic components can be mounted based on a cross section of a drawing, and "lower side, lower portion, bottom surface" are used to mean the opposite direction. However, this is a definition of directions for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by such directional descriptions.

[0077] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0078] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe each unique feature that is different from the others. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0079] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0080] 110: First insulating part 111: First insulating layer 112: Core 113: Second insulating layer 120: 1st wiring section 121: 1st wiring 122: First via 130: 2nd-1 wiring section 140: 2nd-2nd wiring section 131: 2nd-1 wiring 132: 2nd-1st Beer 141: 2nd-2nd wiring 142: 2nd-2nd beer 150: 3rd wiring section 151: 3rd wiring 152: 3rd via 210: First integrated circuit chip 220: Second integrated circuit chip 211, 221: Main unit 212, 222: Pad 230: First semiconductor chip 240: Second semiconductor chip 231, 241: Main unit 232, 242: Pad 300: Connecting member C: Cavity 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera module 1060: Antenna module 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Main board inside a smartphone 1120: Electronic components inside smartphones 1121: Antenna module inside a smartphone 1130: Camera module inside a smartphone 1140: Speaker inside smartphone

Claims

1. a first wiring section including a plurality of first wirings; a first integrated circuit chip connected to one side of the first wiring portion and converting N signals (N is a natural number) into one signal; a second integrated circuit chip connected to an opposite side of the first wiring portion and converting one signal into N signals (N is a natural number); a second wiring unit connected to the first integrated circuit chip and including a plurality of second wirings; a second-second wiring unit connected to the second integrated circuit chip and including a plurality of second-second wirings; When the number of the plurality of first wirings is X and the number of the plurality of 2-1 wirings is Y1, X and Y1 satisfy Y1 / N<X.

2. 2. The printed circuit board according to claim 1, wherein when the number of said plurality of 2-2 wirings is Y2, said X and Y2 satisfy Y2 / N<X.

3. The printed circuit board of claim 1 , wherein at least one of the plurality of first wirings is open and does not connect the first integrated circuit chip to the second integrated circuit chip.

4. 4. The printed circuit board according to claim 3, wherein when the number of the first wirings that are opened among the plurality of first wirings is Z, X, Y1, and Z satisfy Y1 / N≦X−Z.

5. 2. The printed circuit board of claim 1, wherein at least two of the plurality of first wirings are short-circuited to each other and do not connect the first integrated circuit chip and the second integrated circuit chip.

6. further comprising a first insulating portion; 2. The printed circuit board according to claim 1, wherein the first wiring portion, the second-1 wiring portion, and the second-2 wiring portion are each disposed on the first insulating portion or within the first insulating portion.

7. The printed circuit board of claim 6 , wherein the first integrated circuit chip and the second integrated circuit chip are each disposed on the first insulating portion.

8. the first insulating portion includes a plurality of first insulating layers and a cavity penetrating at least a portion of the plurality of first insulating layers; The printed circuit board of claim 6 , wherein the first integrated circuit chip is disposed within the cavity.

9. 9. The printed circuit board of claim 8, further comprising a connecting member connecting the first integrated circuit chip to the second-1 wiring portion and the first integrated circuit chip to the first wiring portion.

10. the first insulating portion includes a core layer having a through portion; The printed circuit board of claim 6 , wherein the first integrated circuit chip and the second integrated circuit chip are disposed within the via.

11. the first wiring section includes a plurality of first vias penetrating at least a portion of the first insulating section to connect the plurality of first wirings to the first integrated circuit chip or the second integrated circuit chip; The printed circuit board of claim 10 , wherein the first integrated circuit chip and the first wirings, and the second integrated circuit chip and the first wirings are connected to each other through the first vias.

12. the first integrated circuit chip includes a demultiplexer circuit; 10. The printed circuit board of claim 1, wherein said second integrated circuit chip includes a multiplexer circuit.

13. a first semiconductor chip connected to the second-1 wiring portion; The printed circuit board of claim 1 , further comprising: a second semiconductor chip connected to the second-2 wiring portion.

14. the first semiconductor chip and the first integrated circuit chip are connected at the shortest distance via the second-1 wiring portion; 14. The printed circuit board of claim 13, wherein the second semiconductor chip and the second integrated circuit chip are connected via the second-2 wiring portion at the shortest distance.

15. a first insulating portion including a plurality of first insulating layers and a plurality of cavities each penetrating a portion of the plurality of first insulating layers; a first integrated circuit chip mounted within one of the plurality of cavities, the first integrated circuit chip including a demultiplexer circuit; a second integrated circuit chip mounted within one of the plurality of cavities and including a multiplexer circuit; a second insulating portion disposed across a portion of the first integrated circuit chip and a portion of the second integrated circuit chip; a first wiring portion disposed on or within the second insulating portion and connecting the first integrated circuit chip and the second integrated circuit chip; the first wiring section includes a plurality of first wirings, At least one of the plurality of first wirings is open, or at least two of the plurality of first wirings are short-circuited, so that the first integrated circuit chip and the second integrated circuit chip are not connected to each other.

16. a first semiconductor chip disposed across another portion of the first integrated circuit chip and a portion of the first insulating portion; The printed circuit board of claim 15 further comprising a second semiconductor chip disposed across another portion of the second integrated circuit chip and a portion of the first insulating portion.

Images