Semiconductor device and manufacturing method of them

Abstract

To provide a semiconductor device and a manufacturing method of them.SOLUTION: A semiconductor device contains: a semiconductor overlapping layer containing a first type semiconductor layer and a second type semiconductor layer; a protection layer that is positioned onto the semiconductor overlapping layer, and includes n first open holes and m second open holes; a first electrode that is positioned onto the n first open holes, and is electrically connected to the first type semiconductor layer while having a first outer surface; a second electrode that is positioned onto the m second open holes, and is electrically connected to the second type semiconductor layer while having a second outer surface; a first conductive bump that is positioned onto the first electrode, and includes a first top part projected to an outside; and a second conductive bump that is positioned onto the second electrode, and includes a second top part projected to the outside. In a cross-sectional view, a contact surface of the first conductive bump and the first electrode includes a first horizontal width, and a contact surface of the second conductive bump and the second electrode includes a second horizontal width. A ratio of the first and second horizontal width is 0.8 to 1.2. Both of the first and second top parts actually has the same horizontal height.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to an electrical connection structure of a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In semiconductor manufacturing processes, wiring layers at different horizontal heights are usually connected through conductive materials filled into holes in dielectric layers, but filling these holes at different depths completely with conductive materials to form a flat surface usually requires multiple steps, making the process complicated and expensive.

[0003] In addition, semiconductor wafer package structures typically use conductive bumps to establish electrical connection with external circuits, but conventional conductive bump manufacturing methods often fail to accurately control the height of the conductive bumps, resulting in the apexes of multiple conductive bumps on the semiconductor wafer not being flush with each other, which affects the production yield of the semiconductor wafers. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, embodiments of the present disclosure provide a method for precisely controlling the size of an electrical connection structure in a semiconductor device, such as precisely controlling the height of a conductive bump in a semiconductor device, and a semiconductor device manufactured by this process. [Means for solving the problem]

[0005] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a semiconductor superposition layer including a first type semiconductor layer and a second type semiconductor layer; a protective layer located on the semiconductor superposition layer and having n first openings and m second openings; a first electrode located in the n first openings, having a first outer surface and electrically connected to the first type semiconductor layer; a second electrode located in the m second openings, having a second outer surface and electrically connected to the second type semiconductor layer; a first conductive bump located on the first electrode and having a first apex protruding outward; and a second conductive bump located on the second electrode and having a second apex protruding outward, wherein, in a cross-sectional view, a contact surface between the first conductive bump and the first electrode has a first horizontal width, and a contact surface between the second conductive bump and the second electrode has a second horizontal width, a ratio of the first horizontal width to the second horizontal width is 0.8 to 1.2, and the first apex and the second apex have substantially the same horizontal height.

[0006] In order to facilitate understanding of the following content, the present disclosure may be referred to in conjunction with the drawings and its detailed description. Through specific examples in this specification and with reference to the corresponding drawings, the embodiments of the present disclosure will be described in detail, and the working principles of the specific examples of the present disclosure will be described. Note that the features in the drawings may not be drawn to actual scale for clarity. Therefore, the dimensions of some features in some drawings may be intentionally enlarged or reduced. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 1 is a perspective view of a semiconductor device according to one embodiment of the present disclosure. [Figure 1B] 1B is a cross-sectional view of the semiconductor element of FIG. 1A taken along line AA'. [Figure 2A] FIG. 1 is a perspective view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2B] 2B is a cross-sectional view of the semiconductor element of FIG. 2A taken along line BB'. [Figure 3A] 1 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure; [Figure 3B]1 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure; [Figure 4] 1 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure; [Figure 5A] 1 is a flow diagram for fabricating a semiconductor device according to one embodiment of the present disclosure. [Figure 5B] 1 is a flow diagram for fabricating a semiconductor device according to one embodiment of the present disclosure. [Figure 5C] 1 is a flow diagram for fabricating a semiconductor device according to one embodiment of the present disclosure. [Figure 5D] 1 is a flow diagram for fabricating a semiconductor device according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present disclosure provides several different embodiments that can be used to realize various features of the present disclosure. For ease of explanation, the present disclosure also describes examples of specific components and configurations. These embodiments are provided for illustrative purposes only and are not intended to be limiting. Various embodiments of the present disclosure may use repeated reference numbers and / or annotations. These repeated reference numbers and annotations are used to make the description more concise and clear, and are not intended to show a relationship between different embodiments and / or configurations.

[0009] Additionally, spatial descriptors used in this disclosure, such as "below...", "low", "below", "upper", "above", "top", "top", "bottom" and the like, are all used for convenience of description to describe the relative relationship of one element or feature in the figures to another element or feature(s). In addition to the orientation shown in the figures, these spatial descriptors are also used to describe the orientation of each element during use and operation. When elements are oriented differently (rotated 90 degrees or at other orientations), the relative descriptors used to describe the orientation should be interpreted accordingly.

[0010] In the present disclosure, terms such as first, second, and third are used to describe elements, members, regions, layers, and / or sections, but it should be understood that the elements, members, regions, layers, and / or sections are not limited by these terms. These terms are used only to distinguish one element, member, region, layer, and / or section from another element, member, region, layer, and / or section, and do not themselves imply or specify any order of elements, or indicate the order of arrangement or manufacturing process of one part from another part. Thus, a first element, member, region, layer, or section discussed below can also be referred to as a second element, member, region, layer, or section without departing from the scope of the specific embodiments of the present disclosure.

[0011] The term "about" or "substantially" used in the present disclosure generally refers to within 20%, preferably within 10%, more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities. That is, even if there is no specific description of "about" or "substantially", the meaning of "about" or "substantially" may still be implicit.

[0012] As used in this disclosure, the terms "coupled," "connected," and "electrically connected" include all direct and indirect means of electrical connection. For example, when a first member is coupled to a second member, this means that the first member may be directly electrically connected to the second member, or may be indirectly electrically connected to the second member through another device or connection.

[0013] FIG. 1A is a perspective view of a semiconductor device 1 according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of the semiconductor device 1 taken along line A-A' in FIG. 1A. The semiconductor device 1 may be a light-emitting diode (LED), a laser diode (LD), a transistor, or the like. The semiconductor device 1 has a first electrode 3a and a second electrode 3b on the opposite side to a substrate 10. The first conductive bump 2a and the second conductive bump 2b are directly disposed on the first electrode 3a and the second electrode 3b, respectively. The upper surfaces of the first conductive bump 2a and the second conductive bump 2b are arc-shaped and protrude outward, and are non-parallel to the upper surfaces of the first electrode 3a and the second electrode 3b.

[0014] The substrate 10 may be a growth substrate for the semiconductor device 1, or may be a carrier for supporting the semiconductor device 1 instead of a growth substrate. Materials for the substrate 10 include germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO 2 ), Zinc Oxide (ZnO), Gallium Nitride (GaN), Aluminum Nitride (AlN), metal, glass, Thermal Release Tape, UV release tape, Chemical Release Tape, Heat Resistant Tape, Blue Tape, or Tape with a Dynamic Release Layer (DRL).

[0015] The electrode material includes a metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), or an alloy of the above materials, or a combination of stacks of the above materials. The conductive bump material can include a low melting point metal or a low liquidus melting point alloy, for example, the melting point or liquidus melting point is less than 210°C, or for example, the conductive bump material includes bismuth (Bi), tin (Sn), indium (In), or an alloy thereof. In one embodiment, the melting point of the metal or the liquidus melting point of the alloy is less than 170°C. The alloy material can be a tin-indium alloy or a tin-bismuth alloy.

[0016] The maximum side length of the semiconductor element 1 does not exceed 100 μm, or does not exceed 50 μm. For example, the side length of the semiconductor element 1 is about 40 μm, and the width is about 20 μm. The first conductive bump 2a and the second conductive bump 2b have opposite polarities (positive and negative poles), and the minimum horizontal distance D between the two bumps 2a and 2b is less than 40 μm, for example, the maximum side length of the semiconductor element 1 is about 40 μm, and D is about 15 μm. The first conductive bump 2a and the second conductive bump 2b completely cover the electrodes (for example, the first electrode 3a and the second electrode 3b in FIG. 1B), and each has an outwardly protruding arc shape and a first apex 21a and a second apex 21b. Referring to FIG. 1A, the first apex 21a and the second apex 21b are located approximately at the geometric center of the first conductive bump 2a and the second conductive bump 2b, and / or the first electrode 3a and the second electrode 3b.

[0017] In one embodiment, the semiconductor element 1 is an example of a light-emitting diode. The semiconductor element 1 (light-emitting diode) is disposed on a substrate 10 and has a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, a second conductive bump 2b, and a lower surface 17. The outermost edge 19 of the semiconductor overlapping layer 14 is an inclined surface, and the inner included angle θ between the outermost edge 19 and a horizontal extension line H of the lower surface 17 is greater than 70° and less than 85°. The semiconductor overlapping layer 14 includes a first-type semiconductor layer 11, an active layer 12, and a second-type semiconductor layer 13. The first-type semiconductor layer 11 and the second-type semiconductor layer 13 can provide electrons and holes, respectively, and the electrons and holes are recombined in the active layer 12 to emit light. In another embodiment, the included inner angle between the outermost edge 19 of the semiconductor overlay layer 14 and the horizontal extension H of the lower surface 17 is equal to or nearly equal to 90° (not shown). The included inner angle can be modified in magnitude by subjecting the outermost edge 19 of the semiconductor overlay layer 14 to various etching processes or by adjusting the parameters of the etching process.

[0018] In one embodiment, the semiconductor device 1 is, for example, a light emitting diode, and the first type semiconductor layer 11, the active layer 12, and the second type semiconductor layer 13 are made of III-V semiconductor materials, for example Al. x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P (wherein 0≦x, y≦1, (x+y)≦1). Depending on the material of the active layer 12, the semiconductor device 1 (light emitting diode) can emit red light with a peak value of 610 nm to 650 nm, green light with a peak value of 530 nm to 570 nm, cyan light with a peak value of 500 nm to 485 nm, blue light with a peak value of 450 nm to 490 nm, violet light with a peak value of 400 nm to 450 nm, or ultraviolet light with a peak value of 280 nm to 400 nm. The maximum thickness of the semiconductor superposition layer 14 is about 10 μm or less. In one embodiment, the lower surface 17 of the first-type semiconductor layer 11 is in contact with the substrate 10 and is a rough surface having a regular or irregular texture, but the portion not in contact with the lower surface 17 of the substrate 10 is a flat surface. In another embodiment, the lower surface 17 of the first-type semiconductor layer 11 is a substantially flat surface when viewed macroscopically (not shown). In yet another embodiment, the substrate 10 is a growth substrate for epitaxially growing the semiconductor layer 14, and the entire upper surface of the substrate 10 facing the semiconductor layer 14 is a rough surface (not shown) having a regular or irregular texture, for example, the substrate 10 is a patterned sapphire substrate (PSS).

[0019] 1B, the semiconductor device 1 is disposed on the substrate 10 and includes a semiconductor overlay layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The semiconductor overlay layer 14 has a first opening 5a exposing a part of the first-type semiconductor layer 11 covered by the active layer 12 and the second-type semiconductor layer 13, and the first opening 5a also has a first inner wall 7a. The semiconductor overlay layer 14 further has a second opening 5b exposing a part of the second-type semiconductor layer 13, and the second opening 5b also has a second inner wall 7b. The protective layer 15 covers a part of the upper surface of the second-type semiconductor layer 13, the sidewall of the first-type semiconductor layer 11, the sidewall of the active layer 12, and the sidewall of the second-type semiconductor layer 13, and has an outermost upper surface 151. The bottom end of the protective layer 15 may be in direct contact with the substrate 10 (as shown in FIG. 1B) or may be separated (not shown). A portion of the first electrode 3a is located within the first opening 5a and electrically connected to the exposed first-type semiconductor layer 11, and another portion is formed on the protective layer 15 and covers a portion of the protective layer 15 around the first opening 5a. A portion of the second electrode 3b is located within the second opening 5b and electrically connected to the exposed second-type semiconductor layer 13, and another portion is located on the portion of the protective layer 15 around the second opening 5b.

[0020] The protective layer 15 can be a single layer or a multi-layer structure and is electrically insulating. The single layer material can include oxides, nitrides, or polymers. Oxides include aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), Tantalum Pentoxide (Ta 2 O 5 ) or aluminum oxide (AlO x ). The nitrides include aluminum nitride (AlN), silicon nitride (SiN x The polymer may include polyimide or benzocyclobutane (BCB). The multi-layered material may include aluminum oxide (Al2 O 3 ), silicon dioxide (SiO 2 ), titanium dioxide (TiO 2 ), niobium pentoxide (Nb 2 O 5 ), silicon nitride (SiN x ), or a combination of the above materials. The multi-layer structure may also be a Distributed Bragg Reflector (DBR).

[0021] 1B, the first conductive bump 2a is formed on the first electrode 3a and fills the first opening 5a, and the outermost surface 22a of the first conductive bump 2a is a smooth arc-shaped surface protruding outward from a macroscopic perspective. The first conductive bump 2a has a first apex 21a, which is a region where the distance between the first conductive bump 2a and the substrate 10 is maximum. The second conductive bump 2b is formed on the second electrode 3b and fills the second opening 5b, and the outermost surface 22b of the second conductive bump 2b is a smooth arc-shaped surface protruding outward from a macroscopic perspective. The second conductive bump 2b has a second apex 21b, which is a region where the distance between the second conductive bump 2b and the substrate 10 is maximum.

[0022] In practice, the bottom surfaces of the first conductive bump 2a and the second conductive bump 2b are usually conformally formed on the first electrode 3a and the second electrode 3b, respectively. If the first conductive bump 2a and the second conductive bump 2b are fabricated at the same time in the same step, the horizontal elevations of the first electrode 3a and the second electrode 3b are usually not the same, and as a result, the positions of the first apex 21a and the second apex 21b are often not at the same horizontal elevation. In order to solve the above problem, the first conductive bump 2a and the second conductive bump 2b are formed separately in separate steps by appropriately adjusting the amount of material and process conditions, so that the apex 21a of the first conductive bump 2a and the apex 21b of the second conductive bump 2b are almost at the same horizontal elevation, for example, the ratio of the height H1 to the height H2 is 0.8 to 1.2.

[0023] FIG 2A is a perspective schematic diagram of a semiconductor device 2 according to another embodiment of the present disclosure, and FIG 2B is a cross-sectional view of the semiconductor device 2 taken along line B-B' in FIG 2A. In order to later stably fix the semiconductor device 2 on a conductive circuit of a circuit board or a display panel via the conductive bumps, in one embodiment, as shown in FIG 2B, in the semiconductor device 2, the outermost surface 22a of the first conductive bump 2a is a macroscopically smooth and outwardly protruding arc shape, the outermost surface 22b of the second conductive bump 2b is a macroscopically smooth and outwardly protruding arc shape, the first apex 21a and the second apex 21b of the second conductive bump 2b are located at substantially the same horizontal height, the first inner side wall 7a in the first opening 5a has a first inclination, and the second inner side wall 7b in the second opening 5b has a second inclination, and the first inclination and the second inclination are not the same. In one embodiment, the first inclination is greater than the second inclination. That is, the first inner side wall 7a of the first opening 5a and the horizontal extension line H of the bottom surface form a first included angle θ1, and the second inner side wall 7b of the second opening 5b and the horizontal extension line H of the bottom surface form a second included angle θ2, θ1 being greater than θ2. Since the volume of the opening becomes smaller as the inclination of the inner side wall increases, when the conductive bump is formed by filling the conductive bump with the same volume of material, the height of the conductive bump becomes higher as the inclination of the inner side wall of the opening increases, provided that the material does not lose its shape. Therefore, the height of the conductive bump can be adjusted so that the first apex 21a of the first conductive bump 2a and the second apex 21b of the second conductive bump 2b are located at approximately the same horizontal height, that is, the height H1 and the height H2 are approximately equal. The manufacturing process of the conductive bump will be described later.

[0024] 3A and 3B are cross-sectional views of a semiconductor element 3 according to another embodiment of the present disclosure. In the semiconductor element 3, the outermost surface 22a of the first conductive bump 2a is a macroscopically smooth arc-shaped protruding outward, and the outermost surface 22b of the second conductive bump 2b is a macroscopically smooth arc-shaped protruding outward. The first conductive bump 2a and the second conductive bump 2b are at the same horizontal height (the ratio of height H1 to height H2 is 0.9 to 1.1) so that the semiconductor element 3 can be stably fixed on a conductive circuit of a circuit board or a display panel via the conductive bumps, and for example, the projected areas on the outermost upper surface 151 of the protective layer 15 are approximately the same size. As can be seen from FIG. 3A, the first conductive bump 2a has a first (maximum) horizontal width W1, and the second conductive bump 2b has a second (maximum) horizontal width W2. In one embodiment, the first (maximum) horizontal width W1 and the second (maximum) horizontal width W2 are equal or similar, for example, the ratio of the first (maximum) horizontal width W1 to the second (maximum) horizontal width W2 is between 0.8 and 1.2.

[0025] As shown in FIG. 3A, in one embodiment, the structure directly below the first conductive bump 2a, for example, the upper surface of the first electrode 3a (at the location directly in contact with the first conductive bump 2a) is roughened. In one embodiment, to form a rough surface on the upper surface of the first electrode 3a (at the location directly in contact with the conductive bump 2a), the upper surface of the first electrode 3a can be roughened by an etching process. In another embodiment, a part of the upper surface of the first-type semiconductor layer 11 and the outermost upper surface 151 of the protective layer 15 located below and in direct contact with the first electrode 3a can also be selectively formed with a rough upper surface by an etching process. That is, if the surface of the structure directly below the first electrode 3a (a part of the first-type semiconductor layer 11 and the protective layer 15) that is in contact with the first electrode 3a is rough, the first electrode 3a is formed conformal to the rough surface of the lower structure when the first electrode 3a is formed, so that the first electrode 3a has a rough upper surface. The detailed structure can be understood from the enlarged view of the partial region R1 in the left half of FIG. 3A.

[0026] In the process of manufacturing the conductive bump, the material of the conductive bump is first melted and turned into a liquid state. Since the surface tension of the liquid varies depending on the roughness of the contact surface, the contact angle between the material of the conductive bump and the contact surface varies depending on the roughness of the contact surface, and thus the radius of curvature and / or height (or horizontal height) of the finally formed conductive bump is modified. In general, the rougher the contact surface, the stronger the cohesive force of the material of the conductive bump, and the smaller the radius of curvature of the formed conductive bump. Thus, by fine-tuning the surface roughness of the lower structure of the material of the first conductive bump 2a and the second conductive bump 2b, the final formed height (or horizontal height) of the first conductive bump 2a and the second conductive bump 2b can be controlled, and thus the first apex 21a and the second apex 21b having the same horizontal height can be formed.

[0027] In FIG. 3A, the contact surface below the first conductive bump 2a (the first outer surface 30a of the first electrode 3a) is rougher than the contact surface below the second conductive bump 2b (the second outer surface 30b of the second electrode 3b). Therefore, the radius of curvature of the first conductive bump 2a is smaller than the radius of curvature of the second conductive bump 2b. As shown in the enlarged view of the R2 region in FIG. 3B, the contact surface below the second conductive bump 2b (the second outer surface 30b of the second electrode 3b) is rougher than the contact surface below the first conductive bump 2a (the first outer surface 30a of the first electrode 3a). Therefore, the radius of curvature of the first conductive bump 2a is larger than the radius of curvature of the second conductive bump 2b. As described above, the surface roughening process may be performed by etching the surface of the semiconductor overlay layer, and then providing a conformal rough surface to the protective layer and electrode that are laminated on top of it, or the outer surface of the electrode layer alone may be roughened by etching, and the present disclosure is not limited thereto.

[0028] 3A and 3B, a part of the outermost upper surface 151 of the protective layer 15 exposed from the periphery of the first electrode 3a or the second electrode 3b may also be rough. With such a design, even if the raw material of the conductive bump is melted and becomes liquid and then spills onto the rough outermost upper surface 151 of the protective layer 15, the surface tension of the contact surface is modified during the process by the surface roughness of the outermost upper surface 151, and thus the curvature radius of the conductive bump formed thereafter is modified.

[0029] 4 is a cross-sectional view of a semiconductor element 4 according to another embodiment of the present disclosure. In the semiconductor element 4, the outermost surface 22a of the first conductive bump 2a is a macroscopically smooth arc-shaped protruding outward, and the outermost surface 22b of the second conductive bump 2b is a macroscopically smooth arc-shaped protruding outward. The first conductive bump 2a and the second conductive bump 2b are at the same horizontal height (the ratio of height H1 to height H2 is 0.9 to 1.1) and have similar projected areas so that the semiconductor element 4 can be stably fixed on a conductive circuit of a circuit board or a display panel via the conductive bumps. As shown in FIG. 4, the first conductive bump 2a has a first (maximum) horizontal width W1, and the second conductive bump 2b has a second (maximum) horizontal width W2. In one embodiment, the first (maximum) horizontal width W1 and the second (maximum) horizontal width W2 are equal or similar, for example, the ratio of the first (maximum) horizontal width W1 to the second (maximum) horizontal width W2 is between 0.8 and 1.2.

[0030] As shown in FIG. 4, in one embodiment, the protective layer 15 has n first apertures below the first conductive bump 2a, where n=2, which are the first first aperture 5a1 and the second first aperture 5a2, respectively. The first electrode 3a is conformally disposed in the two first apertures 5a1 and 5a2 and is electrically connected to the first-type semiconductor layer 11. The protective layer 15 has m second apertures 5b below the second conductive bump 2b, where m=1. The second electrode 3b is conformally disposed in the second aperture 5b and is electrically connected to the second-type semiconductor layer 13. In the above configuration, the numbers n and m are merely examples, and the total volume in the apertures can be controlled by appropriately changing the number of apertures below the conductive bump. Therefore, when a conductive bump is manufactured using materials with similar volumes, the height at which the conductive bump is formed can be adjusted so that the conductive bump formed later has the first apex 21a and the second apex 21b of the same horizontal height (the ratio of height H1 to height H2 is 0.9 to 1.1). The ratio of the first apertures to the second apertures may differ between the cross-sectional view and the top view, depending on the cutting position of the cross-sectional view and the arrangement pattern of the apertures. In one embodiment, when the conductive bump is ignored, the number of n first apertures and m second apertures in the top view of the semiconductor element 4 may be the same or different. When n and / or m are a specific number or more, the overall shape represented by the n first apertures and / or m second apertures may be an irregular shape or a regular shape. The regular shape may be, for example, a circle, a square, a triangle, or another polygon. When n and / or m are 3 or more, the distance between two adjacent apertures may be a fixed value or an indefinite value.

[0031] 5A-5D are schematic diagrams of steps for fabricating a semiconductor device 1 according to an embodiment of the present disclosure. As shown in FIG. 5A, a plurality of semiconductor units 100 are disposed on a substrate 10. The semiconductor units 100 include a semiconductor overlapping layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor units 100 are disposed on the substrate 10 in a manner that the first electrode 3a and the second electrode 3b are spaced apart from the substrate 10. In one embodiment, the semiconductor overlapping layer 14 is a light-emitting diode, and includes a first-type semiconductor layer 11, an active layer 12, and a second-type semiconductor layer 13. The first electrode 3a and the second electrode 3b each have a correspondingly opened recess. For a detailed structure description, please refer to the relevant paragraph above. First, the first bonding pad 23a and the second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b, respectively, by using electroplating, chemical plating, or deposition. The upper surface 24a of the first bonding pad 23a and the upper surface 24b of the second bonding pad 23b are substantially conformal to the upper surfaces of the first electrode 3a and the second electrode 3b, i.e., the contours of the two are similar, and have concaves and / or rough textures. A mass of adhesive 83 is formed on the semiconductor unit 100, the first bonding pad 23a, and the second bonding pad 23b. In one embodiment, the adhesive 83 includes only resin. In another embodiment, the adhesive 83 includes resin and conductive particles (not shown) having the same composition as the bonding pads 23a and / or 23b. In one embodiment, the adhesive 83 may be formed by printing, coating, spraying, or dispensing. The printing method may include aerosol jet printing or ink-jet printing. The resin materials include thermosetting plastics and flux. The thermosetting plastics can be epoxy, silicone, polymethyl methacrylate, and episulfide.When conductive particles are included in the adhesive 83, the melting point of the conductive particles is lower than the curing temperature of the resin. In one embodiment, the material of the conductive particles can be gold, silver, copper, or tin. In another embodiment, the material of the conductive particles can be a low melting point metal or a low liquidus melting point alloy. In one embodiment, the melting point or liquidus temperature of the low melting point metal or low liquidus melting point alloy is lower than 210° C. In another embodiment, the melting point or liquidus temperature of the low melting point metal or low liquidus melting point alloy is lower than 170° C. The material of the low liquidus melting point alloy can be a tin alloy, for example, a tin-indium alloy or a tin-bismuth alloy.

[0032] As shown in FIG. 5B, the positions of the first bonding pad 23a and the second bonding pad 23b are irradiated with laser energy L, thereby heating the adhesive 83, the first bonding pad 23a, and the second bonding pad 23b. The laser energy L may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L is an infrared laser beam having a wavelength in the range of 750 to 2000 nm. As shown in FIG. 5C, during the heating process, the first bonding pad 23a and the second bonding pad 23b are melted in the adhesive 83 by the heat, and are aggregated on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles, some or all of the conductive particles after receiving the heat also move toward the first electrode 3a and the second electrode 3b), or partially overflow onto the upper surface of the protective layer around the electrodes (not shown), forming the first conductive bump 2a and the second conductive bump 2b having an arc shape protruding outward. The adhesive 83 migrates onto the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After the heating is completed, the first conductive bump 2a and the second conductive bump 2b are cured, and the adhesive 83 (or resin) covering them is also heated, but is not completely cured and is in a liquid or semi-liquid state. Next, as shown in FIG. 5D, a cleaning step is performed to remove the uncured adhesive 83 (or resin) and expose the first conductive bump 2a and the second conductive bump 2b to the outside environment. The cleaning step can be performed using a solvent, which can include N-Methylpyrrolidinone (NMP), Methyl Ethyl Ketone (MEK), Acetone (ACE), or Isopropyl Alcohol (IPA).

[0033] The above process method is merely an example of a process aspect, and the present disclosure is not limited thereto. The process of heating and reshaping the bonding pads can be applied to the formation of conductive bumps 2a, 2b having an outwardly protruding shape on the semiconductor elements 2, 3, 4 in any of the above-mentioned embodiments. By adjusting the structure of the semiconductor elements according to the above-mentioned embodiment, the final conductive bumps 2a, 2b on the semiconductor elements 2, 3, 4 can have first apex 21a and second apex 21b of substantially the same horizontal height. With such a structure, the semiconductor elements can be stably bonded when later welded and fixed on the conductive circuit of the circuit board / display panel via the conductive bumps, improving the reliability of the entire structure.

[0034] Although the present disclosure has been described above through specific embodiments, the principles of the present disclosure may be applied to other embodiments. In addition, some details may be omitted to avoid obscuring the gist of the present disclosure. These omitted details are within the knowledge of those skilled in the art. [Explanation of symbols]

[0035] 1, 2, 3, 4 Semiconductor elements 2a First conductive bump 2b Second conductive bump 3a 1st electrode 3b 2nd electrode 5a 1st hole 5a1 1st opening 5a2 Second first opening 5b 2nd hole 7a 1st inner wall 7b Second inner wall 10 Substrate 10' top surface 11 First-type semiconductor layer 12 Active layer 13 Second-type semiconductor layer 14 Semiconductor Overlay Layer 15 Protective layer 17 Lower surface 19 Outermost edge 21a 1st top 21b 2nd top 22a, 22b outermost surface 23a 1st Bonding Pad 23b Second bonding pad 24a, 24b top surface 30a 1st outer surface 30b Second outer surface 83 Adhesive 100 Semiconductor Units 151 Top outermost surface A-A', B-B' line segments D Minimum horizontal distance H horizontal line H1, H2 height L Laser Energy R1, R2 subregion W1 1st (maximum) horizontal width W2 2nd (maximum) horizontal width θ Inside included angle θ1 1st included angle θ2 2nd included angle

Claims

1. a semiconductor overlapping layer including a first type semiconductor layer and a second type semiconductor layer; a protective layer located on the semiconductor superposition layer and having n first openings and m second openings; a first electrode located within the n first openings, the first electrode having a first outer surface and electrically connected to the first-type semiconductor layer; a second electrode located within the m second openings, the second electrode having a second outer surface and electrically connected to the second type semiconductor layer; a first conductive bump located on the first electrode and having a first apex protruding outward; a second conductive bump located on the second electrode and having a second apex protruding outward; Including, In a cross-sectional view, a contact surface between the first conductive bump and the first electrode has a first horizontal width, a contact surface between the second conductive bump and the second electrode has a second horizontal width, and a ratio of the first horizontal width to the second horizontal width is between 0.8 and 1.2; The first apex and the second apex have substantially the same horizontal height.

2. 2. The semiconductor device of claim 1, wherein in the cross-sectional view, the first aperture has a first inner wall, the second aperture has a second inner wall, and an extension direction of the first inner wall and an extension direction of the second inner wall form different first and second included angles with a horizontal line, respectively.

3. The semiconductor device of claim 2 , wherein the first included angle is greater than the second included angle.

4. 2. The semiconductor device of claim 1, wherein in the cross-sectional view, the first conductive bump contacts the first outer surface and the second conductive bump contacts the second outer surface, and the first outer surface and the second outer surface have different roughnesses.

5. The semiconductor device of claim 4 , wherein the roughness of the first outer surface is greater than the roughness of the second outer surface.

6. The semiconductor device according to claim 4 , wherein the protective layer covers the first electrode and the second electrode, and n=m=1.

7. 2. The semiconductor element of claim 1, wherein in the cross-sectional view, the first conductive bump contacts a first electrode outer surface of the first electrode, the second conductive bump contacts a second electrode outer surface of the second electrode, and the first electrode outer surface and the second electrode outer surface have different roughnesses.

8. The semiconductor device according to claim 7 , wherein the roughness of the first electrode outer surface is greater than the roughness of the second electrode outer surface.

9. The semiconductor device of claim 7 , wherein the first electrode and the second electrode cover the protective layer, and n=m=1.

10. The semiconductor device according to claim 1 , wherein n and m are different in the cross-sectional view.

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