System and method for simulating quantum processor

Abstract

To propose a system for testing, developing and calibrating a quantum computing system and confirming a design object model without resort to the availability of a user-compatible quantum processor.SOLUTION: A digital processor carries out a QPU model including a representation-model set and a device-connectivity representation and simulates a quantum-processor design or physical quantum processor, thereby simulating a quantum computing system. The digital processor receives an analog waveform and generates a digital-waveform representation including a waveform-value set corresponding to a bias to be applied to a programmable device in the quantum processor. The digital processor selects a subset of waveform values based on a channel in the device-connectivity representation.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Field This disclosure generally relates to systems and methods for simulating a quantum processor. The disclosed systems and techniques can be applied to a computing system including a digital processor or a digital processor and a quantum processor. The digital processor is operable to generate a digital waveform representation based on an analog waveform and to calculate a response based on a set of waveform values ​​and physical parameter values ​​via a representation model. Additionally, systems and methods for generating and validating device connectivity representations are described. [Background technology]

[0002] background quantum computing A quantum computer is a system that uses at least one quantum mechanical phenomenon (e.g., superposition, tunneling, and entanglement) directly to perform operations on data. The elements of a quantum computer are qubits. Quantum computers can speed up certain computational problems (e.g., those that simulate quantum physics).

[0003] Quantum Annealing Quantum annealing is a computational method that can be used to find a low-energy state of a system, typically and preferably the ground state of the system. Similar in concept to classical simulated annealing, this method relies on the fundamental principle that natural systems tend toward lower energy states because lower energy states are more stable. Quantum annealing may use quantum effects (e.g., quantum tunneling) as a source of delocalization to reach the energy minimum more accurately and / or faster than classical annealing.

[0004] Adiabatic quantum computing may be considered a special case of quantum annealing. In adiabatic quantum computing, ideally, the system begins and remains in the ground state of the system throughout the adiabatic evolution. Thus, those skilled in the art will appreciate that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this specification and claims, any reference to quantum annealing is intended to include adiabatic quantum computing, unless the context requires otherwise.

[0005] Quantum annealing uses quantum mechanics as a source of randomness during the annealing process. We define the objective function (e.g., an optimization problem) as a Hamiltonian H P The algorithm is H P A random Hamiltonian H that does not commute with D We introduce quantum effects by adding: H E ∝A(t)H D +B(t)H P where A(t) and B(t) are time-dependent envelope functions. For example, A(t) can vary from a large value to essentially zero during the evolution, and H E can be considered as the expansion Hamiltonian. H D (i.e., by decreasing A(t)), the clutter is slowly removed.

[0006] Thus, in quantum annealing, the system starts with an initial Hamiltonian and, via an evolution Hamiltonian, develops a final “problem” Hamiltonian H, whose ground states encode the answer to the problem. P Expand to.

[0007] The general problem Hamiltonian includes a first component proportional to the diagonal single-qubit term and a second component proportional to the diagonal multi-qubit term, and can be of the form:

number

number

[0008] Where:

number

number

number

number

[0009] Throughout this specification, the terms "problem Hamiltonian" and "final Hamiltonian" are used interchangeably unless the context requires otherwise. Certain states of a quantum processor are energetically favored, or simply preferred, by the problem Hamiltonian. These states include ground states, but may also include excited states.

[0010] Hybrid computing systems including quantum processors The hybrid computing system may include a digital computer communicatively coupled to an analog computer. In some implementations, the analog computer is a quantum computer and the digital computer is a classical computer. The quantum computer may be a gate model quantum computer or a quantum computer that performs adiabatic quantum computing. The digital computer may include a digital processor operable to perform classical digital processing tasks described in the present systems and methods. The digital computer may include at least one system memory operable to store various sets of computer or processor readable instructions, application programs, and / or data.

[0011] A quantum computer can include a quantum processor having programmable elements (e.g., qubits, couplers, and other programmable devices). The qubits can be read out via a readout system, and the results are communicated to a digital computer. The qubits and couplers can be characterized by qubit control systems and coupler control systems, respectively. In some implementations, the qubit control systems and coupler control systems can be used to perform quantum annealing in an analog computer.

[0012] The computing system may include a server that takes a problem Hamiltonian and compiles the problem Hamiltonian into commands that are sent to a digital or analog processor. It may be advantageous for the system to include more than one server to reduce variability in problem solving throughput.

[0013] Testing, development, validation, and calibration of quantum computing systems typically require quantum processors installed in cryogenic coolers. However, installation of quantum processors can be time and resource intensive, making user-enabled quantum processors a limited resource. Furthermore, quantum processors are typically shared among many users. Some users may present large problems to the quantum processor that are computationally expensive and take a long time to solve, thus further reducing the availability of the quantum processor. In some cases, limited availability of quantum processors may be an issue when one user needs to develop a time-sensitive experiment and other users are using the quantum processor. One approach to address this issue is to implement a quantum processor scheduler that allocates time to quantum processors based on priority. However, pausing or stopping an ongoing problem to run a different experiment instead may be impractical. Another approach is to increase the number of accessible quantum processors. However, manufacturing and installation of quantum processors can be expensive and time consuming. Furthermore, in some cases, the number of programmable parameters may be limited for each device of the quantum processor, which may make the calibration process and complete validation of algorithms difficult.

[0014] The limited availability of quantum processors may reduce the efficiency of processor design. A method for designing a processor may require a design object model to be generated based on a device connectivity representation. The device connectivity representation includes a representation of devices in the processor and the interconnections of the devices extracted from the device connectivity data, and the couplings of the devices to global bias lines.

[0015] The presence, various properties, biases, and connectivity of devices (e.g., qubits, couplers, and readout devices) can be programmably extracted from the device connectivity representation. Typically, the device connectivity representation is manually generated from the design intent, and the accuracy of the device connectivity representation is verified by testing the processor structure after manufacturing. However, such manual verification methods are time consuming and highly error prone. Furthermore, manual verification methods require manufacturing processors that are expensive and not suitable for design verification.

[0016] Quantum processor calibration may include calibration rules that are used for dependency resolution and to track progress. In some cases, the calibration rules may require describing and verifying relationships between programmable devices, device connectivity, and biasing mechanisms. One approach is to generate an appropriate representation of such data, and to independently devise data structures for each calibration rule. However, designing appropriate data structures for each calibration algorithm is time consuming, especially when there is significant overlap in the requirements of the set of calibration algorithms. Furthermore, designing appropriate continuation and version control mechanisms for each calibration algorithm is time consuming, inefficient, and error prone.

[0017] Thus, there is a general need for systems and methods for testing the foundations of quantum computing systems, developing experiments for characterization and calibration procedures, and validating design object models associated with processor designs without relying on an available user-enabled quantum processor.

[0018] The above examples of the related art and limitations related to the related art are intended to be illustrative and not exhaustive. Other limitations of the related art will become apparent to those of ordinary skill in the art upon reading the specification and studying the drawings. Summary of the Invention [Problem to be solved by the invention]

[0019] overview A quantum computing system includes one or more quantum computers and / or digital computers as well as infrastructure that helps build and operate the quantum computing system. The quantum computing infrastructure may include servers, device connectivity, software APIs, etc. Typically, it is beneficial to have an existing quantum processor to test the quantum computing system infrastructure (e.g., test server capacity, device connectivity validity, software connectivity, etc.). Similarly, it is beneficial to have an existing quantum processor to develop experiments for characterization and calibration purposes and to verify the accuracy and robustness of calibration algorithms. Additionally, it is challenging to test design ideas before designing and manufacturing the actual processor.

[0020] Quantum computing systems may be shared among users, including a user who performs routine calibration and maintenance. Because only one user may have access to the quantum computing system at a time, developing time-sensitive experiments or experiments requiring extensive research may be inefficient. Furthermore, developing and testing calibration processes for future generations of quantum processors may be postponed until new processor chips are installed in the quantum computing system, which may result in delays in operating new quantum computer systems.

[0021] Therefore, there is a need for a system and method for testing, developing and calibrating quantum computing systems and validating design object models without relying on the availability of a user-enabled quantum processor.

[0022] A device object model, which represents the physical design of a device, can be generated by reading the device connectivity representation. The presence, various characteristics, biases, and connectivity of the device in a processor can be programmably extracted from the device connectivity representation. Existing approaches to validating the design object model and / or the device connectivity representation require the associated processor to be manufactured, and the validation step is manual and, as a result, error prone. Thus, there is a need for a system and method for generating a device connectivity representation and validating the design object model without requiring the manufacture of the associated processor.

[0023] Processor calibration may include a set of calibration rules that require a description of the relationships between programmable devices, device connectivity, and biasing mechanisms for each calibration instance. Designing appropriate data structures for each calibration rule is time consuming, especially when there is significant overlap in the requirements of the calibration rules. Designing appropriate continuation and version control mechanisms separately for each calibration rule is time consuming, inefficient, and error prone. Thus, a data structure that is suitable for representing a processor in many calibration instances is needed. [Means for solving the problem]

[0024] Aspect 1. A method of operation of at least one digital processor can be summarized as including generating a digital waveform representation for a set of programmable devices of a quantum processor topology, the quantum processor topology including: specifying a set of control lines capable of biasing at least one of the set of programmable devices; decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation including a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels; setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices of the quantum processor topology; and calculating a response via the representation model.

[0025] Aspect 2. The method of aspect 1, wherein generating the digital waveform representation includes generating the digital waveform representation based on an analog waveform received from a server coupled to the quantum processor.

[0026] Aspect 3. The method of aspect 1, wherein decomposing the digital waveform representation into a set of waveform values ​​includes decomposing the digital waveform representation into a set of waveform values ​​based on a set of channels in a device connectivity representation, the set of channels representing a number of communicative couplings of a set of programmable devices to a set of control lines in a quantum processor topology.

[0027] Aspect 4. The method of aspect 1, wherein identifying a subset of the set of channels in the device connectivity representation includes identifying a subset of the set of channels that represents a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in the quantum processor topology.

[0028] Aspect 5. The method of aspect 1, wherein selecting a subset of the set of waveform values ​​corresponding to a subset of the set of channels includes selecting a subset of the set of waveform values, each of which represents a bias applied to a respective quantum bit or coupler in a quantum processor topology.

[0029] Aspect 6. The method of aspect 1, wherein setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices in the quantum processor topology includes setting a plurality of physical parameter values ​​for at least one of critical current, object inductance, and capacitance of the programmable devices in the quantum processor topology.

[0030] Aspect 7. The method of aspect 1, wherein calculating the response via the representation model includes calculating the response based on a subset of the set of the plurality of physical parameter values ​​and waveform values.

[0031] Aspect 8. The method of aspect 1, wherein calculating the response via the representation model includes calculating a set of output values.

[0032] Example 9. The method of example 1 can further include converting the response to a classical state.

[0033] Example 10. The method of example 1 may further include returning a response to the user.

[0034] Aspect 11. The method of aspect 1, wherein embodying the quantum processor topology in at least one physical instance of a physical quantum processor and generating a digital waveform representation for a set of programmable devices of the quantum processor topology includes generating a digital waveform representation for the at least one physical instance of the physical quantum processor.

[0035] Aspect 12. The method of aspect 1, wherein instantiating the quantum processor topology into at least one non-physical instance of a theoretical quantum processor and generating a digital waveform representation for a set of programmable devices of the quantum processor topology includes generating a digital waveform representation for the at least one non-physical instance of the theoretical quantum processor.

[0036] Aspect 13. A system can be summarized as including at least one digital processor and at least one non-transitory computer-readable storage medium communicatively coupled to the at least one digital processor, the at least one non-transitory computer-readable storage medium storing processor-executable instructions that, when executed, cause the at least one digital processor to perform any of the methods of aspects 1-12.

[0037] Example 14. The system of example 13 may further include at least one server operable to generate a waveform based on a received Hamiltonian characterizing or representing the problem, the server being communicatively coupled to the at least one digital processor to provide the generated waveform to the at least one digital processor, and the server being communicatively coupled to the at least one quantum processor.

[0038] Aspect 15. A method of simulating a quantum processor, the quantum processor including a set of programmable devices communicatively coupled to a set of control lines, each one of the set of control lines operable to bias at least one of the set of programmable devices, wherein the method performed by the digital processor can be summarized as including: generating a digital waveform representation; decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation including a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels; setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices of the quantum processor; and calculating a response via the representation model.

[0039] Example 16. The method of example 15, wherein generating the digital waveform representation includes generating the digital waveform representation based on an analog waveform received from a server coupled to the quantum processor.

[0040] Aspect 17. The method of aspect 15, wherein decomposing the digital waveform representation into a set of waveform values ​​includes decomposing the digital waveform representation into a set of waveform values ​​based on a set of channels in a device connectivity representation, the set of channels representing a number of communicative couplings of a set of programmable devices to a set of control lines in a quantum processor.

[0041] Aspect 18. The method of aspect 15, wherein identifying a subset of the set of channels in the device connectivity representation includes identifying a subset of the set of channels that represents a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in the quantum processor.

[0042] Aspect 19. The method of aspect 15, wherein selecting a subset of the set of waveform values ​​corresponding to a subset of the set of channels includes selecting a subset of the set of waveform values, each of which represents a bias applied to a respective programmable device in the quantum processor.

[0043] Aspect 20. The method of aspect 19, wherein selecting a subset of the set of waveform values, each of which represents a bias applied to a respective programmable device in the quantum processor, includes selecting a subset of the set of waveform values, each of which represents a bias applied to a quantum bit in the quantum processor.

[0044] Aspect 21. The method of aspect 19, wherein selecting a subset of the set of waveform values, each of which represents a bias applied to a respective programmable device in the quantum processor, includes selecting a subset of the set of waveform values, each of which represents a bias applied to a coupler in the quantum processor.

[0045] Aspect 22. The method of aspect 15, wherein setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices in the quantum processor includes setting a plurality of physical parameter values ​​for at least one of critical current, object inductance, and capacitance of the programmable devices in the quantum processor.

[0046] Aspect 23. The method of aspect 15, wherein calculating the response via the representation model includes calculating the response based on a subset of the set of the plurality of physical parameter values ​​and waveform values.

[0047] Aspect 24. The method of aspect 15, wherein calculating the response via the representation model includes calculating a set of output values.

[0048] Example 25. The method of example 15 can further include converting the response to a classical state.

[0049] Example 26. The method of example 150 may further include returning a response to the user.

[0050] Aspect 27. A system for simulating a quantum processor, the quantum processor including a set of programmable devices communicatively coupled to a set of control lines, each one of the set of control lines operable to bias one of the set of programmable devices. The system can be summarized as including a digital processor and a non-transitory computer-readable storage medium storing processor-executable instructions that, when executed, cause the digital processor to perform any of the methods of aspects 15-26.

[0051] Aspect 28. A method of extracting a device object model from an integrated circuit layout, the method being performed by a digital processor, can be summarized as including autonomously by the digital processor: extracting a device schematic from a design schematic; extracting device connectivity data from the device schematic; writing the device connectivity data to a device connectivity representation; extracting a set of biases from the device connectivity data; and writing the set of biases to the device connectivity representation.

[0052] Embodiment 29. The method of embodiment 28, wherein extracting the device schematic from the design schematic includes extracting the device schematic from the design schematic that is verifiable by a layout-to-schematic tool.

[0053] Embodiment 30. The method of embodiment 28, wherein extracting the device schematic from the design schematic includes extracting the device schematic corresponding to a directed acyclic graph.

[0054] Aspect 31. The method of aspect 30, wherein extracting a device schematic corresponding to the directed acyclic graph includes extracting a device schematic including at least one atomic device node corresponding to the directed acyclic graph.

[0055] Aspect 32. The method of aspect 28, wherein extracting the device connectivity data includes extracting at least one of a device designation, a characteristic annotation, and at least one neighboring device connection.

[0056] Embodiment 33. The method of embodiment 28, wherein extracting a set of biases from the device connectivity data includes extracting a set of global biases.

[0057] Embodiment 34. The method of embodiment 33, wherein extracting the set of global biases includes extracting a set of connections electrically coupling the pad to at least one programmable device.

[0058] Example 35. The method of example 28 may further include executing the device connectivity representation to calculate the device object model.

[0059] Aspect 36. A computing system can be summarized as including at least one digital processor and at least one non-transitory processor-readable storage medium communicatively coupleable to the at least one digital processor, the non-transitory processor-readable storage medium storing at least one of the processor-executable instructions that, when executed by the at least one digital processor, cause the at least one digital processor to perform any of the methods of aspects 28-35.

[0060] Aspect 37. A method for validating a design of an analog processor including a set of programmable devices, the method being performed by a digital processor, may include autonomously loading by the digital processor a device connectivity representation based at least in part on a design implementation, the device connectivity representation including a set of characteristics characterizing at least one programmable device, identifying a set of n rules, iteratively selecting an ith rule (where 1≦i≦n) from the set of rules until the device connectivity representation passes the nth rule, and determining whether the device connectivity representation passes or does not pass the ith rule.

[0061] Example 38. The method of example 37 may further include, in response to determining that the device connectivity representation does not pass the i-th rule, iteratively identifying at least one characteristic of the set of characteristics that did not pass the i-th rule, identifying a portion of the design implementation that corresponds to the at least one characteristic that did not pass the i-th rule, and adjusting the design implementation until the device connectivity representation passes the i-th rule.

[0062] Aspect 39. The method of aspect 37, wherein identifying a set of rules includes identifying a set of rules that tests a number of programmable devices.

[0063] Aspect 40. The method of aspect 37, wherein identifying a set of rules includes identifying a set of rules that tests a number of control devices.

[0064] Aspect 41. The method of aspect 37, wherein identifying a set of rules includes identifying a set of rules that examines a set of device connectivity data characteristics.

[0065] Aspect 42. The method of aspect 37, wherein identifying a set of rules includes identifying a set of rules that examines a set of addressing line characteristics.

[0066] Aspect 43. A computing system can be summarized as including at least one digital processor and at least one non-transitory processor-readable storage medium communicatively coupleable to the at least one digital processor, the non-transitory processor-readable storage medium storing at least one of the processor-executable instructions that, when executed by the at least one digital processor, cause the at least one digital processor to perform any of the methods of aspects 37-42.

[0067] BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING In the drawings, the same reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve visibility in the drawings. Furthermore, the particular shapes of the elements as shown are not necessarily intended to convey any information regarding the actual shape of the particular elements, but may simply be selected for ease of recognition in the drawings. [Brief description of the drawings]

[0068] [Figure 1] 1 is a schematic diagram of an example computing system including a digital processor in communication with a quantum processor and a storage medium storing instructions associated with a quantum processing unit (QPU) model in accordance with the present systems and methods. [Diagram 2] 1 is a flow chart illustrating a method for simulating a quantum processor in accordance with the present systems and methods. [Diagram 3] 1 is a schematic diagram of an exemplary computing system including a digital computer and an analog computer in accordance with the present systems and methods. [Figure 4] 4 is a flow diagram of an example method for generating a device connectivity representation by a processor in accordance with the present systems and methods. [Diagram 5]4 is a flow diagram of an example method for ascertaining a device object model based on a device connectivity representation by a processor in accordance with the present systems and methods. [Figure 6] 1 is a schematic diagram of an example system for extracting and validating a design object model in accordance with the present systems and methods. [Figure 7] 7 is a diagram illustrating an example of a data structure 700 operable to represent an operating processor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] Detailed Description In the following description, certain specific details are set forth to provide a thorough understanding of various disclosed implementations. However, those skilled in the art will recognize that implementations can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communication networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of implementations.

[0070] Unless the context requires otherwise, throughout the following specification and claims, the term "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, non-recited elements or method actions).

[0071] References throughout this specification to "one implementation" or "an implementation" mean that a particular feature, structure, or characteristic described in connection with an implementation is included in at least one implementation. Thus, appearances of the phrase "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0072] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. It should also be noted that the term "or" is generally used in its sense to include "and / or" unless the context clearly indicates otherwise.

[0073] The headings and abstracts provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0074] The term "representative model" is used in this specification and the appended claims to include, for example, numerical or analytical methods, mathematical models, and physical simulations.

[0075] The term "output values" is used in this specification and the appended claims to include, for example, eigenvalues, eigenvectors output from lookup tables, from mathematical models, waveforms, and the like.

[0076] The term "device connectivity representation" is used in this specification and the appended claims to include, for example, device connectivity files, databases, graphs, and the like.

[0077] Typically, a quantum processor is accessible to only one user at a time, and as a result, it can be relatively inefficient for a user to develop time-sensitive experiments or experiments that require extensive research when many users need the quantum processor. One approach to address this problem is to use a digital processor that implements a quantum processing unit (QPU) model to represent a quantum processor for time-sensitive or research-intensive experiments.

[0078] QPU models that simulate existing physical quantum processors A QPU model includes a set of representation models that can be executed by a digital computer. In some cases, a QPU model can be considered a software platform that is a digital representation of a physical quantum processor. For example, a QPU model can be a digital representation of a physical quantum processor installed in a cryostat, and the QPU model can be used to develop test and calibration algorithms for the physical quantum processor while the physical quantum processor is unavailable. When the physical quantum processor becomes available, the test and calibration algorithms developed via the QPU model can be executed on the physical quantum processor.

[0079] The physical quantum processor includes programmable devices (e.g., qubits and couplers) in the form of superconducting quantum interference devices (SQUIDs). The QPU model can include a set of representation models (e.g., device models) each characterizing a response from each device or combination of devices in the physical quantum processor. Each representation model can digitally represent each device in the physical quantum processor. For example, a first representation model can represent a qubit in the physical quantum processor and a second representation model can represent a coupler in the physical quantum processor. The representation models can digitally represent qubits including compound Josephson junctions (JJs). An example of a qubit in the form of a JJ SQUID is described in U.S. Pat. No. 9,152,923.

[0080] QPU model to simulate quantum processor designs In some cases, a QPU model may be considered a software platform that is a digital representation of a theoretical quantum processor (i.e., a quantum processor design that has not yet been manufactured into a physical quantum processor). A QPU model implemented on a digital processor may be useful for simulating a quantum processor design because the QPU model can avoid some of the challenges associated with traditional methods of calibrating and testing a physical quantum processor.

[0081] Conventional calibration techniques require that the quantum processor be manufactured. Due to manufacturing defects, variations in the programmable devices (e.g., qubits, couplers, etc.) of the physical quantum processor may exist, which may cause poor results when performing calculations. A typical approach to address this is to adjust a set of physical parameters to at least partially homogenize the programmable devices across the physical quantum processor. Examples of such physical parameters include, but are not limited to, physical inductance, capacitance, and critical current. However, it may be difficult to adjust these physical parameters in a physical quantum processor. For example, biasing the qubits while controlling the critical current and inductance may be straightforward, but difficult. In such cases where physical parameters are difficult to control, values ​​for these physical parameters are obtained from responses from the quantum processor. However, having these values ​​as outputs rather than controllable inputs may significantly limit the capabilities of the quantum processor, since control of these physical parameters is essential for the proper operation of the quantum processor.

[0082] Therefore, the above limitations of a physical quantum processor can make a digital representation of the quantum processor (e.g., a QPU model) advantageous for calibration and design.

[0083] From the context of calibration, a digital processor implementing a QPU model can be used to simulate an existing physical quantum processor so that calibration algorithms can be run. For example, the digital processor can simulate a quantum processor that is unavailable for use by a higher priority experiment. Instead of interrupting an experiment running on a physical quantum processor, a digital processor implementing a QPU model can be used to test the computational infrastructure (e.g., server capabilities, device connectivity checks, solution connectivity, etc.) and develop calibration algorithms.

[0084] From a design context, using a digital processor implementing a QPU model to design a theoretical processor can be more flexible than using a physical quantum processor. This is because a user can input values ​​for physical parameters into a device model included in a QPU model implemented in a digital processor. However, it is difficult to adjust these physical parameters in a physical quantum processor. A digital processor implementing a QPU model allows a user to model a quantum processor design and manufacture and test a physical quantum processor without expending resources. Furthermore, the ability to adjust physical parameters in a QPU model can be useful in developing calibration algorithms for future quantum processor designs before manufacturing the quantum processor design. For example, a digital processor implementing a QPU model can be used to develop algorithms that characterize how device responses are affected by changing physical parameters. Once the relationships are better understood, learning can be applied to optimize the quantum processor design, for example, by determining the specifications and device characteristics.

[0085] The present system and method describes a digital processor implementing a QPU model that simulates a quantum processor. The digital processor is coupled to a server operable to serve the digital processor or quantum processor. The digital processor is operable to receive an analog waveform executable by the quantum processor. The digital processor is operable to generate a digital representation of the waveform (herein referred to as a "waveform representation") upon receipt of the waveform. The waveform representation can be decomposed by the digital processor into a set of waveform values. Each waveform value represents a bias applied to a programmable device in the quantum processor. The waveform values ​​can be in the form of a numeric value readable by the digital processor. The decomposition of the waveform representation into waveform values ​​can be based on a device connectivity representation implemented in the digital processor.

[0086] The device connectivity representation can be a precisely accurate representation of a quantum processor (e.g., an existing physical quantum processor or quantum processor design) and can include data that characterizes the response of programmable devices in the quantum processor. The device connectivity representation can include data that describes programmable device designations and couplings (also called "channels") between the programmable devices. For example, the device connectivity representation can include channels that describe control lines that bias compound Josephson junctions (CJJs) of a particular qubit.

[0087] The digital processor can implement a QPU model that decomposes the waveform representation into waveform values ​​based on the device connectivity representation. In one implementation, this can include determining a number of channels in the device connectivity representation for a particular programmable device, selecting a set of waveform values ​​that correspond to biases to be applied to the programmable device, and sending the set of waveform values ​​to the representation model.

[0088] The digital processor is operable to set a number of physical parameter values ​​that are implemented in a representation model. Based on the physical parameter values ​​and the waveform values, the digital processor can implement the representation model to calculate a set of output values ​​that characterize the response. In some cases, values ​​for annealing parameters including persistent currents and tunneling energies can be obtained from the set of output values.

[0089] A physical instance of a quantum processor or a design for a physical or even theoretical quantum processor has an associated topology (e.g., collection and arrangement of qubits, couplers, programming or biasing interfaces, control lines, and / or readouts (e.g., SQUIDS)) that essentially defines the quantum processor and defines the operation of the quantum processor based on applied values ​​(e.g., biases). A quantum processor topology specifies, for example, a set of control lines that can bias at least one device of a set of programmable devices.

[0090] 1 is a schematic diagram of an example computing system 100 including a digital processor 102 implementing a QPU model 104 that simulates a quantum processor 106. The digital processor 102 is in communication with a non-transitory computer-readable storage medium (not shown in FIG. 1, see FIG. 3). The system 100 includes a server 108 operable to serve the digital processor 102 and the quantum processor 106. The server 108 is communicatively coupled to both the digital processor 102 and the quantum processor 106. The server 108 is coupled to the quantum processor 106 via a set of input / output (I / O) electronics 110 (e.g., signal conductors, filters, switches, etc.) operable to transfer an analog waveform 112 to the quantum processor 106.

[0091] The server 108 may be a hardware-based server or a software-based server running on a processor-based device. The server 108 is operable to receive a Hamiltonian that characterizes or represents a problem (e.g., a problem posed by a user) and generate a waveform 112 based on the Hamiltonian. The waveform 112 may be executed by the quantum processor 106 and may be received by the digital processor 102.

[0092] In some cases, if the quantum processor 106 is unavailable, the waveform 112 is sent to the digital processor 102. For example, if the quantum processor 106 is unavailable due to another user, the waveform 112 is sent to the digital processor 102, which is in communication with a persistent processor-readable storage medium (e.g., a memory circuit, a magnetic medium, or an optical medium) that stores processor-executable instructions associated with the QPU model 104.

[0093] In other cases, the waveform 112 is sent to the digital processor 102 if the user is interested in simulating a theoretical quantum processor or quantum processor design. For example, if the user is designing a theoretical quantum processor, it may be desirable to adjust the device physical parameter values ​​114 of the theoretical quantum processor, submit the problem to the server 108, and observe the response of the QPU model 104 to optimize the theoretical quantum processor. In such a case, the quantum processor 106 of the system 100 is a theoretical quantum processor or quantum processor design. Learnings from simulating the theoretical quantum processor with the adjusted physical parameter values ​​114 can be applied to design cycles prior to manufacturing the physical quantum processor.

[0094] If the problem is to be solved in the quantum processor 106, the waveforms 112 follow the order illustrated by the dashed arrows in Figure 1. If the problem is to be solved in the digital processor 102, the waveforms 112 follow the order illustrated by the solid arrows in Figure 1. The order illustrated by the solid arrows will be explained shortly.

[0095] The waveform 112 is executable by the quantum processor 106 and is receivable by the digital processor 102. The digital processor 102 is in communication with at least one persistent storage medium that stores processor-executable instructions implementing the QPU model 104. In operation, upon receipt of the waveform 112, the digital processor 102 generates a digital waveform representation 116 that characterizes or represents a set of programmable devices 118 of the quantum processor 106. The digital processor 102 decomposes the digital waveform representation 116 into a set of waveform values ​​120a, 120b, 120c (collectively and individually 120). For ease of explanation, only three waveform values ​​120 are shown in FIG. 1. However, one skilled in the art will appreciate that the digital waveform representation 116 can be decomposed into fewer or more than three waveform values ​​120. The waveform values ​​120 can be a set of numbers that represent biases applied to the programmable devices 118 of the quantum processor 106.

[0096] The digital processor 102 is operable to identify a programmable device 118 to be simulated and implement a device connectivity representation 122. The device connectivity representation 122 includes a number of channels 124a, 124b, 124c (collectively 124), each channel representing a communicative coupling of the programmable device 118 to a control line for biasing or to another programmable device 118. For ease of explanation, only three channels 124 are shown in FIG. 1. However, one skilled in the art will appreciate that the device connectivity representation 122 can include fewer or more than three channels 124. Additionally, the device connectivity representation 122 includes data characterizing or representing device designations, device connectivity, and biases applied to the programmable device 118 in the quantum processor 106. In some implementations, the quantum processor 106 is a quantum processor design (i.e., a theoretical quantum processor). The digital processor 102 is operable to identify a subset of the channels 124 in the device connectivity representation 122 that control the programmable device being simulated, and is operable to select and transmit a corresponding subset of the waveform values ​​120 to the representation model 126.

[0097] Each waveform value 120 corresponds to a respective one of a set of biases 128 (respectively 128a, 128b, 128c) applied to a programmable device 118 of the quantum processor 106. For ease of explanation, only three biases 128 are shown in FIG. 1 . However, one skilled in the art will appreciate that fewer or more than three biases 128 can be applied to the programmable device 118. In one implementation, the waveform value 120a can correspond to a bias 128a applied to a qubit, h in the system Hamiltonian: i In one implementation, the waveform values ​​120b can correspond to biases 128b applied to the combiners that set the coupling strength, and the J ij terms (i.e., the coupling strengths of the couplers in a quantum processor).

[0098] When executing instructions associated with the QPU model 104, the digital processor 102 sets many physical parameter values ​​114. The physical parameter values ​​114 include macroscopic (i.e., directly measurable) parameter values ​​that characterize the behavior of the programmable device 118. In some cases, the physical parameter values ​​114 can be adjusted to at least partially homogenize the programmable device 118 across the quantum processor 106. The physical parameter values ​​114 can include values ​​for critical current, inductance, capacitance, or combinations thereof. In one implementation, the physical parameter is a critical current carried by a Josephson junction of the programmable device. In one implementation, the physical parameter value is a value for a capacitance across a Josephson junction of the programmable device. In one implementation, the physical parameter value is a value for an inductance in an object loop of the programmable device. At least a portion of the physical parameter values ​​114 are derived from the design of the quantum processor 106 and the programmable device 118. In some implementations, when quantum processor 106 is a theoretical quantum processor, at least a portion of the physical parameter values ​​114 are defined by an external user.

[0099] The digital processor 102 uses the representation model 126 to calculate a response in the form of a set of output values ​​130 based on the physical parameter values ​​114 and the waveform values ​​120. In some implementations, the representation model 126 characterizes or represents each response of an individual programmable device 118. In some implementations, the representation model 126 characterizes the response of many programmable devices 118. Annealing parameters of the programmable devices can be derived from the output values ​​130. The annealing parameters can provide information about the energy scale of the quantum processor 106. For example, annealing parameters such as tunneling energy and persistent current of the qubit can be derived from the output values ​​130. In some cases, the quantum processor 106 is a theoretical quantum processor or quantum processor design. In some implementations, the digital processor 102 converts the output values ​​130 to a classical state (e.g., a +1 or -1 state) and returns the classical state to the user via the digital processor 102.

[0100] In an example application of system 100 in operation, a user sends a request to server 108 to simulate biasing a programmable device 118 labeled “qubit A” in quantum processor 106 for a calibration experiment. Server 108 generates and sends waveform 112 to digital processor 102. Upon receiving waveform 112, digital processor 102 generates a digital waveform representation 116 that characterizes or represents all programmable devices 118 (e.g., “qubit A,” “qubit B,” etc.) of quantum processor 106. Digital processor 102 resolves digital waveform representation 116 into a set of waveform values ​​120 that represent the biases to be applied to all programmable devices 118 of quantum processor 106. The device connectivity representation 122 includes a first channel 124a "qubit-cjj-A" that represents a bias applied to the CJJ of "qubit A," a second channel 124b "qubit-fb-A" that represents a bias applied to the object loop of "qubit A," and a third channel 124c "qubit-cjj-B" that represents a bias applied to the CJJ of "qubit B" (note that implementations can typically use a substantially larger number of channels 124, and for simplicity of explanation here, only three channels are selected). To simulate "qubit A," the digital processor 102 identifies a subset of channels (e.g., channel "qubit-cjj-A" 124a and channel "qubit-fb-A" 124b) that represent lines communicatively coupled to "qubit A" in the device connectivity representation 122. The digital processor selects corresponding subsets of waveform values ​​120a, 120b from the waveform values ​​120 that represent instructions to bias channels “qubit-cjj-A” and “qubit-fb-A.” The digital processor 102 uses the representation model 126 to calculate a response based on the waveform values ​​120a, 120b and the physical parameter values ​​114.

[0101] In some cases, the server 108 may transmit a waveform 112 to be executed by the quantum processor 106. If a problem is to be solved by the quantum processor 106, the waveform 112 is operable to follow the sequence illustrated by the dashed arrows in FIG.

[0102] In an example implementation of the sequence illustrated by the dashed arrows, a waveform 112 can be executed by a quantum processor 106. The quantum processor 106 is operable to receive the waveform 112 via I / O electronics 110. The quantum processor 106 is operable to execute the waveform 112 and can include applying a bias 128 to the programmable device 118. The bias 128 can be applied to the programmable device 118 via a control line 132. The control line 132 can be communicatively coupled to the programmable device 118. For example, the system Hamiltonian h i A bias can be applied to the qubit via a control line that is inductively coupled to the qubit that realizes the term J ij A bias can be applied to the coupler via an inductively coupled control line that realizes the term

[0103] The quantum processor 106 is operable to calculate a response in the form of an output value 130. Annealing parameters that provide information about the quantum annealing process and energy measures (e.g., the transverse energy A(s) and the energy applied to the problem Hamiltonian B(s)) can be derived from the output value 130. Examples of annealing parameters can include persistent currents, tunneling energies, and other parameters of the programmable device 118. In some implementations, the quantum processor 106 is not operable to set the physical parameter values ​​114 and thus derive the physical parameter values. The physical parameter values ​​114 can be derived from the output value 130. Examples of physical parameters can include critical currents, inductances, and capacitances. In some cases, the output values ​​130 calculated by the QPU model 104 are within a magnitude range of the output values ​​130 calculated by the quantum processor 106 or are equal to the output values ​​130 calculated by the quantum processor 106.

[0104] 2 is a flow chart illustrating a method 200 of simulating a quantum processor in accordance with the present systems and methods. Method 200 includes acts 202-216, although other implementations may omit certain acts and / or add additional acts. Method 200 may be performed in response to instructions or a problem posed by a user by a computing system including one or more digital processors, one or more non-transitory computer-readable storage media (also referred to herein as non-transitory processor-readable storage media), and optionally a physical analog processor.

[0105] The method 200 begins at 202, for example, in response to a call from another routine.

[0106] At 204, a digital waveform representation is generated. Generating the digital waveform representation can include generating the digital waveform representation based on an analog waveform received from a server coupled to both the digital processor and the quantum processor. In one implementation, the digital waveform representation characterizes or represents a set of programmable devices in the quantum processor. In one implementation, the digital waveform representation characterizes or represents all programmable devices in a theoretical quantum processor (e.g., a quantum processor design).

[0107] At 206, the digital waveform representation is decomposed into a set of waveform values. The digital waveform representation can be decomposed into a set of waveform values ​​based on a device connectivity representation that includes a number of channels. The device connectivity representation can include data that characterizes device designations, device connectivity, and biases applied to programmable devices in the quantum processor. In one implementation, decomposing the digital waveform representation into a set of waveform values ​​can include decomposing the digital waveform representation into a set of waveform values ​​based on a number of channels that represent communicative couplings of programmable devices to control lines that bias the quantum processor.

[0108] At 208, a subset of the channels in the device connectivity representation is identified. Identifying the subset of the channels in the device connectivity representation can include identifying a subset of the channels that control a subset of the programmable devices in the quantum processor. In one implementation, identifying the subset of the channels in the device connectivity representation includes identifying a subset of the channels that control a subset of the programmable devices in a theoretical quantum processor (i.e., a quantum processor design).

[0109] At 210, a subset of waveform values ​​corresponding to the subset of channels is selected from the set of waveform values. Selecting the subset of waveform values ​​corresponding to the subset of channels can include selecting the subset of waveform values, each of which represents a bias applied to a respective programmable device in the quantum processor. The waveform values ​​are determined by the h i Each bias applied to the qubit that realizes the term, or J of the system Hamiltonian ij There can be many sets or a number of sets corresponding to respective biases applied to combiners that realize the terms (i.e., coupling strengths). In one implementation, selecting a subset of waveform values ​​corresponding to a subset of channels includes selecting a subset of waveform values, each of which represents a bias applied to a qubit in a quantum processor. In one implementation, selecting a subset of waveform values ​​corresponding to a subset of channels includes selecting a subset of waveform values, each of which represents a bias applied to a programmable device in a theoretical quantum processor (i.e., quantum processor design).

[0110] At 212, a number of physical parameter values ​​are set. The physical parameters include macroscopic (i.e., directly measurable) parameters that characterize the behavior of the programmable device. The physical parameter values ​​can be set to at least partially homogenize the programmable device across the quantum processor. Examples of physical parameters can include a critical current carried by a JJ of the programmable device, an inductance of an object loop of the programmable device, a capacitance across the JJ of the programmable device, or a combination thereof. In one implementation, setting the number of physical parameter values ​​can include setting values ​​for a critical current, an inductance, a capacitance, or a combination thereof.

[0111] At 214, a response is calculated. Computing the response may include implementing a representation model to calculate a set of output values ​​based on the number of physical parameter values ​​set at 212 and the subset of waveform values ​​selected at 210. The representation model characterizes the response of the programmable devices or the interactions between many programmable devices in the quantum processor. In some implementations, computing the response may include computing a set of output values ​​that characterize the response of a set of programmable devices in the quantum processor. In some implementations, computing the response may include computing a set of output values ​​that characterize the response of a set of programmable devices in a theoretical quantum processor (i.e., a quantum processor design). In some implementations, computing the response may further include converting the set of output values ​​to a classical state and returning the classical state to a user.

[0112] At 216, the method 200 ends, eg, until the method 200 is called again.

[0113] FIG. 3 illustrates a computing system 300 including a digital computer 302. The example digital computer 302 includes one or more digital processors 304 that can be used to perform classical digital processing tasks. The digital computer 302 may further include at least one system memory 306 and at least one system bus 308 that couples various system components, including the system memory 306, to the digital processor 304. The system memory 306 may store a QPU model instruction module 310 and other instructions. The other instructions may include methods for extracting device object models and validating processor designs. The system memory 306 may store processor-executable instructions that cause one or more processors to perform methods for collecting and modifying devices, aggregating and retrieving data from object device models, and continually managing aggregated data. The system memory 306 may store methods that are each applicable to a number of algorithms (e.g., calibration algorithms).

[0114] The system memory 306 can store data structures that represent the processors in operation. The processors in operation can include a processor being calibrated or tested. The data structures can be applied to multiple algorithms for calibration. The data structures can include representations of sets of devices, connectivity between each set of devices, unique characteristics of each device, and bias information for each device. The system memory 306 can store an interface (e.g., device connectivity representation 614 of FIG. 6) that loads the data structures and the prescribed sets for each device.

[0115] Digital processor 304 may be any logical processing unit or circuit (e.g., integrated circuit), such as, for example, one or more central processing units ("CPUs"), graphic processing units ("GPUs"), digital signal processors ("DSPs"), application specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers ("PLCs"), or the like, and / or combinations thereof.

[0116] In some implementations, the computing system 300 includes an analog computer 312, which may include one or more quantum processors 314. The digital computer 302 may be in communication with the analog computer 312, for example, via a controller 316. Certain calculations may be performed by the analog computer 312 at the direction of the digital computer 302, as described in more detail herein.

[0117] The digital computer 302 may include a user input / output subsystem 318. In some implementations, the user input / output subsystem includes one or more user input / output components (e.g., a display 320, a mouse 322, and / or a keyboard 324).

[0118] The system bus 308 may use any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. The system memory 306 may include non-volatile memory (e.g., read only memory ("ROM"), static random access memory ("SRAM"), flash NAND), and volatile memory (e.g., random access memory (RAM) (not shown)), and may include a persistent computer or processor readable storage medium.

[0119] Additionally, the digital computer 302 may include other non-transitory computer or processor readable storage media, or non-volatile memory 326. The non-volatile memory 326 may take various forms, including a hard disk drive that reads and writes to a hard disk (e.g., a magnetic disk), an optical disk drive that reads and writes to a removable optical disk, and / or a solid-state drive (SSD) that reads and writes to a solid-state medium (e.g., a NAND-based flash memory). The optical disk may be a CD-ROM or a DVD, while the magnetic disk may be a rigid rotating magnetic disk, or a magnetic floppy disk or diskette. The non-volatile memory 326 may communicate with the digital processor via a system bus 308, and may include a suitable interface or controller 316 coupled to the system bus 308. The non-volatile memory 326 may serve as long-term storage for processor or computer readable instructions, data structures, or other data (also referred to as program modules) for the digital computer 302.

[0120] Although the digital computer 302 is described as using hard disks, optical disks, and / or solid state storage media, those skilled in the art will appreciate that other types of persistent and non-volatile computer readable media (e.g., magnetic cassettes, flash memory cards, flash, ROM, smart cards, etc.) can be used. Those skilled in the art will appreciate that some computer architectures use persistent volatile memory and persistent non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory. Alternatively, solid state disks use integrated circuits to provide non-volatile memory.

[0121] Various processor or computer readable instructions, data structures, or other data may be stored in the system memory 306. For example, the system memory 306 may store instructions for communicating with remote clients and scheduling the use of resources, including resources on the digital computer 302 and the analog computer 312. Additionally, for example, the system memory 306 may store at least one of the processor executable instructions or data that, when executed by the at least one processor, cause the at least one processor to execute various algorithms that execute the instructions to perform the quantum processor simulation methods described herein. For example, the system memory 306 may store a quantum processor simulation instruction module 310 that includes processor or computer readable instructions for generating a digital waveform representation, selecting waveform values ​​corresponding to channels in the device connectivity representation, and / or calculating a response. Such definition may include, for example, decomposing the waveform representation into a set of waveform values ​​and calculating a set of output values, as described in more detail herein.

[0122] In some implementations, the system memory 306 may store processor or computer readable computational instructions and / or data that perform pre-processing, inter-processing, and post-processing for the analog computer 312. The system memory 306 may store a set of analog computer interface instructions that interact with the analog computer 312. The analog computer 312 may include at least one analog processor (e.g., quantum processor 314). The analog computer 312 may be provided in an insulating environment, e.g., an insulating environment that shields the internal elements of the quantum computer from heat, magnetic fields, and other external noise (not shown). The insulating environment may include a cooler (e.g., a dilution cooler) operable to cryogenically cool the analog processor, e.g., to a temperature of less than about 1° Kelvin.

[0123] Analog computer 312 may include programmable elements (e.g., qubits, couplers, and other programmable devices). The qubits may be read out via readout system 328. Readout results may be received by other computer or processor readable instructions of digital computer 302. The qubits may be controlled via qubit control system 330. The qubit control system 330 may include an on-chip digital-to-analog converter (DAC) and an analog line operable to bias a target device. The couplers that couple the qubits may be controlled via coupler control system 332. The coupler control system 332 may include tuning elements (e.g., on-chip DAC and analog lines).

[0124] A design object model is a representation of the data of a system (e.g., a computing system) that clearly indicates the design intent of the system, and may include a description of the input and output ports of a device in a processor (e.g., a quantum processor). A device object model that represents the physical design of the device can be generated by reading the device connectivity representation. The presence, various characteristics, biases, and connectivity of the device in the processor can be programmably extracted from the device connectivity representation. Existing approaches to verifying the design object model and / or the device connectivity representation require the associated processor to be manufactured, and the verification step is manual and, as a result, error-prone. Figures 4, 5, and 6 describe systems and methods for generating device connectivity representations and verifying the design object model without requiring the manufacture of the associated processor.

[0125] 4 is a flow diagram of an example method 400 of generating a device connectivity representation in a processor in accordance with the present systems and methods. In some implementations, the device connectivity representation generated by method 400 can be implemented in device connectivity representation 122 of FIG. 1 or method 200 of FIG. 2. In some implementations, method 400 can be followed by method 500 of FIG. 5. Method 400 includes operations 402-420, although other implementations can omit certain operations and / or add additional operations. Method 400 can be performed by a processor (e.g., digital processor 304 of FIG. 3).

[0126] The method 400 begins at 402, for example, in response to a call from another routine.

[0127] At 404, a conceptual design is generated. The conceptual design can be a representation of a user's intent for a processor design. The conceptual design can include a simulation of at least one structure or feature of the processor design. For example, the conceptual design can include a simulation of a Josephson junction in a superconducting integrated circuit.

[0128] At 406, a design implementation is generated to realize the conceptual design. The design implementation can be an integrated circuit layout. In one implementation, generating the design implementation includes designing an analog processor layout in an analog design and simulation environment.

[0129] At 408, a design schematic is generated. The design schematic may be generated based on the design implementation (i.e., the analog processor layout). In one implementation, the design schematic may be generated based on the conceptual design. The design schematic can be verified by a layout-to-schematic tool. In some implementations, the design schematic can be verified by other conventional electronic design automation tools. In one implementation, the design schematic can be generated in the same analog design and simulation environment as the design implementation.

[0130] At 410, a device schematic is extracted. The device schematic may be extracted from the design schematic. The device schematic may correspond to a directed acyclic graph. In one implementation, the device schematic includes at least one atomic device node that corresponds to an element (e.g., a vertex, a leaf, etc.) of the directed acyclic graph.

[0131] At 412, device connectivity data is extracted from the device schematic. The device connectivity data may be represented by a device connectivity graph. The device connectivity data may be extracted by a netlister, a tool that writes the device schematic to a text file, representing each feature of the device connectivity data. In one implementation, the device connectivity data is extracted by a custom-written netlister. The device connectivity data may include device characteristics and the connectivity of each device to at least one neighboring device. One example of a device characteristic is a device designation that indicates a type or function of the device. For example, the device designation may indicate that the device is a qubit. Another example of a device characteristic is a property annotation that may include metadata attached to the device. The property annotation may include at least one default property. In one implementation, extracting the device connectivity data includes extracting a device designation, a property annotation, a neighboring device connection (i.e., local bias), or a combination thereof.

[0132] Optionally, at 414, the device connectivity data is written to a device connectivity representation stored in a persistent computer-readable medium.

[0133] At 416, bias information is extracted. The bias information may be extracted from the device connectivity data by an algorithm. Extracting the bias information may include extracting a set of global biases. The global biases include biases applied to at least one device by a set of global bias lines. The global bias lines may bias the set of devices in succession. In a quantum processor, the global bias lines electrically couple pads (e.g., bonding pads) to a set of devices and apply each bias to each device. The bias information includes a representation of the electrical coupling of the pads to each set of devices in the quantum processor. In one implementation, extracting the bias information includes extracting a set of local biases that include biases applied to the device by at least one neighboring device.

[0134] The bias information is written to the device connectivity representation at 418. If operation 414 was omitted in the method 400, then both the device connectivity data and the bias information are written to the device connectivity representation at 418.

[0135] At 420, the method 400 ends, eg, until the method 400 is called again.

[0136] In some cases, the device object model can be considered as an accurate conceptual representation of the processor design. Therefore, it is desirable to perform certain checks of the device object model to verify the accuracy and completeness of the processor design. In one implementation, the check of the device object model can include checking that a specific number of qubits is included. Since the device object model can be generated by loading the device connectivity representation in memory, the device object model can be verified by checking the properties of the device connectivity representation, including the device connectivity data properties, against a list of rules. The rules depend on the specific design of the processor and indicate the design intent. An example of a rule is a processor with a specific number of qubits. The device connectivity representation is part of a chain that includes the design implementation. Thus, if a property does not pass the rule, the failing property can be identified and traced back to the design implementation, and the design implementation can be adjusted until the property passes the rule.

[0137] 5 is a flow diagram of an example method 500 of validating a device object model based on a device connectivity representation in a processor in accordance with the present systems and methods. In some implementations, method 500 can be preceded by method 400 of FIG. 4. Method 500 includes operations 502-520, although in other implementations certain operations can be omitted and / or additional operations can be added. Method 500 can be performed by a processor (e.g., digital processor 304 of FIG. 3).

[0138] The method 500 begins at 502, for example, in response to a call from another routine.

[0139] At 504, a device connectivity representation is loaded. The device connectivity representation can be based at least in part on a design implementation (e.g., a design layout). The device connectivity representation can include a set of characteristics that characterize at least one programmable device. In one implementation, loading the device connectivity representation includes loading the device connectivity representation in a calibration environment. In some implementations, loading the device connectivity representation can include loading a device object model (e.g., device object model 622 in FIG. 6).

[0140] At 506, a set of n rules is identified. The set of n rules can examine characteristics of the device connectivity representation. In some implementations, the set of n rules can examine characteristics of the device schematic, the device connectivity data, the bias information, or a combination thereof. The set of n rules can examine at least one of the following: The presence and / or number of programmable devices (e.g., qubits, combiners, shift register elements, readout elements, etc.). The completeness and / or number of control devices (e.g., digital-to-analog converters (DACs)) associated with each programmable device. Device connectivity data characteristics including the order of the qubits, the connections between the control device and the programmable device, etc. Inspect a visual representation of the shift register graph, including the connections from the qubits to the readout elements (e.g., readout routes). Addressing line characteristics including the presence of uniquely addressable DACs, speed of parallel programming, efficiency of filling addressable space, etc. Bias coloring of the device (e.g., the ability of each qubit to anneal independently from its neighbors).

[0141] In some implementations, identifying the set of n rules may include identifying a set of n rules that checks for different characteristics than the characteristics mentioned above.

[0142] At 508, an i-th rule is selected from the set of n rules, where 1≦i≦n. For example, the first rule is selected from the set of n rules.

[0143] At 510, it is determined whether the device connectivity representation passes or fails the i-th rule. For example, the digital processor can determine whether the device connectivity representation passes or fails the first rule. For example, the digital processor can determine whether the device connectivity representation includes a particular number of qubits. The device connectivity representation includes a representation of a device written from the device connectivity data. Furthermore, the device connectivity representation includes a representation of a bias written from the bias information. Each element of the device connectivity representation can be associated with a respective device connectivity data characteristic. Each device connectivity data characteristic can correspond to a portion of the design implementation of operation 504. If the device connectivity representation passes the i-th rule, perform operation 518. If the device connectivity representation does not pass the i-th rule, perform operation 512. For example, if the device connectivity representation does not pass the first rule indicating that the device connectivity representation requires a particular number of qubits, perform operation 512.

[0144] At 512, a failing device connectivity data characteristic is identified. A failing device connectivity data characteristic may not pass the first rule. For example, if the first rule indicates that the device connectivity data requires a specific number of qubits, the digital processor may identify the failing device connectivity data characteristic as the number of qubits. The device connectivity data may be extracted from a device schematic that is based on the design schematic. The design schematic may then be generated based on the design implementation. Thus, a chain including the above-mentioned elements (as depicted in system 600 of FIG. 6) may be traced from the device connectivity data to the design implementation.

[0145] At 514, a portion of the design implementation that corresponds to the failed device connectivity data characteristic is identified. For example, for a first rule indicating that the device connectivity expression requires a particular number of qubits, the design implementation may be an analog processor layout and the failed device connectivity data characteristic is the number of qubits. Thus, the digital processor may identify a portion of the analog processor layout that corresponds to the number of qubits.

[0146] At 516, at least a portion of the design implementation is adjusted until the device connectivity representation passes the i-th rule. For example, for a first rule indicating that the device connectivity representation requires a certain number of qubits, a portion of the analog processor layout may be adjusted. Adjusting the analog processor layout may directly or indirectly change the device connectivity representation, for example, by changing a failing device connectivity data characteristic. The analog processor layout may be adjusted until the device connectivity representation includes the number of qubits indicated by the first rule. In some implementations, adjusting at least a portion of the design implementation may directly or indirectly change the device connectivity representation, for example, by changing a design schematic, a device schematic, bias information, or a combination thereof.

[0147] At 518, it is determined whether the device connectivity representation passes the full set of n rules. If the device connectivity representation passes the full set of n rules, the method 500 ends at operation 520, e.g., until method 500 is called again. If the device connectivity representation does not pass the full set of n rules, or if not all rules in the set of n rules have been checked, operation 508 is performed. In such a case, the next rule (i.e., the i+1th rule) is selected at operation 508, and the next operation of method 500 is performed. For example, in at least one implementation, n=2 and the set of n rules may include a first rule indicating that the device connectivity representation requires a certain number of qubits, and a second rule indicating that the device connectivity representation requires a certain number of DACs. The digital processor may determine whether the device connectivity representation passes these two rules. If the device connectivity representation passes these two rules, the method 500 ends at 520. If the device connectivity representation passes the first rule but does not pass the second rule (i.e., it contains the required number of qubits but does not contain the required number of DACs, or the number of DACs has not been checked), then perform operation 508. Then, the second rule indicating the number of DACs is identified, and the next operation of method 500 is performed.

[0148] In some implementations, the device connectivity representation in method 500 can be replaced with a device object model. In such a case, operation 504 is replaced with an operation of loading the device object model. Loading the device object model can include extracting a representation of the device connectivity data and bias information from a device schematic. Loading the device object model can include loading the device connectivity data and bias information in a calibration software environment. The device connectivity data can include a local bias of the device relative to adjacent devices, and the bias information can include a global bias of the analog line for a set of devices.

[0149] Method 400 of Figure 4 can be used to generate a device connectivity representation, and method 500 of Figure 5 can be used to verify a device object model. At least one of methods 400 and 500 can be performed by a digital processor storing instructions that include system 600 of Figure 6.

[0150] 6 is a schematic diagram of an example system 600 for extracting and validating a design object model. The elements of system 600 may be stored on a non-transitory computer-readable storage medium that, when executed, causes a digital processor to perform operations involving the elements of system 600.

[0151] The system 600 includes a conceptual design 602, which can be a representation of a user's intent for a processor design. In one implementation, the conceptual design 602 can include a simulation of a structure (e.g., a Josephson junction) that constitutes a portion of a superconducting integrated circuit. The conceptual design 602 can be realized in a design implementation 604. The design implementation 604 can be at least a portion of a design layout. In one implementation, the design implementation 604 is at least a portion of an integrated circuit design layout. In one implementation, the design implementation 604 is at least a portion of an analog processor (e.g., a quantum processor) layout. The design implementation 604 can be generated in an analog design and simulation environment. The system 600 includes a design schematic 606 based on the design implementation 604. In some implementations, the design schematic 606 is based on the conceptual design 602. The design schematic 606 can be verified against the design implementation 604 using a layout-to-schematic tool 608 or other electronic design automation tools. In one implementation, the design implementation 604 and the design schematic 606 can be generated in the same analog design and simulation environment.

[0152] The system 600 includes a device schematic 610. The device schematic 610 can be extracted from the design schematic 606. In some implementations, the device schematic 610 can be in the form of a directed acyclic graph. For example, the device schematic 610 can include at least one atomic device node that corresponds to an element (e.g., a vertex, a leaf, etc.) of the directed acyclic graph.

[0153] The system 600 includes device connectivity data 612. The device connectivity data 612 includes device characteristics and the connectivity of each device to at least one neighboring device. In one implementation, the device connectivity data 612 can be a graph. In one implementation, the device connectivity data 612 includes a set of local biases including biases applied to a device by at least one neighboring device. One example of a device characteristic is a device designation, which can indicate a type or function of a device. For example, the device designation may indicate that the device is a qubit. Another example of a device characteristic is a characteristic annotation, which can include metadata attached to a device. The device connectivity data 612 can also be known as a netlist. The device connectivity data 612 can be written to a device connectivity representation 614.

[0154] The system 600 includes bias information 616. The bias information 616 can be extracted from the device connectivity data 612. The bias information 616 includes a set of global biases that include biases applied to at least one device by a set of global bias lines. In a quantum processor, the global bias lines electrically couple pads (e.g., bonding pads) to a set of devices and apply each bias to each device. The global bias lines can bias the set of devices in succession. The bias information 616 includes a representation of the electrical coupling of the pads to each set of devices. The bias information 616 can be written to the device connectivity representation 614.

[0155] The device connectivity representation 614 includes a representation of the programmable device 618 written from the device connectivity data 612 and a representation of the bias 620 written from the bias information 616. The device connectivity representation 614 may be read by a digital processor. In response to reading the device connectivity representation 614, the digital processor may compute a device object model 622. In some implementations, the device object model 622 may be computed by extracting the device connectivity data 612 and the bias information 616 from the device schematic 610 (i.e., without the device connectivity representation 614). The device connectivity data 612 and the bias information 616 are operable to be loaded in a calibration software environment.

[0156] The elements of the system 600 constitute a chain of reference from the conceptual design 602 to the device object model 622. The conceptual design 602 can be validated against the device object model 622. Validation 624 can include inspection of the device object model 622 to assess the conceptual accuracy of the conceptual design 602. By tracing back the chain of reference, errors can be identified. A method of validation 624 is illustrated by method 500 in FIG. 5. In some implementations, the device object model 622 is a representation of a quantum processor.

[0157] Processor calibration can include a set of calibration rules that require a description of the relationship between the programmable device, device connectivity, and biasing mechanisms for each calibration instance. Figure 7 illustrates a data structure suitable for representing a processor in many calibration instances and that includes certain elements of the system 600 of Figure 6.

[0158] 7 is a diagram illustrating an example of a data structure 700 operable to represent a processor in operation. The elements of the data structure 700 may be stored on a non-transitory computer-readable storage medium that, when executed, causes a digital processor to perform operations involving the elements of the data structure 700.

[0159] The data structure 700 includes a programmable device description and a device connectivity representation 702 that includes bias information extracted from a device schematic (e.g., device schematic 610 of FIG. 6). The device connectivity representation 702 is an interface that loads the programmable device description into memory, thereby computing a device object model. The programmable device description can include device designation, device connectivity, intrinsic characteristics of each device, and local biases for each device by neighboring devices. The programmable device description can represent a processor (e.g., an analog processor or a quantum processor) under operation. In particular, the programmable device description can represent a quantum process under calibration. Examples of programmable devices include, but are not limited to, qubits, couplers, DACs, shift register stages, readout elements, inductance tuners, process control monitoring devices, and heaters.

[0160] The data structure 700 includes a representation of ongoing calibration data 704. The calibration data 704 can be data that is aggregated in and retrieved from a device object model 710. The data structure 700 includes a representation of a programmable device definition 706. The programmable device definition 706 includes configuration property annotations, bias annotations, and connectivity annotations for each programmable device. The programmable device definition 706 includes at least one set of meta objects (e.g., structures and classes). Additionally, the data structure 700 includes instructions for programmable device methods 708, including methods for collecting and modifying devices. Some examples of programmable device methods 708 can include, but are not limited to, the following: Identifying the set of qubits bound to a particular qubit. Identifying the bias that addresses a particular DAC. Identifying the set of DACs associated with a particular device. Identifying a shift register stage that forms at least a portion of the path from the qubit to the readout.

[0161] The device object model 710 includes a programmable device representation based on the device connectivity representation 702. The data structure 700 includes instructions for a calibration algorithm 712. The calibration algorithm 712 can include methods for aggregating data and retrieving data from the programmable device representations included in the device object model 710. For example, the calibration algorithm 712 can be used to aggregate data from the device object model 710 into the device representation during calibration. The calibration algorithm 712 can include methods for managing versions of the calibration data 704 over time.

[0162] The above-described methods, processes, or techniques may be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods, processes, or techniques described above are performed in part by a dedicated device, such as an adiabatic quantum computer or quantum annealer or system that programs or otherwise controls the operation of the adiabatic quantum computer or quantum annealer (e.g., a computer including at least one digital processor). The above-described methods, processes, or techniques may include various operations, although one of skill in the art will appreciate that in alternative examples, certain operations may be omitted and / or additional operations may be added. One of skill in the art will appreciate that the illustrated order of operations is shown for illustrative purposes only and may vary in alternative examples. Some of the exemplary acts or operations of the above-described methods, processes, or techniques are performed iteratively. Some operations of the above-described methods, processes, or techniques may be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0163] The above description of example implementations, including those described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made without departing from the spirit and scope of the disclosure. The teachings set forth herein of various implementations can be applied to other methods of quantum computing (not necessarily the exemplary methods for quantum computing generally described above).

[0164] The various implementations described above can be combined to provide further implementations. All commonly-owned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referenced herein and / or listed in Application Data Sheets, including, but not limited to, U.S. Patent No. 9,152,923, U.S. Patent Application Publication No. 2007 / 0239366, U.S. Patent Application No. 62 / 873,711, filed July 12, 2019, and U.S. Patent Application No. 62 / 879,946, filed July 29, 2019, are hereby incorporated by reference in their entirety.

[0165] These and other changes can be made to the implementations in light of the above description. In general, in the claims that follow, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and claims, but rather to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Thus, the claims are not limited by the disclosure.

Claims

1. 1. A method of operation of at least one digital processor, comprising: generating a digital waveform representation for a set of programmable devices of a quantum processor topology, the quantum processor topology specifying a set of control lines capable of biasing at least one of the set of programmable devices; decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation that includes a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels; setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices of the quantum processor topology; Calculating the response via the representation model; The method includes:

2. The method of claim 1 , wherein generating the digital waveform representation comprises generating the digital waveform representation based on an analog waveform received from a server coupled to the quantum processor.

3. 2. The method of claim 1 , wherein decomposing the digital waveform representation into a set of waveform values ​​comprises decomposing the digital waveform representation into a set of waveform values ​​based on the set of channels in the device connectivity representation, the set of channels representing a number of communicative couplings of the set of programmable devices to a set of control lines in the quantum processor topology.

4. 2. The method of claim 1 , wherein identifying a subset of the set of channels in the device connectivity representation comprises identifying a subset of the set of channels that represents a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in the quantum processor topology.

5. 2. The method of claim 1 , wherein selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels comprises selecting a subset of the set of waveform values, each subset representing a bias applied to a respective qubit or coupler in the quantum processor topology.

6. 2. The method of claim 1 , wherein setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices in the quantum processor topology comprises setting a plurality of physical parameter values ​​for at least one of critical currents, object inductances, and capacitances of programmable devices in the quantum processor topology.

7. The method of claim 1 , wherein calculating a response via a representation model comprises calculating a response based on the subset of the set of the plurality of physical parameter values ​​and waveform values.

8. The method of claim 1 , wherein computing the response via the representation model comprises computing a set of output values.

9. The method of claim 1 , further comprising converting the response to a classical state.

10. The method of claim 1 , further comprising returning the response to a user.

11. 2. The method of claim 1 , wherein instantiating the quantum processor topology into at least one physical instance of a physical quantum processor and generating a digital waveform representation for a set of programmable devices of a quantum processor topology comprises generating the digital waveform representation for the at least one physical instance of the physical quantum processor.

12. 2. The method of claim 1 , wherein instantiating the quantum processor topology into at least one non-physical instance of a theoretical quantum processor and generating a digital waveform representation for a set of programmable devices of a quantum processor topology comprises generating the digital waveform representation for the at least one non-physical instance of the theoretical quantum processor.

13. at least one digital processor; at least one non-transitory computer-readable storage medium communicatively coupled to said at least one digital processor, said non-transitory computer-readable storage medium storing processor-executable instructions that, when executed, cause said at least one digital processor to perform a method according to any one of claims 1 to 12; A system including:

14. 14. The system of claim 13, further comprising at least one server operable to generate a waveform based on a received Hamiltonian characterizing or representing a problem, the server being communicatively coupled to the at least one digital processor to provide the generated waveform to the at least one digital processor, and at least one server being communicatively coupled to at least one quantum processor.

15. 1. A method of simulating a quantum processor, the quantum processor including a set of programmable devices communicatively coupled to a set of control lines, each one of the set of control lines operable to bias at least one of the set of programmable devices, the method being performed by a digital processor; generating a digital waveform representation; decomposing the digital waveform representation into a set of waveform values ​​based on a device connectivity representation that includes a set of channels; identifying a subset of the set of channels in the device connectivity representation; selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels; setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices of the quantum processor; Calculating the response via the representation model; The method includes:

16. 16. The method of claim 15, wherein generating the digital waveform representation comprises generating the digital waveform representation based on an analog waveform received from a server coupled to the quantum processor.

17. 16. The method of claim 15, wherein decomposing the digital waveform representation into a set of waveform values ​​comprises decomposing the digital waveform representation into a set of waveform values ​​based on the set of channels in the device connectivity representation, the set of channels representing a number of communicative couplings of the set of programmable devices to a set of control lines in a quantum processor.

18. 16. The method of claim 15, wherein identifying a subset of the set of channels in the device connectivity representation comprises identifying a subset of the set of channels that represents a subset of the set of programmable devices that are communicatively coupled to a subset of the set of control lines in a quantum processor.

19. 16. The method of claim 15, wherein selecting a subset of the set of waveform values ​​corresponding to the subset of the set of channels comprises selecting a subset of the set of waveform values, each subset representing a bias applied to a respective programmable device in a quantum processor.

20. 20. The method of claim 19, wherein selecting a subset of the set of waveform values, each of which represents a bias applied to a respective programmable device in a quantum processor, comprises selecting a subset of the set of waveform values, each of which represents a bias applied to a qubit in a quantum processor.

21. 20. The method of claim 19, wherein selecting a subset of the set of waveform values, each of which represents a bias applied to a respective programmable device in a quantum processor, comprises selecting a subset of the set of waveform values, each of which represents a bias applied to a coupler in a quantum processor.

22. 16. The method of claim 15, wherein setting a plurality of physical parameter values ​​characterizing at least one of the set of programmable devices in a quantum processor comprises setting a plurality of physical parameter values ​​for at least one of critical current, body inductance, and capacitance of programmable devices in a quantum processor.

23. The method of claim 15 , wherein calculating a response via a representation model comprises calculating a response based on the subset of the set of the plurality of physical parameter values ​​and waveform values.

24. The method of claim 15 , wherein computing the response via the representation model includes computing a set of output values.

25. The method of claim 15 , further comprising converting the response to a classical state.

26. The method of claim 15, further comprising returning the response to a user.

27. 1. A system for simulating a quantum processor, the quantum processor including a set of programmable devices communicatively coupled to a set of control lines, each one of the set of control lines operable to bias one of the set of programmable devices, the system comprising: A digital processor; a non-transitory computer readable storage medium storing processor executable instructions which, when executed, cause said digital processor to perform a method according to any one of claims 15 to 26; A system including:

28. 1. A method for extracting a device object model from an integrated circuit layout, the method being executed by a digital processor and autonomously performed by the digital processor, comprising: Extracting a device schematic from a design schematic; extracting device connectivity data from the device schematic; writing said device connectivity data to a device connectivity representation; extracting a set of biases from the device connectivity data; writing said set of biases into said device connectivity representation; The method includes:

29. 30. The method of claim 28, wherein extracting the device schematic from the design schematic comprises extracting the device schematic from the design schematic that is verifiable by a layout-to-schematic tool.

30. 30. The method of claim 28, wherein extracting a device schematic from a design schematic comprises extracting a device schematic that corresponds to a directed acyclic graph.

31. 31. The method of claim 30, wherein extracting a device schematic corresponding to the directed acyclic graph comprises extracting a device schematic including at least one atomic device node corresponding to the directed acyclic graph.

32. 30. The method of claim 28, wherein extracting the device connectivity data includes extracting at least one of a device designation, a characteristic annotation, and at least one neighboring device connection.

33. 30. The method of claim 28, wherein extracting a set of biases from the device connectivity data comprises extracting a set of global biases.

34. 34. The method of claim 33, wherein extracting a set of global biases includes extracting a set of connections electrically coupling the pads to at least one programmable device.

35. 30. The method of claim 28, further comprising executing the device connectivity representation to compute a device object model.

36. at least one digital processor; at least one non-transitory processor-readable storage medium communicatively couplable to said at least one digital processor, said non-transitory processor-readable storage medium storing at least one processor-executable instruction that, when executed by said at least one digital processor, causes said at least one digital processor to perform a method according to any one of claims 28 to 35; A computing system comprising:

37. 1. A method for validating a design of an analog processor including a set of programmable devices, the method being performed by a digital processor and autonomously performed by the digital processor, the method comprising: loading a device connectivity representation based at least in part on the design implementation, the device connectivity representation including a set of characteristics characterizing at least one programmable device; identifying a set of n rules; iteratively until the device connectivity expression passes the nth rule; selecting an i-th rule from said set of rules, where 1≦i≦n; determining whether the device connectivity expression passes or fails the i-th rule; The method includes:

38. in response to the determination that the device connectivity representation does not pass the i-th rule, iteratively until the device connectivity representation passes the i-th rule. identifying at least one property of said set of properties that fails said i-th rule; identifying a portion of the design implementation that corresponds to the at least one characteristic that fails the i-th rule; adjusting the design implementation; and 38. The method of claim 37, further comprising:

39. 40. The method of claim 37, wherein identifying a set of rules includes identifying a set of rules that tests multiple programmable devices.

40. 40. The method of claim 37, wherein identifying a set of rules includes identifying a set of rules that examines multiple control devices.

41. 40. The method of claim 37, wherein identifying a set of rules includes identifying a set of rules that examines a set of device connectivity data characteristics.

42. 38. The method of claim 37, wherein identifying a set of rules comprises identifying a set of rules that examines a set of addressing line characteristics.

43. at least one digital processor; at least one non-transitory processor-readable storage medium communicatively couplable to said at least one digital processor, said non-transitory processor-readable storage medium storing at least one processor-executable instruction that, when executed by said at least one digital processor, causes said at least one digital processor to perform a method according to any one of claims 37 to 42; A computing system comprising:

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