Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing signal delay and performing product-sum operation in parallel.SOLUTION: A semiconductor device comprises first through fourth registers, an adder, a multiplier, a selector and a first storage section. The first register has an output terminal electrically connected to an input terminal of the second register, and the second register has an output terminal electrically connected to a first input terminal of the multiplier. The multiplier has an output terminal electrically connected to a first input terminal of the adder, and the adder has an output terminal electrically connected to an input terminal of the third register. The third register has an output terminal electrically connected to a first input terminal of the selector, and the selector has an output terminal electrically connected to an input terminal of the fourth register, and the first storage section is electrically connected to a second input terminal of the multiplier. The first storage section has a function to read out first data matched with a context signal inputted to the first storage section and input the same to the second input terminal of the multiplier.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an arithmetic circuit, a semiconductor device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. Such integrated circuits incorporate the mechanisms of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with extremely low power consumption compared to the von Neumann architecture, which consumes more power as the processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with an accuracy comparable to or even exceeding that of humans. In a neural network, the main operation is the weighted sum of neuron outputs, that is, the product-sum operation.

[0005] Since optimal values ​​such as the depth of the hierarchy and the number of neuron elements of the artificial neural network vary depending on the problem that the artificial neural network is to deal with, it is preferable to construct an artificial neural network suitable for the problem. For example, Patent Document 1 discloses a semiconductor device that has programmable logic elements and switches between conductive and non-conductive states between circuits according to multiple contexts to perform product-sum operations with a circuit scale suitable for a desired artificial neural network. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2018-110386 A Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, artificial intelligence has been actively developed, and the "inference" (sometimes called "cognition") performed by artificial intelligence is derived from the results of calculations in an artificial neural network. In order for artificial intelligence to solve complex problems, it is necessary to increase the scale of the artificial neural network. In other words, it is necessary to take measures such as deepening the layers of the artificial neural network and increasing the number of neuron elements contained in the layers.

[0008] When implementing a product-sum operation circuit as an operation of an artificial neural network, it is preferable to arrange the product-sum operation circuit with a high degree of parallelism. On the other hand, when the scale of the artificial neural network becomes large, the number of parallel product-sum operation circuits increases. In this case, depending on the arrangement relationship of the input terminals and output terminals of the parallel product-sum operation circuits, the buffer memory for storing the operation results, etc., the wiring distance may become long in the circuit layout. When the wiring distance becomes long, the parasitic resistance of the wiring and the parasitic capacitance with other surrounding wiring or elements also increase, so that the signal transmitted to the wiring may be delayed, and the operating speed of the product-sum operation circuit may decrease.

[0009] An object of one embodiment of the present invention is to provide a novel arithmetic circuit. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that includes the above arithmetic circuit, in which signal delay can be suppressed and product-sum operation can be performed in parallel.

[0010] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Another object of one embodiment of the present invention is to provide an electronic device including the semiconductor device.

[0011] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0012] (1) One aspect of the present invention is an arithmetic circuit having a first register, a second register, a third register, a fourth register, an adder, a multiplier, a selector, and a first storage unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, an output terminal of the adder is electrically connected to an input terminal of the third register, an output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register. In addition, the first storage unit is electrically connected to a second input terminal of the multiplier, and the first storage unit has a function of reading out first data corresponding to a context signal input to the first storage unit and inputting the first data to the second input terminal of the multiplier.

[0013] (2) Alternatively, one embodiment of the present invention is a semiconductor device including a first arithmetic circuit and a second arithmetic circuit. The second arithmetic circuit has the same circuit configuration as the first arithmetic circuit. The first arithmetic circuit includes a first storage unit, a first register, a second register, a third register, a first terminal, a second terminal, a third terminal, and a fourth terminal. In the first arithmetic circuit, an input terminal of the first register is electrically connected to the first terminal, an output terminal of the first register is electrically connected to an input terminal of the second register and the second terminal, and an output terminal of the third register is electrically connected to the fourth terminal. In addition, the first arithmetic circuit has a function of reading out first data corresponding to the context signal from the first storage unit by receiving a context signal in the first storage unit. In addition, the first arithmetic circuit has a function of holding the second data input to the first terminal in the first register or the second register. The first arithmetic circuit has a function of multiplying the first data by the second data held in the second register to generate third data, a function of adding the third data and fourth data input from the third terminal to generate sum data, and a function of holding the sum data in the third register. The first arithmetic circuit has a function of outputting the second data held in the first register to the second terminal and inputting the sum data to the first terminal of the second arithmetic circuit, and a function of outputting the sum data held in the third register to the fourth terminal and inputting the sum data as the fourth data to the third terminal of the second arithmetic circuit.

[0014] (3) Alternatively, in one embodiment of the present invention, the configuration of (2) above may further include an input register and a second storage unit. The second storage unit is electrically connected to an input terminal of the input register. The second storage unit has a function of reading out second data and inputting the second data from an output terminal of the input register to a first terminal of the first arithmetic circuit via the input register.

[0015] (4) Alternatively, one aspect of the present invention may include a third arithmetic circuit having the same circuit configuration as the first arithmetic circuit in the configuration (3), and each of the first arithmetic circuit and the third arithmetic circuit may include a selector, a fourth register, a fifth terminal, and a sixth terminal. In each of the first arithmetic circuit and the third arithmetic circuit, a first input terminal of the selector is electrically connected to an output terminal of the third register, a second input terminal of the selector is electrically connected to the fifth terminal, an output terminal of the selector is electrically connected to an input terminal of the fourth register, an output terminal of the fourth register is electrically connected to the sixth terminal, and the fifth terminal of the first arithmetic circuit is electrically connected to the sixth terminal of the third arithmetic circuit.

[0016] (5) Alternatively, in the configuration of (4) above, one aspect of the present invention may further include a circuit that performs an activation function calculation on data output from a sixth terminal of the first arithmetic circuit or the third arithmetic circuit, and stores a result of the calculation in a second storage unit.

[0017] (6) Alternatively, in one embodiment of the present invention, in the configurations (2) to (5) above, a plurality of first switches and a plurality of second switches may be provided, where the second terminal of the first arithmetic circuit is electrically connected to the first terminal of the second arithmetic circuit via the plurality of first switches, and the third terminal of the first arithmetic circuit is electrically connected to the fourth terminal of the second arithmetic circuit via the plurality of second switches.

[0018] (7) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (2) to (6) above and a housing, The electronic device has a function of performing calculations on a neural network using the semiconductor device.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices.

[0020] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0024] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0025] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0026] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be rephrased as "resistance", "load", "region having a resistance value", and the like, and conversely, the terms "resistance", "load", and "region having a resistance value" can be rephrased as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0027] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance appearing between wirings, a gate capacitance appearing between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0028] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be replaced. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0029] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0030] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0031] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0032] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0033] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0034] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0035] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0037] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wiring" are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0038] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0039] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When an impurity is contained, for example, the defect level density in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, a transition metal other than the main component, and in particular, for example, hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 15 element (however, oxygen and hydrogen are not included), and the like.

[0040] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0043] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0044] According to one embodiment of the present invention, a novel arithmetic circuit can be provided. Alternatively, according to one embodiment of the present invention, by including the arithmetic circuit, a semiconductor device in which signal delay can be suppressed and which can perform product-sum operations in parallel can be provided.

[0045] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0046] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0047] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Diagram 2] FIG. 2 is a block diagram showing a configuration example of the semiconductor device. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Diagram 5] FIG. 5 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a CNN. [Figure 7] FIG. 7 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 8]FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9A is a diagram for explaining filter values ​​included in a filter, and FIG. 9B is a block diagram showing the filter values ​​read out into the arithmetic circuit. [Figure 10] FIG. 10A is a diagram for explaining pixel data included in image data, and FIG. 10B is a diagram for explaining pixel data input to a calculation circuit. [Figure 11] FIG. 11 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 12] 12A and 12B are diagrams for explaining pixel data input to the arithmetic circuit. [Figure 13] FIG. 13 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 14] FIG. 14 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 15] FIG. 15 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 16] FIG. 16 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 17] FIG. 17 is a diagram for explaining the calculation result output from the calculation circuit. [Figure 18] FIG. 18 is a diagram for explaining image data (feature map) from which only characteristic parts are extracted by a filter. [Figure 19] 19A and 19B are block diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 20] FIG. 20 is a block diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 21] FIG. 21 is a timing chart showing an example of the operation of the semiconductor device. [Figure 22] 22A and 22B are diagrams for explaining pixel data input to the arithmetic circuit. [Diagram 23] FIG. 23 is a diagram for explaining the filter value read out to the arithmetic circuit. [Figure 24] 24A to 24C are diagrams for explaining the calculation results output from the calculation circuit. [Diagram 25] FIG. 25 is a block diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a diagram for explaining neuron signals input to the arithmetic circuit and weighting coefficients read out to the arithmetic circuit. [Figure 27] 27A to 27C are circuit diagrams showing examples of the configuration of a memory cell included in a memory circuit. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 30] 30A to 30C are schematic cross-sectional views showing configuration examples of transistors. [Diagram 31] 31A and 31B are schematic cross-sectional views showing configuration examples of a transistor. [Diagram 32] FIG. 32 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 33] 33A and 33B are schematic cross-sectional views showing configuration examples of a transistor. [Diagram 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Diagram 35] FIG. 35A is a top view showing a configuration example of a capacitor, and FIGS. 35B and 35C are cross-sectional perspective views showing the configuration example of a capacitor. [Diagram 36] FIG. 36A is a top view showing an example of the configuration of a capacitor, FIG. 36B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 36C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 37] FIG. 37A is a diagram for explaining the classification of IGZO crystal structures, FIG. 37B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 37C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. [Figure 38]FIG. 38A is a perspective view showing an example of a semiconductor wafer, FIG. 38B is a perspective view showing an example of a chip, and FIGS. 38C and 38D are perspective views showing examples of an electronic component. [Figure 39] FIG. 39 is a perspective view illustrating an example of an electronic device. [Diagram 40] 40A to 40C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0049] In addition, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), it is possible for the network to output new information based on the connection strengths. In this way, the process of outputting new information based on given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0050] Examples of neural network models include the Hopfield type and hierarchical type. In particular, a neural network with a multi-layer structure is sometimes called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning."

[0051] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS FET or an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0052] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0053] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0054] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0055] In addition, the contents described in the embodiments refer to the contents described in each embodiment (or example) using various figures, or the contents described using text in the specification.

[0056] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0057] The embodiments described in this specification will be described with reference to the drawings. However, it is possible to implement the embodiments in many different ways, and it is easily understood by those skilled in the art that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views and the like, the description of some components may be omitted in order to ensure the clarity of the drawings.

[0058] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0059] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0060] (Embodiment 1) In this embodiment, a configuration of a digital arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0061] 1 is a block diagram showing a configuration example of a calculation device 100. The calculation device 100 includes a control circuit CTLR, a MAC (Multiply-Accumulate) array MAR, a memory unit MEMD, and circuits AF[1] to AF[v] (v is an integer of 2 or more).

[0062] As an example, the MAC array MAR has a plurality of arithmetic circuits MA, which are arranged in a matrix of u×v (u is an integer equal to or greater than 2) in the MAC array MAR. That is, the MAC array MAR has u×v arithmetic circuits MA. In FIG. 1, [,] is added to the symbols to indicate the positions at which the arithmetic circuits MA are arranged. For example, the arithmetic circuit MA located in row 1, column 1 is represented as arithmetic circuit MA[1,1], and the arithmetic circuit MA located in row u, column v is represented as arithmetic circuit MA[u,v].

[0063] The arithmetic circuit MA has a function of MAC, for example. Specifically, the arithmetic circuit MA has a function of performing a product-sum operation between first data (for example, w[1] to w[m], where m is a positive integer) and second data (for example, x[1] to x[m]). For example, the first data can be one of multiplier data or multiplicand data, and the second data can be the other of multiplier data or multiplicand data. For example, when performing an operation of a hierarchical neural network in the arithmetic device 100, the first data can be a weighting coefficient and the second data can be a value of an output signal of a neuron, thereby calculating the product-sum of the weighting coefficient and the value of an output signal of a neuron.

[0064] The MAC array MAR also has a plurality of programmable switches PR and a plurality of programmable switches PC. In Fig. 1, one of the plurality of programmable switches PR is electrically connected to one of the plurality of arithmetic circuits MA, and one of the plurality of programmable switches PC is electrically connected to one of the plurality of arithmetic circuits MA. Therefore, in Fig. 1, like the arithmetic circuits MA, the reference numerals of the programmable switches PR and PC are marked with [, ] to indicate their positions.

[0065] The number of wirings electrically connected between the arithmetic circuit MA and the programmable switch PR may be one or more. The number of wirings electrically connected between the arithmetic circuit MA and the programmable switch PC may be one or more. In other words, the number of wirings electrically connecting the programmable switch PR and the programmable switch PC to the arithmetic circuit MA can be determined according to the number of terminals of the arithmetic circuit MA.

[0066] The programmable switches PR[1,1] through PR[1,v] located in the first row of the MAC array MAR are electrically connected in series. Similarly, the programmable switches PR[2,1] through PR[2,v] located in the second row of the MAC array MAR are electrically connected in series, and the programmable switches PR[u,1] through PR[u,v] located in the u-th row of the MAC array MAR are electrically connected in series.

[0067] Also, the programmable switches PC[1,1] through PC[u,1] located in the first column of the MAC array MAR are electrically connected in series. Similarly, the programmable switches PC[1,2] through PC[u,2] located in the second column of the MAC array MAR are electrically connected in series, and the programmable switches PC[1,v] through PC[u,v] located in the vth column of the MAC array MAR are electrically connected in series.

[0068] For example, the programmable switches PR[1,1] to PR[u,1] are electrically connected to wirings XL[1] to XL[u], respectively. Also, for example, the programmable switches PC[u,1] to PC[u,v] are electrically connected to wirings YL[1] to YL[v], respectively.

[0069] For example, each of the wirings XL[1] to XL[u] is electrically connected to the memory unit MEMD via a plurality of resistors RG. Also, for example, each of the wirings YL[1] to YL[v] is electrically connected to the memory unit MEMD.

[0070] The memory unit MEMD has a function of holding, for example, second data to be input to the MAC array MAR via the wirings XL[1] to XL[u] in order to execute a multiplication and addition operation between the first data and the second data in the MAC array MAR, and also has a function of holding, for example, a result of the multiplication and addition operation between the first data and the second data transmitted from the MAC array MAR via the wirings YL[1] to YL[v].

[0071] A plurality of registers RG electrically connected to each of the wirings XL[1] to XL[u] are provided for pipeline processing in the arithmetic device 100. Specifically, for example, in FIG. 1, the plurality of registers RG are provided with registers RG[1,1] to RG[1,p] (p is an integer equal to or greater than 1) on the wiring XL[1] between the programmable switch PR[1,1] of the MAC array MAR and the memory unit MEMD. Note that, in the registers RG[1,1] to RG[1,p], the input terminals and output terminals of the adjacent registers RG are electrically connected, and the input terminal of the register RG[1,1] is electrically connected to the memory unit MEMD, and the output terminal of the register RG[1,p] is electrically connected to the programmable switch PR[1,1].

[0072] Similarly, the wiring XL[2] between the programmable switch PR[2,1] of the MAC array MAR and the memory unit MEMD is provided with registers RG[2,1] to RG[2,p]. The input terminals and output terminals of the registers RG[2,1] to RG[2,p] are electrically connected to each other in the adjacent registers RG, and the input terminal of the register RG[2,1] is electrically connected to the memory unit MEMD, and the output terminal of the register RG[2,p] is electrically connected to the programmable switch PR[2,1]. The wiring XL[u] between the programmable switch PR[u,1] of the MAC array MAR and the memory unit MEMD is provided with registers RG[u,1] to RG[u,p]. In addition, the input terminals and output terminals of adjacent registers RG[u,1] to RG[u,p] are electrically connected, and the input terminal of register RG[u,1] is electrically connected to the memory unit MEMD, and the output terminal of register RG[u,p] is electrically connected to the programmable switch PR[u,1].

[0073] The register RG has a function of temporarily holding data (which may be digital data, or may be an electric potential, for example) given to the input terminal of the register RG when a pulse voltage is given as a clock signal given to the register RG. The register RG also has a function of outputting the data held in the register RG to the output terminal of the register RG. In this specification, the register RG is assumed to temporarily hold the data given to the input terminal of the register RG and output first data to the output terminal of the register RG when a high-level electric potential is given as a clock signal. Therefore, the register RG functions as an input register for transmitting the first data to the MAC array MAR.

[0074] The clock signal may be, for example, a signal sent through a line CKL, which will be described later.

[0075] The register RG preferably holds, for example, 8-bit data, more preferably 16-bit data, and even more preferably 32-bit or more data.

[0076] Incidentally, for example, the registers RG[1,1] through RG[1,p] between the programmable switch PR[1,1] and the memory unit MEMD may be replaced with one shift register. Similarly, for example, the registers RG[2,1] through RG[2,p] between the programmable switch PR[2,1] and the memory unit MEMD may also be replaced with one shift register, and the registers RG[u,1] through RG[u,p] between the programmable switch PR[u,1] and the memory unit MEMD may also be replaced with one shift register.

[0077] As described above, data transmission from the memory unit MEMD to the MAC array MAR can be pipelined by electrically connecting a plurality of registers RG in series between the memory unit MEMD and the MAC array MAR as shown in Fig. 1. Also, by connecting a plurality of registers RG in series, delays in signals for transmitting data caused by parasitic resistance and parasitic capacitance can be suppressed.

[0078] The control circuit CTLR is electrically connected to the MAC array MAR. Furthermore, the control circuit CTLR and the MAC array MAR are electrically connected to a wiring CKL.

[0079] For example, the wiring CKL functions as a wiring for supplying a clock signal. The clock signal may be, for example, a pulse voltage.

[0080] The control circuit CTLR has a function of controlling the arithmetic circuits MA[1,1] through MA[u,v] included in the MAC array MAR, for example. Specifically, for example, the control circuit CTLR has a function of transmitting a selection signal for writing data to a memory unit (corresponding to a memory unit OSM, etc., described later) included in the arithmetic circuit MA, and a function of transmitting the data. Also, for example, the control circuit CTLR has a function of transmitting a signal for controlling a register (register RG2 through register RG4, etc., described later) included in the arithmetic circuit MA. Also, the control circuit CTLR may have a function of generating a different clock signal based on a clock signal from the wiring CKL.

[0081] The circuits AF[1] to AF[v] are electrically connected to the wirings YL[1] to YL[v], respectively. The circuits AF[1] to AF[v] are electrically connected to the memory unit MEMD, respectively.

[0082] Each of the circuits AF[1] to AF[v] can be a function circuit that outputs an activation function value using the results of multiplication and addition operations sent from the wirings YL[1] to YL[v]. The activation function can be, for example, a step function, a ReLU function, a sigmoid function, a tanh function, or the like.

[0083] Each of the circuits AF[1] to AF[v] may be a circuit that performs a pooling process, such as maximum pooling, average pooling, or Lp pooling.

[0084] Furthermore, each of the circuits AF[1] to AF[v] may be a circuit having a function circuit that outputs the value of an activation function, a circuit that performs pooling processing, and the like.

[0085] In other words, by using the arithmetic device 100, it is possible to perform calculations of a hierarchical neural network, calculations of a convolutional neural network (CNN), and the like.

[0086] However, one embodiment of the present invention is not limited to the semiconductor device illustrated in Fig. 1. One embodiment of the present invention may have a configuration in which the semiconductor device illustrated in Fig. 1 is modified depending on the situation. For example, like the arithmetic device 100A illustrated in Fig. 2, the arithmetic device 100 illustrated in Fig. 1 may not include the circuits AF[1] to AF[v].

[0087] <Configuration example of arithmetic circuit MA> Next, a configuration example of the arithmetic circuit MA will be described.

[0088] 3 is a block diagram showing an example of the arithmetic circuit MA. The arithmetic circuit MA includes, as an example, a register RG1, a register RG2, a register RG3, a register RG4, a multiplier MP, an adder AD, a selector SLC, and a storage unit OSM.

[0089] Moreover, the arithmetic circuit MA shown in FIG. 3 has, as an example, a terminal SI, a terminal SO, a terminal MI, a terminal MO, a terminal AI, and a terminal AO.

[0090] The register RG1 has a terminal IT1 corresponding to an input terminal and a terminal OT1 corresponding to an output terminal. The register RG2 has a terminal IT2 corresponding to an input terminal, a terminal OT2 corresponding to an output terminal, and a terminal CT2 corresponding to an enable input terminal. The register RG3 has a terminal IT3 corresponding to an input terminal, a terminal OT3 corresponding to an output terminal, and a terminal CT3 corresponding to an enable input terminal. The register RG4 has a terminal IT4 corresponding to an input terminal and a terminal OT4 corresponding to an output terminal. Although not shown in FIG. 3, each of the registers RG1 to RG4 is electrically connected to a wiring CKL and receives a clock signal from the wiring CKL.

[0091] The multiplier MP has a terminal WI corresponding to a first input terminal, a terminal XI corresponding to a second input terminal, and a terminal ZO corresponding to an output terminal, while the adder AD has a terminal FT corresponding to the first input terminal, a terminal ST corresponding to a second input terminal, and a terminal TT corresponding to an output terminal.

[0092] The terminal IT1 of the register RG1 is electrically connected to the terminal SI, the terminal OT1 of the register RG1 is electrically connected to the terminal IT2 and the terminal SO of the register RG2, the terminal OT2 of the register RG2 is electrically connected to the terminal XI of the multiplier MP, and the terminal CT2 of the register RG2 is electrically connected to the line SLT.

[0093] The storage unit OSM is electrically connected to the wiring CF, the wiring WDT, and the wiring CTX, and is also electrically connected to the terminal WI of the multiplier MP.

[0094] A terminal ZO of the multiplier MP is electrically connected to a terminal FT of the adder AD, and a terminal ST of the adder AD is electrically connected to a terminal AI.

[0095] The terminal IT3 of the register RG3 is electrically connected to the terminal TT of the adder AD, the terminal OT3 of the register RG3 is electrically connected to the terminal AO and the first input terminal of the selector SLC, and the terminal CT3 of the register RG3 is electrically connected to the line URST.

[0096] A terminal IT4 of the register RG4 is electrically connected to the output terminal of the selector SLC, and a terminal OT4 of the register RG4 is electrically connected to the terminal MO.

[0097] A second input terminal of the selector SLC is electrically connected to the terminal MI, and a control terminal of the selector SLC is electrically connected to the line SEL.

[0098] The register RG1 has a function of temporarily holding data (which may be digital data, or may be an electric potential, for example) given to the terminal IT1 when a pulse voltage is given as a clock signal. In this specification, the register RG1 temporarily holds the data given to the input terminal of the register RG1 when a potential change occurs, for example from a low level electric potential to a high level electric potential, as the clock signal, and outputs the data from the output terminal of the register RG1. The register RG1 has a function of outputting the data held in the register RG1 to the terminal OT1, for example.

[0099] As an example, the register RG2 temporarily holds the data (which can be digital data, for example) given to the terminal IT2 when an enable signal is given to the terminal CT2, which is an enable input terminal, and a pulse voltage is given as a clock signal. Note that in this specification, the register RG2 temporarily holds the data given to the input terminal of the register RG2, for example, when a high-level potential is input to the enable input terminal and a potential change occurs from a low-level potential to a high-level potential as the clock signal. Also, as an example, the register RG2 has a function of outputting the data held in the register RG2 to the terminal OT2.

[0100] In addition, when a low-level potential is input to the terminal CT2 of the register RG2, even if a potential change occurs from a low-level potential to a high-level potential as a clock signal, the register RG2 does not hold the data input to the terminal IT2. However, even when a low-level potential is input to the terminal CT2 of the register RG2, the data held in the register RG2 is output.

[0101] For example, the line SLT functions as a line that supplies an enable signal to the register RG2.

[0102] The potential applied by the line CKL of the register RG1 changes from a low level potential to a high level potential, for example, to hold the data input to the terminal IT1, and transmits the data from the terminal OT1 of the register RG1 to the terminal IT2 of the register RG2. Also, when a high level potential is applied to the line SLT, the potential applied by the line CKL of the register RG2 changes from a low level potential to a high level potential, for example, to hold the data input to the terminal IT2 of the register RG2, and transmits the data from the terminal OT2 of the register RG2 to the terminal XI of the multiplier MP.

[0103] The storage unit OSM has a function of holding data according to a context, for example. The data according to the context here can be, for example, first data used in the calculation of the multiplier MP. The storage unit OSM has a function of acquiring a context signal from the wiring CTX, selecting a data set according to the context signal, and inputting a plurality of first data to the terminal WI of the multiplier MP. The context signal may be a digital signal or an analog signal.

[0104] Moreover, the storage unit OSM has a function of acquiring a write signal from the line WDT and writing configuration data sent from the line CF to a context corresponding to the write signal.

[0105] The context signal, the write signal, and the configuration data can be supplied from, for example, a control circuit CTLR. In this case, the lines CTX, WDT, and CF may be electrically connected to the control circuit CTLR.

[0106] The multiplier MP has a function of multiplying, for example, the first data input to the terminal WI by the second data input to the terminal XI, and outputting the result of the multiplication (hereinafter referred to as multiplied data) to the terminal ZO. For example, when w is input to the terminal WI as the first data and x is input to the terminal XI as the second data, w×x is output to the terminal ZO of the multiplier MP as the multiplied data.

[0107] The adder AD has a function of adding multiplication data input to a terminal ZO and data input to a terminal ST, for example, and outputting the result of the addition (hereinafter referred to as added data) to a terminal TT.

[0108] The register RG3 has a function of temporarily holding the addition data given to the terminal IT3 when an enable signal is given to the terminal CT3, which is an enable input terminal, and a pulse voltage is given as a clock signal. In this specification, the register RG3 temporarily holds the data given to the input terminal of the register RG3 when, for example, a high-level potential is input to the enable input terminal and a potential change occurs from a low-level potential to a high-level potential as a clock signal. The register RG3 has a function of outputting the data held in the register RG3 to the terminal OT3.

[0109] Also, when a low-level potential is input to the terminal CT3 of the register RG3, even if a potential change occurs from a low-level potential to a high-level potential as a clock signal, the register RG3 does not hold the data input to the terminal IT3. However, even when a low-level potential is input to the terminal CT3 of the register RG3, the data held in the register RG3 is output.

[0110] The line URST functions, for example, as a line that supplies an enable signal to the register RG3.

[0111] The selector SLC has a function of bringing one of the first input terminal or the second input terminal into a conductive state with the output terminal, and bringing the other of the first input terminal or the second input terminal into a non-conductive state with the output terminal. The selection of the first input terminal or the second input terminal that is brought into a conductive state with the output terminal by the selector SLC is determined by the potential of the wiring SEL input to the control terminal. Here, as an example, when a high-level potential is input to the control terminal, the selector SLC brings the first input terminal into a conductive state with the output terminal, and when a low-level potential is input to the control terminal, the selector SLC brings the second input terminal into a conductive state with the output terminal.

[0112] In the selector SLC, when the first input terminal and the output terminal are in a conductive state and the second input terminal and the output terminal are in a non-conductive state, the addition data from the terminal OT3 of the register RG3 is input to the terminal IT4 of the register RG4. Or, when the second input terminal and the output terminal are in a conductive state and the first input terminal and the output terminal are in a non-conductive state in the selector SLC, the data from the terminal MI is input to the terminal IT4 of the register RG4.

[0113] The line SEL functions, for example, as a line that supplies a signal for controlling the selector SLC.

[0114] As an example, the register RG4 stores data (which may be digital data, for example) provided to the terminal IT4 when a pulse voltage is provided as a clock signal. Note that in this specification, the register RG4 temporarily stores the data provided to the input terminal of the register RG4 when, for example, a potential change occurs from a low level potential to a high level potential as a clock signal. Also, as an example, the register RG4 has a function of outputting the data stored in the register RG4 to the terminal OT4.

[0115] <Programmable switch configuration> Next, the programmable switches PR and PC will be described with reference to FIGS.

[0116] Programmable switches PR[s,1] to PR[s,v] (not shown in Figures 1 and 2) located in the sth row (s is an integer greater than or equal to 1 and less than or equal to u) have the function of controlling the conductive and non-conductive states of the arithmetic circuits MA[s,1] to MA[s,v], respectively.

[0117] For example, the programmable switch PR can have the circuit configuration shown in Fig. 4. Fig. 4 illustrates not only configuration examples of the programmable switch PR[s,g] (g is an integer greater than 1 and less than v-1) and the programmable switch PR[s,h] (h is an integer greater than g and less than v), but also the arithmetic circuit MA[s,g] and the arithmetic circuit MA[s,h].

[0118] FIG. 4 also illustrates terminals SI, SO, AI, and AO as terminals that the arithmetic circuit MA[s,g] and the arithmetic circuit MA[s,h] have, respectively.

[0119] The programmable switches PR[s,g] and PR[s,h] are electrically connected to a plurality of wirings SL. The programmable switches PR[s,g] and PR[s,h] are also electrically connected to a plurality of wirings ALX.

[0120] The multiple wirings SL and multiple wirings ALX are, as an example, wirings extending in the row direction of the MAC array MAR.

[0121] In addition, the multiple wirings SL are electrically connected to the wiring XL[s]. Note that, although multiple wirings XL[s] are illustrated in FIG. 4, the wiring XL[s] may be a single wiring and may be electrically connected to one of the multiple wirings SL.

[0122] As an example, each of the programmable switches PR[s,g] and PR[s,h] has a plurality of switches. For example, Fig. 4 shows a configuration in which the programmable switch PR[s,g] has a plurality of switches SW_SI[s,g], a plurality of switches SW_SO[s,g], a plurality of switches SW_AIX[s,g], and a plurality of switches SW_AOX[s,g], and the programmable switch PR[s,h] has a plurality of switches SW_SI[s,h], a plurality of switches SW_SO[s,h], a plurality of switches SW_AIX[s,h], and a plurality of switches SW_AOX[s,h].

[0123] The terminal SI of the arithmetic circuit MA[s,g] is electrically connected to each of the first terminals of the multiple switches SW_SI[s,g], and one second terminal of the multiple switches SW_SI[s,g] is electrically connected to one of the multiple wirings SL. The terminal SO of the arithmetic circuit MA[s,g] is electrically connected to each of the first terminals of the multiple switches SW_SO[s,g], and one second terminal of the multiple switches SW_SO[s,g] is electrically connected to one of the multiple wirings SL. The terminal AI of the arithmetic circuit MA[s,g] is electrically connected to each of the first terminals of the multiple switches SW_AIX[s,g], and one second terminal of the multiple switches SW_AIX[s,g] is electrically connected to one of the multiple wirings ALX. The terminal AO of the arithmetic circuit MA[s,g] is electrically connected to each of the first terminals of the multiple switches SW_AOX[s,g], and one second terminal of the multiple switches SW_AOX[s,g] is electrically connected to one of the multiple wirings ALX.

[0124] The terminal SI of the arithmetic circuit MA[s,h] is electrically connected to each of the first terminals of the multiple switches SW_SI[s,h], and one second terminal of the multiple switches SW_SI[s,h] is electrically connected to one of the multiple wirings SL. The terminal SO of the arithmetic circuit MA[s,h] is electrically connected to each of the first terminals of the multiple switches SW_SO[s,h], and one second terminal of the multiple switches SW_SO[s,h] is electrically connected to one of the multiple wirings SL. The terminal AI of the arithmetic circuit MA[s,h] is electrically connected to each of the first terminals of the multiple switches SW_AIX[s,h], and one second terminal of the multiple switches SW_AIX[s,h] is electrically connected to one of the multiple wirings ALX. The terminal AO of the arithmetic circuit MA[s,h] is electrically connected to each of the first terminals of the multiple switches SW_AOX[s,h], and one second terminal of the multiple switches SW_AOX[s,h] is electrically connected to one of the multiple wirings ALX.

[0125] For example, to establish electrical continuity between the terminal SO of the arithmetic circuit MA[s,g] and the terminal SI of the arithmetic circuit MA[s,h], one of the multiple wirings SL is selected, and the switch SW_SO[s,g] and the switch SW_SI[s,h] directly connected to that wiring are each turned on, and the remaining multiple switches SW_SO[s,g] and the remaining multiple switches SW_SI[s,h] are each turned off.

[0126] Like the programmable switch PR, the programmable switches PC[1,t] to PC[u,t] (not shown in Figures 1 and 2) located in the tth column (t is an integer greater than or equal to 1 and less than or equal to v) have the function of controlling the conductive and non-conductive states of each of the arithmetic circuits MA[1,t] to MA[u,t], respectively.

[0127] For example, the programmable switch PC can have the circuit configuration shown in Fig. 5. Fig. 5 illustrates not only configuration examples of the programmable switch PC[e,t] (e is an integer equal to or greater than 1 and equal to or less than u-1) and the programmable switch PC[f,t] (f is an integer greater than e and equal to or less than u), but also the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t].

[0128] FIG. 5 also illustrates terminals AI, AO, MI, and MO as terminals that the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t] have, respectively.

[0129] The programmable switch PC[e,t] and the programmable switch PC[f,t] are electrically connected to a plurality of wirings ML and a plurality of wirings ALY.

[0130] The multiple wirings ML and the multiple wirings ALY are, for example, wirings extending in the column direction of the MAC array MAR.

[0131] In addition, the multiple wirings ML are electrically connected to the wiring YL[t]. Note that, although multiple wirings YL[t] are illustrated in FIG. 5, the wiring YL[t] may be a single wiring that is electrically connected to one of the multiple wirings ML.

[0132] As an example, each of the programmable switch PC[e,t] and the programmable switch PC[f,t] has a plurality of switches. For example, Fig. 5 shows a configuration in which the programmable switch PC[e,t] has a plurality of switches SW_MI[e,t], a plurality of switches SW_MO[e,t], a plurality of switches SW_AIY[e,t], and a plurality of switches SW_AOY[e,t], and the programmable switch PC[f,t] has a plurality of switches SW_MI[f,t], a plurality of switches SW_MO[f,t], a plurality of switches SW_AIY[f,t], and a plurality of switches SW_AOY[f,t].

[0133] The terminal MI of the arithmetic circuit MA[e,t] is electrically connected to each of the first terminals of the multiple switches SW_MI[e,t], and one second terminal of the multiple switches SW_MI[e,t] is electrically connected to one of the multiple wirings ML. The terminal MO of the arithmetic circuit MA[e,t] is electrically connected to each of the first terminals of the multiple switches SW_MO[e,t], and one second terminal of the multiple switches SW_MO[e,t] is electrically connected to one of the multiple wirings ML. The terminal AI of the arithmetic circuit MA[e,t] is electrically connected to each of the first terminals of the multiple switches SW_AIY[e,t], and one second terminal of the multiple switches SW_AIY[e,t] is electrically connected to one of the multiple wirings ALY. The terminal AO of the arithmetic circuit MA[e,t] is electrically connected to each of the first terminals of the multiple switches SW_AOY[e,t], and one second terminal of the multiple switches SW_AOY[e,t] is electrically connected to one of the multiple wirings ALY.

[0134] The terminal MI of the arithmetic circuit MA[f,t] is electrically connected to each of the first terminals of the multiple switches SW_MI[f,t], and one second terminal of the multiple switches SW_MI[f,t] is electrically connected to one of the multiple wirings ML. The terminal MO of the arithmetic circuit MA[f,t] is electrically connected to each of the first terminals of the multiple switches SW_MO[f,t], and one second terminal of the multiple switches SW_MO[f,t] is electrically connected to one of the multiple wirings ML. The terminal AI of the arithmetic circuit MA[f,t] is electrically connected to each of the first terminals of the multiple switches SW_AIY[f,t], and one second terminal of the multiple switches SW_AIY[f,t] is electrically connected to one of the multiple wirings ALY. The terminal AO of the arithmetic circuit MA[f,t] is electrically connected to each of the first terminals of the multiple switches SW_AOY[f,t], and one second terminal of the multiple switches SW_AOY[f,t] is electrically connected to one of the multiple wirings ALY.

[0135] For example, when a conductive state is established between the terminal MO of the arithmetic circuit MA[e,t] and the terminal MI of the arithmetic circuit MA[f,t], one of the multiple wirings ML is selected, and the switches SW_MO[e,t] and SW_MI[f,t] directly connected to the wiring are turned on, and the remaining multiple switches SW_MO[e,t] and the remaining multiple switches SW_MI[f,t] are turned off. Also, when a conductive state is established between the terminal AO of the arithmetic circuit MA[e,t] and the terminal AI of the arithmetic circuit MA[f,t], one of the multiple wirings ALY is selected, and the switches SW_AOY[e,t] and SW_SI[f,t] directly connected to the wiring are turned on, and the remaining multiple switches SW_AOY[e,t] and the remaining multiple switches SW_AIY[f,t] are turned off.

[0136] 4 shows a configuration in which the programmable switch PR is electrically connected to the terminals SI, SO, AI, and AO of the arithmetic circuit MA, and FIG 5 shows a configuration in which the programmable switch PC is electrically connected to the terminals AI, AO, MI, and MO of the arithmetic circuit MA, but one embodiment of the present invention is not limited to this. For example, the arithmetic device 100 may have a configuration in which the programmable switch PR is electrically connected not only to the terminals SI, SO, AI, and AO, but also to the terminals MI and MO, and the programmable switch PC may be electrically connected not only to the terminals AI, AO, MI, and MO, but also to the terminals SI and SO.

[0137] The MAC array MAR can change the scale of circuits related to the multiply-and-accumulate operation by the programmable switches PR[1,1] through PR[u,v] and the programmable switches PC[1,1] through PC[u,v]. For example, when performing a multiply-and-accumulate operation using the MAC array MAR, if the operation is sufficient with only the arithmetic circuits MA[1,t] through MA[u,t], the programmable switches PR[1,t] through PR[u,t] and the programmable switches PC[1,t] through PC[u,t] may be turned on, and the other programmable switches may be turned off.

[0138] <How it works> Next, a description will be given of an example of the operation of the arithmetic device 100. Note that in this operation method, an example of the operation in the calculation of a convolutional neural network (CNN) will be described.

[0139] CNN is one of the computational models used for extracting features from images, etc. Figure 6 shows an example of the configuration of CNN. CNN is composed of a convolutional layer CL, a pooling layer PL, and a fully connected layer FCL. In this operation method, for example, image data IPD read from the memory unit MEMD is input to the MAC array MAR, and feature extraction is performed.

[0140] The convolution layer CL has the function of performing convolution processing on image data. The convolution processing is performed by repeating product-sum calculations between a partial area of ​​the image data and the filter value of the weight filter. The convolution in the convolution layer CL extracts image features.

[0141] In the convolution process, one or more weight filters can be used. When multiple weight filters are used, it is possible to extract multiple features contained in the image data. FIG. 6 shows a filter fil 1 , filter fil 2 , filter fil 3Although three filters are shown in FIG. 6, the number of filters used in the convolution process may be one, two, or four or more. In FIG. 6, the image data input to the convolution layer CL is filtered using the filter fil 1 ,fil 2 ,fil 3 The image data D 1 , D 2 , D 3 The following shows an example of the generated

[0142] Convolved image data D 1 , D 2 , D 3 For example, a calculation may be performed using an activation function. As an example of the activation function, ReLU (Rectified Linear Units) or the like can be used. ReLU is a function that outputs "0" when the input value is negative, and outputs the input value as is when the input value is "0" or more. In addition, as another activation function, a sigmoid function, a tanh function, or the like can also be used.

[0143] Image data D, regardless of whether it is calculated using an activation function or not 1 , D 2 , D 3 is output to, for example, the pooling layer PL. The pooling layer PL has a function of performing pooling on the image data input from the convolution layer CL. Pooling is a process of dividing the image data into a plurality of regions, extracting predetermined data for each region, and arranging the data in a new matrix shape. Pooling reduces the image data while retaining the features extracted by the convolution layer CL. Note that maximum pooling, average pooling, Lp pooling, etc. can be used as the pooling.

[0144] The CNN extracts features by, for example, the above-mentioned convolution process, pooling process, etc. The CNN may have multiple convolution layers CL and / or multiple pooling layers PL. In FIG. 6, as an example, a layer L composed of a convolution layer CL and a pooling layer PL is provided in z layers (where z is an integer equal to or greater than 1) (layer L 1 to layer L z ), convolution processing and pooling processing are performed z times. In this case, feature extraction can be performed in each layer L, making it possible to perform more advanced feature extraction. 1 , layer L 2 , layer L z is shown, and other layers L are omitted.

[0145] The fully connected layer FCL is, for example, the layer L 1 to layer L z It has a function of judging an image using image data obtained through the above. The fully connected layer FCL has a configuration in which all nodes in a layer are connected to all nodes in the next layer. In other words, the fully connected layer FCL performs calculations using a fully connected neural network (FNN). The image data output from the convolution layer CL or pooling layer PL is a two-dimensional feature map, which is expanded into one dimension when input to the fully connected layer FCL. Then, the image data OPD obtained by inference using the fully connected layer FCL is output.

[0146] <<Operation of Convolutional Layer CL 1>> Here, a method of computing the convolutional layer CL using the computing device 100 will be described. Note that, as an example, the computing circuits MA included in the MAC array MAR of the computing device 100 are arranged in a matrix of 9 rows and 10 columns. In other words, the MAC array MAR used in this operation method includes the computing circuits MA[1,1] to MA[9,10].

[0147] The MAC array MAR in this operation method has a circuit configuration as shown in FIG. 7, using programmable switches PR and PC. Specifically, in an arithmetic circuit MA included in one row of the MAC array MAR, the programmable switch PR is set so that the terminal SO of the arithmetic circuit MA is in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. For example, the programmable switch PR[1,1] and the programmable switch PR[1,2] are set so that the terminal SO of the arithmetic circuit MA[1,1] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,2], and the programmable switch PR[1,2] and the programmable switch PR[1,3] are set so that the terminal SO of the arithmetic circuit MA[1,2] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,3]. The wiring XL[1] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,1] via the programmable switch PR[1,1]. In this manner, in this operating method, it is assumed that the programmable switches PR are set so that the arithmetic circuits MA are serially connected to each other and brought into a conductive state in each row of the MAC array MAR.

[0148] In addition, in the MAC array MAR in this operation method, specifically, in the arithmetic circuit MA included in one column of the MAC array MAR, the programmable switch PC is set so that the terminal AO of the arithmetic circuit MA is in a conductive state with the terminal AI of the adjacent arithmetic circuit MA. For example, the programmable switch PC[1,1] and the programmable switch PC[2,1] are set so that the terminal AO of the arithmetic circuit MA[1,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[2,1]. Note that the wiring YL[1] is in a conductive state with the terminal AO of the arithmetic circuit MA[9,1] via the programmable switch PC[9,1]. In this way, in this operation method, it is assumed that the programmable switch PC is set so that the arithmetic circuits MA are in a conductive state in series in each column of the MAC array MAR.

[0149] Figure 8 shows the time T 1 From time T 98 is a timing chart showing changes in data input to terminals SI, SO, XI, WI, AI (ST), TT, and AO of arithmetic circuit MA[2,1] during and around the time. Fig. 8 also shows changes in potential of wiring CKL, wiring SLT, wiring SEL, and wiring URST. Note that "high" in Fig. 8 represents high-level potential, and "low" represents low-level potential.

[0150] In this operation method, it is assumed that a high level potential is always input to the line SLT, and therefore the register RG2 is in an enabled state during this operation method.

[0151] In this operation method, the line SEL is always supplied with a low-level potential, so that the selector SLC always keeps the first input terminal and the output terminal in a non-conductive state and the second input terminal and the output terminal in a conductive state.

[0152] The calculation method performed in the MAC array MAR will be described below with reference to the timing chart of FIG.

[0153] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, at time T 1 Prior to this, it is preferable that initialization data is input to the terminals SI, SO, XT, WT, AI (terminal ST), TT, and AO of each of the arithmetic circuits MA[1,1] to MA[9,10] (not shown in FIG. 8). The initialization data may be data with a value of "0", for example. In addition, the potential of the wiring URST is changed from a low-level potential to a high-level potential, and the potential of the terminal AO is adjusted to an appropriate value by the register RG3. At this time, it is preferable that the potential of the terminal AO is set to a potential corresponding to the value of "0", for example.

[0154] [Step 1: Reading filter values] After step 0 and at time T1 Prior to this, in each of the arithmetic circuits MA[1,1] to MA[9,10] of the MAC array MAR of the arithmetic device 100, a filter value is read from the storage unit OSM. Specifically, a context signal is supplied from the wiring CTX, and data corresponding to a desired context, i.e., a filter value, is read from the storage unit OSM. Here, as an example, the filter fil is stored in the storage unit OSM of each of the arithmetic circuits MA[1,t] to MA[9,t] located in the t-th column (where t is an integer between 1 and 10). t The filter value of the filter fil is read. t For example, the matrix is ​​3 rows and 3 columns as shown in FIG. 9A. t is a matrix element of fil t [1,1] to fil t For example, the storage unit OSM of the arithmetic circuit MA[1,t] has fil t [1,1] is read, and the storage unit OSM of the arithmetic circuit MA[2,t] is t [1,2] is read, and the storage unit OSM of the arithmetic circuit MA[3,t] is t [1,3] is read, and the storage unit OSM of the arithmetic circuit MA[4,t] is t [2,1] is read, and the memory unit OSM of the arithmetic circuit MA[5,t] is t [2,2] is read, and the storage unit OSM of the arithmetic circuit MA[6,t] is t [2,3] is read, and the memory unit OSM of the arithmetic circuit MA[7,t] is t [3,1] is read, and the memory unit OSM of the arithmetic circuit MA[8,t] is t [3,2] is read, and the memory unit OSM of the arithmetic circuit MA[9,t] is t Let [3,3] be read.

[0155] For this reason, the arithmetic circuit MA of the MAC array MAR has a filter fil in each of the first to tenth columns as shown in FIG. 1 or filter fil 10 is read out.

[0156] In each of the arithmetic circuits MA[1,1] to MA[9,10], the filter value read out from the storage unit OSM is input to a terminal WI of the multiplier MP.

[0157] [Step 2: Input image data] Next, the operation of inputting image data IPD to the MAC array MAR will be described.

[0158] As an example, the image data IPD here is composed of multiple pixel data pix[1,1] to pixel data pix[m,n] in m rows and n columns (where m and n are integers greater than or equal to 1), as shown in Figure 10A.

[0159] Moreover, the image data IPD is read out from the memory unit MEMD of the arithmetic device 100, for example.

[0160] Incidentally, since the arithmetic circuits MA of the MAC array MAR are arranged in a matrix of 9 rows and 10 columns, the registers RG[1,p] through RG[9,p] are electrically connected to the MAC array MAR. Also, the registers RG[s,1] through RG[s,p] are electrically connected to the s-th row (where s is an integer between 1 and 9) of the MAC array MAR. In other words, when the pixel data pix read out from the memory unit MEMD is input to the arithmetic circuit MA[s,1] of the MAC array MAR, it passes through the registers RG[s,1] through RG[s,p].

[0161] The registers RG[s,1] to RG[s,p] sequentially transmit multiple pixel data pix read out from the memory unit MEMD each time a clock signal, for example, a potential change from a low level potential to a high level potential, is input to the wiring CKL.

[0162] FIG. 10B shows the time T 1 From time T 913 is a block diagram showing pixel data pix that is held in each of registers RG[1, p] through RG[9, p] and input to the MAC array MAR during the period from 1st to 2nd.

[0163] For example, in FIG. 1 10B, a potential change from a low level potential to a high level potential occurs in the wiring CKL, pixel data pix[1,1] is stored in each of the registers RG[1,p] to RG[3,p], and the pixel data pix[1,1] is input to the terminals SI of the arithmetic circuits MA[1,1] to MA[3,1]. 2 10B, a potential change from a low level potential to a high level potential occurs in the wiring CKL, pixel data pix[1,2] is stored in each of the registers RG[1,p] to RG[3,p], and the pixel data pix[1,2] is input to the terminals SI of the arithmetic circuits MA[1,1] to MA[3,1]. 3 In this figure, a potential change from a low level potential to a high level potential occurs on wiring CKL, pixel data pix[1,3] is stored in each of registers RG[1,p] to RG[3,p], and pixel data pix[1,3] is input to terminals SI of arithmetic circuits MA[1,1] to MA[1,3].

[0164] For example, in FIG. 10B, at time T 4 In this figure, a potential change from a low level potential to a high level potential occurs in the wiring CKL, pixel data pix[1,4] is stored in each of the registers RG[1,p] through RG[3,p], the pixel data pix[1,4] is input to the terminals SI of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[2,1] is stored in each of the registers RG[4,p] through RG[6,p], and the pixel data pix[2,1] is input to the terminals SI of the arithmetic circuits MA[4,1] through MA[6,1].

[0165] For example, in FIG. 10B, at time T 7 In this figure, a potential change from a low level to a high level occurs in the wiring CKL, pixel data pix[1,7] is stored in each of the registers RG[1,p] through RG[3,p], the pixel data pix[1,7] is input to the terminal SI of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[2,4] is stored in the registers RG[4,p] through RG[6,p], the pixel data pix[2,4] is input to the terminal SI of each of the arithmetic circuits MA[4,1] through MA[6,1], pixel data pix[3,1] is stored in the register RG[7,p], and the pixel data pix[3,1] is input to the terminal SI of the arithmetic circuit MA[7,1].

[0166] As described above, the pixel data pix[1,1] to pix[1,n] are sequentially input to the arithmetic circuits MA[1,1] to MA[3,1] each time a potential change from low to high occurs as a clock signal on the wiring CKL. Also, the pixel data pix[2,1] to pix[2,n] are sequentially input to the arithmetic circuits MA[4,1] to MA[6,1] after the potential change from low to high occurs three times as a clock signal on the wiring CKL after data is input to the arithmetic circuits MA[1,1] to MA[3,1]. In addition, after data is input to the arithmetic circuits MA[4,1] to MA[6,1], the pixel data pix[3,1] to pix[3,n] are sequentially input to the arithmetic circuits MA[7,1] to MA[9,1] after three potential changes from low-level potential to high-level potential occur as a clock signal on the wiring CKL.

[0167] In addition, after pixel data pix[1,n] is input to the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[4,1] through pix[4,n] may be input sequentially. Similarly, after pixel data pix[2,n] is input to the arithmetic circuits MA[4,1] through MA[6,1], pixel data pix[5,1] through pix[5,n] may be input sequentially, and after pixel data pix[3,n] is input to the arithmetic circuits MA[7,1] through MA[9,1], pixel data pix[6,1] through pix[6,n] may be input sequentially. In this way, after pixel data pix for one row is input to the arithmetic circuits MA[1,1] through MA[9,1], the pixel data pix for the next row may be input to continue the arithmetic processing.

[0168] In addition, as will be described later in detail, in FIG. 10B, pixel data pix (e.g., time T 1 In the above, the pixel pix[1,1] stored in the register RG[2,p] and the register RG[3,p] and input to the arithmetic circuit MA[2,1] and the arithmetic circuit MA[3,1], etc., is data that is not used in the CNN calculation. Therefore, when performing calculations in the MAC array MAR, only the data of the pixel pix enclosed by the solid line may be input to the MAC array MAR. However, when actually configuring a calculation device, it may be easier to configure the calculation device by configuring the pixel pix enclosed by the dotted line to be sent as dummy data together with the pixel pix enclosed by the black line, rather than inputting only the data of the pixel pix enclosed by the solid line to the MAC array MAR.

[0169] The pixel data pix is ​​input to the MAC array MAR through the filter fil 1 or filter fil 10 This can only be applied when the filter has 3 rows and 3 columns. 1 or filter fil 10When the filter read into the arithmetic circuit MA of the MAC array MAR has a row and b columns (a is an integer equal to or greater than 1, and b is an integer equal to or greater than 1), the MAC array MAR to which the pixel data pix is ​​input from the register RG may have a×b rows (i.e., the number of rows in the arithmetic circuit MA of the MAC array MAR may be a×b). Also, the pixel data pix may be input into the MAC array MAR in groups of a rows with a difference of a clock signal. For example, when the filter read into the arithmetic circuit MA of the MAC array MAR has 2 rows and 3 columns, the pixel data and timing input from the register RG to the MAC array MAR may be as shown in FIG. 11.

[0170] Next, with reference to Fig. 3, consider the case where pixel data pix is ​​input to terminal SI of arithmetic circuit MA. The pixel data pix input to terminal SI of arithmetic circuit MA is input to terminal IT1 of register RG1 included in arithmetic circuit MA. When the clock signal changes from low level potential to high level potential, for example, register RG1 holds the pixel data pix input to terminal IT1 and outputs the pixel data pix from terminal OT1.

[0171] The register RG1 is electrically connected to the wiring CKL, and therefore can output pixel data pix to the terminal OT1 in synchronization with the register RG outside the MAC array MAR described above. The pixel data pix output from the terminal OT1 is input to the terminal SO of the arithmetic circuit MA, and the terminal SO of the arithmetic circuit MA is in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. Therefore, the arithmetic circuits MA included in one row of the MAC array MAR can be regarded as registers connected in series, with the terminal SI as an input terminal and the terminal SO as an output terminal. Therefore, the arithmetic circuits MA included in one row of the MAC array MAR can sequentially transmit pixel data pix in response to a clock signal, similar to the register RG outside the MAC array MAR. For example, the pixel data pix sequentially transmitted to the registers RG[s,1] to RG[s,p] are then sequentially transmitted to the arithmetic circuits MA[s,1] to MA[s,v] (v=10 in this operation example) of the MAC array MAR.

[0172] In this operation method, it is assumed that a high level potential is always applied to the terminal CT2 of the register RG2, that is, a high level potential is always applied to the line SLT.

[0173] The pixel data pix output from the terminal OT1 of the register RG1 is input to the terminal IT2 of the register RG2. The register RG2 is electrically connected to the line CKL, so that the pixel data pix can be output to the terminal OT2 in synchronization with the register RG and the register RG1 external to the MAC array MAR described above. Therefore, the register RG2 holds the pixel data pix input to the terminal IT2 and outputs the pixel data pix to the terminal OT2. The pixel data pix output to the terminal OT2 is input to the terminal XI of the multiplier MP.

[0174] That is, the pixel data pix input to the terminal IT1 of the register RG1 is output to the terminal OT2 of the register RG2 when the potential changes from a low level potential to a high level potential twice as the clock signal input to the line CKL.

[0175] [Step 3: Multiply and accumulate the filter value and pixel data pix] In step 2, the pixel data pix is ​​input to the arithmetic circuit MA, whereby the arithmetic circuit MA multiplies the pixel data pix by a filter value read out from the memory unit OSM of the arithmetic circuit MA.

[0176] [Time T 1 〕 FIG. 12A shows an example of a time T 1 12A is a block diagram illustrating data output to terminals AO of some arithmetic circuits MA of a MAC array MAR in the MAC array MAR in the embodiment 1. Note that Fig. 12A only illustrates registers RG[1,p] through RG[5,p] and arithmetic circuits MA[1,1] through MA[5,1].

[0177] Time T 1 At time T 1 In this example, pixel data pix[1,1] is input to the arithmetic circuits MA[1,1] through MA[3,1], and pixel data is not input to the arithmetic circuits MA[4,1] through MA[9,1]. Therefore, in FIG. 12A, BLK is shown to indicate that no pixel data is input to the arithmetic circuits MA[4,1] through MA[9,1].

[0178] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0179] Time T 1 At this stage, no operation results have been generated in any of the arithmetic circuits MA of the MAC array MAR. Therefore, in FIG. 12A, BLK is shown at the terminals AO of each of the arithmetic circuits MA[1,1] through MA[9,1], indicating that no operation results are being output.

[0180] [Time T2 〕 FIG. 12B shows an example of a time T 2 12B is a block diagram illustrating data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR in ...

[0181] Time T 2 In this case, pixel data pix[1,2] is output from the registers RG[1,p] through RG[3,p], and pixel data is not input from the arithmetic circuits MA[4,1] through MA[9,1]. Also, as described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so that at time T 2 In this example, pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1]. Furthermore, pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[9,1].

[0182] At this time, pixel data pix[1,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] through MA[3,1]. Also, pixel data pix[1,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0183] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] through MA[3,2].

[0184] Time T 2 At this stage, no operation results have been generated in any of the arithmetic circuits MA of the MAC array MAR. Therefore, in Fig. 12B, like Fig. 12A, BLK is shown at the terminals AO of each of the arithmetic circuits MA[1,1] to MA[9,1], indicating that no operation results are being output.

[0185] [Time T 3 〕 Next, at time T 3 Consider the operation of the MAC array MAR at time T 3 13 is a block diagram illustrating data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR in ...

[0186] Time T 3 In this case, pixel data pix[1,3] is input from the registers RG[1,p] to RG[3,p] to the arithmetic circuits MA[1,1] to MA[3,1], and pixel data is not input to the arithmetic circuits MA[4,1] to MA[9,1]. Also, as described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so that at time T 3 In this example, pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[9,1] and the arithmetic circuits MA[4,2] through MA[9,2].

[0187] At this time, pixel data pix[1,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] through MA[3,1]. Also, pixel data pix[1,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0188] The pixel data pix[1,1] is input to a terminal IT2 of a register RG2 in each of the arithmetic circuits MA[1,2] through MA[3,2]. The pixel data pix[1,2] is input to a terminal IT1 of a register RG1 in each of the arithmetic circuits MA[1,2] through MA[3,2].

[0189] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] to MA[3,3].

[0190] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0191] Here, the calculations performed by the calculation circuits MA[1,1] through MA[9,1] will be described.

[0192] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 1 [1,1]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,1] × pix[1,1] is output. Note that in this example, F 1 [1,1] [1]=fil 1 Let [1,1]×pix[1,1]. F 1 [1,1] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0193] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 1 [1,2]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,2] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, so hereafter it will be referred to as FD. This FD is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,1].

[0194] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 1 [1,3]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,3] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, as with the previous calculation circuit MA[2,1], so it will be referred to as FD from now on. This FD is input to terminal IT3 of register RG3 of calculation circuit MA[3,1].

[0195] In the arithmetic circuits MA[4,1] through MA[9,1], no arithmetic operations are performed since pixel data pix is ​​not input to terminal XI of multiplier MP.

[0196] [Time T 4 〕 Next, at time T 4 Consider the operation of the MAC array MAR at time T 414 is a block diagram illustrating data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR in the MAC array MAR in the embodiment 1. Note that Fig. 14 only illustrates the registers RG[1,p] through RG[5,p], the arithmetic circuits MA[1,1] through MA[5,1], the arithmetic circuits MA[1,2] through MA[5,2], and the arithmetic circuits MA[1,3] through MA[5,3].

[0197] In this operation method, it is assumed that a high-level potential is always applied to the terminal CT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[9,10]. In other words, it is assumed that a high-level potential is always applied to the wiring URST.

[0198] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state. 1 [1,1] [1] is input to terminal AI of arithmetic circuit MA[2,1].

[0199] Similarly, in each of the arithmetic circuits MA[2,1] and MA[3,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[2,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[3,1] via the terminal AO of the arithmetic circuit MA[2,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[2,1] is input to the terminal AI of the circuit MA[3,1]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[3,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[4,1] via the terminal AO of the arithmetic circuit MA[3,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[3,1] is input to the terminal AI of the circuit MA[4,1].

[0200] Time T 4 In this example, pixel data pix[1,4] is input from register RG[1,p] to register RG[3,p] to arithmetic circuit MA[1,1] to arithmetic circuit MA[3,1], pixel data pix[2,1] is input from register RG[4,p] to register RG[6,p] to arithmetic circuit MA[4,1] to arithmetic circuit MA[6,1], and no pixel data is input to arithmetic circuit MA[7,1] to arithmetic circuit MA[9,1]. Also, as described above, since the arithmetic circuit MA of the MAC array MAR also functions as a register, at time T 4 In this example, pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Furthermore, pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[9,1], the arithmetic circuits MA[4,2] through MA[9,2], and the arithmetic circuits MA[4,3] through MA[9,3].

[0201] At this time, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] through MA[3,1]. Also, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0202] Furthermore, pixel data pix[1,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] through MA[3,2]. Furthermore, pixel data pix[1,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] through MA[3,2].

[0203] Furthermore, pixel data pix[1,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,3] through MA[3,3]. Furthermore, pixel data pix[1,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] through MA[3,3].

[0204] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] to MA[6,1].

[0205] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0206] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0207] Here, the calculations performed in the arithmetic circuit MA[1,1] through the arithmetic circuit MA[9,1] and the arithmetic circuit MA[1,2] through the arithmetic circuit MA[9,2] will be described.

[0208] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 1 [1,1]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,1] × pix[1,2] is output. Note that in this example, F 1 [1,2] [1]=fil 1 Let [1,1]×pix[1,2]. F 1 [1,2] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0209] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 1 [1,2]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1 [1,1] The value [1] is input. This causes the terminal TT of the adder AD to be F 1 [1,1] [1]+fil 1 [1,1] × pix[1,2] is output. Note that in this example, F 1 [1,1] [2]=F 1 [1,1] [1]+fil 1 Let [1,1]×pix[1,2]. F 1 [1,1][2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,1].

[0210] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 1 [1,3]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is input with the FD output from the terminal AO of the arithmetic circuit MA[2,1]. However, since this calculation result is not used for CNN calculations, hereafter it will be referred to as FD. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0211] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 2 [1,1]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 2 [1,1] × pix[1,1] is output. Note that in this example, F 2 [1,1] [1]=fil 2 Let [1,1]×pix[1,1]. F 2 [1,1] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,2].

[0212] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 2[1,2]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 2 [1,2] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, so hereafter it will be referred to as FD. This FD is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,2].

[0213] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 2 [1,3]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 2 [1,3] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, as with the previous calculation circuit MA[2,2], so it will be referred to as FD from now on. This FD is input to terminal IT3 of register RG3 of calculation circuit MA[3,2].

[0214] In addition, in the arithmetic circuits MA[4,1] through MA[9,1] and MA[4,2] through MA[9,2], no calculations are performed because pixel data pix is ​​not input to the terminal XI of the multiplier MP.

[0215] [Time T 5 〕 Next, at time T 5 Consider the operation of the MAC array MAR at time T 515 is a block diagram illustrating data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR in the MAC array MAR in the embodiment 1. Note that Fig. 15 only illustrates the registers RG[1,p] through RG[5,p], the arithmetic circuits MA[1,1] through MA[5,1], the arithmetic circuits MA[1,2] through MA[5,2], and the arithmetic circuits MA[1,3] through MA[5,3].

[0216] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state. 1 [1,2] [1] is input to the terminal AI of the arithmetic circuit MA[2,1]. Similarly, in the arithmetic circuit MA[2,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and in addition, the terminal AO of the arithmetic circuit MA[2,1] and the terminal AI of the arithmetic circuit MA[3,1] are in a conductive state. 1 [1,1] [2] is input to terminal AI of arithmetic circuit MA[3,1].

[0217] Similarly, in each of the arithmetic circuits MA[3,1] and MA[4,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[3,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[4,1] via the terminal AO of the arithmetic circuit MA[3,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[3,1] is input to the terminal AI of the circuit MA[4,1]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[4,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[5,1] via the terminal AO of the arithmetic circuit MA[4,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[4,1] is input to the terminal AI of the circuit MA[5,1].

[0218] In the arithmetic circuit MA[1,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs 2 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2], and in addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal AI of the arithmetic circuit MA[2,2] are in a conductive state. 2 [1,1] [1] is input to terminal AI of arithmetic circuit MA[2,2].

[0219] Similarly, in each of the arithmetic circuits MA[2,2] and MA[3,2], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[2,2] is in a conductive state with the terminal AI of the arithmetic circuit MA[3,2] via the terminal AO of the arithmetic circuit MA[2,2], so the result FD of the arithmetic circuit MA[2,2] is input to the terminal AI of the circuit MA[3,2]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[3,2] is in a conductive state with the terminal AI of the arithmetic circuit MA[4,2] via the terminal AO of the arithmetic circuit MA[3,2], so the result FD of the arithmetic circuit MA[3,2] is input to the terminal AI of the circuit MA[4,2].

[0220] Time T 5 In this example, pixel data pix[1,5] is input from register RG[1,p] to register RG[3,p] to arithmetic circuit MA[1,1] to arithmetic circuit MA[3,1], pixel data pix[2,2] is input from register RG[3,p] to register RG[6,p] to arithmetic circuit MA[4,1] to arithmetic circuit MA[6,1], and no pixel data is input to arithmetic circuit MA[7,1] to arithmetic circuit MA[9,1]. Also, as described above, since the arithmetic circuit MA of the MAC array MAR also functions as a register, at time T 5 In this example, pixel data pix[1,4] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Pixel data pix[2,1] is output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[6,1]. Pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[7,1] through MA[9,1], the arithmetic circuits MA[4,2] through MA[9,2], and the arithmetic circuits MA[4,3] through MA[9,3].

[0221] At this time, pixel data pix[1,4] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] through MA[3,1]. Also, pixel data pix[1,5] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0222] Furthermore, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] through MA[3,2]. Furthermore, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] through MA[3,2].

[0223] The pixel data pix[1,2] is input to a terminal IT2 of a register RG2 of each of the arithmetic circuits MA[1,3] through MA[3,3]. The pixel data pix[1,3] is input to a terminal IT1 of a register RG1 of each of the arithmetic circuits MA[1,3] through MA[3,3].

[0224] Furthermore, pixel data pix[2,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,1] through MA[6,1]. Furthermore, pixel data pix[2,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] through MA[6,1].

[0225] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,2] through MA[6,2].

[0226] Furthermore, pixel data pix[1,3] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,3] is input to terminal XI of multiplier MP.

[0227] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0228] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0229] Here, the calculations performed in the arithmetic circuit MA[1,1] through the arithmetic circuit MA[9,1], the arithmetic circuit MA[1,2] through the arithmetic circuit MA[9,2], and the arithmetic circuit MA[1,3] through the arithmetic circuit MA[9,3] will be described.

[0230] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 1 [1,1]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,1] × pix[1,3] is output. Note that in this example, F 1 [1,3] [1]=fil 1 Let [1,1]×pix[1,3]. F 1 [1,3] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0231] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1[1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 1 [1,2]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1 [1,2] The value [1] is input. This causes the terminal TT of the adder AD to be F 1 [1,2] [1]+fil 1 [1,2] × pix[1,3] is output. Note that in this example, F 1 [1,2] [2]=F 1 [1,2] [1]+fil 1 Let [1,2]×pix[1,3]. F 1 [1,2] [2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,1].

[0232] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 1 [1,3]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1 [1,1] The value of [2] is input. This causes the terminal TT of the adder AD to be F 1 [1,1] [2]+fil 1 [1,3] × pix[1,3] is output. Note that in this example, F 1 [1,1] [3]=F 1 [1,1] [2]+fil 1 Let [1,3]×pix[1,3]. F 1 [1,1] [3] is input to terminal IT3 of register RG3 of arithmetic circuit MA[3,1].

[0233] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 2 [1,1]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 2 [1,1] × pix[1,2] is output. Note that in this example, F 2 [1,2] [1]=fil 2 Let [1,1]×pix[1,2]. F 2 [1,2] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,2].

[0234] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 2 [1,2]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 2 [1,1] The value [1] is input. This causes the terminal TT of the adder AD to be F 2 [1,1] [1]+fil 2 [1,2] × pix[1,2] is output. Note that in this example, F 2 [1,1] [2]=F 2 [1,1] [1]+fil 2 Let [1,2]×pix[1,2]. F 2 [1,1] [2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,2].

[0235] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 2 [1,3]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is input with the FD output from the terminal AO of the arithmetic circuit MA[2,2]. However, since this calculation result is not used for CNN calculations, hereafter it will be referred to as FD. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2].

[0236] In the arithmetic circuit MA[1,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 3 [1,1]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 3 [1,1] × pix[1,1] is output. Note that in this example, F 3 [1,1] [1]=fil 3 Let [1,1]×pix[1,1]. F 3 [1,1] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,3].

[0237] In the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 3[1,2]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 3 [1,2] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, so hereafter it will be referred to as FD. This FD is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,3].

[0238] In the arithmetic circuit MA[3,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,1] is input to the terminal ZO of the multiplier MP. 3 [1,3]×pix[1,1] is output and input to the terminal FT of the adder AD. Also, for example, a value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 3 [1,3] × pix[1,1] is output. However, this calculation result is not used for CNN calculations, as with the previous calculation circuit MA[2,3], so it will be referred to as FD from now on. This FD is input to terminal IT3 of register RG3 of calculation circuit MA[3,3].

[0239] In addition, in the arithmetic circuits MA[4,1] through MA[9,1], MA[4,2] through MA[9,2], and MA[4,3] through MA[9,3], no calculations are performed because pixel data pix is ​​not input to the terminal XI of the multiplier MP.

[0240] [Time T 6 〕 Next, at time T 6 Consider the operation of the MAC array MAR at time T 616 is a block diagram illustrating data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR in the MAC array MAR in the embodiment 1. Note that Fig. 16 only illustrates the registers RG[1,p] through RG[5,p], the arithmetic circuits MA[1,1] through MA[5,1], the arithmetic circuits MA[1,2] through MA[5,2], and the arithmetic circuits MA[1,3] through MA[5,3].

[0241] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,3] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state. 1 [1,3] [1] is input to the terminal AI of the arithmetic circuit MA[2,1]. Similarly, in the arithmetic circuit MA[2,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and in addition, the terminal AO of the arithmetic circuit MA[2,1] and the terminal AI of the arithmetic circuit MA[3,1] are in a conductive state. 1 [1,2] [2] is input to the terminal AI of the arithmetic circuit MA[3,1]. In addition, in the arithmetic circuit MA[3,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 1 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[3,1], and in addition, the terminal AO of the arithmetic circuit MA[3,1] and the terminal AI of the arithmetic circuit MA[4,1] are in a conductive state. 1 [1,1] [3] is input to terminal AI of arithmetic circuit MA[3,1].

[0242] Similarly, in each of the arithmetic circuits MA[4,1] and MA[5,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[4,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[5,1] via the terminal AO of the arithmetic circuit MA[4,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[4,1] is input to the terminal AI of the circuit MA[5,1]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[5,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[6,1] via the terminal AO of the arithmetic circuit MA[5,1], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[5,1] is input to the terminal AI of the circuit MA[6,1].

[0243] In the arithmetic circuit MA[1,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs 2 [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2], and in addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal AI of the arithmetic circuit MA[2,2] are in a conductive state. 2 [1,2] [1] is input to the terminal AI of the arithmetic circuit MA[2,2]. Similarly, in the arithmetic circuit MA[2,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 2 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,2], and in addition, the terminal AO of the arithmetic circuit MA[2,2] and the terminal AI of the arithmetic circuit MA[3,2] are in a conductive state. 2 [1,1] [2] is input to terminal AI of arithmetic circuit MA[3,2].

[0244] Similarly, in each of the arithmetic circuits MA[3,2] and MA[4,2], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[3,2] is in a conductive state with the terminal AI of the arithmetic circuit MA[4,2] via the terminal AO of the arithmetic circuit MA[3,2], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[3,2] is input to the terminal AI of the circuit MA[4,2]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[4,2] is in a conductive state with the terminal AI of the arithmetic circuit MA[5,2] via the terminal AO of the arithmetic circuit MA[4,2], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[4,2] is input to the terminal AI of the circuit MA[5,2].

[0245] In the arithmetic circuit MA[1,3], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F 3 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,3], and in addition, the terminal AO of the arithmetic circuit MA[1,3] and the terminal AI of the arithmetic circuit MA[2,3] are in a conductive state. 3 [1,1] [1] is input to terminal AI of arithmetic circuit MA[2,3].

[0246] Similarly, in each of the arithmetic circuits MA[2,3] and MA[3,3], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from a low level potential to a high level potential as a clock signal. The terminal OT3 of the register RG3 of the arithmetic circuit MA[2,3] is in a conductive state with the terminal AI of the arithmetic circuit MA[3,3] via the terminal AO of the arithmetic circuit MA[2,3], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[2,3] is input to the terminal AI of the circuit MA[3,3]. In addition, the terminal OT3 of the register RG3 of the arithmetic circuit MA[3,3] is in a conductive state with the terminal AI of the arithmetic circuit MA[4,3] via the terminal AO of the arithmetic circuit MA[3,3], so the result FD of the arithmetic operation performed in the arithmetic circuit MA[3,3] is input to the terminal AI of the circuit MA[4,3].

[0247] Time T 6 In this example, pixel data pix[1,6] is input from register RG[1,p] to register RG[3,p] to arithmetic circuit MA[1,1] to arithmetic circuit MA[3,1], pixel data pix[2,3] is input from register RG[4,p] to register RG[6,p] to arithmetic circuit MA[4,1] to arithmetic circuit MA[6,1], and no pixel data is input to arithmetic circuit MA[7,1] to arithmetic circuit MA[9,1]. Also, as described above, since the arithmetic circuit MA of the MAC array MAR also functions as a register, at time T 6In this example, pixel data pix[1,5] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,4] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Also, pixel data pix[2,2] is output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[6,1], and pixel data pix[2,1] is output from the terminal SO of each of the arithmetic circuits MA[4,2] through MA[6,2]. Furthermore, no pixel data pix is ​​output from the terminals SO of the arithmetic circuits MA[7,1] through MA[9,1], MA[4,2] through MA[9,2], and MA[4,3] through MA[9,3].

[0248] At this time, pixel data pix[1,5] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] through MA[3,1]. Also, pixel data pix[1,6] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] through MA[3,1].

[0249] Furthermore, pixel data pix[1,4] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] through MA[3,2]. Furthermore, pixel data pix[1,5] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] through MA[3,2].

[0250] Furthermore, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,3] through MA[3,3]. Furthermore, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] through MA[3,3].

[0251] Furthermore, pixel data pix[2,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,1] through MA[6,1]. Furthermore, pixel data pix[2,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] through MA[6,1].

[0252] Furthermore, pixel data pix[2,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,2] through MA[6,2]. Furthermore, pixel data pix[2,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,2] through MA[6,2].

[0253] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,3] to MA[6,3].

[0254] Furthermore, pixel data pix[1,4] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,4] is input to terminal XI of multiplier MP.

[0255] Furthermore, pixel data pix[1,3] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,3] is input to terminal XI of multiplier MP.

[0256] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0257] Furthermore, pixel data pix[2,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[4,1] to MA[6,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[2,1] is input to terminal XI of multiplier MP.

[0258] Here, the calculations performed in the arithmetic circuit MA[1,1] through the arithmetic circuit MA[9,1], the arithmetic circuit MA[1,2] through the arithmetic circuit MA[9,2], and the arithmetic circuit MA[1,3] through the arithmetic circuit MA[9,3] will be described.

[0259] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,4] is input to the terminal ZO of the multiplier MP. 1 [1,1]×pix[1,4] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 1 [1,1]×pix[1,4] is output. Note that in this example, F 1 [1,4] [1]=fil 1 Let [1,1]×pix[1,4]. F 1 [1,4] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0260] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,4] is input to the terminal ZO of the multiplier MP. 1 [1,2]×pix[1,4] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1 [1,3] The value [1] is input. This causes the terminal TT of the adder AD to be F1 [1,3] [1]+fil 1 [1,2] × pix[1,4] is output. Note that in this example, F 1 [1,3] [2]=F 1 [1,3] [1]+fil 1 Let [1,2]×pix[1,4]. F 1 [1,3] [2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,1].

[0261] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,4] is input to the terminal ZO of the multiplier MP. 1 [1,3]×pix[1,4] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1 [1,2] The value of [2] is input. This causes the terminal TT of the adder AD to be F 1 [1,2] [2]+fil 1 [1,3] × pix[1,4] is output. Note that in this example, F 1 [1,2] [3]=F 1 [1,2] [2]+fil 1 Let [1,3]×pix[1,4]. F 1 [1,2] [3] is input to terminal IT3 of register RG3 of arithmetic circuit MA[3,1].

[0262] In the arithmetic circuit MA[4,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [2,1] is input to the terminal XI of the multiplier MP, and pixel pix[2,1] is input to the terminal ZO of the multiplier MP. 1 [2,1]×pix[2,1] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 1[1,1] The value of [3] is input. This causes the terminal TT of the adder AD to be F 1 [1,1] [3]+fil 1 [2,1] × pix[2,1] is output. Note that in this example, F 1 [1,1] [4]=F 1 [1,1] [3]+fil 1 Let [2,1]×pix[2,1]. F 1 [1,1] [4] is input to terminal IT3 of register RG3 of arithmetic circuit MA[4,1].

[0263] In the arithmetic circuit MA[5,1], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [2,2] is input to the terminal XI of the multiplier MP, and pixel pix[2,1] is input to the terminal ZO of the multiplier MP. 1 [2,2]×pix[2,1] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is input with the FD output from the terminal AO of the arithmetic circuit MA[4,1]. However, since this calculation result is not used for CNN calculations, hereafter it will be referred to as FD. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[5,1].

[0264] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 2 [1,1]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 2 [1,1] × pix[1,3] is output. Note that in this example, F 2 [1,3] [1]=fil 2 Let [1,1]×pix[1,3]. F2 [1,3] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0265] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP is supplied with a filter value fil 2 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 2 [1,2]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 2 [1,2] The value [1] is input. This causes the terminal TT of the adder AD to be F 2 [1,2] [1]+fil 2 [1,2] × pix[1,3] is output. Note that in this example, F 2 [1,2] [2]=F 2 [1,2] [1]+fil 2 Let [1,2]×pix[1,3]. F 2 [1,2] [2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,2].

[0266] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP is supplied with a filter value fil 1 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,3] is input to the terminal ZO of the multiplier MP. 2 [1,3]×pix[1,3] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 2 [1,1] The value of [2] is input. This causes the terminal TT of the adder AD to be F 2 [1,1] [2]+fil 2 [1,3] × pix[1,3] is output. Note that in this example, F 2 [1,1] [3]=F 2 [1,1][2]+fil 2 Let [1,3]×pix[1,3]. F 2 [1,1] [3] is input to terminal IT3 of register RG3 of arithmetic circuit MA[3,2].

[0267] In the arithmetic circuit MA[1,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,1] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 3 [1,1]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, assume that the value of “0” is input to the terminal ST of the adder AD. This causes the terminal TT of the adder AD to receive the fil 3 [1,1] × pix[1,2] is output. Note that in this example, F 3 [1,2] [1]=fil 3 Let [1,1]×pix[1,2]. F 3 [1,2] [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,3].

[0268] In the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,2] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 3 [1,2]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is 3 [1,1] The value [1] is input. This causes the terminal TT of the adder AD to be F 3 [1,1] [1]+fil 3 [1,2] × pix[1,2] is output. Note that in this example, F 3 [1,1] [2]=F 3 [1,1] [1]+fil 3 Let [1,2]×pix[1,2]. F3 [1,1] [2] is input to terminal IT3 of register RG3 of arithmetic circuit MA[2,3].

[0269] In the arithmetic circuit MA[3,3], the terminal WI of the multiplier MP is supplied with a filter value fil 3 [1,3] is input to the terminal XI of the multiplier MP, and pixel pix[1,2] is input to the terminal ZO of the multiplier MP. 2 [1,3]×pix[1,2] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is input with the FD output from the terminal AO of the arithmetic circuit MA[2,3]. However, since this calculation result is not used for CNN calculations, hereafter it will be referred to as FD. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,3].

[0270] In addition, in the arithmetic circuits MA[6,1] through MA[9,1], MA[4,2] through MA[9,2], and MA[4,3] through MA[9,3], no calculations are performed because pixel data pix is ​​not input to the terminal XI of the multiplier MP.

[0271] The above-mentioned operation is performed at a certain time (here, for example, at time T 11 Continuing this process, we get the terminal AO of the arithmetic circuit MA[9,1], F 1 [1,1] [9] is output. F 1 [1,1] [9], from the above operation, F 1 [1,1] [9]=fil 1 [1,1]×pix[1,1]+fil 1 [1,2]×pix[1,2]+fil 1 [1,3]×pix[1,3]+fil 1 [2,1]×pix[2,1]+fil 1 [2,2]×pix[2,2]+fil 1 [2,3]×pix[2,3]+fil 1[3,1]×pix[3,1]+fil 1 [3,2]×pix[3,2]+fil 1 The result is [3,3]×pix[3,3].

[0272] In other words, F 1 [1,1] [9] filters the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using a filter fil 1 The value is obtained by convolution with

[0273] Also, at time T 11 Therefore, the time when the potential of the clock signal on the wiring CKL changes from a low level potential to a high level potential once (here, for example, time T 12 In this case, the terminal AO of the arithmetic circuit MA[9,1] is connected to F 1 [1,2] [9] is output. F 1 [1,2] [9], from the above operation, F 1 [1,2] [9]=fil 1 [1,1]×pix[1,2]+fil 1 [1,2]×pix[1,3]+fil 1 [1,3]×pix[1,4]+fil 1 [2,1]×pix[2,2]+fil 1 [2,2]×pix[2,3]+fil 1 [2,3]×pix[2,4]+fil 1 [3,1]×pix[3,2]+fil 1 [3,2]×pix[3,3]+fil 1 The result is [3,3]×pix[3,4].

[0274] In other words, F 1 [1,2][9] filters the areas of pixel data pix[1,2] to pix[1,4], pixel data pix[2,2] to pixel data pix[2,4], and pixel data pix[3,2] to pixel data pix[3,4] of the image data IPD using a filter fil 1 The value is obtained by convolution with

[0275] Also, at time T 12 Now, from the terminal AO of the arithmetic circuit MA[9,2], F 2 [1,1] [9] is output. F 2 [1,1] [9], from the above operation, F 2 [1,1] [9]=fil 2 [1,1]×pix[1,1]+fil 2 [1,2]×pix[1,2]+fil 2 [1,3]×pix[1,3]+fil 2 [2,1]×pix[2,1]+fil 2 [2,2]×pix[2,2]+fil 2 [2,3]×pix[2,3]+fil 2 [3,1]×pix[3,1]+fil 2 [3,2]×pix[3,2]+fil 2 The result is [3,3]×pix[3,3].

[0276] In other words, F 2 [1,1] [9] filters the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using a filter fil 2 The value is obtained by convolution with

[0277] In this way, by inputting image data IPD to the MAC array MAR, the filters fil 1 or filter fil 10The results of the convolution operations performed by the convolution are output in sequence. The results of the convolution operations can be expressed as shown in FIG. 17 as an example. In the MAC array MAR shown in FIG. 17, the operation circuits MA[1,1] through MA[1,9] and the operation circuits MA[9,1] through MA[9,9] are selectively illustrated. 12 to time T 20 Each of these is at time T 11 In this case, the time is determined as the time when a potential change from a low level potential to a high level potential occurs once to nine times on the wiring CKL as a clock signal.

[0278] For example, at time T 18 In this case, when a potential change occurs in the wiring CKL from a low level potential to a high level potential as a clock signal, the filters fil 1 or filter fil 8 As a result of the convolution operation performed by 1 [1,8] [9], F 2 [1,7] [9], F 3 [1,6] [9], F 4 [1,5] [9], F 5 [1,4] [9], F 6 [1,3] [9], F 7 [1,2] [9], F 8 [1,1] Note that the convolution calculations have not been completed in the ninth and tenth columns of the MAC array MAR from the arithmetic circuit MA[9,9] and the arithmetic circuit MA[9,10], so no calculation results are output.

[0279] In addition, the convolution calculation results output from the calculation circuits MA[9,1] to MA[9,10] may be processed by the circuits AF[1] to AF

[10] using an activation function, a pooling layer, etc. As an example, the filter fil t F obtained by convolution of t [1,1] [9]~F t [m-2,n-2] [9], we apply the activation function to each of them to obtain F At [1,1] ~F At [m-2,n-2] It is assumed that the following can be obtained.

[0280] Here, F At [1,1] ~F At [m-2,n-2] The image data IPD-F is a matrix of m-2 rows and n-2 columns. t Image data IPD-F t For example, the filter fil t The filter fil is obtained by performing convolution processing with and then operating the result of the convolution processing with an activation function. t It is possible to obtain image data (sometimes called a feature map) that extracts only characteristic parts that depend on the image data IPD-F. t can be expressed, for example, as shown in FIG.

[0281] <<Operation of Convolutional Layer CL 2>> Next, a description will be given of a calculation method for the convolutional layer CL and the pooling layer PL, which is different from the above-mentioned method, using the calculation device 100. Note that, as an example, the calculation circuits MA included in the MAC array MAR of the calculation device 100 are arranged in a matrix of 9 rows and 10 columns, similar to the above-mentioned calculation method.

[0282] Further, the MAC array MAR in this operation method has a circuit configuration as shown in Fig. 19A, Fig. 19B, and Fig. 20 by the programmable switches PR and PC. Specifically, as shown in Fig. 19A, in the arithmetic circuit MA included in the s-th row (here, s is an integer between 1 and 9) of the MAC array MAR, the programmable switch PR is set so that the terminal SO of the arithmetic circuit MA is in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. For example, the programmable switch PR[s,1] and the programmable switch PR[s,2] are set so that the terminal SO of the arithmetic circuit MA[s,1] is in a conductive state with the terminal SI of the arithmetic circuit MA[s,2], and the programmable switch PR[s,2] and the programmable switch PR[s,3] are set so that the terminal SO of the arithmetic circuit MA[s,2] is in a conductive state with the terminal SI of the arithmetic circuit MA[s,3]. The wiring XL[s] is in a conductive state with the terminal SI of the arithmetic circuit MA[s,1] via the programmable switch PR[s,1]. In this manner, in this operation method, it is assumed that the programmable switch PR is set so that the arithmetic circuits MA in each row of the MAC array MAR are in a conductive state in series.

[0283] 19B, the MAC array MAR in this operation method is configured such that the terminal AO of the arithmetic circuit MA[s,1] to the arithmetic circuit MA[s,9] included in one row of the MAC array MAR is electrically connected to the terminal AI of another arithmetic circuit MA, and data output from the terminal AO of a certain arithmetic circuit MA is input to the terminal AI of the original arithmetic circuit MA via a plurality of different arithmetic circuits MA. For example, the programmable switch PR[s,9] and the programmable switch PR[s,8] are configured such that the terminal AO of the arithmetic circuit MA[s,9] is electrically connected to the terminal AI of the arithmetic circuit MA[s,8]. For example, the programmable switch PR[s,8] and the programmable switch PR[s,7] are configured such that the terminal AO of the arithmetic circuit MA[s,8] is electrically connected to the terminal AI of the arithmetic circuit MA[s,7]. Furthermore, the programmable switches PR[s,1] and PR[s,9] are set so that the terminal AO of the arithmetic circuit MA[s,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[s,9]. That is, in this operation method, the programmable switches PR[s,1] to PR[s,9] are set in the arithmetic circuit MA of each row of the MAC array MAR so that data output from the arithmetic circuit MA circulates to other arithmetic circuits MA in the same row. Note that in this operation method, since the arithmetic circuit MA[s,10] is not used, the arithmetic circuit MA[s,10] is in a non-conductive state with the other arithmetic circuits MA by the programmable switch PR[s,10].

[0284] In addition, as shown in FIG. 20, specifically, in the MAC array MAR in this operation method, in the arithmetic circuit MA included in the t-th column (where t is an integer between 1 and 10), the programmable switch PC is set so that the terminal MO of the arithmetic circuit MA is in a conductive state with the terminal MI of the adjacent arithmetic circuit MA. For example, the programmable switch PC[1,t] and the programmable switch PC[2,t] are set so that the terminal MO of the arithmetic circuit MA[1,t] is in a conductive state with the terminal MI of the arithmetic circuit MA[2,t]. Also, for example, the programmable switch PC[2,t] and the programmable switch PC[3,t] are set so that the terminal MO of the arithmetic circuit MA[2,t] is in a conductive state with the terminal MI of the arithmetic circuit MA[3,t]. The wiring YL[t] is in a conductive state with the terminal MO of the arithmetic circuit MA[9,t] via the programmable switch PC[9,t]. In this manner, in this operating method, it is assumed that the programmable switches PC are set so that the arithmetic circuits MA are serially connected to each other and brought into a conductive state in each column of the MAC array MAR.

[0285] FIG. 21 shows the time T 21 From time T 41 21 is a timing chart showing changes in data input to the terminals SI, SO, AI (adder terminal ST), AO, MO, terminals XI and WI of the multiplier MP, terminal TT of the adder, and terminal IT4 of the register RG4 of the arithmetic circuit MA[1,1] during and around the time. Also shown in Fig. 21 are changes in the potentials of the lines CKL, SLT, SEL, and URST. In Fig. 21, "high" represents a high-level potential, and "low" represents a low-level potential.

[0286] The calculation method performed in the MAC array MAR will be described below with reference to the timing chart in Fig. 21. Note that unless otherwise specified, this calculation method is assumed to be performed in the calculation circuits MA[1,1] to MA[1,9].

[0287] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, at time T 21 Prior to this, it is preferable that initialization data is input to the terminals SI, SO, XT, WT, AI (terminal ST), TT, and AO of each of the arithmetic circuits MA[1,1] to MA[9,10] (not shown in FIG. 21). The initialization data may be, for example, data with a value of "0". Furthermore, the potential of the wiring URST is changed from a low-level potential to a high-level potential, and the potential of the terminal AO is made appropriate by the register RG3. At this time, it is preferable that the potential of the terminal AO is set to, for example, a potential corresponding to the value of "0". Furthermore, when the potential of the wiring URST is a low-level potential, the potential of the wiring SEL is set to a high-level potential, and the potential of the terminal MO is made appropriate by the register RG4. At this time, it is preferable that the potential of the terminal MO is set to, for example, a potential corresponding to the value of "0".

[0288] [Step 1: Input image data] Next, pixel data pix of the image data IPD is input to each of the arithmetic circuits MA[1,1] to MA[9,10] of the MAC array MAR of the arithmetic device 100. Note that, as an example, the image data IPD here is composed of a plurality of pixel data pix[1,1] to pix[m,n] in m rows and n columns, as shown in Fig. 10A, in the same manner as in the above-mentioned arithmetic method.

[0289] The image data IPD is read out from the memory unit MEMD of the arithmetic device 100, for example.

[0290] As in the above-described calculation method, in this operation method, the registers RG[1,p] through RG[9,p] are electrically connected to the MAC array MAR, and pixel data pix is ​​input to the s-th row of the MAC array MAR via the registers RG[s,1] through RG[s,p].

[0291] The registers RG[s,1] through RG[s,p] sequentially transmit a plurality of pixel data pix read from the memory unit MEMD each time a potential change from a low level potential to a high level potential is input as a clock signal on the wiring CKL. As described above, the arithmetic circuits MA[s,1] through MA[s,10] in the sth row have a function as a register with the terminal SI as an input terminal and the terminal SO as an output terminal, so that the pixel data pix transmitted to the register RG[s,p] are sequentially transmitted to the arithmetic circuits MA[s,1] through MA[s,10] in response to the clock signal.

[0292] In this operation method, the pixel data pix is ​​transmitted to the MAC array MAR in such a way that the same pixel data pix is ​​input to the same column of the arithmetic circuit MA at the same timing for each row, as shown in FIG. 22A. In FIG. 22A, at time T 23 22A shows the input of pixel data pix to the MAC array MAR. Specifically, for example, pixel data pix[1,1] is held by the register RG1 of each of the arithmetic circuits MA[1,2] to MA[9,2] and output to the terminal SO of each of the arithmetic circuits MA[1,2] to MA[9,2]. Similarly, pixel data pix[1,2] is held by the register RG1 of each of the arithmetic circuits MA[1,1] to MA[9,1]. Note that registers RG[1,p] to RG[9,p] outside the MAC array MAR hold pixel data pix[1,3] and input the pixel data pix[1,3] to the arithmetic circuits MA[1,1] to MA[9,1]. Note that FIG. 22A does not show the arithmetic circuits MA[1,10] to MA[9,10].

[0293] From the stage shown in FIG. 22A, the potential of the clock signal changes six times from a low level potential to a high level potential, and the pixel data pix[3,3] is input to the terminals SI of the arithmetic circuits MA[1,1] to MA[9,1] as shown in FIG. 22B. The time at which this occurs is referred to as time T 29 Let us assume that.

[0294] Note that a low-level potential is input to the line SLT until the pixel data pix[1,1] is held in the register RG1 of the arithmetic circuits MA[1,9] through MA[9,9]. In other words, during the period from when the pixel data pix[1,1] is input to the MAC array MAR until when it is held in the register RG1 of the arithmetic circuits MA[1,1] through MA[9,9], the register RG2 does not acquire the pixel data pix from the terminal IT2.

[0295] After the pixel data pix[1,1] is stored in the register RG1 of the arithmetic circuit MA[1,9] to the arithmetic circuit MA[9,9], a high-level potential is temporarily input to the line SLT (the time at which this occurs is referred to as time T 31 At this time, a potential change from a low level potential to a high level potential occurs as the clock signal, and the register RG2 holds the pixel data pix[1,1] input to the terminal IT2 of the register RG2 of each of the arithmetic circuits MA[1,9] to MA[9,9], and outputs the pixel data pix[1,1] to the terminal OT2. After the pixel data pix[1,1] is held in the register RG2 of each of the arithmetic circuits MA[1,9] to MA[9,9], a low level potential is input to the wiring SLT. This is done to prevent the pixel data pix[1,1] held in the register RG2 from being rewritten when a potential change from a low level potential to a high level potential occurs as the clock signal.

[0296] In the MAC array MAR, the same applies to the arithmetic circuits other than the arithmetic circuit MA[1,9] to the arithmetic circuit MA[9,9] at time T 31 Then, a high-level potential is temporarily input to the line SLT. 31In the above, the pixel data pix input to the terminal IT2 of the register RG2 of each of the arithmetic circuits MA[1,1] to MA[9,8] is held, and the pixel data pix is ​​output to the terminal OT2. For example, since the pixel data pix[3,3] is input to the terminal IT2 of the register RG2 of the arithmetic circuit MA[9,1], a high-level potential is input to the wiring SLT at this time, and the pixel data pix[3,3] is output to the terminal OT2.

[0297] [Step 2: Reading the filter value] Also, at time T 31 At this time, in each of the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR of the arithmetic device 100, a filter value is read out from the storage unit OSM. Ct In addition, the matrix is ​​one component of the matrix included in fil shown in FIG. t As an example, it is assumed that a filter value corresponding to the context CTEX1 is read out from each of the storage units OSM of the arithmetic circuits MA[1,1] to MA[1,10] in the first row of the MAC array MAR.

[0298] The filter value corresponding to the context CTEX1 is the value in the block indicated by the context CTEX1, which is read from the storage unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9], as shown in Fig. 23. Note that Fig. 23 shows not only the filter values ​​corresponding to the context CTEX1, but also the filter values ​​corresponding to each of the contexts CTEX2 to CTEX9.

[0299] Specifically, when a signal of the context CTEX1 is provided to the storage unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9], the storage unit OSM of the arithmetic circuit MA[1,9] outputs a fil C1 [1,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,8]. C2[1,2] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,7]. C3 [1,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,6]. C4 [2,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,5]. C5 [2,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,4]. C6 [2,3] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,3]. C7 [3,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,2]. C8 [3,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,1]. C9 [3,3] is read out.

[0300] [Step 3: Multiplying the pixel data by the filter value] Next, the pixel data and filter values ​​performed by each of the multipliers MP in the arithmetic circuits MA[1,1] to MA[1,9] in the first row of the MAC array MAR will be described.

[0301] For example, in the arithmetic circuit MA[1,9], the terminal WI of the multiplier MP is supplied with a filter value fil C1 [1,1] is input to the register RG2. Also, since the pixel data pix[1,1] is held in the register RG2, the pixel data pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is C1 [1,1]×pix[1,1] is output. Also, assume that the terminal ST of the adder AD is input with data of “0” as the initial value. This causes the terminal FT of the adder AD to C1 When [1,1] × pix[1,1] is input, the terminal TT of the adder AD is filled with fil C1 [1,1]×pix[1,1] is output. Note that in this example, A 1 [1]=fil C1 Let [1,1]×pix[1,1]. A 1[1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,9].

[0302] Also, for example, in the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP is supplied with a filter value fil C9 In addition, since the pixel data pix[3,3] is held in the register RG2, the pixel data pix[3,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is set to fil C1 [3,3]×pix[3,3] is output. Also, assume that the terminal ST of the adder AD is input with data of “0” as the initial value. This causes the terminal FT of the adder AD to C9 When [3,3] × pix[3,3] is input, the terminal TT of the adder AD is filled with fil C9 [3,3] × pix[3,3] is output. 9 [1]=fil C9 Let [3,3]×pix[3,3]. A 9 [1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0303] The same calculations as those of the calculation circuits MA[1,2] through MA[1,8] are performed. At this time, the multiplication results output from the respective adders AD are input to the terminals IT3 of the respective registers RG3. The following table shows the multiplication results input to the terminals IT3 of the respective registers RG3 of the calculation circuits MA[1,1] through MA[1,9]. Each multiplication result is represented as A 9 [1], A 8 [1], A 7 [1], A 6 [1], A 5 [1], A 4 [1], A 3 [1], A 2 [1]

[0304] [Table 1]

[0305] [Step 4: Switching filter values ​​and adding calculation results] When a potential change from a low level potential to a high level potential occurs as the clock signal, the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] holds the addition data input to the terminal IT3 and outputs the addition data to the terminal OT3 of the register RG3 (the time at which this occurs is referred to as time T 32 As a result, as shown in FIG. 24A, the A 9 [1], A 8 [1], A 7 [1], A 6 [1], A 5 [1], A 4 [1], A 3 [1], A 2 [1], A 1 [1] is output.

[0306] A 1 [1] is input to the terminal AI of the arithmetic circuit MA[1,8], and A 2 [1] is input to the terminal AI of the arithmetic circuit MA[1,7], and A 3 [1] is input to the terminal AI of the arithmetic circuit MA[1,6], and A 4 [1] is input to the terminal AI of the arithmetic circuit MA[1,5], and A 5 [1] is input to the terminal AI of the arithmetic circuit MA[1,4], and A 6 [1] is input to the terminal AI of the arithmetic circuit MA[1,3], and A 7 [1] is input to the terminal AI of the arithmetic circuit MA[1,2], and A 8 [1] is input to the terminal AI of the arithmetic circuit MA[1,1], and A 9 [1] is input to terminal AI of arithmetic circuit MA[1,9].

[0307] At this time, it is assumed that in each of the arithmetic circuits MA[1,1] to MA[1,9], a filter value corresponding to the context CNTX2 shown in FIG. 23 is read out from the storage unit OSM.

[0308] Specifically, the storage unit OSM of the arithmetic circuit MA[1,8] stores fil C1 [1,2] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,7]. C2 [1,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,6]. C3 [2,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,5]. C4 [2,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,4]. C5 [2,3] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,3]. C6 [3,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,2]. C7 [3,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,1]. C8 [3,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,9]. C9 Assume that [1,1] is read out.

[0309] As a result, similar to step 3, in each of the arithmetic circuits MA[1,1] to MA[1,9], the pixel data pix held by the register RG2 is input to the terminal XI of the multiplier MP, and the changed filter value is input to the terminal WI of the multiplier MP, so that the multiplication result of the pixel data and the filter value is output from the terminal ZO of the multiplier MP.

[0310] Furthermore, in each of the adders AD of the arithmetic circuits MA[1,1] to MA[1,9], the multiplication result is input to the terminal FT of the adder AD, and the data input to the terminal AI is input to the terminal ST of the adder AD. Therefore, the sum data output from the terminal TT of the adder AD is as shown in the following table. Each multiplication result is represented as A 8 [2], A7 [2], A 6 [2], A 5 [2], A 4 [2], A 3 [2], A 2 [2], A 1 [2], A 9 [2]

[0311] [Table 2]

[0312] Then, the terminal IT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] is connected to A 8 [2], A 7 [2], A 6 [2], A 5 [2], A 4 [2], A 3 [2], A 2 [2], A 1 [2], A 9 [2] is entered.

[0313] In addition, when a potential change from a low level potential to a high level potential occurs as the clock signal, the registers RG3 of the arithmetic circuits MA[1,1] to MA[1,9] respectively output A from the terminals AO of the arithmetic circuits MA[1,1] to MA[1,9] as shown in FIG. 24B. 8 [2], A 7 [2], A 6 [2], A 5 [2], A 4 [2], A 3 [2], A 2 [2], A 1 [2], A 9 [2] is output.

[0314] [Step 5: Repeat step 4] The operation of step 4 is to hold the data input to the register RG3 of each of the arithmetic circuits MA[1,1] through MA[1,9], output the data to the terminal OT3 of the register RG3, read the corresponding filter value from the storage unit OSM of each of the arithmetic circuits MA[1,1] through MA[1,9], and add the multiplication result of the filter value and the pixel data pix to the corresponding data. In particular, the contexts CNTX3 through CNTX9 in FIG. 23 may be sequentially selected as the filter values ​​to be read from the storage unit OSM of each of the arithmetic circuits MA[1,1] through MA[1,9].

[0315] For example, in the arithmetic circuit MA[1,1], at time T 33 From time T 40 During this period, the contexts CNTX3 to CNTX9 in FIG. 23 are selected in order as filter values ​​to be read from the storage unit OSM. C7 [3,3], fil C6 [3,3], fil C5 [3,3], fil C4 [3,3], fil C3 [3,3], fil C2 [3,3], fil C1 The arithmetic circuit MA[1,1] switches from the terminal AO to the terminal A[3,3] by the operations in the contexts CNTX3 to CNTX9. 7 [3], A 6 [4], A 5 [5], A 4 [6], A 3 [7], A 2 [8], A 1 Outputs [9].

[0316] From the above, time T 40 At this stage, A is input to the terminal IT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9]. 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A5 [9], A 4 [9], A 3 [9], A 2 [9] is entered.

[0317] As an example, A 1 [9] is the result of the multiplication and accumulation of the filter value and the pixel data pix by the arithmetic circuits MA[1,1] to MA[1,9]. 1 [9] is, from the above operation, A 1 [9]=fil C1 [1,1]×pix[1,1]+fil C1 [1,2]×pix[1,2]+fil C1 [1,3]×pix[1,3]+fil C1 [2,1]×pix[2,1]+fil C1 [2,2]×pix[2,2]+fil C1 [2,3]×pix[2,3]+fil C1 [3,1]×pix[3,1]+fil C1 [3,2]×pix[3,2]+fil C1 The result is [3,3]×pix[3,3].

[0318] In other words, A 1 [9] filters the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using a filter fil C1 The value is obtained by convolution with

[0319] Similarly, A 9 [9] is, from the above operation, A 9 [9]=fil C9 [3,3]×pix[3,3]+fil C9 [1,1]×pix[1,1]+fil C9 [1,2]×pix[1,2]+fil C9 [1,3]×pix[1,3]+fil C9 [2,1]×pix[2,1]+fil C9[2,2]×pix[2,2]+fil C9 [2,3]×pix[2,3]+fil C9 [3,1]×pix[3,1]+fil C9 The result is [3,2]×pix[3,2].

[0320] In other words, A 9 [9] filters the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using a filter fil C9 The value is obtained by convolution with

[0321] Therefore, A 2 [9] to A 8 [9] Each of 1 [9] and A 9 Similarly to [9], the pixel data pix[1,1] to pixel data pix[1,3], the pixel data pix[2,1] to pixel data pix[2,3], and the pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD are filtered using the filter fil C2 or filter fil C8 The value is obtained by convolution with

[0322] [Step 6: Output the result of the multiply-and-accumulate operation] In step 6, the sum-of-products operation values ​​are output from the terminals MO of the arithmetic circuits MA[1,1] to MA[1,9]. 40 In the above, since a high-level potential is input to the control terminal of each of the selectors SLC of the arithmetic circuits MA[1,1] to MA[1,9], the first input terminal and the output terminal are in a conductive state, and the second input terminal and the output terminal are in a non-conductive state, which causes a conductive state between the terminal OT3 of the register RG3 and the terminal IT4 of the register RG4.

[0323] At this time, a potential change from a low level potential to a high level potential occurs as the clock signal, so that the data input to the terminal IT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] is held and the data is output to the terminal OT3 of the register RG3. Therefore, the data is input to the terminal IT4 of the register RG4.

[0324] That is, in the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9], 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A 5 [9], A 4 [9], A 3 [9], A 2 [9] is held, and the respective data is input to terminal IT4 of register RG4.

[0325] Furthermore, when a potential change from a low level potential to a high level occurs as a clock signal (the time at which this occurs is called T 41 The data input to the terminal IT4 of the register RG4 is held by the register RG4, and the data is output to the terminal OT4 of the register RG4. Therefore, the A 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A 5 [9], A 4 [9], A 3 [9], A 2 [9] is output from the terminals MO of the arithmetic circuits MA[1,1] through MA[1,9].

[0326] In step 6, a low-level potential is input to the control terminal of each selector SLC of the arithmetic circuits MA other than the arithmetic circuits MA[1,1] through MA[1,9] of the MAC array MAR. This causes a non-conductive state between the first input terminal and the output terminal, and a conductive state between the second input terminal and the output terminal. This causes a conductive state between the terminal MI of the corresponding arithmetic circuit MA and the terminal IT4 of the register RG4.

[0327] 20, the terminal MO of the arithmetic circuit MA[1,1] in the first column of the MAC array MAR is in a conductive state with the terminal MI of the arithmetic circuit MA[9,1] via the arithmetic circuits MA[2,1] to MA[8,1]. Similarly, for the other columns, in the same column of the MAC array MAR, the terminal MO of the arithmetic circuit MA located in the first row is in a conductive state with the terminal MI of the arithmetic circuit MA in the ninth row via the arithmetic circuits MA in the second to eighth rows.

[0328] Therefore, the terminals MO to A of the arithmetic circuits MA[1,1] to MA[1,9] 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A 5 [9], A 4 [9], A 3 [9], A 2 After the output of [9], eight potential changes from low level potential to high level potential occur as a clock signal, and as shown in FIG. 24C, A 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A 5 [9], A 4 [9], A 3 [9], A 2[9] is output.

[0329] On the other hand, in the arithmetic circuits MA other than the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR, a low-level potential is input to the control terminal of each selector SLC, so that the first input terminal and the output terminal are in a non-conductive state. 1 [9], A 9 [9], A 8 [9], A 7 [9], A 6 [9], A 5 [9], A 4 [9], A 3 [9], A 2 [9] and the like, and can perform calculations at the same time as outputting the calculation results. Therefore, in the calculation circuits MA other than the first row of the MAC array MAR, for example, convolution calculations may be performed on areas of the image data IPD other than the pixel data pix[1,1] to pixel data pix[1,3], the pixel data pix[2,1] to pixel data pix[2,3], and the pixel data pix[3,1] to pixel data pix[3,3].

[0330] As shown in the timing chart of FIG. 21, during the calculation by the multiplier MP and the adder AD, specifically, at time T 30 From time T 39During this period, the pixel data pix[1,2] through pix[1,4], the pixel data pix[2,2] through pix[2,4], and the pixel data pix[3,2] through pix[3,4] for the next calculation may be sequentially transmitted from the registers RG[1,p] through RG[9,p] to the MAC array MAR. By performing this operation, immediately after the convolution calculations for the pixel data pix[1,1] through pix[1,3], the pixel data pix[2,1] through pix[2,3], and the pixel data pix[3,1] through pix[3,3] are completed, the convolution calculations for the pixel data pix[1,2] through pix[1,4], the pixel data pix[2,2] through pix[2,4], and the pixel data pix[3,2] through pix[3,4] can be performed in the same manner. Moreover, by transmitting pixel data during calculation, the time spent waiting for data transfer can be reduced, thereby improving the efficiency of calculation.

[0331] The convolution calculation results output from the calculation circuits MA[9,1] to MA[9,10] may be processed by the circuits AF[1] to AF

[10] using activation functions, pooling layers, etc. For details of the processing, please refer to the above-mentioned explanation of the operation method.

[0332] In this operation method, as in the above-described operation method, the filter fil is applied to the image data IPD. Ct By performing convolution processing with Ct It is possible to generate image data (feature map) that extracts only the characteristic parts that depend on the

[0333] The above-mentioned operation method can be applied not only to the convolution calculation of image data but also to the calculation of FNN.

[0334] For example, m neurons (where m is an integer equal to or greater than 1) in the (k-1)th layer, N (k-1) 1 Neuron N (k-1)m Then, n neurons N in the kth layer (where n is an integer equal to or greater than 1) (k) 1 Neuron N (k) n Consider the case where a signal is sent to the (k-1)th layer neuron N (k-1) i (where i is an integer between 1 and m) (k-1) i Let N be the neuron in the (k-1)th layer. (k-1) i and the kth layer neuron N (k) j The weighting coefficient between (k-1) i (k) j Then, the (k-1)th layer neuron N (k-1) 1 Neuron N (k-1) m From the k-th layer neuron N (k) j The sum of the products of the signals input to and the weighting coefficients is S (k) j =Σw (k-1) i (k) j xz (k-1) i (Σ is the sum from 1 to m for i).

[0335] Here, the kth layer neuron N (k) 1 Neuron N (k) n S for each (k) j A method of calculating z is described below. (k-1) i Specifically, for example, in FIG. 26, the register RG2 of each of the arithmetic circuits MA[1,1] to MA[1,10] holds z (k-1) 10 ~z (k-1) 1 holds.

[0336] Next, the data read from the storage unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,10] is used as a weighting coefficient to set, for example, contexts CNTXF1 to CNTXF10. The contexts CNTXF1 to CNTXF10 may be set, for example, as shown in FIG. 26. In this way, z (k-1) 10 ~z (k-1) 1 By holding the weighting coefficients as shown in FIG. 26 and setting the contexts CNTXF1 to CNTXF10 to be read from the storage unit OSM, it is possible to perform FNN calculations in the same manner as the above-mentioned convolution calculations.

[0337] FIG. 26 shows the case where the number of neurons in the k-th layer is n=10, but if n is not 10, the number of contexts can be set to the number of n. FIG. 26 also shows the case where the number of neurons in the (k-1)-th layer is m=10, but if m is less than 10, the number of arithmetic circuits MA used for the calculation can be reduced. If m is greater than 10, the neuron signal z (k-1) 1 ~z (k-1) 10 When performing the multiplication and accumulation of the weighting coefficients, the signal of the neuron that will perform the next calculation may be held in advance in the register RG1 of each of the calculation circuits MA[1,1] through MA[1,10].

[0338] Moreover, the operation method of the semiconductor device according to an embodiment of the present invention is not limited to the above-mentioned method. The operation method of the semiconductor device according to an embodiment of the present invention can be changed according to the situation. For example, the configuration of the MAC array MAR set by the programmable switch PR shown in FIG. 19B may be changed to the configuration of the MAC array MAR set by the programmable switch PR shown in FIG. 25.

[0339] 25, the programmable switches PR[s,1] to PR[s,9] are set so that the terminal AO of the arithmetic circuit MA is in a conductive state with the terminal AI of the arithmetic circuit MA next to it. Note that for the arithmetic circuit MA[s,1] and the arithmetic circuit MA[s,2] and the programmable switch PR[s,1] are set so that the terminal AO of the arithmetic circuit MA[s,2] and the terminal AI of the arithmetic circuit MA[s,1] are in a conductive state, and for the arithmetic circuit MA[s,8] and the arithmetic circuit MA[s,9] and the programmable switch PR[s,9] and the programmable switch PR[s,8] are set so that the terminal AO of the arithmetic circuit MA[s,9] and the terminal AI of the arithmetic circuit MA[s,8] are in a conductive state.

[0340] In the configuration shown in FIG. 19B, the distance between terminal AO of arithmetic circuit MA[s,1] and terminal AI of arithmetic circuit MA[s,9] is long, which may cause signal delays. However, in the configuration shown in FIG. 25, the distance between arithmetic circuits MA can be shortened on average, which can suppress signal delays.

[0341] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0342] (Embodiment 2) In this embodiment, a storage circuit that can be applied to the storage unit OSM explained in the above-mentioned embodiment will be explained.

[0343] As the storage unit OSM, for example, a register, a flip-flop, a static random access memory (SRAM), etc. Also, for example, a flash memory, etc. may be used.

[0344] Furthermore, as the storage unit OSM, for example, a Dynamic Oxide Semiconductor Random Access Memory (DOSRAM) (registered trademark) or a Dynamic Oxide Semiconductor Random Access Memory (NOSRAM) (registered trademark) may be applied.

[0345] 27A shows an example of a circuit configuration of a memory cell of a DOSRAM. The memory cell 221 includes a transistor M1 and a capacitance element CA. The transistor M1 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0346] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, a back gate of the transistor M1 is connected to the wiring BGL, and a second terminal of the capacitance element CA is connected to the wiring CVL.

[0347] The transistor M1 functions as a write transistor in the memory cell 221. Note that the write transistor is preferably an OS transistor, which will be described later.

[0348] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CVL.

[0349] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0350] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and establish electrical continuity between the wiring BIL and the first terminal of the capacitor CA.

[0351] Specifically, data is written by applying a potential corresponding to data to be written to the wiring BIL and writing the potential to the first terminal of the capacitor CA through the transistor M1. After writing the data, a low-level potential is applied to the wiring WOL to turn off the transistor M1, so that the potential can be held in the memory cell 221.

[0352] To read data, first, the wiring BIL is precharged to an appropriate potential, for example, a potential intermediate between a low-level potential and a high-level potential, and then the wiring BIL is set in an electrically floating state. After that, a high-level potential is applied to the wiring WOL to turn on the transistor M1 and change the potential of the wiring BIL. Since the change in the potential of the wiring BIL is determined by the potential written to the first terminal of the capacitance element CA, the data held in the memory cell 221 can be read from the changed potential of the wiring BIL.

[0353] Furthermore, the above-described memory cell 221 is not limited to the circuit configuration shown in FIG. 27A, and the circuit configuration of the memory cell 221 may be changed as appropriate.

[0354] 27B shows an example of a circuit configuration of a memory cell of NOSRAM. The memory cell 231 includes a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0355] The transistor M2 functions as a write transistor in the memory cell 231. Note that the write transistor is preferably an OS transistor, which will be described later.

[0356] Moreover, the transistor M3 functions as a read transistor in the memory cell 231. The read transistor is preferably an OS transistor, which will be described later, or a transistor whose semiconductor layer contains silicon. In this operation example, the transistor M3 operates in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor M3 are appropriately biased to voltages within the range in which the transistor M3 operates in the saturation region.

[0357] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SOL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0358] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. During data retention, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL, and when writing and reading data, it is preferable to apply a high-level potential to the line CAL.

[0359] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0360] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WOL to turn off the transistor M2, thereby holding the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0361] Data is read by applying a predetermined potential to the wiring SOL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CB (or the gate of the transistor M3).

[0362] Moreover, the memory cell 231 described above is not limited to the circuit configuration shown in FIG. 27B, and the circuit configuration of the memory cell 231 may be changed as appropriate. For example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. 27C. The memory cell 232 is configured such that the wiring WBL and the wiring RBL of the memory cell 231 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 232 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0363] As described above, DOSRAM and NOSRAM are memory devices having an OS transistor as a write transistor. The semiconductor layer of the OS transistor has the metal oxide described in embodiment 3. The metal oxide can be, for example, one or more materials selected from indium, element M (one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc. In particular, when the semiconductor layer contains a metal oxide made of indium, gallium, or zinc, the band gap of the semiconductor layer can be increased. Therefore, the off-current of the OS transistor can be reduced.

[0364] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0365] (Embodiment 3) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device will be described.

[0366] <Example of semiconductor device configuration> The semiconductor device shown in Fig. 28 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 30A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 30C is a cross-sectional view of the transistor 300 in the channel width direction.

[0367] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has a characteristic of having a small off-state current and a field-effect mobility that does not change even at high temperatures. By applying the transistor 500 to a semiconductor device, such as a transistor included in the arithmetic device 100 or 100A described in the above embodiment, a semiconductor device whose operation capability is not degraded even at high temperatures can be realized. In particular, by utilizing the characteristic of having a small off-state current and applying the transistor 500 to the transistors M1 and M2, a potential written to the memory cell 221, the memory cell 231, the memory cell 232, and the like can be held for a long time.

[0368] 28, for example. The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistors 300 and 500. The capacitor 600 can be a capacitor included in the memory cell 231, the memory cell 232, or the like described in the above embodiment. Depending on the circuit configuration, the capacitor 600 illustrated in FIG. 28 is not necessarily provided.

[0369] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. Note that the transistor 300 can be applied to, for example, a transistor included in the arithmetic device 100 or 100A described in the above embodiments.

[0370] Moreover, as the substrate 311, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0371] 30C, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this manner, the effective channel width is increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0372] The transistor 300 may be either a p-channel type or an n-channel type.

[0373] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0374] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0375] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0376] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0377] 28 is just an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit including only OS transistors (which means a circuit including transistors of the same conductivity type, such as only n-channel transistors in this specification and the like), the structure of the transistor 300 may be the same as that of a transistor 500 including an oxide semiconductor, as shown in FIG 29. Details of the transistor 500 will be described later.

[0378] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 300.

[0379] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0380] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0381] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0382] The insulator 324 is preferably a film having a barrier property that prevents diffusion of hydrogen or impurities from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0383] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0384] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0385] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0386] A conductor 328, a conductor 330, and the like that connect to the capacitor 600 or the transistor 500 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as a plug or a wiring. In addition, a plurality of conductors that function as a plug or a wiring may be collectively given the same reference symbol. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as a wiring and a case where a part of a conductor functions as a plug.

[0387] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0388] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 28 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0389] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0390] Note that, for example, tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, it is possible to suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0391] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 28, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0392] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0393] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 28, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0394] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0395] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 28, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0396] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0397] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0398] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen or hydrogen.

[0399] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0400] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0401] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0402] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0403] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0404] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0405] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistors 300 and 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0406] Above the insulator 516 is a transistor 500 .

[0407] As shown in Figures 30A and 30B, a transistor 500 has a conductor 503 arranged so as to be embedded in an insulator 514 and an insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therebetween overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the formation surface of the oxide 530c, and a conductor 560 arranged on the formation surface of the insulator 550.

[0408] 30A and 30B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIG. 30A and 30B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIG. 30A and 30B.

[0409] In the following, oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.

[0410] Note that, in the transistor 500, a three-layer structure of the oxide 530a, the oxide 530b, and the oxide 530c is illustrated in the region where a channel is formed and in the vicinity thereof; however, one embodiment of the present invention is not limited thereto. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 500, the conductor 560 is illustrated as having a two-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 28, 30A, and 30B is merely an example, and the present invention is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

[0411] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0412] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. As a result, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0413] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.

[0414] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0415] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0416] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or the oxygen.

[0417] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and causing a decrease in conductivity.

[0418] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material mainly composed of tungsten, copper, or aluminum. In that case, the conductor 503a is not necessarily provided. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0419] The insulators 520, 522, and 524 function as a second gate insulating film.

[0420] Here, the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than the oxygen required for the stoichiometric composition. In other words, the insulator 524 preferably has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved. Note that in this specification and the like, oxygen vacancies in a metal oxide are referred to as V O In addition, when there are impurities or oxygen vacancies (V) in the region where the channel is formed in the metal oxide, O ), electrical characteristics are likely to fluctuate and reliability may decrease.O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H) to generate electrons that serve as carriers. This makes it easier for the transistor 500 to have normally-on characteristics.

[0421] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

[0422] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O H→V O The reaction "+H" occurs, and hydrogen is dehydrogenated. Some of the hydrogen generated at this time combines with oxygen to form H 2 As O, hydrogen may be removed from the oxide 530 or an insulator near the oxide 530. In addition, some of the hydrogen may be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0423] Moreover, the microwave treatment is preferably carried out using, for example, an apparatus having a power source for generating high-density plasma, or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator in the vicinity of the oxide 530. The microwave treatment may be carried out under a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. For example, oxygen and argon are used as gases to be introduced into the apparatus for carrying out the microwave treatment, and the oxygen flow ratio (O 2 / (O 2 +Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0424] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0425] In addition, by subjecting the oxide 530 to an oxygen supplying treatment, the oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be promoted to convert the hydrogen into H 2 O. This causes the hydrogen remaining in the oxide 530 to recombine with the oxygen vacancies and form V. O The formation of H can be suppressed.

[0426] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0427] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, so that oxygen contained in the oxide 530 does not diffuse toward the insulator 520. Furthermore, reaction of the conductor 503 with the insulator 524 or oxygen contained in the oxide 530 can be suppressed.

[0428] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or a multilayer structure. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0429] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0430] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0431] In addition, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable laminated structure with a high relative dielectric constant.

[0432] 30A and 30B, the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, a two-layer, or a four or more layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may be a stack structure made of different materials.

[0433] In the transistor 500, it is preferable to use a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the oxide 530. In particular, it is preferable that the In-M-Zn oxide applicable to the oxide 530 is CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). In addition, In-Ga oxide, In-Zn oxide, In oxide, etc. may be used as the oxide 530.

[0434] In addition, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. In order to reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0435] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which may cause oxygen vacancies in the metal oxide. In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen combine to form V O May form H. V OH may function as a donor and generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in a metal oxide is easily moved by stress such as heat or an electric field, so if a metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be obtained.

[0436] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for a metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in a metal oxide, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide, instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration".

[0437] Therefore, when a metal oxide is used for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0438] In addition, when a metal oxide is used for the oxide 530, the metal oxide is a semiconductor that has a wide band gap and is intrinsic (also called I-type) or substantially intrinsic, and the carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0439] Furthermore, when a metal oxide is used for the oxide 530, when the conductors 542a and 542b come into contact with the oxide 530, oxygen in the oxide 530 may diffuse to the conductors 542a and 542b, and the conductors 542a and 542b may be oxidized. When the conductors 542a and 542b are oxidized, the conductivity of the conductors 542a and 542b is likely to decrease. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be expressed in other words as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0440] Furthermore, oxygen in the oxide 530 may diffuse into the conductor 542a and the conductor 542b, forming a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure mainly based on the MIS structure.

[0441] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b. For example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c, between the conductor 542a and the conductor 542b and the oxide 530b, or between the conductor 542a and the conductor 542b and the oxide 530c.

[0442] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0443] The oxide 530 has the oxide 530a below the oxide 530b, so that the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed. Also, the oxide 530 has the oxide 530c on the oxide 530b, so that the diffusion of impurities from structures formed above the oxide 530c to the oxide 530b can be suppressed.

[0444] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a. In addition, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0445] Specifically, the oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. The oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga and Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and the atomic ratio of In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0446] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, In:Ga:Zn=10:1:3 or thereabouts, or the like, can be used as oxide 530b.

[0447] In addition to the compositions described above, the oxide 530b may be a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0448] It is preferable to combine these oxides 530a, 530b, and 530c while satisfying the above-mentioned atomic ratio relationship. For example, it is preferable to use metal oxides having a composition of In:Ga:Zn=1:3:4 for the oxides 530a and 530c, and metal oxides having a composition of In:Ga:Zn=4:2:3 to 4.1 for the oxides 530b. The above composition indicates the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. In addition, it is preferable to increase the ratio of In in the composition of the oxide 530b, since this can increase the on-current or field effect mobility of the transistor.

[0449] In addition, the energy of the conduction band minimum of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0450] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0451] Specifically, the oxides 530a and 530b, and the oxides 530b and 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxides 530a and 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0452] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0453] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0454] 30A and 30B, the conductor 542a and the conductor 542b are shown as a single-layer structure, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. Alternatively, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0455] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0456] 30A , regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0457] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0458] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0459] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0460] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later step. Note that the insulator 544 is not an essential component when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or when the conductivity does not decrease significantly even when oxygen is absorbed. It may be designed appropriately depending on the desired transistor characteristics.

[0461] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 580 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0462] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0463] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0464] By providing an insulator that releases oxygen when heated as the insulator 550 in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0465] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0466] The insulator 550 may have a laminated structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0467] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 30A and 30B, it may have a single-layer structure or a laminated structure of three or more layers.

[0468] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N 2 O, NO, NO 2 It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or the like. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). When the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. In addition, an oxide semiconductor that can be applied to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0469] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0470] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they allow for easy formation of an excess oxygen region in a later step.

[0471] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, which releases oxygen when heated, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0472] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0473] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0474] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0475] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0476] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0477] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0478] Furthermore, conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same structure as conductor 546 and conductor 548, which will be described later.

[0479] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0480] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0481] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0482] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0483] The conductor 546 and the conductor 548 function as a plug or a wiring connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0484] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 514 or the insulator 522 and form the insulator having a high barrier property in contact with the insulator 514 or the insulator 522, since this can serve as part of the manufacturing process of the transistor 500. As the insulator having a high barrier property against hydrogen or water, for example, a material similar to that of the insulator 522 may be used.

[0485] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0486] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0487] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0488] 28, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0489] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0490] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0491] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, a change in electrical characteristics can be suppressed and reliability can be improved, or miniaturization or high integration can be achieved in a semiconductor device including a transistor having an oxide semiconductor.

[0492] Next, another example of the structure of an OS transistor shown in FIGS. 28 and 29 will be described.

[0493] 31A and 31B are modifications of the transistor 500 shown in Figures 30A and 30B, where Figure 31A is a cross-sectional view of the transistor 500 in the channel length direction and Figure 31B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the structures shown in Figures 31A and 31B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0494] 31A and 31B differs from the transistor 500 shown in Figures 30A and 30B in that the transistor 500 includes an insulator 402 and an insulator 404. The transistor 500 also differs from the transistor 500 shown in Figures 30A and 30B in that an insulator 552 is provided in contact with a side surface of the conductor 540a and an insulator 552 is provided in contact with a side surface of the conductor 540b. The transistor 500 also differs from the transistor 500 shown in Figures 30A and 30B in that the transistor 500 does not include an insulator 520.

[0495] 31A and 31B, the insulator 402 is provided over the insulator 512. Furthermore, the insulator 404 is provided over the insulator 574 and the insulator 402.

[0496] 31A and 31B, the insulator 514, the insulator 516, the insulator 522, the insulator 524, the insulator 544, the insulator 580, and the insulator 574 are provided, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 402.

[0497] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, the insulators 402 and 404 are preferably made of silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration of the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0498] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of an insulator having a high hydrogen barrier property, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is preferably used as the insulator 552 because it has a high hydrogen barrier property. By using a material having a high hydrogen barrier property as the insulator 552, impurities such as water or hydrogen can be suppressed from diffusing from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0499] 32 is a cross-sectional view showing a configuration example of a semiconductor device in which the transistor 500 and the transistor 300 have the configurations shown in FIG 31A and FIG 31B.

[0500] The transistor 500 shown in FIG. 31A and FIG. 31B may have a different configuration depending on the situation. For example, the transistor 500 shown in FIG. 31A and FIG. 31B may be modified to the transistor shown in FIG. 33A and FIG. 33B as a modified example. FIG. 33A is a cross-sectional view of the transistor in the channel length direction, and FIG. 33B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIG. 33A and FIG. 33B is different from the transistor shown in FIG. 31A and FIG. 31B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.

[0501] The oxide 530c1 is in contact with the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0502] The oxide 530c1 may be, for example, an In-Zn oxide. The oxide 530c2 may be the same material as that used for the oxide 530c when the oxide 530c has a single-layer structure. For example, the oxide 530c2 may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0503] By forming the oxide 530c in a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be applied as, for example, a power MOS transistor. The oxide 530c of the transistor having the configuration shown in FIG. 30A and FIG. 30B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0504] 33A and 33B can be applied to, for example, the transistor 300 illustrated in Figures 28 and 29. As described above, the transistor 300 can be applied to the semiconductor device described in the above embodiment, such as the transistor included in the arithmetic device 100 or 100A described in the above embodiment. Note that the transistors illustrated in Figures 33A and 33B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one embodiment of the present invention.

[0505] 34 is a cross-sectional view illustrating a structural example of a semiconductor device in which the transistor 500 has the transistor structure illustrated in FIG. 30A and the transistor 300 has the transistor structure illustrated in FIG. 33A. Note that an insulator 552 is provided on a side surface of the conductor 546, as in the case of FIG. 32. As illustrated in FIG. 34, in the semiconductor device of one embodiment of the present invention, the transistors 300 and 500 are both OS transistors, but the transistors 300 and 500 can have different structures.

[0506] Next, a capacitive element that can be applied to the semiconductor devices of FIGS. 28, 29, 32, and 34 will be described.

[0507] Fig. 35 shows a capacitive element 600A as an example of the capacitive element 600 applicable to the semiconductor device shown in Fig. 28, Fig. 29, Fig. 32, and Fig. 34. Fig. 35A is a top view of the capacitive element 600A, Fig. 35B is a perspective view showing a cross section of the capacitive element 600A taken along dashed line L3-L4, and Fig. 35C is a perspective view showing a cross section of the capacitive element 600A taken along dashed line W3-L4.

[0508] The conductor 610 functions as one of a pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A. The insulator 630 functions as a dielectric material sandwiched between the pair of electrodes.

[0509] As the insulator 630, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, etc. can be used, and can be provided as a stacked layer or a single layer.

[0510] In this specification, hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen, and hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0511] Also, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitive element 600A can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitive element 600A can improve its dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitive element 600A.

[0512] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0513] Alternatively, the insulator 630 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3An insulator containing a high-k material such as (BST) may be used as a single layer or a stacked layer. For example, when the insulator 630 is a stacked layer, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order may be used, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed in this order may be used. The insulator 630 may also be a compound containing hafnium and zirconium. As semiconductor devices become more miniaturized and highly integrated, problems such as leakage current of transistors and capacitors may occur due to thinning of the gate insulator and the dielectric used in the capacitor. By using a high-k material as the insulator that functions as the gate insulator and the dielectric used in the capacitor, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor while maintaining the physical film thickness.

[0514] The capacitor 600 is electrically connected to the conductor 546 and the conductor 548 at the bottom of the conductor 610. The conductor 546 and the conductor 548 function as plugs or wiring for connecting to other circuit elements. In addition, in Figures 35A to 35C, the conductor 546 and the conductor 548 are collectively referred to as the conductor 540.

[0515] Also, in order to clarify the figure, FIG. 35 omits the insulator 586 in which the conductor 546 and the conductor 548 are embedded, and the insulator 650 covering the conductor 620 and the insulator 630.

[0516] 28, 29, 32, 34, 35A, 35B, and 35C are planar type capacitive elements, but the shape of the capacitive element is not limited thereto. For example, the capacitive element 600 may be a cylindrical capacitive element 600B shown in FIGS. 36A to 36C.

[0517] 36A is a top view of the capacitive element 600B, FIG. 36B is a cross-sectional view of the capacitive element 600B taken along dashed line L3-L4, and FIG. 36C is a perspective view showing the cross-section of the capacitive element 600B taken along dashed line W3-L4.

[0518] In Figure 36B, the capacitor 600B has an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0519] Also, in FIG. 36C, insulator 586, insulator 650, and insulator 651 are omitted for clarity.

[0520] The insulator 631 can be, for example, a material similar to that of the insulator 586.

[0521] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of, for example, the same material as the conductors 330 and 518.

[0522] The insulator 651 can be, for example, a material similar to that of the insulator 586.

[0523] As described above, the insulator 651 has an opening that overlaps with the conductor 611.

[0524] The conductor 610 is formed on the bottom and side surfaces of the opening. In other words, the conductor 621 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0525] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. Thereafter, the conductor 610 deposited on the insulator 651 may be removed by chemical mechanical polishing (CMP) or the like, leaving the conductor 610 deposited in the opening.

[0526] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric material sandwiched between a pair of electrodes in the capacitor.

[0527] Conductor 620 is formed on insulator 630 so that the opening of insulator 651 is filled.

[0528] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0529] The cylindrical capacitive element 600B shown in FIG. 36 can have a higher capacitance value than the planar capacitive element 600A.

[0530] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0531] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0532] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0533] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 37A. Fig. 37A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0534] As shown in FIG. 37A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0535] The structure in the bold frame shown in Fig. 37A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0536] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 37B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 37B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 37B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 37B is 500 nm.

[0537] As shown in Figure 37B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 37B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0538] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 37C. FIG. 37C is a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 37C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0539] As shown in FIG. 37C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0540] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 37A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0541] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0542] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0543] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0544] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0545] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0546] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0547] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0548] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0549] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0550] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0551] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0552] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0553] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0554] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0555] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0556] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0557] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0558] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0559] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0560] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0561] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0562] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0563] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0564] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0565] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0566] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0567] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0568] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2×10 18 atoms / cm 3 Less than or equal to 2×10 17atoms / cm 3 The following applies.

[0569] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0570] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0571] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0572] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0573] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0574] (Embodiment 5) This embodiment mode describes an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0575] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG. 38A.

[0576] 38A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0577] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0578] The next step is a dicing step. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) shown by dashed lines. In order to facilitate the dicing step, it is preferable that the spacing 4803 is arranged so that the multiple scribe lines SCL1 are parallel to each other, the multiple scribe lines SCL2 are parallel to each other, and the scribe lines SCL1 and SCL2 are perpendicular to each other.

[0579] By performing a dicing process, chips 4800a as shown in FIG. 38B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. Note that spacing 4803a is preferably as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately equal to the cutting allowance of scribe line SCL1 or the cutting allowance of scribe line SCL2.

[0580] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Fig. 38A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process of the element and the device for manufacturing the element.

[0581] <Electronic components> FIG. 38C shows a perspective view of electronic component 4700 and a substrate (mounted substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 38C has chip 4800a in mold 4711. As shown in FIG. 38C, chip 4800a may have a configuration in which circuit section 4802 is laminated. FIG. 38C omits a part of electronic component 4700 in order to show the inside of electronic component 4700. Electronic component 4700 has land 4712 on the outside of mold 4711. Land 4712 is electrically connected to electrode pad 4713, and electrode pad 4713 is electrically connected to chip 4800a by wire 4714. Electronic component 4700 is mounted on, for example, printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted substrate 4704.

[0582] 38D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has interposer 4731 provided on package substrate 4732 (printed circuit board), and semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0583] The electronic component 4730 has a semiconductor device 4710. The semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), or the like. The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0584] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0585] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 4731, and the integrated circuits and the package substrate 4732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0586] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0587] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0588] In addition, in SiPs and MCMs that use silicon interposers, reliability is less likely to decrease due to differences in the expansion coefficient between the integrated circuit and the interposer. In addition, because the surface of the silicon interposer is highly flat, connection defects are less likely to occur between the integrated circuit mounted on the silicon interposer and the silicon interposer. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0589] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 4730. When providing a heat sink, it is preferable to make the height of an integrated circuit provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in this embodiment, it is preferable to make the height of the semiconductor device 4710 and the height of the semiconductor device 4735 uniform.

[0590] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. FIG. 38D shows an example in which electrodes 4733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Electrodes 4733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0591] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. For example, a mounting method such as a Staggered Pin Grid Array (SPGA), a Land Grid Array (LGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN) can be used.

[0592] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0593] (Embodiment 6) In this embodiment, an example of an electronic device including the semiconductor device described in the above embodiment will be described. Note that Fig. 39 illustrates a state in which an electronic device includes an electronic component 4700 including the semiconductor device.

[0594] [mobile phone] 39 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0595] The information terminal 5500 can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0596] [Wearable devices] 39 also illustrates an information terminal 5900, which is an example of a wearable terminal. The informatio...

Claims

1. A calculation circuit is provided. the arithmetic circuit has a first storage unit, a first register, a second register, a third register, a fourth register, a multiplier, an adder, a selector, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal; an input terminal of the first register is electrically connected to the first terminal; an output terminal of the first register is electrically connected to an input terminal of the second register; an output terminal of the first register is electrically connected to the second terminal; an output terminal of the second register is electrically connected to a first input terminal of the multiplier; an output terminal of the first storage unit is electrically connected to a second input terminal of the multiplier; an output terminal of the multiplier is electrically connected to a first input terminal of the adder; a second input terminal of the adder electrically connected to the third terminal; an output terminal of the adder is electrically connected to an input terminal of the third register; an output terminal of the third register is electrically connected to the fourth terminal; an output terminal of the third register is electrically connected to a first input terminal of the selector; a second input terminal of the selector electrically connected to the fifth terminal; an output terminal of the selector is electrically connected to an input terminal of the fourth register; an output terminal of the fourth register is electrically connected to the sixth terminal; Semiconductor device.

2. In claim 1, a circuit; The circuit comprises: The sixth terminal has a function of calculating an activation function for the data output from the sixth terminal. Semiconductor device.

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