Semiconductor memory device

Abstract

To provide a semiconductor memory device that reduces time required to write data.SOLUTION: A semiconductor memory device is provided that includes: a memory cell having a gate electrode including a select gate and a memory gate, a source line connected to a source, and a bit line connected to a drain; an extracting part that extracts a current flowing from the source side to the drain side from the bit line when writing in the memory cell; a discharging part that has a higher current passing capacity than the extracting part and reduces a voltage of the bit line; a charging part having a higher current passing capacity than the discharging part and applies a voltage to the bit line; and a control unit that lowers a voltage of the bit line by the discharging part when starting to write to the memory cell and applies the voltage to the bit line by the charging part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] Conventionally, split-gate memory cells having a select gate transistor and a memory gate transistor are known (for example, Patent Document 1). Such memory cells have a gate electrode divided into two parts, a select gate and a memory gate, and are therefore also called SG-MONOS (Split Gate-Metal Oxide Nitride Oxide Silicon). MONOS is a structure in which three layers, an oxide film, a nitride film (trap film), and an oxide film, are formed on a silicon substrate, and a gate electrode (metal) is disposed thereon. SG-MONOS is used, for example, as a flash memory structure mounted on a microcomputer or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-288503 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, there is room for improvement in the time required for writing data. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] In one embodiment, a semiconductor memory device is provided having a memory cell having a gate electrode including a select gate and a memory gate, a source line connected to the source, and a bit line connected to the drain, an extraction section that extracts from the bit line a current flowing from the source side to the drain side when writing to the memory cell, a discharge section that has a higher current passing ability than the extraction section and reduces the voltage of the bit line, a charge section that has a higher current passing ability than the discharge section and applies a voltage to the bit line, and a control section that, when starting to write to the memory cell, causes the discharge section to reduce the voltage of the bit line and the charge section to apply a voltage to the bit line. Effect of the Invention

[0006] According to the embodiment, the time required to write data can be reduced. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to the embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of the configuration of a memory cell according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing an example of the operation during writing to the memory cell according to the embodiment. [Figure 4] FIG. 4 is a flowchart showing an example of a write operation to a memory cell in the semiconductor memory device according to the embodiment. [Diagram 5] FIG. 5 is a time series chart showing an example of the voltage on the bit line during writing according to the embodiment. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of the semiconductor memory device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present disclosure will be described with reference to some exemplary embodiments. It should be understood that these embodiments are provided for illustrative purposes only, to help those skilled in the art understand and practice the present disclosure, without implying any limitation on the scope of the disclosure. The disclosure described herein can be implemented in various ways other than those described below.

[0009] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. <Configuration> The configuration of a semiconductor memory device 10 according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a diagram showing an example of the configuration of the semiconductor memory device 10 according to this embodiment. The semiconductor memory device 10 has a memory cell 11, a control unit 12, a switch 13, a bias unit 14, a pull-out unit 15, a discharge unit 16, and a charge unit 17. Note that FIG. 1 shows each element necessary for the explanation of this disclosure, and explanations of elements that are less relevant to the explanation of this disclosure are omitted as appropriate. Therefore, for parts not shown in FIG. 1, those used in known semiconductor memory devices (semiconductor memories) can be used as necessary.

[0011] The memory cell 11 is a circuit that stores data, etc. The memory cell 11 may be a multi-level cell (MLC) that has multiple levels of stored charge and can record information exceeding one bit by taking three or more different states.

[0012] The bit line BL connects the memory cell 11 to the bias section 14, the extraction section 15, the discharge section 16, and the charge section 17. Although not shown in FIG. 1, as shown by the repetition diagram 21, the semiconductor memory device 10 may include a plurality of bit lines and memory cells, one memory cell connected to one bit line, and the memory cell to be controlled may be selected by the switch 13.

[0013] The control unit 12 controls each unit of the semiconductor memory device 10. For example, the control unit 12 instructs each unit of the semiconductor memory device 10 to perform an operation required for writing data to the memory cell 11. The control unit 12 may control the operation of each unit by controlling, for example, a voltage or a signal applied to each input unit of each unit.

[0014] The bias unit 14 is turned on at a specific point in time before the control unit 12 instructs the memory cell 11 to start writing data (phase 1), and supplies a power supply voltage V inh (e.g., 1.5 V) is applied to the bit line BL. In addition, the bias unit 14 is turned off in the stage (phase 2) after the control unit 12 instructs the start of writing data to the memory cell 11, and stops applying a voltage to the bit line BL.

[0015] The pull-out unit 15 is turned off in phase 1. The pull-out unit 15 is turned on in phase 2, and pulls out the current Ids that flows from the source S side to the drain D side during writing in the memory cell 11 from the bit line BL with a constant current (for example, 1.3 μA). Therefore, the pull-out unit 15 reduces the voltage V on the bit line BL by the constant current. bl Decreases.

[0016] The discharge unit 16 has, for example, an NMOS (n-type MOS (Metal-Oxide-Semiconductor)) transistor. When a specific signal is input and the gate is set to H (high) level, the discharge unit 16 operates in such a way that the extraction unit 15 reduces the voltage V blTherefore, the discharge unit 16 has the ability to pass a current much higher than the constant current (e.g., 1.3 μA) that is passed when drawing out the voltage V on the bit line BL while a specific signal is being input. bl is rapidly decreased.

[0017] The charge unit 17 operates as a source follower circuit (a common drain circuit) that is a voltage buffer. The charge unit 17 has the same mechanism (film thickness and implantation conditions) as the select gate CG of the memory cell 11 described later, and has an NMOS transistor (work gate (WG) poly transistor) larger in size than the select gate CG.

[0018] The WG polysilicon transistor may be produced by the same process as the select gate CG, for example, to have the same film thickness and implantation conditions as the select gate CG. The voltage at which the WG polysilicon transistor starts to pass current (gate threshold voltage) is the gate threshold voltage V of the select gate CG. tm is equivalent to.

[0019] The WG poly transistor may have a different size and current passing capability (current capacity) compared to the select gate CG. The WG poly transistor has a higher current passing capability than the discharge unit 16. Therefore, if the current capacity of the charge unit 17 is CAc, the current capacity of the discharge unit 16 is CAd, and the current capacity of the pull-out unit 15 is CAh, the following inequality (1) holds. CAc>CAd>>CAh (1)

[0020] The charge section 17 is connected to the bit line BL, and is configured by serially arranging a WG polysilicon transistor and a PMOS transistor that operates as a switch. The charge section 17 receives the voltage V cg The same voltage is applied from the power supply. Also, the gate threshold voltage of the WG poly transistor is V tm Therefore, when the charge unit 17 is turned on, V cg -Vtm A voltage of about 1 V is applied to the bit line BL.

[0021] <Regarding memory cell 11> <<Configuration of memory cell 11>> Next, the configuration of the memory cell 11 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the memory cell 11 according to the embodiment. In the example of Fig. 2, the memory cell 11 has three layers, an oxide film 202 / a nitride film (trap film) 203 / an oxide film 204, formed on a silicon substrate 201, and a memory gate MG, which is a gate electrode (metal), disposed thereon. A high-density electron trap level is formed in the nitride film 203.

[0022] This type of structure is also called MONOS (Metal Oxide Nitride Oxide Silicon). In the example of FIG. 2, the gate electrode is divided into two gates, a selection gate CG and a memory gate MG. This type of gate electrode is also called SG (Split Gate). Therefore, the memory cell 11 shown in FIG. 2 is also called SG-MONOS, and is used in embedded flash memories for microcomputers, for example.

[0023] <<Operation when writing to memory cell 11>> Next, the operation of the memory cell 11 during writing will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the operation of the memory cell 11 during writing according to the embodiment. In the example of Fig. 3, the voltage V mg A positive high voltage (for example, 10 V) is applied as a voltage V sl A positive high voltage (for example, 5V) is applied as the select gate CG voltage V cg A positive voltage (for example, 1 V) is applied as a voltage V bl A positive voltage (e.g., 0.7 V) is applied as a

[0024] Voltage V mg, and voltage V sl By applying a high voltage to the silicon substrate 201, hot electrons are injected from the silicon substrate 201 into the nitride film 203. This hot electron injection technique is also called SSI (Source Side Injection).

[0025] Here, the control unit 12 limits the current of the bit line BL to a constant current (for example, 1.3 μA) to control the voltage of the bit line BL to V cg -V tm The V tm is the voltage at which the select gate CG passes current (gate threshold voltage). Also, V cg -V tm is the voltage applied by the selection gate CG to the bit line BL. This causes a current Ids (e.g., about 1 to 4 μA) to flow from the source S side to the drain D side, and writing is performed by hot electron injection. The current Ids from the source S side to the drain D side is a constant current (e.g., 1.3 μA) that is drawn from the bit line BL by the drawing unit 15.

[0026] <<Operation when reading memory cell 11>> When reading memory cell 11, the voltage V mg and voltage V sl For example, let us set the voltage V cg and voltage V bl A positive voltage (for example, 1.5V and 1.25V, respectively) is applied to each of these.

[0027] <<Operation when erasing memory cell 11>> When erasing data from the memory cell 11, the voltage V cg and voltage V bl is set to 0V, and the voltage V mg A negative high voltage, voltage V sl A positive high voltage is applied to the insulating film 203. This effectively lowers the energy barrier of the insulating film, and holes are tunneled from the silicon substrate 201 to the nitride film 203. Then, the electrons in the trap level recombine with the holes and disappear, so the accumulated charge disappears.

[0028] <Writing Operation of Semiconductor Memory Device 10> Next, an operation of writing to the memory cell 11 of the semiconductor memory device 10 will be described with reference to Figs. 4 and 5. Fig. 4 is a flow chart showing an example of a write operation to the memory cell 11 of the semiconductor memory device 10 according to the embodiment. Fig. 5 shows the voltage V on the bit line BL during writing according to the embodiment. bl 4 is a time series chart showing an example of the process of FIG. 4. The process of FIG.

[0029] In step S1, the control unit 12 detects that writing is to be performed to the memory cell 11. Here, the control unit 12 may determine the memory cell 11 to be written to when, for example, a write instruction is received from an external microcomputer or the like.

[0030] Next, the control unit 12 causes each unit of the semiconductor memory device 10 to transition to Phase 1, which is also a preparation stage before the start of writing (step S2). Here, the control unit 12 turns on the bias unit 14 and applies the power supply voltage V inh (for example, 1.5V) is applied to the bit line BL. Also, the control unit 12 applies a voltage V bl In order to prevent the voltage V on the bit line BL in FIG. bl As shown in the transition 501, before the time point ts, the voltage V bl is the voltage V inh If each unit of the semiconductor memory device 10 is already in the state of Phase 1, the process of step S2 (processing for transitioning to Phase 1) is not necessary.

[0031] Next, the control unit 12 applies a voltage to each line other than the bit line BL of the memory cell 11 (step S3). mg A positive high voltage (e.g., 10 V) is applied as the source line SL voltage V slThe control unit 12 applies a positive high voltage (for example, 5 V) to the selection gate CG. cg A positive voltage (e.g., 1V) is applied as

[0032] Next, the control unit 12 instructs the memory cell 11 to start writing data, thereby moving to Phase 2, which is the stage after the start of writing (step S4). Here, the control unit 12 turns off the bias unit 14, and stops the application of voltage to the bit line BL. The control unit 12 also turns on the extraction unit 15, and applies a constant current (e.g., 1.3 μA) to the bit line BL to apply a voltage V bl Pull out (reduce voltage).

[0033] In addition, the control unit 12 inputs a pulse signal (one-shot signal) of a specific time length (width) to the discharge unit 16 (almost simultaneously) and turns on the charge unit 17 for a specific time length. By inputting the one-shot signal to the discharge unit 16, the voltage V bl is the power supply voltage V inh This is because the current capability CAd of the discharge unit 16 is much higher than the current capability CAh of the extraction unit 15 (CAd>>CAh).

[0034] In addition, when the charge unit 17 is turned on, V cg -V tm This creates a path through which a voltage of about V on the bit line BL is applied to the bit line BL while the charge unit 17 is turned on. bl V cg -V tm When the voltage V on the bit line BL drops to about 1 V, a current is supplied to the bit line BL from the WG poly transistor. Here, since the current capability CAc of the charge unit 17 is higher than the current capability CAd of the discharge unit 16 (CAc>CAd), the voltage V on the bit line BL bl Rapidly V cg -V tm This makes it possible to reduce undershoot.

[0035] The voltage V on the bit line BL in FIG. bl As shown in the transition 501 of the voltage V bl is the voltage V inh From V cg -V tm It then drops rapidly to about 100% and stabilizes.

[0036] Note that the voltage V on the bit line BL bl V cg -V tm When the potential difference reaches about 1, a current flows from the source S side to the drain side in the memory cell 11, and writing by hot electron injection actually starts. In the example of Fig. 5, writing by hot electron injection is performed between time t1 and time t2.

[0037] Next, the control unit 12 returns to phase 1 by instructing to end writing data to the memory cells 11 (step S5). Note that the control unit 12 may sequentially execute the processes from step S2 onward for each address of one or more memory cells to be written among the multiple memory cells of the semiconductor memory device 10.

[0038] <Other> In comparison with the configuration of the present disclosure shown in FIG. 1, a configuration without a discharge unit 16 and a charge unit 17 will be described. In this configuration, it takes about 1 μsec from the time ts when an instruction to start writing data to the memory cell 11 is given to the time t2 when the writing is completed by hot electron injection. Among these, the voltage V on the bit line BL is increased by the extraction unit 15, whose main role is to extract a constant current from the bit line BL during writing. bl supply voltage V inh From V cg -V tm It takes, for example, about 500 nanoseconds for the voltage to drop to that level.

[0039] Next, a configuration that does not have the charge unit 17 will be described as compared with the configuration of the present disclosure shown in FIG. cg -V tm Furthermore, since the one-shot signal has a PVT (Process-Voltage-Temperature) dependency, it is relatively difficult for the discharge unit 16 to set the target voltage.

[0040] On the other hand, according to the present disclosure, the discharge unit 16 and the charge unit 17 can rapidly and appropriately discharge the voltage V on the bit line BL. bl to the target voltage V cg -V tm This can increase the speed of writing data to the memory cells 11. In particular, this can achieve stable and high-speed writing in MLC, where the write time tends to become short due to successive write operations.

[0041] <Modification> In the example of Fig. 1, a configuration in which one charge unit 17 is provided for a plurality of bit lines has been described. With reference to Fig. 6, a configuration in which one charge unit 17A is provided for each bit line will be described. Fig. 6 is a block diagram showing an example of the configuration of a semiconductor memory device according to the embodiment.

[0042] 1, the WG poly transistor of the charge unit 17 must be larger in size than the select gate CG of the memory cell 11 in order to be shared by multiple memory cells. Therefore, even if the WG poly transistor of the charge unit 17 is produced by the same manufacturing method as the select gate CG, the larger size of the WG poly transistor of the charge unit 17 may result in characteristics that are slightly different from those of the select gate CG.

[0043] In the example of Fig. 6, the exact same memory cell 11 can be used as part of the charge section 17A, so that the difference in characteristics due to the difference in size can be reduced. Note that in the example of Fig. 6, compared to the example of Fig. 1, the size of the entire semiconductor memory device 10 may increase because n dummy cells are provided for each of one or more bit lines.

[0044] <<Configuration of the modified example>> In Fig. 6, the same components as those in Fig. 1 are denoted by the same reference numerals to avoid duplication of explanation. The following mainly describes the configuration and operation in Fig. 6 that differ from those in Fig. 1.

[0045] The example of Figure 6 differs from the example of Figure 1 in that, instead of charge section 17 connected to bit line BL via switch 13, it has charge section 17A connected to bit line BL without via switch 13.

[0046] The charge unit 17A has a mechanism similar to that of the memory cell 11, and has n (plural) dummy cells that are not used for recording data. Here, since the charge unit 17A has n dummy cells, the current capability CAc' of the charge unit 17A is higher than the current capability CAd of the discharge unit 16 (CAc'>CAd). Therefore, the following inequality (2), which is the same as the example in FIG. 1, holds true. CAc'>CAd>>CAh (2)

[0047] The current capability CAh of the extraction unit 15 is equal to the current Ids (for example, 1.3 μA) that flows from the source S side to the drain D side during writing to the memory cell 11, so CAc′=CAh×n.

[0048] <<Operation of the modified example>> The operation of the modified example differs from the operation of the example in Fig. 1 in the process of transitioning to Phase 2 in step S4 in Fig. 4. In the modified example, in step S4 in Fig. 4, control unit 12 inputs a pulse signal (one-shot signal) of a specific time length (width) to discharge unit 16 (almost simultaneously) and turns on charge unit 17A for a specific time length.

[0049] When the charge unit 17A is turned on, V cg -V tm This creates a path through which a voltage of about V on the bit line BL is applied to the bit line BL while the charge section 17A is turned on. bl V cg -V tm When the potential drops to about 10V, a current is supplied to the bit line BL from the n dummy cells.

[0050] As in the example of FIG. 1, the current capability CAc′ of the charge unit 17A is higher than the current capability CAd of the discharge unit 16 (CAc′>CAd), so that the voltage V bl Rapidly V cg -V tm This makes it possible to reduce undershoot.

[0051] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0052] 10. Semiconductor memory device 11 Memory Cell 201 Silicon Substrate 202 Oxide film 203 Nitride film 204 Oxide film BL Bit Line CG Selection Gate MG Memory Gate SL Source Line 12 Control section 13. Switch 14 Bias section 15 Pull-out section 16 Discharge section 17 Charging section

Claims

1. A memory cell having a gate electrode including a select gate and a memory gate, a source line connected to a source, and a bit line connected to a drain; a pull-out section that pulls out, from the bit line, a current that flows from a source side to a drain side when writing to the memory cell; a discharge section having a higher current passing capability than the extraction section and lowering the voltage of the bit line; a charge section having a higher current passing capability than the discharge section and applying a voltage to the bit line; a control unit that, when starting writing to the memory cell, causes the discharge unit to reduce the voltage of the bit line and causes the charge unit to apply a voltage to the bit line; A semiconductor memory device having:

2. The control unit is A power supply voltage is applied to the bit line before starting writing to the memory cell; when starting to write to the memory cell, stopping the application of the power supply voltage to the bit line, and setting the voltage of the bit line by the discharge unit and the charge unit to a value corresponding to a value obtained by subtracting a gate threshold voltage of the select gate from the voltage applied to the select gate; 2. The semiconductor memory device according to claim 1.

3. The charge unit has the same gate threshold voltage as the select gate, and applies the same voltage to the bit line as the voltage applied to the bit line by the select gate.

2. The semiconductor memory device according to claim 1.

4. The charge unit has a mechanism similar to that of the select gate and an NMOS transistor larger in size than the select gate.

4. The semiconductor memory device according to claim 3.

5. the charge unit has a mechanism similar to that of the memory cells and includes a plurality of dummy cells that are not used for recording data; 4. The semiconductor memory device according to claim 3.

6. The memory cell is a multi-level cell (MLC) that has multiple levels of charge stored therein and can store more than one bit of information by taking three or more different states.

2. The semiconductor memory device according to claim 1.

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