Memory access control program, memory access control method and information processing device

Abstract

To improve performance of access from a plurality of processors to a common memory.SOLUTION: When one of a plurality of processors controls access from each of the plurality of processors to a common memory including a storage area shared among the plurality of processors, the number of first processors controllable by hardware when the hardware controls the access is determined, and control of the access from second processors of the remaining number exceeding the determined number of processors among the plurality of processors to the common memory is executed under first control performed by software to be executed by the second processors or second control to be executed by the first processors with commands to be issued by the second processors, based upon the frequency of the access from the plurality of processors to the common memory.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a memory access control program, a memory access control method, and an information processing device. [Background technology]

[0002] 2. Description of the Related Art Systems that include a plurality of processors and a shared memory that includes a storage area shared among the plurality of processors are known.

[0003] A processor, for example a CPU (Central Processing Unit), has a cache, so when the processor accesses a shared memory, access control is performed to prevent data inconsistency between the processor's cache and the shared memory. Such control includes consistency control (coherency control) to maintain the consistency of the shared memory.

[0004] For example, assume that processor #0 reads the value "0" from memory address #0 in the shared memory and stores it in the cache of processor #0, and then processor #1 rewrites the value of memory address #0 to "1." In this case, in consistency control, the value "0" of memory address #0 stored in the cache of processor #0 is invalidated.

[0005] Such processing is performed, for example, by hardware that handles protocols for controlling consistency. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2020 / 0349075 Summary of the Invention [Problem to be solved by the invention]

[0007] When consistency control is performed by hardware, the number of processors that can control consistency may be limited depending on the performance of the hardware.

[0008] On the other hand, in order to avoid such restrictions and connect all processors to the shared memory, it is possible to use software to control the consistency of accesses from all processors to the shared memory. However, software-based consistency control involves checking sequential and interrelated cache states by software, which means that the processing costs, for example the delay time (latency) due to consistency control, are large compared to hardware-based consistency control. This increases the delay time, and there is a possibility that the performance of accesses to the shared memory from multiple processors will be significantly reduced.

[0009] In one aspect, an object of the present invention is to improve the performance of access to a shared memory from a plurality of processors. [Means for solving the problem]

[0010] In one aspect, the memory access control program may cause any one of the multiple processors to execute the following process when controlling access from each of the multiple processors to a shared memory including a storage area shared among the multiple processors. The process may determine the number of first processors that can be controlled by the hardware when the access is controlled by hardware. The process may also be performed by a first control performed by software executed by the second processor based on the frequency of access to the shared memory from the multiple processors, the remaining number of second processors exceeding the determined number of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. Effect of the Invention

[0011] In one aspect, the present invention can improve the performance of access to a shared memory from multiple processors. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram showing an example of the configuration of a system according to an embodiment; [Diagram 2] 2 is a diagram illustrating an example of a state of consistency control of each of the multiple processors illustrated in FIG. 1. [Diagram 3] FIG. 2 is a block diagram showing an example of a hardware configuration of a node according to an embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of a software configuration of a node according to an embodiment. [Diagram 5] FIG. 11 illustrates an example of processor management information. [Figure 6] FIG. 4 is a diagram illustrating an example of application management information. [Figure 7] FIG. 11 is a diagram illustrating an example of first latency estimation information. [Figure 8] FIG. 11 is a diagram illustrating an example of second latency estimation information. [Figure 9] 11 is a flowchart illustrating an example of an operation of the first latency monitoring. [Figure 10] 13 is a flowchart illustrating an example of an operation of second latency monitoring. [Figure 11] 11 is a flowchart illustrating an example of an operation of a control method determination process. [Figure 12] 11 is a flowchart illustrating an example of an operation of a process performed when the number of applications changes; [Figure 13] 13 is a flowchart illustrating an example of the operation of an allocation number adjustment process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not specified below. For example, this embodiment can be modified in various ways without departing from the spirit of the invention. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0014] [A] Description of a system according to one embodiment 1 is a block diagram showing an example of the configuration of a system 1 according to an embodiment. The system 1 illustratively includes a plurality of (e.g., m nodes: m is an integer equal to or greater than 2) nodes 2, one or more (one in the example of FIG. 1) switches 3, and one or more (one in the example of FIG. 1) shared memories 4.

[0015] The nodes 2 (represented as nodes #0 to #2 in FIG. 1; hereinafter, may be represented as nodes #0 to #m-1) may be, for example, a server, and is an example of a computer or information processing device. The node 2 may include, for example, a plurality of (two in the example of FIG. 1) processors 2a, one or more (one in the example of FIG. 1) memories 2b, and a plurality of (two in the example of FIG. 1) caches 20.

[0016] The processor 2a is an example of a processing unit that performs various controls and calculations. The processor 2a is connected to the memory 2b.

[0017] The memory 2b is an example of a main memory (primary storage device) that stores various types of data, programs, and other information. The memory 2b on the node 2 may be considered as a “local memory” for the processor 2a mounted on the node 2.

[0018] The cache 20 is an example of a cache memory having a storage area for storing part of data (cache data) used in the execution of a program by the processor 2a. Examples of the cache 20 include volatile memories such as SRAM (Static Random Access Memory) having a higher access speed than the memory 2b and the shared memory 4, and an example of an Ln (n is an integer equal to or greater than 1, for example, 1≦n≦3) cache of a CPU. In other words, the cache 20 may be implemented in the processor 2a.

[0019] Hereinafter, the processor 2a and the cache 20 may be referred to as processor #0 or #1, and cache #0 or #1, respectively.

[0020] A plurality of nodes 2 may be connected to each other by a high-speed interconnect 1a so that they can communicate with each other. The interconnect 1a may include, for example, a switch conforming to the communication standard of the transmission line in addition to a high-speed transmission line. The transmission line may include, for example, a transmission line conforming to a communication standard such as InfiniBand, Myrinet, Ethernet (registered trademark), or optical communication (e.g., FC (Fibre Channel)).

[0021] Each of the multiple nodes 2 and the switch 3 may be connected to each other via a high-speed interconnect 1b so that they can communicate with each other. The interconnect 1b may include a transmission path (fabric) that complies with communication standards such as CXL (Compute Express Link) and PCIe (Peripheral Component Interconnect Express). CXL is a communication standard based on PCIe.

[0022] The switch 3 relays communication (access) from each of the multiple nodes 2 to the shared memory 4. For example, if the system 1 includes multiple shared memories 4, the switch 3 may transmit a packet to the shared memory 4 that is the access destination from the node 2. The switch 3 is a switch that complies with the communication standard of the transmission path, and may be a CXL switch, for example, if the shared memory 4 is a CXL shared memory.

[0023] The shared memory 4 is an example of a memory that stores information such as various data and programs used by multiple nodes 2. A non-limiting example of the shared memory 4 is a CXL shared memory that complies with CXL (e.g., CXL 3.0) and subsequent standards.

[0024] The shared memory 4 may illustratively include a control circuit 4a, which is an example of hardware that performs consistency control, and one or more memories 4b that realize the storage area of ​​the shared memory 4. The memory 4b may be, for example, a memory module equipped with a volatile memory chip such as a DRAM (Dynamic Random Access Memory), or a memory module equipped with a non-volatile memory chip such as a PM (Persistent Memory).

[0025] The control circuit 4a is an example of hardware that performs consistency control. In one embodiment, the control circuit 4a has a limit on the number of processors 2a that can perform consistency control, in other words, the control circuit 4a performs consistency control on a predetermined number k or less of the multiple processors 2a. The predetermined number k is an upper limit on the number of processors that can control access by hardware. The access control may include, for example, data consistency control by access to the shared memory 4. For example, if the number of processors 2a in the system 1 is 2m, the predetermined number k is an integer less than 2m.

[0026] In the following description, the processor 2a under the control of the consistency control by the control circuit 4a may be referred to as the processor 2a "under hardware control" or "subject to hardware control". On the other hand, the processor 2a not under the control of the consistency control by the control circuit 4a (not subject to hardware control) may be referred to as the processor 2a "under software control" or "subject to software control".

[0027] Fig. 2 is a diagram showing an example of the state of consistency control of each of the multiple processors 2a shown in Fig. 1. The example shown in Fig. 2 shows a case where the processor #0 of the node #0 is under hard control (denoted as "hard control"), and the processor #1 of the node #0 and the processors #0 and #1 of the nodes #1 and #2 are under soft control (denoted as "soft control").

[0028] Here, at least one of the processors 2a may execute a control program (memory access control program) according to one embodiment. In Fig. 2, an example is shown in which the processor #0 of the node #0 under hardware control executes the control program, but the present invention is not limited to this example, and the control program may be executed by the processor 2a under software control (the processor #1 of the node #0 in the example of Fig. 2).

[0029] The processor 2a that executes the control program may execute an application 11 (see FIG. 4) that is a task executed by the system 1 (node ​​2), like the other processors 2a in the system 1.

[0030] The control program controls the consistency control of the access of each of the multiple processors 2a to the shared memory 4 between hardware control and software control based on the frequency of access from each of the multiple processors 2a to the shared memory 4, and also controls switching of the software control method.

[0031] For example, the control program determines the number of first processors 2a that can be controlled by the hardware when the access is controlled by the hardware. The method of determining the number of processors to be controlled by the hardware will be described later.

[0032] Then, the control program designates the remaining second processors 2a among the multiple processors 2a, which exceed the determined number of processors, as targets of software control, and causes the second processors 2a subject to software control to execute either the first control or the second control.

[0033] (An example of the first control) The first control is a method of controlling consistency by software executed by the processor 2a that is the subject of software control. As an example of the first control, the following first method is given, which performs consistency control by software using the management information 41 stored in the shared memory 4.

[0034] For example, in the first method, multiple processors 2a that are software controlled use a part of a memory area 40 (memory area #0) of a memory 4b of a shared memory 4 for consistency control between a memory area 42 (memory area #1) of the shared memory 4 and the cache 20. The memory area 42 is a memory area that is accessed by the processors 2a in conjunction with the execution of an application 11.

[0035] 2, each processor 2a that is a software control target stores various information used for consistency control, such as information about the cache state, in management information 41 stored in a storage area 40 via the interconnect 1b. Information about the cache state includes, for example, an area in the storage area 42 that is held in its own cache 20 as read cache data, and the presence or absence of write cache data in its own cache 20.

[0036] In addition, in the first method, at least one of the processors 2a under hardware control (hereinafter, for convenience, may be referred to as the "representative processor") 2a includes control according to the management information 41 in its consistency control.

[0037] For example, as shown by symbol C in Fig. 2, when the representative processor 2a accesses the storage area 42 under hardware control, the representative processor 2a refers to the management information 41 via the interconnect 1b and determines whether or not there is an access contention in the storage area 42 accessed by the representative processor 2a. Determining whether or not there is an access contention may include, for example, determining whether or not an area in the storage area 42 that the representative processor 2a is attempting to access matches an area recorded in the management information 41 by the processor 2a that is subject to software control (such as an area updated on the cache 20).

[0038] If the determination result is that there is no access contention, in other words, if there is no change in the data in the accessed memory area 42, the representative processor 2a performs (normal) access to the memory area 42 under hardware control. For example, if the accessed data in the memory area 42 exists in the cache 20 of the representative processor 2a, the representative processor 2a need only access (for example, reference) the cache 20.

[0039] On the other hand, if the determination indicates that there is an access conflict, in other words, if there is a change in the data in the accessed memory area 42, the representative processor 2a performs consistency maintenance processing for the memory areas 40 and 42, and then accesses the memory area 42 under hardware control.

[0040] The consistency maintenance process is, for example, a process of reflecting unreflected update contents in the storage area 42 by a plurality of processors 2a under software control in the storage area 42. The consistency maintenance process is not limited to this, and various processes may be executed.

[0041] In the above-described first technique, in order to prevent inconsistencies in the management information 41 from occurring among the multiple processors 2a, all the processors 2a may refrain from storing the management information 41 in their own caches 20 when accessing the storage area 40. For example, each processor 2a may flush its own cache 20 when accessing the management information 41, or may access the management information 41 directly without going through the cache 20.

[0042] As described above, the first method checks the sequential and interrelated cache states by software, and therefore, compared to hardware-based consistency control, the processing cost, for example, the delay time (latency) due to consistency control, is large. This increases the delay time, and there is a possibility that the performance of access from the multiple processors 2a to the shared memory 4 will be significantly degraded.

[0043] For example, the higher the frequency of access (read and write) to the shared memory 4 by the software-controlled processor 2a, the greater the impact on (deterioration of) the performance of the hardware-controlled processor 2a. This is because data (control information) stored in the cache 20 of the software-controlled processor 2a is invalidated, and the hardware-controlled processor 2a accesses the shared memory 4.

[0044] However, in the first technique, when the processor 2a under software control accesses the shared memory 4 infrequently, the latency of access from the processor 2a to the shared memory 4 can be suppressed to, for example, 200 ns (nanoseconds) or less.

[0045] The above-described first method is merely one example of the first control. The first control is not limited to the above-described first method, and various types of processing by software may be adopted.

[0046] (An example of the second control) The second control is a method of making the first processor 2a, which is a hard-control target, execute consistency control by a command issued by the second processor 2a, which is a soft-control target. As an example of the second control, the following second method can be given, in which the second processor 2a, which is a soft-control target, instructs the first processor 2a, which is a hard-control target, to access the storage area 42 of the shared memory 4.

[0047] For example, in the second method, as shown by symbol B in Figure 2, multiple processors 2a that are subject to software control may issue a command to access memory area 42 (memory area #1) of the shared memory 4 to a first processor 2a that is subject to hardware control.

[0048] The command communication method in the second method may be provided by, for example, an IF similar to an RPC (Remote Procedure Call). The first processor 2a that receives the command may access the shared memory 4 as a local function if the command can be executed locally, or as a remote function if not. In one embodiment, the above-mentioned RPC is used as the command communication method, but this is not limiting, and various methods may be used to call and execute a program on the processor 2a connected via the interconnect 1a.

[0049] In the second method, the first processor 2a that is requested to access (operate data) the storage area 42 by RPC accesses the storage area 42 to which the access is requested via the interconnect 1b in accordance with the command, as illustrated by reference character D in Fig. 2. By the first processor 2a executing the command, the control of the access (consistency control) instructed by the executed command can be executed by hardware (the control circuit 4a).

[0050] In the second method described above, even if the processor 2a under software control frequently accesses (reads and writes) the shared memory 4, the performance degradation of the access from the processor 2a to the shared memory 4 is small. On the other hand, the access from the processor 2a under software control to the shared memory 4 is RPC processing via communication in the interconnect 1a, so the latency is large, for example, about 1.5 μs (microseconds) or more.

[0051] As described above, in the first technique, if the frequency of access from the software-controlled processor 2a to the shared memory 4 is low, degradation in performance of access from the processor 2a to the shared memory 4 during execution of the application 11 can be suppressed.

[0052] On the other hand, in the second method, although the latency due to RPC processing is large, the fluctuation in latency is small even when the software-controlled processor 2a accesses the shared memory 4 frequently, so that degradation of access performance can be suppressed.

[0053] A control program according to an embodiment causes the processor 2a subject to software control to execute consistency control by first control or second control based on the frequency of access from the multiple processors 2a to the shared memory 4, using a method described below. This allows the access control of the processor 2a subject to software control to be appropriate control (first control or second control) according to the frequency of access, for example, and improves the performance of access from the multiple processors to the shared memory. In addition, it is possible to maintain consistency related to access from the multiple processors 2a to the shared memory 4. Therefore, it is possible to provide an access method that achieves both maintaining consistency and improving the performance of the system 1.

[0054] [B] Example of node hardware configuration Fig. 3 is a block diagram showing an example of a hardware configuration of a node 2 according to an embodiment. As shown in Fig. 3, the node 2 may exemplarily include, as a HW configuration, a graphics processing device 2c, a storage device 2d, a communication IF (Interface) 2e, an IO device 2f, a reading device 2g, and a device IF 2h in addition to the processor 2a and memory 2b shown in Fig. 1. These devices 2a to 2h may be connected to each other so as to be able to communicate with each other via various buses 2k.

[0055] Examples of the processor 2a include integrated circuits (ICs) such as a CPU, MPU, APU, DSP, ASIC, and FPGA. MPU is an abbreviation for Micro Processing Unit. APU is an abbreviation for Accelerated Processing Unit. DSP is an abbreviation for Digital Signal Processor. ASIC is an abbreviation for Application Specific Integrated Circuit, and FPGA is an abbreviation for Field Programmable Gate Array.

[0056] The processor 2a may be a combination of two or more of these integrated circuits. The processor 2a may be a multiprocessor including a plurality of processors, a multicore processor having a plurality of processor cores, or a configuration having a plurality of multicore processors. In one embodiment, as illustrated in FIG. 1 and FIG. 2, each node 2 is provided with two processors 2a. Each processor 2a is provided with a cache 20.

[0057] The memory 2b may be, for example, a volatile memory such as a DRAM, a non-volatile memory such as a PM, or both. The memory 2b may be, for example, a memory module equipped with a DRAM chip, or a non-volatile memory module such as a PM.

[0058] The graphics processing device 2c controls screen display for an output device such as a monitor of the IO device 2f. The graphics processing device 2c may also have a configuration as an accelerator that executes machine learning processing and inference processing using a machine learning model. Examples of the graphics processing device 2c include various arithmetic processing devices, such as integrated circuits (ICs) such as GPUs (Graphics Processing Units), APUs, DSPs, ASICs, and FPGAs.

[0059] The storage device 2d is an example of hardware that stores various data, programs, and other information. Examples of the storage device 2d include various storage devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as an SSD, and a non-volatile memory. Examples of the non-volatile memory include a flash memory, a storage class memory (SCM), and a read only memory (ROM).

[0060] The storage device 2d may store a program 2i (control program, memory access control program) that realizes all or part of the various functions of the node 2.

[0061] For example, the processor 2a of the node 2 can implement the function of the node 2 (for example, the control unit 14 shown in FIG. 4) described later by loading a program 2i stored in the storage device 2d into the memory 2b and executing it.

[0062] The communication IF2e controls connections and communications between the nodes 2, between the node 2 and a host device (not shown) that issues various instructions to the node 2, etc. For example, the communication IF2e may include an adapter that complies with the communication standard of the interconnect 1a shown in Fig. 1. The communication IF2e may be connected to other nodes 2 via the interconnect 1a.

[0063] The program 2i may be downloaded to the node 2 from a network (not shown) via the communication IF 2e and stored in the storage device 2d.

[0064] The IO device 2f may include one or both of an input device and an output device. Examples of the input device include a keyboard, a mouse, a touch panel, and the like. Examples of the output device include a display device such as a monitor, a projector, and a printer, and the like. The IO device 2f may also include a touch panel in which the input device and the output device are integrated. The output device may be connected to the graphics processing device 2c.

[0065] The reading device 2g is an example of a reader that reads out data or program information recorded on the recording medium 2j. The reading device 2g may include a connection terminal or device to which the recording medium 2j can be connected or inserted. Examples of the reading device 2g include an adapter that complies with USB (Universal Serial Bus) or the like, a drive device that accesses a recording disk, and a card reader that accesses a flash memory such as an SD card. The recording medium 2j may store the program 2i, and the reading device 2g may read the program 2i from the recording medium 2j and store it in the storage device 2d.

[0066] Examples of the recording medium 2j include non-transitory computer-readable recording media such as magnetic / optical disks and flash memories. Examples of the magnetic / optical disks include flexible disks, CDs (Compact Discs), DVDs (Digital Versatile Discs), Blu-ray Discs, and HVDs (Holographic Versatile Discs). Examples of the flash memory include semiconductor memories such as USB memories and SD cards.

[0067] The device IF2h controls connections and communications between the node 2 and the switch 3, between the nodes 2, etc. For example, the device IF2h may include an adapter that complies with the communication standard of the interconnect 1b shown in Fig. 1. The device IF2h may be connected to the switch 3 (and one or more shared memories 4) via the interconnect 1b.

[0068] The above-mentioned hardware configuration of the node 2 is an example. Therefore, the hardware in the node 2 may be increased or decreased (for example, adding or deleting any block), divided, integrated in any combination, or added or deleted buses, etc. may be appropriately performed. For example, the node 2 may omit the IO device 2f and the reader 2g, etc.

[0069] [C] Software configuration example Fig. 4 is a block diagram showing an example of a software configuration of the node 2 according to an embodiment. As shown in Fig. 4, the node 2 may include a processing unit 10 as a software configuration. The processing unit 10 may be realized by a processor 2a (for example, the processor 2a shown in Fig. 1).

[0070] In the following description, among the symbols of each software configuration including the processing unit 10, the symbol A is added to the software configuration specific to the node 2 that executes the control program. For example, the processing unit 10 of the node 2 that executes the control program is represented as processing unit 10A. In the following description, software configurations that do not have the symbol A added are software configurations that exist in common to both the node 2 that executes the control program and the node 2 that does not execute the control program.

[0071] [C-1] Example of common software configuration for processing section First, a description will be given of an example of a common software configuration of the processing unit 10. As illustrated in Fig. 4, the processing unit 10 may include an application 11, a library 12, and a memory unit 13. The application 11 and the library 12 are examples of a control unit 14.

[0072] The application 11 is software executed on an OS (Operating System) of the node 2, and is an example of a program. The application 11 may be executed by one or more processors 2a. In one embodiment, for simplicity, it is assumed that the application 11 is executed by multiple processors 2a, and each processor 2a executes one application 11.

[0073] The memory unit 13 is an example of a storage area, and stores various data used by the node 2. The memory unit 13 may be realized, for example, by a storage area of ​​at least one of the cache 20 shown in Fig. 1, the memory 2b and the memory 4b shown in Fig. 1 and Fig. 3, and the storage unit 2d shown in Fig. 3. The memory unit 13 may be realized by a storage area of ​​the memory 2b of another node 2.

[0074] 4, the memory unit 13 may be capable of storing, for example, processor management information 13a and application management information 13b. In the following description, the information 13a and 13b are expressed in a table format, but the information 13a and 13b are not limited to this, and may be data in various formats such as a DB (database) format and an array format.

[0075] Fig. 5 is a diagram showing an example of the processor management information 13a. The processor management information 13a is information for managing each of the multiple processors 2a included in the system 1. As shown in Fig. 5, the processor management information 13a may include items such as a processor number, a node number, an application ID (Identifier), a control flag, an RPC-used memory area address and size, and a host IP (Internet Protocol) address.

[0076] The processor number is an example of identification information of the processor 2a included in the system 1. The node number is an example of identification information of the node 2 included in the system 1.

[0077] The app ID is an example of identification information of the application 11 executed by the processor 2a. The processor 2a that executes the application 11 may be determined or identified when the application 11 is executed in the system 1. For example, when the processor 2a that executes the application 11 is identified, the library 12 or 12A (see FIG. 4) may set the identification information of the application 11 as the app ID of the processor 2a.

[0078] The control flag is a flag indicating whether the consistency control of the processor 2a is hard control or soft control. For example, the control flag "0" indicates soft control, and "1" indicates hard control.

[0079] The RPC memory area address and size are the address and size of the memory 2b to which the RPC command is written when an RPC is performed for the processor 2a. The host IP address is an example of the address of the processor 2a.

[0080] For example, when processor #1 of node #1 issues an RPC command to processor #0 of node #0, processor #1 need only write a command of 1024 bytes or less to address "0x1000" in memory 2b of host IP address "192.168.0.1".

[0081] Fig. 6 is a diagram showing an example of the application management information 13b. The application management information 13b is information for managing each of the multiple applications 11 executed by the processor 2a. As shown in Fig. 6, the application management information 13b may include items such as an application ID, a shared memory address, and a size.

[0082] The application ID is an example of identification information of the application 11. The shared memory address and size are the address and size of the storage area 42 of the shared memory 4 allocated to the application 11.

[0083] The processor management information 13a and the application management information 13b may be created and updated by a library 12A of the processing unit 10A, which will be described later.

[0084] The library 12 is user-level software located in a layer between the OS and the application 11. The library 12 may include a shared memory access unit 121.

[0085] The shared memory access unit 121 accesses the shared memory 4 in association with the execution of the application 11. The address and size of the shared memory 4 (storage area 42) to be accessed for each application 11 can be acquired from the application management information 13b.

[0086] For example, when an access to the shared memory 4 occurs from the application 11, the shared memory access unit 121 refers to the processor management information 13a and identifies whether its own processor 2a is under hardware control or software control.

[0087] (When your own processor 2a is under hardware control) When its own processor 2a is under hard control, the shared memory access unit 121 accesses the shared memory 4 via the interconnect 1b. The access is subjected to consistency control by the control circuit 4a of the shared memory 4. At this time, when the processor 2a under software control is under first control, the shared memory access unit 121 may perform the following process. Also, when the processor 2a under software control is under second control, the shared memory access unit 121 may perform the following process.

[0088] Whether the processor 2a subject to software control is under the first control or the second control may be notified to each processor 2a by the processing unit 10A when the software control method is determined or changed, for example.

[0089] When the processor 2a that is the subject of software control is under the first control. When the processor 2a subject to software control is under the first control, the shared memory access unit 121 judges whether its own processor 2a is the representative processor 2a that performs control according to the management information 41. The representative processor 2a may be designated by the processing unit 10A, for example, or may be the processor 2a with the smallest node number and processor number (processor #0 of node #0 in the example of FIG. 5) among a plurality of entries whose control flags are "1" in the processor management information 13a.

[0090] When the shared memory access unit 121 is the representative processor 2a, it performs processing as the representative processor 2a in the first control described above. For example, when there is a change in the data in the accessed memory area 42, the shared memory access unit 121 performs consistency maintenance processing on the memory areas 40 and 42 before accessing the memory area 42.

[0091] On the other hand, if the processor itself is not the representative processor 2a, the shared memory access unit 121 accesses the shared memory 4 via the interconnect 1b, in the same manner as in the case of normal hardware control.

[0092] When the processor 2a that is the subject of software control is under the second control. When the processor 2a that is the subject of software control is under the second control, the shared memory access unit 121 accesses the shared memory 4 via the interconnect 1b in the same manner as in the case of normal hardware control.

[0093] The processor 2a under the hardware control may receive an RPC command from the processor 2a under the second control. In this case, the shared memory access unit 121 executes access to the shared memory 4 requested by the processor 2a under the second control in response to the command written in the RPC use memory area address of the processor management information 13a.

[0094] (When own processor 2a is under software control) When its own processor 2a is under software control, the shared memory access unit 121 may perform the following processing depending on whether the software control is the first control or the second control.

[0095] When soft control is the primary control. When the software control is the first control, the shared memory access unit 121 performs processing as the processor 2a subject to the software control in the first control described above. For example, the shared memory access unit 121 records (sets) information regarding the cache of data stored in the memory area 42 in the management information 41 of the memory area 40.

[0096] When soft control is the second control. When the software control is the second control, the shared memory access unit 121 performs processing as the processor 2a that is the subject of software control in the above-mentioned second control. For example, the shared memory access unit 121 generates an RPC command that instructs access to the storage area 42 of the shared memory 4, and stores (transmits) the command in the RPC use memory area of ​​the processor 2a under hardware control. The processor 2a under hardware control to which the RPC command is sent may be, for example, any processor 2a whose control flag is "1" in the processor management information 13a, or may be the representative processor 2a.

[0097] [C-2] Software configuration example of the processing unit that executes the control program Next, an example of the software configuration of the processing unit 10A will be described. The processing unit 10A may include an application 11, a library 12A, and a memory unit 13A, as illustrated in Fig. 4. The application 11 and the library 12A are examples of a control unit 14A (14).

[0098] The memory unit 13A may be capable of storing, for example, first latency estimation information 13c and second latency estimation information 13d in addition to the information 13a and 13b stored in the memory unit 13. In the following description, the information 13c and 13d are expressed in a table format, but are not limited to this, and the information 13c and 13d may be data in various formats such as DB format and array format.

[0099] The library 12A may include, in addition to the shared memory access unit 121 included in the library 12, a latency monitor 122, a control method determination unit 123, and an allocation number adjustment unit 124, for example.

[0100] During the first control, the latency monitor 122 monitors (first monitoring) the latency of access to the shared memory 4 by each processor 2a, and updates the first latency estimation information 13c. During the second control, the latency monitor 122 monitors (second monitoring) the latency of access to the shared memory 4 by each processor 2a, and updates the second latency estimation information 13d. Note that various methods may be used as a method for monitoring the access latency.

[0101] The latency monitor 122 monitors, for example, the average latency of accesses during a predetermined period (for example, one minute) in all processors 2a that are subject to hardware control and software control (first control) to the storage area 42 of the shared memory 4. The latency monitor 122 sets the monitoring result in the first latency estimation information 13c.

[0102] 7 is a diagram showing an example of the first latency estimation information 13c. As shown in FIG. 7, the first latency estimation information 13c may include items such as the number of processors under hardware control, the number of processors under the first control (under software control), the number of requests per second under hardware control, the number of requests per second under the first control (under software control), and the average latency (ns).

[0103] The number of processors under hardware control and the number of processors under first control are the numbers of processors 2a that are subject to hardware control and the first control when the first monitoring is executed, and can be acquired from, for example, the processor management information 13a.

[0104] The number of requests per second under hardware control is the (average) number of requests per second issued from all processors 2a subject to hardware control to the storage area 42 of the shared memory 4. The number of requests per second under first control is the (average) number of requests per second issued from the processor 2a subject to first control to the storage area 42 of the shared memory 4.

[0105] The average latency is, for example, the average value over a specified period of time of the delay time (latency) between issuing an access request to the shared memory 4 and receiving a response indicating access completion for the processors 2a of both the hardware control target and the first control target.

[0106] For example, the latency monitor 122 sets the calculated average latency in the first latency estimation information 13c together with the number of processors under hardware control and first control at that time, and the acquired (calculated) number of requests per second under hardware control and first control.

[0107] In addition, in the second monitoring, the latency monitor 122 monitors the average latency of accesses in a predetermined period (e.g., one minute) in all of the processors 2a that are subject to hardware control and software control (second control) to the storage area 42 of the shared memory 4. The latency monitor 122 sets the monitoring result in the second latency estimation information 13d.

[0108] Fig. 8 is a diagram showing an example of the second latency estimation information 13d. As shown in Fig. 8, the second latency estimation information 13d may include items such as the number of processors under hardware control, the number of processors under the second control (under software control: using RPC), the number of requests per second under hardware control, the number of requests per second under the second control (under software control: using RPC), and the average latency (ns).

[0109] The number of processors under hardware control and the number of processors under second control are the numbers of processors 2a that are subject to hardware control and second control when the second monitoring is executed, and can be acquired from, for example, the processor management information 13a.

[0110] The number of requests per second under hardware control is the (average) number of requests per second issued from all processors 2a subject to hardware control to the storage area 42 of the shared memory 4. The number of requests per second under second control is the (average) number of requests per second issued from the processor 2a subject to second control to the storage area 42 of the shared memory 4, for example the (average) number of RPC commands issued.

[0111] The average latency is, for example, the average value over a specified period of time of the delay time (latency) between issuing an access request (or RPC command) to the shared memory 4 and receiving a response indicating that the access is completed, for both the processors 2a of the hardware control target and the second control target.

[0112] For example, the latency monitor 122 sets the calculated average latency in the second latency estimation information 13d together with the number of processors under hardware control and second control at that time, and the acquired (calculated) number of requests per second under hardware control and second control.

[0113] The latency monitor 122 may perform initial monitoring in an initial state such as when the system 1 is started. In the initial monitoring, the latency monitor 122 may calculate average latencies under various conditions while changing the conditions for each of the first control and the second control, and set the average latencies in the first latency estimation information 13c and the second latency estimation information 13d. The conditions are combinations of the values ​​of the number of processors under hardware control, the number of processors under software control, the number of requests per second under hardware control, and the number of requests per second under software control.

[0114] The control method determination unit 123 determines the control method (first control or second control) of the consistency control of the processor 2a that is the software control target, based on the first latency estimation information 13c and the second latency estimation information 13d.

[0115] For example, at a predetermined timing, the control method determination unit 123 compares the monitoring result of the average latency in the currently active control method with an estimated value of the average latency under the same conditions in the currently inactive control method.

[0116] The currently valid control method is the control method currently applied to the processor 2a that is the target of software control of the first control or the second control, and the currently invalid control method is the control method currently not applied to the processor 2a that is the target of software control of the first control or the second control. Examples of the predetermined timing include the timing when the number of accesses to the shared memory 4 exceeds a first threshold (for example, 100,000), the timing when a certain time (for example, one minute) has passed, etc.

[0117] As an example, assume that the second control is currently enabled, the number of processors under hard control is 8, the number of processors under second control is 24, the number of requests per second under hard control is 10,000, and the number of requests per second under second control is 40.

[0118] In this case, the control method determination unit 123 acquires the most recent second monitoring result acquired from the latency monitor 122 (for example, average latency: 1500 ns).

[0119] In addition, the control method determination unit 123 searches the first latency estimation information 13c for an entry that meets the same conditions: number of processors under hardware control: 8, number of processors under first control: 24, number of requests per second under hardware control: 10,000, number of requests per second under first control: 40.

[0120] If the first latency estimation information 13c contains an entry whose conditions match the conditions of the second monitoring, the control method determination unit 123 obtains the average latency of the entry: 600 ns (see the fourth entry in Figure 7) as an estimate.

[0121] On the other hand, if there is no matching entry, the control method determination unit 123 may calculate an estimate of the average latency under approximately the same conditions from multiple entries included in the first latency estimation information 13c using various methods, such as obtaining the nearest neighbor value or calculating linear interpolation.

[0122] The control method determination unit 123 determines the control method to be the first control, for example, by disabling the second control and enabling the first control, because the average latency (1500 ns) of the currently valid second control is greater than the average latency (600 ns) of the currently invalid first control.

[0123] If the average latency (estimated value) of the currently inactive control method is equal to or less than the average latency (monitoring result) of the currently active control method, the control method decision unit 123 may decide to maintain the currently active control method.

[0124] The same applies to the case where the currently effective control method is the first control. For example, when the average latency (monitoring result) of the currently effective first control is greater than the average latency (estimated value) of the currently invalid second control, the control method determination unit 123 determines the control method to be the second control.

[0125] In this way, the control method determination unit 123 selects the first control or the second control based on the result of comparing the access latency when the first control is executed with the access latency when the second control is executed. This makes it possible to select a consistency control method that reduces the latency, thereby improving the performance of access from the multiple processors 2a to the shared memory 4.

[0126] When each of a plurality of applications 11 is executed by one or more processors 2a, the allocation number adjustment unit 124 adjusts the number of processors 2a subject to hardware control to be allocated to each application 11. Hereinafter, the number of processors 2a subject to hardware control may be referred to as the "hardware control allocation number" or simply the "allocation number".

[0127] The allocation number adjustment unit 124 may adjust the allocation number for each of the multiple applications 11 so that the average latency of the combined processor 2a subject to hardware control and the processor 2a subject to software control becomes equal between the applications 11, for example.

[0128] As described above, the number of processors that can be subjected to consistency control by the control circuit 4a (hardware) is limited to a predetermined number k. In addition, the performance of access from the processor 2a to the shared memory 4 is higher (latency is smaller) with hardware control than with software control.

[0129] Therefore, as an example, when there is a change in the number of applications 11 executed in the system 1, the allocation number adjustment unit 124 may evenly distribute the hardware control allocation number to each application 11, with a predetermined number k as an upper limit. A case where there is a change in the number of applications 11 is, for example, a case where the allocation number adjustment unit 124 detects the addition or termination of an application 11.

[0130] The processor 2a and the number of processors that execute each application 11 may differ for each application 11. Therefore, the allocation number adjustment unit 124 may refer to the processor management information 13a and perform distribution based on the ratio of the number of processors that execute each application 11, so that, for example, the application 11 with a larger number of processors has a larger number of hardware control allocations.

[0131] In addition, when the allocation number adjustment unit 124 determines the number of hardware control allocations, it determines the number of processors 2a to be subject to software control (hereinafter, sometimes referred to as the "software control allocation number") as the number obtained by subtracting the hardware control allocation number from the number of processors 2a executing the application 11.

[0132] With the above-mentioned distribution method, for example, the maximum allocatable number of hardware control allocations is allocated to the application 11 that is first introduced when the system 1 is not executing the application 11. The maximum allocatable number of hardware control allocations is the predetermined number k when the number of processors that execute the application 11 is greater than or equal to the predetermined number k, and is the number of processors that execute the application 11 when the number of processors that execute the application 11 is less than the predetermined number k. Furthermore, when the next application 11 is introduced into the system 1, the number of hardware control allocations allocated to the first application 11 is reduced, and the reduced number of hardware control allocations is allocated to the next application 11.

[0133] Furthermore, the allocation number adjustment unit 124 may determine the number of processors 2a to be subjected to hardware control for each application 11 of the hardware control allocation number.

[0134] For example, the allocation number adjustment unit 124 may monitor, for each processor 2a, the frequency with which access contention occurs for the shared memory 4, and may preferentially determine the processor 2a that frequently causes access contention as the target of hardware control. Various methods may be used to monitor the frequency with which access contention occurs.

[0135] Alternatively, the allocation number adjustment unit 124 may preferentially determine the processor 2a having the smallest node number and processor number in the processor management information 13a as the processor to be controlled by hardware, or may use various other methods to determine the processor 2a to be controlled by hardware.

[0136] The allocation number adjustment unit 124 may update the control flag of the processor management information 13a when determining the number of hard control allocations, the number of soft control allocations, the processor 2a subject to hard control, and the processor 2a subject to soft control for each application 11. This makes it possible to specify, from the processor management information 13a, the processor 2a that executes a certain application 11, the information on hard control or soft control of the processor 2a, the number of hard control allocations, and the number of soft control allocations.

[0137] Incidentally, the frequency of access from the processor 2a to the shared memory 4 differs for each application 11 executed by the processor 2a. Therefore, if the number of hardware control allocations is evenly distributed to each application 11 by the above-mentioned distribution method, there is a possibility that a bias in the access performance will occur among the applications 11.

[0138] For example, it is conceivable to preferentially allocate a larger number of hardware control allocations to an application 11 with a high access frequency. However, in this case, the application 11 will monopolize the consistency control function by the hardware, making it difficult to maintain fairness with other applications 11.

[0139] Therefore, the allocation number adjustment unit 124 measures the average latency of access to the shared memory 4 for each application 11 for each predetermined period (e.g., one minute). For example, the allocation number adjustment unit 124 may cause the latency monitor 122 to measure the average latency for each processor group, with one or more processors 2a (processor group) that executes the application 11 as the measurement target.

[0140] As a result, the allocation number adjustment unit 124 obtains, for each application 11, the number of processors under hardware control and software control of the processor group, the number of requests per second under hardware control and software control, and the average latency during a predetermined period.

[0141] Then, if there is a difference in the measured average latency between the applications 11 that exceeds a second threshold, the allocation number adjustment unit 124 determines that there is a bias in the number of hardware control allocations between the applications 11, and adjusts the number of hardware control allocations to each application 11.

[0142] For example, the allocation number adjustment unit 124 may calculate statistical information of a plurality of average latencies measured for all applications 11 executed in the system 1. An example of the statistical information is variance. When the variance exceeds a second threshold, the allocation number adjustment unit 124 may determine that there is a bias in the hardware control allocation numbers among the applications 11.

[0143] When the variance exceeds the second threshold, the allocation number adjustment unit 124 refers to, for example, the first latency estimation information 13c or the second latency estimation information 13d of the currently effective control method (first control or second control). In the following, it is assumed that the currently effective control method is the first control.

[0144] For example, the allocation number adjustment unit 124 acquires from the first latency estimation information 13c the average latency (first average latency) in an entry having the same condition as the condition when the average latency of the application 11 was measured. Also, the allocation number adjustment unit 124 acquires from the first latency estimation information 13c the average latency (second average latency) in an entry having a condition in which the number of processors under hardware control and software control is changed among the conditions when the average latency of the application 11 was measured.

[0145] The allocation number adjustment unit 124 compares the first average latency and the second average latency for each application 11, and specifies the hardware control allocation number for each application 11 so as to satisfy a predetermined condition between the applications 11. The predetermined condition may include, for example, the average latencies being equal. The average latencies being equal may mean, for example, that the average latencies of the multiple applications 11 are the same or approximately the same, in other words, that the difference between the average latencies approaches 0 (zero).

[0146] For example, the allocation number adjustment unit 124 may allocate a larger number of hard-controlled allocations than when the average latency was measured to an application 11 whose average latency is smaller than that of other applications 11. This may mean that the second average latency condition (the number of processors under hard control, the number of processors under soft control) when the first average latency is greater than the second average latency is allocated to the application 11.

[0147] On the other hand, the allocation number adjustment unit 124 may allocate a smaller hard-controlled allocation number than that at the time of measuring the average latency to an application 11 having a larger average latency than other applications 11. This may mean that the second average latency condition (the number of processors under hard control, the number of processors under soft control) when the first average latency is smaller than the second average latency is allocated to the application 11.

[0148] The allocation number adjustment unit 124 performs adjustment (search) of the hardware control allocation number by comparing the first average latency and the second average latency for each application 11. For example, the allocation number adjustment unit 124 may repeatedly perform the search until the difference in average latency between the applications 11 becomes equal to or less than the third threshold. This makes it possible to average (fair) the performance of access to the shared memory 4 by the applications 11.

[0149] In the above-mentioned adjustment, the allocation number adjustment unit 124 may determine the processor 2a to be subject to hardware control by the above-mentioned method, such as by preferentially determining the processor 2a that frequently causes access contention as the processor to be subject to hardware control.

[0150] The method of adjusting the hard control allocation numbers by the allocation number adjustment unit 124 is not limited to the above-mentioned method, and various other methods may be used.

[0151] [D] Example of operation Next, an operation example of the system 1 according to an embodiment will be described. An operation example of the processing unit 10A realized by the processor 2a that executes a control program will be described with reference to Figs.

[0152] [D-1] Example of latency monitor operation 9 and 10 are flowcharts illustrating examples of the operation of the first latency monitoring and the second latency monitoring, respectively. Note that the processes in Fig. 9 and Fig. 10 may be executed at predetermined intervals.

[0153] As illustrated in FIG. 9, the latency monitor 122 measures the average latency of accesses during a recent predetermined period of the processor 2a under the first control (software control) (step S1).

[0154] The latency monitor 122 measures the average latency of accesses made by the processor 2a under the hardware control during a given period of time immediately preceding the first control (step S2).

[0155] The latency monitor 122 records the conditions at the time of measurement in steps S1 and S2 and the average value of the average latency measured in steps S1 and S2 in the first latency estimation information 13c (step S3), and the process ends. The conditions at the time of measurement include, for example, the number of processors that are hard-controlled and soft-controlled, and the number of requests per second that are hard-controlled and soft-controlled.

[0156] As illustrated in FIG. 10, the latency monitor 122 measures, under the second control, the average latency of accesses of the processor 2a subject to the second control (software control) during a recent predetermined period (step S11).

[0157] The latency monitor 122 measures the average latency of accesses made by the processor 2a under the hardware control during a given period of time immediately preceding the second control (step S12).

[0158] The latency monitor 122 records the conditions under which the measurements were made in steps S11 and S12, and the average value of the average latencies measured in steps S11 and S12 in the second latency estimation information 13d (step S13), and the process ends.

[0159] [D-2] Example of operation of control method decision unit Fig. 11 is a flowchart for explaining an operation example of the control method determination process. As illustrated in Fig. 11, when an access to the shared memory 4 occurs (step S21), the control method determination unit 123 updates a counter (step S22) and determines whether the counter has exceeded a first threshold value (for example, 100000) (step S23).

[0160] If the counter does not exceed the first threshold (NO in step S23), the process ends. If the counter exceeds the first threshold (YES in step S23), the control method determination unit 123 determines whether the first control is being executed (enabled) as the soft control (step S24).

[0161] If the first control is being executed (YES in step S24), the control method determination unit 123 acquires the most recent measurement value (monitoring result) of the first latency by the latency monitor 122 and estimates the second latency (step S25). For example, the control method determination unit 123 may acquire, as the second latency, an average latency under the same conditions as those when the first latency was measured, from the second latency estimation information 13d.

[0162] The control method determination unit 123 determines whether the measured value of the first latency is greater than the estimated value of the second latency (step S26). If the measured value of the first latency is less than or equal to the estimated value of the second latency (NO in step S26), the process ends.

[0163] If the measured value of the first latency is greater than the estimated value of the second latency (YES in step S26), the control method determination unit 123 switches the control method from the first control to the second control (step S27), and the process ends.

[0164] In step S24, if the second control is being executed (NO in step S24), the control method determination unit 123 acquires the most recent measurement value (monitoring result) of the second latency by the latency monitor 122 and estimates the first latency (step S28). For example, the control method determination unit 123 may acquire, as the first latency, an average latency under the same conditions as those when the second latency was measured, from the first latency estimation information 13c.

[0165] The control method determination unit 123 determines whether the measured value of the second latency is greater than the estimated value of the first latency (step S29). If the measured value of the second latency is less than or equal to the estimated value of the first latency (NO in step S29), the process ends.

[0166] If the measured value of the second latency is greater than the estimated value of the first latency (YES in step S29), the control method determination unit 123 switches the control method from the second control to the first control (step S30), and the process ends.

[0167] [D-3] Example of operation of allocation number adjustment unit Fig. 12 is a flowchart for explaining an example of the operation of the process when the number of applications changes. Fig. 13 is a flowchart for explaining an example of the operation of the allocation number adjustment process. Note that the process in Fig. 13 may be executed at predetermined intervals.

[0168] 12, when the allocation number adjustment unit 124 detects the addition or termination of an application 11 (step S31), it identifies the number of hardware control allocations of the added or terminated application 11 (step S32). For example, when an application 11 is added, the allocation number adjustment unit 124 calculates the number of hardware control allocations to be allocated to the application 11, and when an application 11 is terminated, it identifies the number of hardware control allocations that was allocated to the application 11.

[0169] The allocation number adjustment unit 124 determines whether or not there is another application 11 being executed (step S33). If there is another application 11 being executed (YES in step S33), the allocation number adjustment unit 124 changes the hardware control allocation numbers of the other applications 11 (step S34).

[0170] In addition, in step S32 (when adding an application 11) and step S34, the allocation number adjustment unit 124 may calculate the hardware control allocation number so that the hardware control allocation numbers are equal among the applications 11. For this calculation, information such as the number of applications 11 being executed, the number of processors executing each application 11, and a predetermined number k may be used.

[0171] After step S34 is completed, or if there is no other application 11 being executed in step S33 (NO in step S33), the process proceeds to step S35.

[0172] In step S35, the allocation number adjustment unit 124 determines whether or not the application 11 was added in step S31. If the application 11 was not added in step S31 (NO in step S35), the process ends.

[0173] If the application 11 is added in step S31 (YES in step S35), the allocation number adjustment unit 124 starts execution of the added application 11 (step S36), and the process ends.

[0174] As illustrated in FIG. 13, the allocation number adjustment unit 124 acquires a latency monitoring result (measurement value) for each application 11 in the most recent predetermined period from the latency monitor 122 (step S41).

[0175] The allocation number adjustment unit 124 calculates statistical information (eg, variance) of the latency measurement values ​​(first latencies) of the multiple applications 11 (step S42).

[0176] The allocation number adjustment unit 124 determines whether the statistical information exceeds the second threshold (step S43). If the statistical information does not exceed the second threshold (NO in step S43), the process ends.

[0177] If the statistical information exceeds the second threshold (YES in step S43), the allocation number adjustment unit 124 searches for a hardware control allocation number for each application 11 so that the latencies of the multiple applications 11 are uniform (step S44).

[0178] The allocation number adjustment unit 124 reflects the hardware control allocation number in each application 11 (step S45), and the process ends.

[0179] [E] Other The technology according to the above-described embodiment can be modified and changed as follows.

[0180] For example, the shared memory access unit 121, the latency monitor 122, the control method determination unit 123, and the allocation number adjustment unit 124 included in the library 12A shown in Fig. 4 may be merged in any combination or may be divided. Also, the processor management information 13a, the application management information 13b, the first latency estimation information 13c, and the second latency estimation information 13d stored in the memory unit 13A may be merged in any combination or may be divided.

[0181] In addition, in the embodiment, the application 11 and the processor 2a are described as the smallest units of control, but this is not limiting. For example, the library 12A may switch between hardware control and software control (first control and second control) on a process basis instead of on an application 11 basis. Also, the library 12A may switch between hardware control and software control (first control and second control) on a processor core basis or a node 2 basis instead of on a processor 2a basis. In these cases, the processor management information 13a and the application management information 13b may be managed on a processor core basis or a process basis.

[0182] [F] Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

[0183] (Appendix 1) When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. A memory access control program that causes any one of the plurality of processors to execute a process.

[0184] (Appendix 2) The process of executing the access control of the second processor includes a process of selecting the first control or the second control based on a comparison result between an access latency from the multiple processors to the shared memory when the first control is executed and an access latency from the multiple processors to the shared memory when the second control is executed. 2. The memory access control program according to claim 1.

[0185] (Appendix 3) The control of the access includes a control of data consistency due to the access; The first control is the second processor sets information regarding a cache state in management information stored in a predetermined storage area of ​​the shared memory; The first processor executes the consistency control by referring to the management information when accessing the shared memory. 3. The memory access control program according to claim 1 or 2.

[0186] (Appendix 4) The second control is the second processor issues the command to the first processor to instruct the first processor to access the shared memory; The first processor executes the command, whereby the access instructed by the executed command is controlled by the hardware. The memory access control program according to any one of claims 1 to 3.

[0187] (Appendix 5) Each of the plurality of processors executes a program assigned to one or more processors; the process of determining the number of processors includes a process of determining, for each of the plurality of programs, the number of processors to be operated as the first processor from one or more processors that execute the process, such that the latency of access to the shared memory from each of the plurality of programs executed by the plurality of processors satisfies a predetermined condition between the plurality of programs; The memory access control program according to any one of claims 1 to 4.

[0188] (Appendix 6) When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. A memory access control method, in which processing is executed by any one of the plurality of processors.

[0189] (Appendix 7) The process of executing the access control of the second processor includes a process of selecting the first control or the second control based on a comparison result between an access latency from the multiple processors to the shared memory when the first control is executed and an access latency from the multiple processors to the shared memory when the second control is executed. 7. The memory access control method according to claim 6.

[0190] (Appendix 8) The control of the access includes a control of data consistency due to the access; The first control is the second processor sets information regarding a cache state in management information stored in a predetermined storage area of ​​the shared memory; The first processor executes the consistency control by referring to the management information when accessing the shared memory. 8. The memory access control method according to claim 6 or 7.

[0191] (Appendix 9) The second control is the second processor issues the command to the first processor to instruct the first processor to access the shared memory; The first processor executes the command, whereby the access instructed by the executed command is controlled by the hardware. The memory access control method according to any one of claims 6 to 8.

[0192] (Appendix 10) Each of the plurality of processors executes a program assigned to one or more processors; the process of determining the number of processors includes a process of determining, for each of the plurality of programs, the number of processors to be operated as the first processor from one or more processors that execute the process, such that the latency of access to the shared memory from each of the plurality of programs executed by the plurality of processors satisfies a predetermined condition between the plurality of programs; The memory access control method according to any one of claims 6 to 9.

[0193] (Appendix 11) When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. An information processing device comprising a control unit.

[0194] (Appendix 12) the control unit, in a process of executing the access control of the second processor, selects the first control or the second control based on a comparison result between an access latency from the plurality of processors to the shared memory when the first control is executed and an access latency from the plurality of processors to the shared memory when the second control is executed. 12. The information processing device according to claim 11.

[0195] (Appendix 13) The control of the access includes a control of data consistency due to the access; The first control is the second processor sets information regarding a cache state in management information stored in a predetermined storage area of ​​the shared memory; The first processor executes the consistency control by referring to the management information when accessing the shared memory. 13. The information processing device according to claim 11 or 12.

[0196] (Appendix 14) The second control is the second processor issues the command to the first processor to instruct the first processor to access the shared memory; The first processor executes the command, whereby the access instructed by the executed command is controlled by the hardware. The information processing device according to any one of claims 11 to 13.

[0197] (Appendix 15) Each of the plurality of processors executes a program assigned to one or more processors; the control unit, in the process of determining the number of processors, determines, for each of the plurality of programs, the number of processors to be operated as the first processor from one or more processors executing the processing of the plurality of programs such that an access latency from each of the plurality of programs executed by the plurality of processors to the shared memory satisfies a predetermined condition between the plurality of programs; The information processing device according to any one of claims 11 to 14. [Explanation of symbols]

[0198] 1 System 1a,1b Interconnect 10,10A Processing section 11 Applications 12,12A Library 121 Shared Memory Access Unit 122 Latency Monitor 123 Control Method Decision Unit 124 Allocation Adjustment Department 13,13A Memory section 13a Processor Management Information 13b Application Management Information 13c Information for estimating first latency 13d Information for estimating second latency 14, 14A Control section 2 Node 2a Processor 2b,4b Memory 2c Graphics Processing Unit 2d storage device 2e Communication Interface 2f IO device 2g reader 2h Device IF 2i Program 2j Recording media 2k bus 20. Cache 3 Switch 4. Shared Memory 4a Control circuit 40,42 storage area 41 Management Information

Claims

1. When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. A memory access control program that causes any one of the plurality of processors to execute a process.

2. The process of executing the access control of the second processor includes a process of selecting the first control or the second control based on a comparison result between an access latency from the plurality of processors to the shared memory when the first control is executed and an access latency from the plurality of processors to the shared memory when the second control is executed.

2. The memory access control program according to claim 1.

3. The control of the access includes a control of data consistency due to the access; The first control is the second processor sets information regarding a cache state in management information stored in a predetermined storage area of ​​the shared memory; The first processor executes the consistency control by referring to the management information when accessing the shared memory.

3. The memory access control program according to claim 1.

4. The second control is the second processor issues the command to the first processor to instruct the first processor to access the shared memory; a process in which the first processor executes the command, whereby the access instructed by the executed command is controlled by the hardware; 3. The memory access control program according to claim 1.

5. Each of the plurality of processors executes a program assigned to one or more processors; the process of determining the number of processors includes a process of determining, for each of the plurality of programs, the number of processors to be operated as the first processor from one or more processors that execute the process, such that the latency of access to the shared memory from each of the plurality of programs executed by the plurality of processors satisfies a predetermined condition between the plurality of programs; 3. The memory access control program according to claim 1.

6. When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. A memory access control method, in which processing is executed by any one of the plurality of processors.

7. When controlling access from each of a plurality of processors to a shared memory including a storage area shared among the plurality of processors, determining a number of first processors that can be controlled by the hardware when the access is controlled by the hardware; control of the accesses to the shared memory from the remaining second processors, which number exceeds the determined number of processors, among the plurality of processors, by a first control performed by software executed by the second processor, based on the frequency of the accesses to the shared memory from the plurality of processors, or a second control that causes the first processor to execute the control by a command issued by the second processor. An information processing device comprising a control unit.

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