High-performance input buffer and memory device having the same

Abstract

To provide a high-performance input buffer and a memory device having the same.SOLUTION: A method of operating a memory device includes the steps of: receiving an input including command signals, address signals, and data signals; transmitting the command signals or the address signals to a low-speed buffer; and transmitting the data signals to a high-speed buffer.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present application relates to the field of semiconductor technology, and in particular to three-dimensional (3D) memory devices, input buffer structures, and methods for configuring input buffers. [Background technology]

[0002] Not-AND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. With the increasing demands of home appliances, cloud computing, and big databases, there is a constant need for larger capacity and better performance NAND memory. As traditional two-dimensional (2D) NAND memory is approaching its physical limits, three-dimensional (3D) NAND memory now plays an important role. 3D NAND memory uses multiple stack layers on a single die to achieve higher density, larger capacity, faster performance, lower power consumption, and more cost-effectiveness.

[0003] As the input / output (I / O) speed of NAND devices increases, more static power is consumed during idle cycles. For example, higher I / O speeds can result in higher bus idle currents. There is a challenge to speed up I / O performance while meeting power consumption requirements in NAND devices. The disclosed systems and methods are directed to solving one or more of the problems set forth above, as well as other problems. Summary of the Invention [Means for solving the problem]

[0004] In one aspect of the disclosure, a method for operating a memory device includes receiving inputs including command signals, address signals, and data signals via input / output (I / O) components, sending the command signals or the address signals to a low speed buffer, and sending the data signals to a high speed buffer.

[0005] In another aspect of the disclosure, a memory device includes an I / O component for receiving inputs including command signals, address signals, and data signals, a low speed buffer for buffering the command signals or the address signals, and a high speed buffer for buffering the data signals, the I / O component being adaptable to send the command signals or the address signals to the low speed buffer and send the data signals to the high speed buffer.

[0006] In another aspect of the disclosure, a method for operating a memory device includes receiving input including command signals, address signals, and data signals, enabling a low speed buffer, performing a command cycle and buffering the command signals using the low speed buffer or performing an address cycle and buffering the address signals using the low speed buffer, enabling a high speed buffer, and performing a data input cycle and buffering the high speed signals using the high speed buffer.

[0007] One aspect of the present disclosure can be understood by one of ordinary skill in the art in light of the description, claims, and drawings of the present disclosure. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of an exemplary three-dimensional (3D) memory device according to various embodiments of the present disclosure. [Diagram 2] FIG. 1 is a block diagram of a 3D memory device according to various embodiments of the present disclosure. [Diagram 3] FIG. 2 is a block diagram of a fast path and a slow path according to various embodiments of the present disclosure. [Figure 4] FIG. 4 is a timing diagram of a command cycle according to various embodiments of the present disclosure. [Diagram 5] 4A-4C are timing diagrams of address cycles according to various embodiments of the present disclosure. [Figure 6] FIG. 4 is a timing diagram of a data input cycle according to various embodiments of the present disclosure. [Figure 7] FIG. 2 is a block diagram of a buffer configuration according to various embodiments of the present disclosure. [Figure 8] 4A-4D are timing diagrams of address and data input cycles according to various embodiments of the present disclosure. [Figure 9] FIG. 4 is a timing diagram of a command / address cycle and a data input cycle according to various embodiments of the present invention. [Figure 10] 1 illustrates timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 11] 1 illustrates timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 12] 1 illustrates timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 13] 1 illustrates timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 14] 1 illustrates timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 15] 1 is a schematic flow chart illustrating a method for buffering an input signal according to various aspects of the present disclosure. [Figure 16] 1 is a schematic flow chart illustrating a method for buffering an input signal according to various aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The technical solutions in the embodiments of the present disclosure will be described below with reference to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same or similar parts as much as possible. It is clear that the described embodiments are only a part, but not all, of the embodiments of the present disclosure. Features in various embodiments may be exchanged and / or combined. Other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without inventive efforts are within the scope of the present disclosure.

[0010] FIG. 1 illustrates a schematic cross-sectional view of an exemplary 3D memory device according to an embodiment of the present disclosure. The 3D memory device 100 may be a discrete memory device operating individually. The 3D memory device 100 may be part of a memory system having multiple memory devices 100. In some embodiments, the 3D memory device 100 may be coupled to or embedded in a host device (not shown). The host device may include computing devices such as mobile phones, smartphones, smart watches, tablet computers, laptop computers, personal computers, data servers, and workstations, among other host devices.

[0011] In some cases, the 3D memory device 100 may include a memory array device 110 and a peripheral device 120. The memory array device 110 may include memory cells forming one or more 3D arrays. The peripheral device 120 may include circuitry including control circuitry for controlling the operation of the 3D memory device 100. In some embodiments, the memory array device 110 and the peripheral device 120 may be manufactured separately and then combined to form a stack-like structure as shown in FIG. 1. Alternatively, the memory array device 110 and the peripheral device 120 may be integrated into one device. For example, the peripheral device 120 may be manufactured first, and then the memory array device 110 may be fabricated above the peripheral device 120 using the peripheral device 120 as a substrate. In some other embodiments, the memory array device 110 and the peripheral device 120 may be manufactured separately and then mounted side-by-side on a printed circuit board (PCB).

[0012] FIG. 2 illustrates a block diagram of a 3D memory device 200 according to an embodiment of the present disclosure. The 3D memory device 200 may include a memory array 210 and a control circuit 212 that serves as a controller for the 3D memory device 200. The memory array 210 may include a 3D array of memory cells (not shown). The memory cells may include Not-AND (NAND) memory cells, Not-OR (NOR) memory cells, and / or other types of memory cells. In some cases, the memory array 210 may include a two-dimensional (2D) array of memory cells (not shown) including NAND memory cells, NOR memory cells, and / or other types of memory cells. The 3D memory device 200 may further include an input / output (I / O) interface 214, a low-speed buffer 216, a high-speed buffer 218, a row decoder 220, and a column decoder 222. In some embodiments, the term "low speed" as used herein may refer to speeds less than 100 megahertz (MHz), and the term "high speed" as used herein may refer to speeds of 1 gigahertz (GHz) or greater. In some cases, and in some other cases, "fast" and "slow" may be defined relative to one another, with "fast" indicating at least one order of magnitude faster than "slow." That is, a high-speed buffer may be at least one order of magnitude faster than a low-speed buffer. The control circuitry 212 may perform various functions of the 3D memory device 200. For example, the control circuitry 212 may perform read, write, and erase operations. The I / O interface 214 may also be referred to as an I / O component or I / O connection and may include I / O circuitry for receiving command, address, and data signal inputs to the 3D memory device 200 and transmitting data and status information from the 3D memory device 200 to another device (e.g., a host device). The low-speed buffer 216 is also referred to as a low-speed page buffer and buffers or temporarily stores command / address signals, while the high-speed buffer 218 is also referred to as a high-speed page buffer and buffers or temporarily stores data signals.The row decoder 220 and the column decoder 222 may respectively decode row address signals and column address signals for accessing the memory array 210. The row decoder 220 and the column decoder 222 may also respectively receive different voltages from a voltage generator circuit (not shown) and transfer the received voltages to selected objects, such as word lines or bit lines, of the memory array 210.

[0013] The I / O interface 214 may detect command signals, address signals, and data signals from the input. In some embodiments, the I / O interface 214 may send command and / or address signals to the low-speed buffer 216 and send data signals to the high-speed buffer 218. In some cases, the I / O interface 214 may send command and / or address signals only to the low-speed buffer 216 and send data signals only to the high-speed buffer 218. In some cases, the control circuit 212 may send command signals, address signals, and data signals to the buffers 216 and 218 by sending instructions to the I / O interface 214. The low-speed buffer 216 may include one or more low-speed buffers and be configured to receive and buffer command signals, address signals, and / or other signals that do not require high-speed processing. When the low-speed buffer 216 includes multiple low-speed buffers, one of the low-speed buffers may be used to receive command signals and another low-speed buffer may be used to store address signals. The high-speed buffer 218 may include one or more high-speed buffers and be configured to receive and buffer data signals and / or other signals that require high-speed processing.

[0014] In some memory devices, command signals, address signals, and data signals are all sent from the I / O interface to a high-speed buffer to facilitate high-speed operation. The high-speed buffer then passes the command / address signals to a command / address latch and passes the data signals to a deserializer. The command / address signals are latched and accept a command / address sequence with a write enable (WE_n) cycle. The data signals are deserialized and synchronize the parallel data for writing cache data in a high-speed clock cycle with a data strobe (DQS) signal (e.g., a DQS_t or DQS_c signal). However, the high-speed buffer consumes high static power and requires a high-speed reference bias wake-up process. The data signals require a high-speed buffer for high-speed operation. For example, the speed of the data signals sent to the buffer may reach at least 1 GHz in some cases. However, for the command / address signals, a speed of less than 100 MHz may be sufficient to support operation in the WE_n cycle. Thus, the command / address signals may not require high-speed operation in some cases. A low-speed buffer may provide sufficient efficiency for the command / address signals in such cases.

[0015] As shown in FIG. 2, the low-speed buffer 216 is configured to receive and buffer command and / or address signals, while the high-speed buffer 218 is configured to receive and buffer data signals. In some embodiments, the command / address signals may be passed only to the low-speed buffer 216, and the data signals may be passed only to the high-speed buffer 218. Because the command / address signals are processed by the low-speed buffer 216, static power in idle mode may be reduced compared to a scenario in which high-speed buffers are configured for all input signals. Also, because the command / address signals are processed by the low-speed buffer 216, active power may also be reduced. Furthermore, the operating frequency of the high-speed buffer 218 may be increased to improve high-speed performance of the 3D memory device 200 while static power consumption is controlled.

[0016] FIG. 3 illustrates a block diagram 300 of high-speed and low-speed paths configured to process input signals for a memory device according to an embodiment of the present disclosure. The high-speed path may be configured to propagate and process data signals, and the low-speed path may be configured to propagate and process command / address signals. The high-speed path may include devices such as a current-mode logic (CML) buffer 310, an amplifier 312, and a deserializer 314. The CML buffer is based on a differential circuit. For example, the CML buffer 310 may receive differential input signals Vinp and Vinn and generate differential output signals Vop and Von. The CML buffer can operate at low signal voltages and can operate at high speeds (e.g., 1 GHz) with low supply voltages, but draws high static currents and remains in common mode. The high-speed path may include multiple CML buffers (not shown). The amplifier 312 may be, for example, a differential operational amplifier. The differential operational amplifier amplifies the difference between two input signals, such as two input voltages. The high-speed path may include multiple amplifiers, for example, multiple amplifiers 312. The deserializer 314 may include a deserialization circuit that converts serial data into parallel data that may be sent to a write cache and temporarily stored in the write cache before being written to the memory array.

[0017] The low speed path may include an amplifier 316 and a command / address latch 318. Similar to amplifier 312, amplifier 316 may be, for example, a differential operational amplifier. The low speed path may include multiple amplifiers, for example, multiple amplifiers 316. The command / address latch 318 may latch the command / address signals sent to the row decoder and column decoder.

[0018] A metal-oxide semiconductor field effect transistor (MOSFET) M1 may be coupled to the CML buffer 310 and may provide a HighSpeedEnable signal to the CML buffer 310. A MOSFET M2 may be coupled to the amplifier 312 and may provide a HighSpeedEnable signal to the amplifier 312. A MOSFET M3 may be coupled to the CML buffer 310 and may provide a reference signal to the CML buffer 310. A MOSFET M4 may be coupled to the amplifier 316 and may provide a LowSpeedEnable signal to the amplifier 316. As used herein, the term "coupled" refers to electrically connected.

[0019] Thus, an input signal received at a memory device may be split into two parts. One part includes data signals and the other part includes command / address signals. The data signals may be sent and buffered along a high-speed path and the command / address signals may be sent and buffered along a low-speed path. In some embodiments, the data signals may be sent and buffered only along the high-speed path and the command / address signals may be sent and buffered only along the low-speed path. Because the command / address signals are not passed along the high-speed path, the static power consumption of the memory device may be controlled when high-speed operations are performed at the memory device.

[0020] FIG. 4 illustrates a schematic timing diagram of a command cycle of a memory device according to various embodiments of the present disclosure. The command cycle may include command signals such as a chip enable (CE_n) signal, a command latch enable (CLE) signal, an address latch enable (ALE) signal, a WE_n signal, a read enable (RE_t) signal, a complement read enable (RE_c) signal, a DQS_t signal, a DQS_c signal, and a DQ[7:0] signal. The CE_n signal may be used to select a NAND target. A NAND target may include a set of logical units (LUNs) that share one CE_n signal within a NAND package. tCS is the CE_n setup time, and tCH is the CE_n hold time. The CLE signal may be used to indicate the type of bus cycle (e.g., command bus cycle, address bus cycle, or data bus cycle). The ALE signal may be used to indicate the type of bus cycle (e.g., command bus cycle, address bus cycle, or data bus cycle). tCALS is the CLE and ALE setup time, and tCALH is the CLE and ALE hold time. tCSD is the ALE, CLE, WE_n hold time from CE_n high. The WE_n signal may be used to control the latching of the command, address, and input data. tWP is the WE_n low pulse width. The RE_t signal may be used to enable the serial data output. The RE-c signal is the complement of the RE_t signal. The DQS_t signal is the data strobe signal, and the DQS_c signal is the complement of the DQS_t signal. The DQ[7:0] signals are data I / O signals. tCAS is the command / address DQ setup time, and tCAH is the command / address DQ hold time.

[0021] 4, the LowSpeedEnable signal is used to enable the low speed buffers for the command cycle. For example, the low speed buffers may be enabled at the beginning of tCS and disabled at the end of tCH. As indicated above, the command signals may be passed to the low speed buffers and buffered at a low speed. Thus, the static power consumption of the memory device may be reduced compared to when the command signals are buffered using a high speed buffer.

[0022] FIG. 5 illustrates a schematic timing diagram 500 of an address cycle of a memory device according to various embodiments of the present disclosure. The address cycle may have command signals similar to those of the command cycle in FIG. 4, such as a CE_n signal, a CLE signal, an ALE signal, a WE_n signal, a RE_t signal, a RE_c signal, a DQS_t signal, a DQS_c signal, and a DQ[7:0] signal. A LowSpeedEnable signal may be used to enable a low-speed buffer for the address cycle. For example, the low-speed buffer may be enabled at the beginning of tCS and disabled at the end of tCH. As indicated above, the address signal may be passed to a low-speed buffer and buffered at a low speed. Thus, the static power consumption of the memory device may be reduced compared to when the address signal is buffered using a high-speed buffer.

[0023] In some cases, the idle mode of the memory device may be implemented only when the low-speed buffer is enabled and the high-speed buffer is in standby mode or off mode. In some embodiments, command or address cycles are performed using only the low-speed buffer. That is, the command / address signals are buffered using only the low-speed buffer. Therefore, lower active power and lower static power may be achieved compared to using high-speed buffers to buffer the command / address signals.

[0024] FIG. 6 shows a schematic timing diagram 600 of a data input cycle of a memory device according to various embodiments of the present disclosure. The data input cycle may have command signals such as CE_n, CLE, ALE, WE_n, RE_t, RE_c, DQS_t, DQS_c, and DQ[7:0] signals. tCS1 is the CE_n setup time for a data burst with termination resistor (ODT) disabled, and tCS2 is the CE_n setup time with DQS / DQ[7:0] ODT enabled. tCALS is the CLE and ALE setup time, while tCALS2 is the CLE and ALE setup time when ODT is enabled. tCD is the CE_n setup time to DQS (DQS_t) low after CE_n has been high for more than 1 microsecond. tDBS is the DQS (DQS_t) high and RE_n (RE_t) high setup to ALE, CLE, and CE_n low during the data burst. tCDQSS is the DQS setup time for data input start. tWPRE is the DQS write preamble, and tWPRE2 is the DQS write preamble when ODT is enabled. tDQSH is the DQS high width, while tDQSL is the DQS low width. tDSC is the DQS cycle time. tDS is the data setup time. tDH is the data hold time. tWPST is the DQS write postamble. tWPSTH is the DQS write postamble hold time. tCDQSH is the DQS hold time for data input burst end. D0~D N is the data byte / word to be written to the addressed page. 10h is the second cycle of the Page Program command.

[0025] Referring to FIG. 6, the HighSpeedEnable signal may be used to enable a high-speed buffer for a data input cycle. For example, the high-speed buffer may be enabled when the ODT is enabled and disabled when the ODT is disabled. As exemplified above, the data input signal may be passed to the high-speed buffer and buffered at high speed. In an idle mode, the high-speed buffer may be disabled. Thus, the static power consumption of the memory device in an idle mode may be reduced compared to when the high-speed buffer remains enabled in the idle mode.

[0026] FIG. 7 shows a schematic block diagram 700 of a buffer configuration of a memory device according to an embodiment of the present disclosure. The buffer configuration may include a high-speed buffer 710, a low-speed buffer 712, an input buffer control 714, a reference bias 716, a high-speed deserializer 718, and a command / address latch 720. The input buffer control 714 may use a ChipEnable signal to select a NAND target and a DDR_DINCYCLE signal to detect command, address, and data signals, respectively, from the input signal. When the input signal is a data signal, the input buffer control 714 may generate a HighSpeedEnable signal and send the HighSpeedEnable signal to the high-speed buffer 710. The HighSpeedEnable signal enables the high-speed buffer 710. When the input signal is a command signal or an address signal, the input buffer control 714 may generate a LowSpeedEnable signal and send the LowSpeedEnable signal to the low-speed buffer 712. The LowSpeedEnable signal enables the low-speed buffer 712. The ChipEnable signal may enable a reference bias 716 that provides a reference signal to the high-speed buffer 710 when the high-speed buffer 710 is enabled. The input signals include command signals, address signals, and / or data signals, and may include differential or single-ended data. The command / address signals are sent to the low-speed buffer 712. The data signals are sent to the high-speed buffer 710. Further, the high-speed buffer 710 may pass the data signals to the high-speed deserializer 718, and the low-speed buffer 712 may forward the command / address signals to the command / address latch 720. In some embodiments, the command / address signals are sent only to the low-speed buffer 712 in order to reduce the active and static power of the memory device. In some cases, in order to reduce the static power of the memory device, the idle mode of the memory device may be enabled only when the high-speed buffer 710 is disabled. Thus, the low-speed buffer may be enabled in the idle mode.

[0027] FIG. 8 illustrates a schematic timing diagram 800 of an address cycle and a subsequent data input cycle of a memory device according to various embodiments of the present disclosure. In some cases, the address cycle may be replaced by a command cycle. As illustrated in FIG. 8, the address cycle and the data input cycle may have command signals such as a CE_n signal, a CLE signal, an ALE signal, a WE_n signal, a RE_t signal, a RE_c signal, a DQS_t signal, a DQS_c signal, and a DQ[7:0] signal. A LowSpeedEnable signal may be used to enable a low-speed buffer for the address cycle. A HighSpeedEnable signal may be used to enable a high-speed buffer for the data input cycle. As illustrated above, the address signal may be passed to a low-speed buffer and buffered by a low-speed operation, and the data input signal may be passed to a high-speed buffer and buffered by a high-speed operation. For example, the low-speed buffer may be enabled at the start of tCS and disabled at the end of tCH. Meanwhile, the high-speed buffer may be enabled when ODT is enabled and disabled when ODT is disabled. In an idle mode of the memory device, the slow buffers may be enabled to reduce static power consumption while the high speed buffers may be disabled.

[0028] Referring to FIG. 8, the controller of the memory device may, for example, first detect an address signal. Furthermore, the low-speed buffer may be enabled by the controller. The address signal may be sent to the low-speed buffer, and the address cycle may be performed using the low-speed buffer. After the address cycle is completed and the low-speed buffer is disabled, the controller may detect a data signal. Then, the high-speed buffer may be enabled by the controller when the ODT is enabled, and the data signal may be sent to the high-speed buffer. The data input cycle may be performed using the high-speed buffer. When the ODT is disabled, the high-speed buffer is disabled and the data input cycle is terminated. Thus, when an address cycle and / or a command cycle is performed, the high-speed buffer is disabled. The high-speed buffer is enabled only when a data input cycle is performed or when a data input cycle is performed in a page program operation. Thus, the active power and static power of the memory device may be reduced compared to a scenario in which a high-speed buffer is used to store command / address data.

[0029] FIG. 9 illustrates a schematic timing diagram 900 of a low-speed command / address cycle and a high-speed data input cycle of a memory device according to various embodiments of the present disclosure. The memory device includes a controller for controlling certain operations. As illustrated in FIG. 9, the operations may include command signals such as a CE_n signal, a CLE signal, an ALE signal, a DQS_t signal, a DQ[7:0] signal, a WE_n signal, a LowSpeedEnable signal, and a HighSpeedEnable signal. In FIG. 9, other command signals are omitted to simplify the diagram. As illustrated above, the LowSpeedEnable signal is used to enable a low-speed buffer for a low-speed command / address cycle, while the HighSpeedEnable signal is used to enable a high-speed buffer for a high-speed data input cycle. The command / address signals may be sent to a low-speed buffer and buffered by the low-speed operation, and the data input signals may be sent to a high-speed buffer and buffered by the high-speed operation.

[0030] 9, before time t1 and during the period between t1 and t2, the LowSpeedEnable signal may be high and the HighSpeedEnable signal may be low. Thus, during this period, the low speed buffers may be enabled and the high speed buffers may be disabled by the controller. The controller may obtain the command / address signals using the DQ[7:0] signals and control the latching of the command / address signals using the WE_n signals. The command / address signals may be latched into the low speed buffers during the low speed command / address cycles.

[0031] At time t2, when the command / address cycle is completed and the CE_n / CLE / ALE / DQS_t signals (i.e., the CE_n signal, the CLE signal, the ALE signal, and the DQS_t signal) are low, the controller may activate the high-speed mode by bringing the HighSpeedEnable signal high and deactivate the low-speed mode by bringing the LowSpeedEnable signal low. That is, the high-speed buffers may be enabled and the low-speed buffers may be disabled. A high-speed data input cycle may then be performed in the high-speed buffers by the controller. At time t3, the controller may bring the HighSpeedEnable signal low and the LowSpeedEnable signal high. The high-speed buffers may then be disabled and the low-speed buffers enabled, and another command / address cycle may be performed.

[0032] FIG. 10 illustrates a schematic timing diagram 1000 including an address cycle, a command cycle, and a data input cycle for a memory device according to various embodiments of the present disclosure. When an I / O interface of the memory device receives an input, a controller of the memory device may cause the I / O interface to pass the input command / address signals to a low speed buffer and pass the data signals to a high speed buffer. The command signals, address signals, and data signals may be sent sequentially from the I / O interface. The command cycle, address cycle, and data input cycle may be performed sequentially. For example, at time t1, the controller may enable the low speed buffer and perform an address cycle. The address cycle may end at time t2 when the low speed buffer is disabled. Then, at time t3, the controller may enable the high speed buffer and perform a data input cycle. In some embodiments, the high speed mode is activated and the high speed buffer is enabled when the CE_n / CLE / ALE / DQS_t signal is low. At time t4, the controller may disable the high speed buffer and end the data input cycle. At time t5, the controller may re-enable the slow buffers and perform the command cycle, which may end when the slow buffers are disabled at time t6. Thus, address and command cycles may be performed using the slow buffers. Furthermore, when address and command cycles are performed, the high-speed buffers may be disabled to reduce power consumption in the active mode. The high-speed buffers may be enabled only when data input cycles are performed.

[0033] FIG. 11 illustrates a schematic timing diagram 1100 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, a low-speed buffer, a high-speed buffer, and a controller that controls the operation of the memory device. After the I / O connection receives an input, the input command / address signal may be sent to the low-speed buffer and the data signal may be sent to the high-speed buffer. The command signal, address signal, and data signal may be sent from the I / O connection sequentially or in parallel. The command cycle, address cycle, and data input cycle may be performed sequentially or in parallel by the controller. For example, at time t1, the controller may enable the low-speed buffer and perform a first address cycle. The first address cycle may end at time t2 when the low-speed buffer is disabled. Then, the controller may enable the high-speed buffer and perform a data input cycle at t3. In some embodiments, the high-speed buffer is enabled when the CE_n / CLE / ALE / DQS_t signal is low. During the period of the data input cycle, the I / O connection may receive an additional address signal. At time t4, the controller may enable the slow buffer and perform a second address cycle. The second address cycle and the data input cycle are performed in parallel because the two cycles are within the same period from t4 to t5. During the period from t4 to t5, the address signal and the data signal may be sent from the I / O connection to the slow buffer and the fast buffer simultaneously. That is, in some aspects, the address signal (or command signal) and the data signal may be sent in parallel from the I / O connection. The second address cycle may end at time t5 when the slow buffer is disabled. At time t6, the controller may disable the fast buffer and stop the data input cycle. At time t7, the controller may re-enable the slow buffer and perform a command cycle, which may end when the slow buffer is disabled at time t8.Thus, address and command cycles may only be performed using the low speed buffers, and the high speed buffers may only be enabled when data input cycles are performed.

[0034] FIG. 12 illustrates a schematic timing diagram 1200 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, a low-speed buffer, a high-speed buffer, and a controller that controls the operation of the memory device. After the I / O connection receives an input, the input command / address signal may be sent to the low-speed buffer and the data signal may be sent to the high-speed buffer. In some embodiments, the I / O connection represents an I / O interface and may simultaneously receive command signals, address signals, and data signals and simultaneously forward the command signals, address signals, and data signals to different destinations (e.g., different buffers). At time t1, the controller may enable the low-speed buffer and perform a first address cycle. The first address cycle may end at time t2 when the low-speed buffer is disabled. Furthermore, at time t3, the controller may enable the high-speed buffer and perform a data input cycle. In some embodiments, the high-speed buffer is enabled when the CE_n / CLE / ALE / DQS_t signal is low. During a period of a data input cycle, the I / O connection may receive address and / or command signals. For example, at time t4, the controller may enable the slow buffer and execute a second address cycle using the slow buffer. The second address cycle may end at time t5, when the slow buffer is disabled. At time t6, the controller may re-enable the slow buffer and execute a command cycle using the slow buffer. At time t7, the slow buffer may be disabled and the command cycle may end. At time t8, the controller may disable the high-speed buffer and stop the data input cycle. Thus, address and command cycles may be executed only using the low-speed buffer. The high-speed buffer may be enabled only when a data input cycle is executed.

[0035] FIG. 13 illustrates a schematic timing diagram 1300 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, one or more low-speed buffers, a high-speed buffer, and a controller that controls the operation of the memory device. In response to receiving an input, the I / O connection may transfer an input command / address signal to one or more low-speed buffers and an input data signal to a high-speed buffer, respectively. In some embodiments, the I / O connection may simultaneously receive command signals, address signals, and data signals and may simultaneously send the command, address, and data signals to different destinations (e.g., different buffers, respectively). At time t1, the controller may enable one or more low-speed buffers and perform address and command cycles. The address and command cycles may be performed by the controller simultaneously or in parallel. During the period from t1 to t2, the address and command signals may be sent simultaneously or in parallel from the I / O connection to one or more low-speed buffers. For example, address and command signals may be sent in parallel from an I / O connection to a first slow buffer and a second slow buffer within a period from t1 to t2. The address and command cycle may end at time t2 when one or more slow buffers are disabled. At time t3, the controller may enable the high speed buffers and perform a data input cycle. At time t4, the controller may disable the high speed buffers and end the data input cycle. Thus, the address and command cycle may be performed using the low speed buffers. Also, the high speed buffers may be enabled only when a data input cycle is performed.

[0036] FIG. 14 illustrates a schematic timing diagram 1400 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, one or more low-speed buffers, a high-speed buffer, and a controller that controls the operation of the memory device. In response to receiving an input, the I / O connection may transfer an input command / address signal to one or more low-speed buffers and an input data signal to a high-speed buffer, respectively. In some embodiments, the I / O connection may simultaneously receive command signals, address signals, and data signals and simultaneously transmit command, address, and data signals to different destinations, respectively. At time t1, the controller may enable one or more low-speed buffers and perform a first address cycle and a command cycle. The first address cycle and the command cycle may be performed simultaneously by the controller. The first address cycle and the command cycle may end at time t2, when one or more low-speed buffers are disabled. At time t3, the controller may enable a high-speed buffer and perform a data input cycle. During the period of the data input cycle, the I / O connection may receive an additional address signal. At time t4, the controller may enable one of the one or more slow buffers and perform a second address cycle. Similarly, if additional command signals are received over the I / O connection, additional command cycles may be performed by the controller between t3 and t6. The second address cycle may end at time t5, when one of the one or more slow buffers is disabled. At time t6, the controller may disable the high speed buffers and terminate the data input cycle. Thus, address and command cycles may be performed using the low speed buffers. Additionally, the high speed buffers may be enabled only when a data input cycle is performed.

[0037] 15 shows a schematic flow chart 1500 illustrating a method for buffering an input signal in a memory device according to an embodiment of the present disclosure. The memory device may include a controller, an I / O interface, a low speed buffer, and a high speed buffer. The controller controls the operation of the memory device.

[0038] At 1510, the I / O interface receives an input. The input may include command signals, address signals, and data signals. The I / O interface may receive the signals sequentially or in parallel. At 1520, the I / O interface detects the command signals, address signals, and data signals from the input.

[0039] At 1530, the I / O interface sends the command / address signals to the slow buffer. Alternatively, the controller may prompt the I / O interface to send the command / address signals to the slow buffer. In some embodiments, the I / O interface may send the command signals to the slow buffer and the controller may execute one or more command cycles in one period. The I / O interface may send the address signals to the slow buffer and the controller may execute one or more address cycles in another period. When a command or address cycle is executed, the slow buffer is enabled and used to buffer the command or address signal. In some cases, when a command or address cycle is executed, only the slow buffer is used to buffer the command or address signal.

[0040] At 1540, the I / O interface sends the data signal to the high speed buffer. Alternatively, the controller may prompt the I / O interface to send the data signal to the high speed buffer. In some embodiments, the I / O interface may send the data signal to the high speed buffer and the controller may perform one or more data input cycles in a period of time. When a data input cycle is performed, the high speed buffer is enabled and used to buffer the data signal. In some embodiments, the high speed buffer may be enabled only when a data input cycle is performed.

[0041] 16 shows a schematic flow chart 1600 for illustrating a method for buffering an input signal in a memory device according to an embodiment of the present disclosure. The memory device may include a controller, an I / O interface, a low speed buffer, and a high speed buffer. The controller controls the operation of the memory device.

[0042] At 1610, the I / O interface receives input. The input may include command signals, address signals, and data signals. The I / O interface passes the command and address signals to a low speed buffer and passes the data signals to a high speed buffer.

[0043] At 1620, the controller enables the low-speed buffer and executes command and address cycles to buffer the command / address signals. After the low-speed buffer is enabled, for example, the controller executes the command cycle and then the address cycle. That is, the command and address cycles may be executed sequentially. Alternatively, the command and address cycles may be executed in parallel, that is, the command and address cycles may be performed in the same period. In some embodiments, the command and / or address cycles may be initiated only when the low-speed buffer is enabled. In some cases, the command and / or address cycles need only be executed through the low-speed buffer.

[0044] At 1630, the controller enables the high-speed buffer and performs a data input cycle to buffer the data signal. In some embodiments, the controller activates the high-speed mode and enables the high-speed buffer when the CE_n / CLE / ALE / DQS_t signal is low. After the high-speed buffer is enabled, the controller may perform one or more data input cycles. The command or address cycle and the data input cycle may be performed sequentially. For example, during a first period, a command cycle or an address cycle may be performed. During a second period after the end of the first period, a data input cycle may be performed. Alternatively, the command or address cycle and the data input cycle may be performed in parallel. For example, during a first period, a command cycle or an address cycle may be performed. During a second period that overlaps with the first period, a data input cycle may be performed. In some embodiments, the high-speed buffer may be enabled only when a data input cycle is performed.

[0045] Thus, a low speed buffer and a high speed buffer may be used to buffer the input signals. The command / address signals may be sent to the low speed buffer. The data signals may be sent to the high speed buffer. The active power and static power may be reduced compared to when high speed buffers are used to buffer the command, address, and data signals.

[0046] Although the principle and implementation of the present disclosure have been described by using the specific embodiments herein, the above description of the embodiments is merely intended to facilitate understanding of the present disclosure. In addition, the features of the above different embodiments may be combined to form additional embodiments. Those skilled in the art may make modifications to the specific implementation and scope of application according to the spirit of the present disclosure. Therefore, the contents of this specification should not be interpreted as limitations of the present disclosure.

[0047] [1] A method for operating a memory device, comprising: receiving input via an input / output (I / O) component, the input including command signals, address signals, and data signals; sending the command signal or the address signal to a low speed buffer; and transmitting the data signal to a high speed buffer. [2] The method according to [1], further comprising the step of transmitting the command signal or the address signal only to the low speed buffer. [3] enabling the low speed buffer; The method of claim 1, further comprising the steps of: performing a command cycle and buffering the command signal using the low-speed buffer; or performing an address cycle and buffering the address signal using the low-speed buffer. [4] The method according to [3], further comprising the step of performing the command cycle using only the low speed buffer or performing the address cycle using only the low speed buffer. [5] enabling the high speed buffer; and performing a data input cycle and buffering the data signal using the high speed buffer. [6] The method according to [5], wherein the high speed buffer is enabled only when the data input cycle is performed. [7] The method according to [1], wherein the step of sending the command signal or the address signal to the low speed buffer and the step of sending the data signal to the high speed buffer are performed sequentially. [8] The method according to [1], wherein the step of sending the command signal or the address signal to the low speed buffer and the step of sending the data signal to the high speed buffer are performed in parallel. [9] The method of [1], further comprising the step of initiating an idle mode only when the high speed buffer is disabled.

[10] The method of [1], further comprising the step of detecting the command signal, the address signal, and / or the data signal from the input.

[11] The method of [1], wherein the high speed buffer is faster than the low speed buffer by a predetermined factor.

[12] A memory device, comprising: an input / output (I / O) component for receiving inputs, the inputs including command signals, address signals, and data signals; a low speed buffer for buffering the command signal or the address signal; a high speed buffer for buffering the data signal; A memory device, wherein the I / O component is adaptable to transmit the command signals or the address signals to the low speed buffer and to transmit the data signals to the high speed buffer.

[13] a controller for controlling the memory device, coupled to the I / O components; Sending the command signal or the address signal only to the low speed buffer; The memory device of

[12] , further comprising a controller configured to send the data signal only to the high-speed buffer.

[14] The controller, Enabling the slow buffer; The memory device of

[13] , further configured to: perform command cycles and buffer the command signals using the low-speed buffer; or perform address cycles and buffer the address signals using the low-speed buffer.

[15] The controller, The memory device of

[14] , further configured to execute the command cycle using only the low speed buffer or to execute the address cycle using only the low speed buffer.

[16] The controller, Enabling the high speed buffer; The memory device of

[13] , further configured to perform a data input cycle and buffer the data signal using the high-speed buffer.

[17] The memory device according to

[16] , wherein the high-speed buffer is enabled only when the data input cycle is executed.

[18] The controller, The memory device of

[13] , further configured to control the memory device to enter an idle mode only when the high-speed buffer is disabled.

[19] The memory device of

[12] , further comprising an input buffer control for detecting the command signal, the address signal, and / or the data signal from the input.

[20] The memory device of

[12] , further comprising a three-dimensional (3D) NAND memory device.

[21] The memory device of

[12] , wherein the high speed buffer is faster than the low speed buffer by a predetermined factor.

[22] A method for operating a memory device, comprising: receiving inputs including command signals, address signals, and data signals; enabling a low speed buffer and using the low speed buffer to perform command cycles to buffer the command signals or to perform address cycles to buffer the address signals; enabling a high speed buffer and performing a data input cycle to buffer the high speed signal using the high speed buffer.

[23] The method according to

[22] , further comprising the step of executing the command cycle or the address cycle using only the low speed buffer.

[24] The method according to

[22] , further comprising the step of transmitting the command signal or the address signal only to the low speed buffer.

[25] The method according to

[22] , further comprising the step of transmitting the data signal to the high speed buffer.

[26] The method of

[22] , wherein the high speed buffer is enabled only when the data input cycle is performed.

[27] The method according to

[22] , wherein the command cycle or the address cycle and the data input cycle are executed sequentially.

[28] The method according to

[22] , wherein the command cycle or the address cycle and the data input cycle are executed in parallel.

[29] The method of

[22] , further comprising the step of initiating an idle mode only when the high speed buffer is disabled.

[30] The method of

[22] , further comprising the step of detecting the command signal, the address signal, and / or the data signal from the input.

[31] The method of

[22] , wherein the high speed buffer is faster than the low speed buffer by a predetermined factor. [Explanation of symbols]

[0048] 100 3D Memory Devices 110 Memory Array Device 120 Peripheral Devices 200 3D memory devices 210 Memory Array 212 Control circuit 214 Input / Output (I / O) Interface 216 Slow Buffer 218 High Speed ​​Buffer 220 Line Decoder 222 Column Decoder 300 Block Diagram 310 Current Mode Logic (CML) Buffer 312 Amplifier 314 Deserializer 316 Amplifier 500 Outline timing diagram 600 Outline timing diagram 700 Block diagram 710 High Speed ​​Buffer 712 Slow Buffer 714 Input Buffer Control 716 Reference Bias 718 High Speed ​​Deserializer 720 Command / Address Latch 800 Outline timing diagram 900 Outline timing diagram 1000 Outline timing diagram 1100 Outline timing diagram 1200 Outline timing diagram 1300 Outline timing diagram 1400 Outline timing diagram 1500 Outline Flowchart 1600 Outline Flowchart

Claims

1. 1. A memory device comprising: An input / output (I / O) interface; a first buffer and a second buffer coupled to the I / O interface; coupled to the I / O interface, in response to receiving a command signal or an address signal from the I / O interface, enabling the first buffer to perform a command cycle or an address cycle; In response to receiving a data signal from the I / O interface, enabling the second buffer to perform data cycles at a faster rate than the command cycles or the address cycles performed by the first buffer. an input buffer controller configured to A memory device comprising:

2. The input buffer controller includes: Activating the first buffer and at a different time activating the second buffer. The memory device of claim 1 further configured as follows:

3. The input buffer controller includes: in response to receiving the command signal from the I / O interface, enabling the first buffer to execute the command cycle; In response to receiving the address signal from the I / O interface, the first buffer is enabled to perform the address cycle. The memory device of claim 1 further configured as follows:

4. The second buffer comprises: Buffering the data signal when enabled by the input buffer controller The memory device of claim 1 configured as follows:

5. The input buffer controller includes: Enabling an idle mode only when the second buffer is invalidated. The memory device of claim 1 further configured as follows:

6. a command / address latch coupled to the first buffer; The memory device of claim 1 further comprising:

7. a deserializer coupled to the second buffer; The memory device of claim 1 further comprising:

8. a third buffer coupled to the I / O interface, the input buffer controller further comprising: The first buffer is enabled to execute the command cycle, and at the same time, the third buffer is enabled to execute the address cycle. The memory device of claim 1 further configured as follows:

9. 1. A memory device comprising: a memory array comprising an array of memory cells; a peripheral circuit coupled to the memory array, An input / output (I / O) interface; a first buffer and a second buffer coupled to the I / O interface; coupled to the first buffer and the second buffer; in response to receiving a command signal or an address signal from the I / O interface, enabling the first buffer to perform a command cycle or an address cycle; In response to receiving a data signal from the I / O interface, enabling the second buffer to perform a data cycle at a faster rate than the command cycle or the address cycle performed by the first buffer to transfer data to the array of memory cells. an input buffer controller configured to A peripheral circuit comprising: A memory device comprising:

10. The input buffer controller includes: Activating the first buffer and at a different time activating the second buffer. The memory device of claim 9 further configured to:

11. The input buffer controller includes: in response to receiving the command signal from the I / O interface, enabling the first buffer to execute the command cycle; In response to receiving the address signal from the I / O interface, the first buffer is enabled to perform the address cycle. The memory device of claim 9 further configured to:

12. a third buffer coupled to the I / O interface, the input buffer controller further comprising: The first buffer is enabled to execute the command cycle, and at the same time, the third buffer is enabled to execute the address cycle. The memory device of claim 9 further configured to:

13. 1. A method of operating a memory device, comprising: in response to receiving a command signal or an address signal, enabling a first buffer to perform a command cycle or an address cycle; in response to receiving a data signal, enabling a second buffer to perform data cycles at a faster rate than the command or address cycles performed by the first buffer; A method comprising:

14. performing at least one address cycle with the first buffer prior to performing the data cycle with the second buffer; disabling the first buffer before enabling the second buffer; The method of claim 13 further comprising:

15. in response to receiving the command signal from an input / output (I / O) interface, enabling the first buffer to execute the command cycle; in response to receiving the address signal from the I / O interface, enabling the first buffer to perform the address cycle; The method of claim 13 further comprising:

16. performing said command cycle using said first buffer and performing said address cycle using said first buffer at a different time. The method of claim 13 further comprising:

17. performing the data cycle using the second buffer to buffer the data signal; The method of claim 13 further comprising:

18. 14. The method of claim 13, wherein the second buffer is enabled only when the data cycle is performed.

19. Enabling an idle mode only when the second buffer is disabled. The method of claim 13 further comprising:

20. enabling the first buffer to execute the command cycle; simultaneously enabling a third buffer to execute said address cycle; The method of claim 13 further comprising:

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