Power-supply voltage monitoring apparatus and power-supply voltage monitoring method

Abstract

To properly execute reset processing at the start of power supply without fuse trimming.SOLUTION: A power-supply voltage monitoring apparatus 10 includes: a first power-supply voltage monitoring circuit 11 which generates a reference voltage inside and outputs a first reset signal; a second power-supply voltage monitoring circuit 12 which acquires the reference voltage from the outside and outputs a second reset signal; and a selector 14 which is connected to the first power-supply voltage monitoring circuit 11 and the second power-supply voltage monitoring circuit 12. The selector 14 selects one of the first and second reset signals on the basis of a deep sleep control signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power supply voltage monitoring device and a power supply voltage monitoring method. [Background technology]

[0002] For example, Patent Document 1 describes a power supply voltage monitoring circuit that can be used with a low power supply voltage. This power supply voltage monitoring circuit has an input terminal, an output terminal, a ground terminal, a voltage dividing circuit including resistors that generate a divided voltage from a power supply voltage applied to the input terminal, a reference voltage source that generates a reference voltage based on the power supply voltage, a regulator voltage source that generates a regulator voltage higher than the reference voltage based on the power supply voltage, a comparator that uses the regulator voltage as a driving source and compares the reference voltage with the divided voltage to generate a first binary output signal, a first switching means responsive to the comparator, and a second binary conversion means that uses the reference voltage as a driving source and responds to the divided voltage. The first switching means outputs a binary power supply voltage monitoring output signal that monitors the magnitude of the power supply voltage to an output terminal based on a logic operation output signal generated by a logic operation between the first binary output signal and the second binary output signal.

[0003] Generally, LSIs (Large Scale Integration) have a power supply voltage monitoring circuit that outputs a reset signal when the power supply voltage falls below a specified level to prevent malfunction at low voltages. This type of LSI also has a sleep mode to reduce current consumption during intermittent operation, and the current consumption during sleep mode is usually several μA. There is also a deep sleep mode that reduces current consumption to 1 μA or less, and the current consumption required for the power supply voltage monitoring circuit during deep sleep mode is several tens of nA, requiring a power supply voltage monitoring circuit with extremely low power consumption.

[0004] A conventional extremely low power consumption power supply voltage monitoring device will be described with reference to FIGS.

[0005] 4 is a block diagram showing the configuration of a conventional power supply voltage monitoring device 100. The power supply voltage monitoring device 100 includes a first power supply voltage monitoring circuit 101 and a fuse 102. The first power supply voltage monitoring circuit 101 includes a reference voltage generating unit 101A that generates a reference voltage that serves as a reset determination voltage. The power supply voltage monitoring device 100 is connected to a logic circuit 103.

[0006] When the power supply voltage is less than the reset determination voltage of the first power supply voltage monitoring circuit 101, the power supply voltage monitoring device 100 resets the logic circuit 103, and when the power supply voltage is equal to or greater than the reset determination voltage, the power supply voltage monitoring device 100 releases the reset of the logic circuit 103. Furthermore, the first power supply voltage monitoring circuit 101 is previously adjusted by the fuse 102 in a test process so that the variation in the reset determination voltage is reduced;

[0007] 5 is a flowchart showing the flow of power supply voltage monitoring processing by the conventional power supply voltage monitoring device 100. Note that it is assumed that fuse trimming has already been performed on the power supply voltage monitoring device 100.

[0008] 5, the first power supply voltage monitoring circuit 101 performs a reset process on the logic circuit 103 after power supply startup. After power supply startup, the output of the first power supply voltage monitoring circuit 101 becomes "Low," and the first power supply voltage monitoring circuit 101 outputs a reset signal to the logic circuit 103, thereby resetting the logic circuit 103.

[0009] In step S112, the first power supply voltage monitoring circuit 101 judges whether the power supply voltage that increases thereafter is less than the reset judgment voltage, that is, whether a reset has occurred. If it is judged to be a reset (if the judgment is positive), the process returns to step S111, and if it is judged not to be a reset (if the judgment is negative), the process proceeds to step S113.

[0010] In step S113, the first power supply voltage monitoring circuit 101 continues to monitor the power supply voltage, and the process proceeds to step S112 to repeat the process. When the power supply voltage becomes equal to or higher than the reset determination voltage, the output of the first power supply voltage monitoring circuit 101 changes from "Low" to "High," and the logic circuit 103 is released from the reset state.

[0011] 6 is a diagram showing the operating waveforms of a conventional power supply voltage monitoring device 100. (A) shows the waveforms without fuse trimming, with the upper waveform showing the power supply voltage waveform and the lower waveform showing the reset signal (RESET1). (B) shows the waveforms with fuse trimming, with the upper waveform showing the power supply voltage waveform and the lower waveform showing the reset signal (RESET1).

[0012] As shown in FIG. 6, in the case of (A) without fuse trimming, the variation Δr in the reset determination voltage is larger than in the case of (A) with fuse trimming, so there is a possibility that the logic circuit 103 may be released from reset when the power supply voltage is low.

[0013] If the reset is released while the power supply voltage is low as described above, the reset process for the logic circuit 103 may not be performed correctly.

[0014] On the other hand, in the case of (B) where fuse trimming is performed, the variation Δr in the reset determination voltage is adjusted by the fuse 102 so as to be small, and it becomes possible to perform the reset process on the logic circuit 103 correctly. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] JP 2019-184333 A Summary of the Invention [Problem to be solved by the invention]

[0016] In conventional ultra-low power supply voltage monitoring devices, the reset decision voltage fluctuates greatly due to manufacturing and temperature variations, and there are cases where the POR (Power On Reset), i.e., the reset process, cannot be performed correctly when the power supply is turned on. Therefore, it is necessary to use fuse trimming to suppress the fluctuation due to manufacturing variations in advance in the test process, which increases the test time, increases the chip area to mount the fuse, and further imposes restrictions such as the need to select a semiconductor process that can use fuses.

[0017] The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide an extremely low power consumption power supply voltage monitoring device and power supply voltage monitoring method that are capable of properly executing reset processing at power-on without performing fuse trimming. [Means for solving the problem]

[0018] In order to solve the above problems, the power supply voltage monitoring device of the present invention comprises a first power supply voltage monitoring circuit that generates a reference voltage internally and outputs a first reset signal, a second power supply voltage monitoring circuit that acquires a reference voltage from an external source and outputs a second reset signal, and a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit, the selector selecting either the first reset signal or the second reset signal based on a deep sleep control signal.

[0019] Furthermore, in order to solve the above-mentioned problems, the power supply voltage monitoring method of the present invention is a power supply voltage monitoring method for a power supply voltage monitoring device comprising a first power supply voltage monitoring circuit that generates a reference voltage internally and outputs a first reset signal, a second power supply voltage monitoring circuit that acquires a reference voltage from the outside and outputs a second reset signal, and a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit, wherein the selector selects either the first reset signal or the second reset signal based on a deep sleep control signal. Effect of the Invention

[0020] According to the present invention, it is possible to appropriately execute a reset process at power-on with extremely low power consumption without performing fuse trimming. [Brief description of the drawings]

[0021] [Figure 1] 1 is a block diagram showing an example of a configuration of a power supply voltage monitoring device according to an embodiment; [Diagram 2] 4 is a flowchart showing an example of the flow of a power supply voltage monitoring process performed by the power supply voltage monitoring device according to the embodiment. [Diagram 3] 3 is a diagram showing an example of an operational waveform of the power supply voltage monitoring device according to the embodiment; [Figure 4] FIG. 1 is a block diagram showing a configuration of a conventional power supply voltage monitoring device. [Diagram 5] 1 is a flowchart showing a flow of a power supply voltage monitoring process performed by a conventional power supply voltage monitoring device. [Figure 6] 1 is a diagram showing operational waveforms of a conventional power supply voltage monitoring device; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, an example of an embodiment for implementing the technology of the present invention will be described in detail with reference to the drawings. Note that components and processes that perform the same operation, action, and function may be given the same reference numerals throughout all the drawings, and duplicated explanations may be omitted as appropriate. Each drawing is merely a schematic illustration to the extent that the technology of the present invention can be fully understood. Therefore, the technology of the present invention is not limited to only the illustrated examples. In addition, in this embodiment, explanations of configurations that are not directly related to the present invention or well-known configurations may be omitted.

[0023] FIG. 1 is a block diagram showing an example of the configuration of a power supply voltage monitoring device 10 according to this embodiment.

[0024] 1, a power supply voltage monitoring device 10 according to this embodiment includes a first power supply voltage monitoring circuit 11, a second power supply voltage monitoring circuit 12, a register 13, and a selector 14. The power supply voltage monitoring device 10 is connected to a logic circuit 15.

[0025] The first power supply voltage monitoring circuit 11 generates a reference voltage internally and outputs a first reset signal. The first power supply voltage monitoring circuit 11 includes a reference voltage generating unit 11A and generates a reference voltage internally. The reference voltage is a voltage that serves as a reset determination voltage. The first power supply voltage monitoring circuit 11 is a circuit with a large manufacturing variation and a small current consumption compared to the second power supply voltage monitoring circuit 12. In other words, the first power supply voltage monitoring circuit 11 is a circuit with a large variation in the reset determination voltage and a small current consumption compared to the second power supply voltage monitoring circuit 12. The first power supply voltage monitoring circuit 11 operates during a deep sleep period. The first power supply voltage monitoring circuit 11 adjusts the variation in the reset determination voltage used to determine whether or not to output the first reset signal to a small value by the register 13. The register 13 is, for example, a memory circuit configured with a flip-flop.

[0026] The second power supply voltage monitoring circuit 12 obtains a reference voltage from the outside and outputs a second reset signal. The second power supply voltage monitoring circuit 12 is a circuit with smaller manufacturing variations and larger current consumption than the first power supply voltage monitoring circuit 11. In other words, the second power supply voltage monitoring circuit 12 is a circuit with smaller variations in reset determination voltage and larger current consumption than the first power supply voltage monitoring circuit 11. The second power supply voltage monitoring circuit 12 operates during periods other than the deep sleep period. Specifically, the second power supply voltage monitoring circuit 12 operates, for example, at power start-up or in a steady state.

[0027] The selector 14 is connected to the first power supply voltage monitoring circuit 11 and the second power supply voltage monitoring circuit 12. The selector 14 selects either the first reset signal or the second reset signal based on the deep sleep control signal. Specifically, the selector 14 outputs the second reset signal to the logic circuit 15 in the reset process at power startup, and outputs the first reset signal to the logic circuit 15 in the reset process during the deep sleep period. The deep sleep control signal is a control signal for instructing a transition to the deep sleep mode, and is transmitted from a higher-level device (not shown). The deep sleep mode is one of the operation modes of the device, and is a mode that suppresses power consumption by restricting more functions than the sleep mode, which stops some functions when no operation is performed.

[0028] FIG. 2 is a flowchart showing an example of the flow of power supply voltage monitoring processing by the power supply voltage monitoring device 10 according to this embodiment.

[0029] 2, the second power supply voltage monitoring circuit 12 performs a reset process on the logic circuit 15 after power is turned on. The output of the second power supply voltage monitoring circuit 12 becomes "Low" after power is turned on, and the second reset signal is output to the logic circuit 15 via the selector 14, thereby resetting the logic circuit 15. Since the second power supply voltage monitoring circuit 12 has a small variation in the reset determination voltage, it is possible to perform the reset process correctly without releasing the reset at a low power supply voltage. On the other hand, the second power supply voltage monitoring circuit 12 consumes a relatively large current, but at the time of power supply startup, unlike during deep sleep, a slightly large current consumption does not cause a problem.

[0030] In step S102, the second power supply voltage monitoring circuit 12 judges whether the power supply voltage that increases thereafter is less than the reset judgment voltage, that is, whether a reset has occurred. If it is judged to be a reset (if the judgment is positive), the process returns to step S101, and if it is judged not to be a reset (if the judgment is negative), the process proceeds to step S103.

[0031] In step S103, the second power supply voltage monitoring circuit 12 continues to monitor the power supply voltage. After the power supply voltage reaches a steady state, the first power supply voltage monitoring circuit 11 trims the reset determination voltage by the register 13, and adjusts the reset determination voltage so that the variation therein is reduced.

[0032] In step S104, the selector 14 judges whether or not the deep sleep control signal has been received. If it is judged that the deep sleep control signal has been received (if the judgment is positive), the process proceeds to step S105, and if it is judged that the deep sleep control signal has not been received (if the judgment is negative), the process returns to step S102 and repeats the process.

[0033] In step S105, in order to switch to the deep sleep mode, the selector 14 switches the reset signal to be connected to the logic circuit 15 from the second reset signal of the second power supply voltage monitoring circuit 12 to the first reset signal of the first power supply voltage monitoring circuit 11. Then, the first power supply voltage monitoring circuit 11 monitors the power supply voltage in the deep sleep mode in a state in which the variation in the reset determination voltage is adjusted to be small.

[0034] In step S106, the first power supply voltage monitoring circuit 11 judges whether the power supply voltage in the deep sleep mode is less than the reset judgment voltage, that is, whether a reset has occurred. If it is judged to be a reset (if the judgment is positive), the process returns to step S101, and if it is judged not to be a reset (if the judgment is negative), the process proceeds to step S107.

[0035] In step S107, the selector 14 judges whether or not the deep sleep control signal has been received. If it is judged that the deep sleep control signal has been received (if the judgment is positive), the process proceeds to step S105, and if it is judged that the deep sleep control signal has not been received (if the judgment is negative), the process returns to step S102 and repeats the process.

[0036] 3 is a diagram showing an example of the operating waveforms of the power supply voltage monitoring device 10 according to this embodiment. (A) shows the waveform before the register is set, the upper waveform shows the waveform of the power supply voltage, the middle waveform shows the waveform of the first reset signal (RESET1), and the lower waveform shows the waveform of the second reset signal (RESET2). (B) shows the waveform after the register is set, the upper waveform shows the waveform of the power supply voltage, the middle waveform shows the waveform of the first reset signal (RESET1), and the lower waveform shows the waveform of the second reset signal (RESET2).

[0037] As shown in FIG. 3, the supply voltage monitoring device 10 according to this embodiment uses a resistor 13 that can be set from an external terminal instead of a fuse, to adjust the variation in the reset determination voltage of the first supply voltage monitoring circuit 11 to be small.

[0038] In the case of (A) before the register is set, the variation Δr1 in the reset determination voltage of the first supply voltage monitoring circuit 11 is large, and the variation Δr2 in the reset determination voltage of the second supply voltage monitoring circuit 12 is small.

[0039] On the other hand, in the case of (B) after the register setting, the variation Δr1 of the reset determination voltage of the first power supply voltage monitoring circuit 11 is adjusted to a small variation Δr2, making it possible to correctly perform the reset process on the logic circuit 103. In this example, the variation Δr2 of the reset determination voltage of the second power supply voltage monitoring circuit 12 is smaller than the variation Δr1 and does not change before and after the register setting. Also, the variation Δr1 of the reset determination voltage of the first power supply voltage monitoring circuit 11 only needs to be adjusted to be smaller than the variation Δr1, and is not limited to the variation Δr2.

[0040] As described above, in conventional configurations, fuse trimming was required to properly perform reset processing when the power supply was started up. However, in this embodiment, by providing a second power supply voltage monitoring circuit, fuse trimming is no longer necessary, and reset processing can be properly performed when the power supply was started up.

[0041] It is to be noted that the configurations of the power supply voltage monitoring device and power supply voltage monitoring method described in the above embodiments are merely examples, and it goes without saying that the configurations may be changed without departing from the spirit of the embodiments.

[0042] The following supplementary notes are further disclosed regarding the above embodiment.

[0043] (Appendix 1) a first power supply voltage monitoring circuit that internally generates a reference voltage and outputs a first reset signal; a second power supply voltage monitoring circuit that obtains a reference voltage from an external source and outputs a second reset signal; a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit, the selector selecting either the first reset signal or the second reset signal based on a deep sleep control signal; A power supply voltage monitoring device comprising: (Appendix 2) the selector outputs the second reset signal to the logic circuit in a reset process at power-on, and outputs the first reset signal to the logic circuit in a reset process during a deep sleep period. 2. A power supply voltage monitoring device as claimed in claim 1. (Appendix 3) the first power supply voltage monitoring circuit operates during the deep sleep period; The second power supply voltage monitoring circuit operates during a period other than the deep sleep period. 3. A power supply voltage monitoring device according to claim 1 or 2. (Appendix 4) A register is further provided, the first power supply voltage monitoring circuit adjusts, by the register, a variation in a reset determination voltage used for determining whether or not to output the first reset signal; 4. A power supply voltage monitoring device according to claim 1. (Appendix 5) a first power supply voltage monitoring circuit that internally generates a reference voltage and outputs a first reset signal; a second power supply voltage monitoring circuit that obtains a reference voltage from an external source and outputs a second reset signal; a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit; A power supply voltage monitoring method for a power supply voltage monitoring device comprising: The selector: selecting one of the first reset signal and the second reset signal based on a deep sleep control signal; Power supply voltage monitoring method. [Explanation of symbols]

[0044] 10 Power supply voltage monitoring device 11 First power supply voltage monitor circuit 11A Reference voltage generator 12 Second power supply voltage monitor circuit 13 Registers 14 Selectors 15 Logic Circuits

Claims

1. a first power supply voltage monitoring circuit that internally generates a reference voltage and outputs a first reset signal; a second power supply voltage monitoring circuit that obtains a reference voltage from an external source and outputs a second reset signal; a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit, the selector selecting either the first reset signal or the second reset signal based on a deep sleep control signal; A power supply voltage monitoring device comprising:

2. the selector outputs the second reset signal to the logic circuit in a reset process at power-on, and outputs the first reset signal to the logic circuit in a reset process during a deep sleep period.

2. The power supply voltage monitoring device according to claim 1.

3. the first power supply voltage monitoring circuit operates during the deep sleep period; the second power supply voltage monitoring circuit operates outside the deep sleep period; 3. The power supply voltage monitoring device according to claim 1.

4. A register is further provided, the first power supply voltage monitoring circuit adjusts, by the register, a variation in a reset determination voltage used for determining whether or not to output the first reset signal; 3. The power supply voltage monitoring device according to claim 1.

5. a first power supply voltage monitoring circuit that internally generates a reference voltage and outputs a first reset signal; a second power supply voltage monitoring circuit that obtains a reference voltage from an external source and outputs a second reset signal; a selector connected to the first power supply voltage monitoring circuit and the second power supply voltage monitoring circuit; A power supply voltage monitoring method for a power supply voltage monitoring device comprising: The selector: selecting one of the first reset signal and the second reset signal based on a deep sleep control signal; Power supply voltage monitoring method.

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