Memory system and control method thereof

Abstract

To provide a memory system and its control method which can improve reliability.SOLUTION: A memory system includes a memory device having a plurality of memory cells, and a memory controller. The memory controller measures the number of error bits of data read out from the plurality of memory cells, so as to control a write distribution interval in a threshold voltage distribution of the plurality of memory cells on the basis of the measured number of error bits.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present embodiment relates to a memory system and a control method thereof. [Background technology]

[0002] There is a storage device equipped with a memory device including a plurality of memory cells. As the capacity of storage devices has increased in recent years, the amount of data that can be stored in one memory cell has been increased by increasing the number of values. One example of increasing the number of values ​​is data storage using a QLC (Quad-Level Cell). However, in QLC, the threshold voltage of each memory cell after writing is one of 16 values, resulting in a narrower threshold voltage distribution. Changes in the threshold voltage distribution due to stress on the memory cell cause a problem of reduced reliability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0143821 [Patent Document 2] U.S. Patent No. 8,995,197 [Patent Document 3] Patent No. 5410507 Summary of the Invention [Problem to be solved by the invention]

[0004] A memory system capable of improving reliability and a control method thereof are provided. [Means for solving the problem]

[0005] The memory system according to the present embodiment includes a memory device having a plurality of memory cells, and a memory controller, which measures the number of error bits in data read from the plurality of memory cells, and controls a write distribution interval in the threshold voltage distribution of the plurality of memory cells based on the measured number of error bits. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of an information processing system according to a first embodiment. [Diagram 2] 2 is a block diagram showing the configuration of a memory unit according to the first embodiment. FIG. [Diagram 3] 1 is a circuit diagram showing a configuration of a memory cell array according to a first embodiment. [Figure 4] FIG. 2 is a block diagram showing the functional configuration of a CPU according to the first embodiment. [Diagram 5] 3 is a block diagram showing the contents stored in a ROM according to the first embodiment; FIG. [Figure 6] FIG. 4 is a diagram showing threshold voltage distributions of memory cells according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing the number of error bits in a memory cell according to the first embodiment. [Figure 8] 11 is a graph showing the number of error bits in memory cells for each word line according to the first embodiment. [Figure 9] 4 is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 10] FIG. 4 is a diagram showing the contents of a parameter list according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions among the threshold voltage distributions in the Er state to the G state according to the first embodiment is increased. [Figure 12] FIG. 11 is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions among the threshold voltage distributions in the Er state to the G state according to the first embodiment is reduced. [Figure 13]FIG. 4 is a diagram showing the contents of a setting table according to the first embodiment. [Figure 14] 4 is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 15] 4 is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 16] FIG. 11 is a block diagram showing the configuration of a memory according to a second embodiment. [Figure 17] 10 is a flowchart showing the operation of the memory system according to the second embodiment. [Figure 18] FIG. 11 is a diagram showing the contents of a setting table according to the second embodiment. [Figure 19] 10 is a flowchart showing the operation of the memory system according to the second embodiment. [Figure 20] 10 is a flowchart showing the operation of the memory system according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] (First embodiment) FIG. 1 is a block diagram showing the configuration of an information processing system according to the first embodiment.

[0009] The information processing system of the first embodiment includes a memory system 1 and a host device 2. The memory system 1 is, for example, a memory card, a universal flash storage (UFS), or a solid state drive (SSD). The memory system 1 functions as, for example, an external storage device for the host device 2. The host device 2 is an information processing device. The host device 2 is, for example, a personal computer, a server device, or a mobile device. The host device 2 can issue access requests (read requests, write (program) requests, and erase requests) to the memory system 1.

[0010] The memory system 1 includes a memory controller 11 and a memory 12 .

[0011] The memory controller 11 is a semiconductor device that controls the memory 12. The memory controller 11 controls various operations of the memory system 1. For example, the memory controller 11 controls reading of data from the memory 12 based on a received read request. The memory controller 11 also controls writing of data to the memory 12 based on a received write request. The memory controller 11 also controls erasing of data from the memory 12 based on a received erase request.

[0012] The memory 12 (memory device) includes a plurality of memory cells. The memory 12 is, for example, a binary memory. A binary memory is a memory capable of storing two types of values ​​in each memory cell. Alternatively, the memory 12 is, for example, a multi-value memory. A multi-value memory is a memory capable of storing more than two types of values ​​in each memory cell. For example, when the memory 12 is a 16-value memory, each memory cell can store 16 types of values. The 16 types of values ​​include, for example, values ​​from 0 to 15 (0000 to 1111 in binary).

[0013] The memory controller 11 includes a central processing unit (CPU) 11a, a random access memory (RAM) 11b, a read only memory (ROM) 11c, an error correcting code (ECC) circuit 11d, a memory interface (I / F) controller 11e, and a host interface controller 11f. The memory controller 11 may further include a storage device in which software is stored.

[0014] The CPU 11a is a processor that executes various programs.

[0015] The RAM 11b is a volatile memory from which data can be read and written, and provides a work area for the CPU 11a.

[0016] The ROM 11c is a memory from which data can be read and stores various data necessary for the operation of the CPU 11a.

[0017] The ECC circuit 11d is a circuit that performs processing related to error correction. When data (write data) is written to the memory 12, the ECC circuit 11d encodes the write data. Encoding the write data means adding an error correction code to the write data. Furthermore, when data is read from the memory 12, the ECC circuit 11d corrects errors contained in the read data based on the error correction code.

[0018] The memory I / F controller 11e is a circuit that manages the interface between the memory controller 11 and the memory 12. The memory I / F controller 11e controls data transfer between the memory controller 11 and the memory 12 under the control of the CPU 11a.

[0019] The host I / F controller 11f is a circuit that manages the interface between the memory controller 11 and the host device 2. The host I / F controller 11f controls data transfer between the memory controller 11 and the host device 2 under the control of the CPU 11a.

[0020] The memory 12 includes one or more memory units 12a. FIG. 1 shows, as an example, a case where the memory 12 includes three memory units 12a. The memory unit 12a is a memory chip or a memory die. The memory unit 12a includes a memory cell array including a plurality of memory cells. The memory cell array functions as a memory area capable of storing data. Details of the memory cell array will be described later. The memory 12 is, for example, a NAND type flash memory.

[0021] FIG. 2 is a block diagram showing the configuration of the memory unit 12a according to the first embodiment.

[0022] Each memory unit 12a in this embodiment includes an I / O (Input / Output) signal processing circuit 31, a control signal processing circuit 32, a chip control circuit 33, a RY / BY generation circuit 34, a command register 35, an address register 36, a row decoder 41, a column decoder 42, a data register 43, a sense amplifier 44, and a memory cell array 45.

[0023] The I / O signal processing circuit 31 processes input signals to the memory unit 12a and output signals from the memory unit 12a. The I / O signal processing circuit 31 functions as a buffer. The commands, addresses, and data latched by the I / O signal processing circuit 31 are assigned to a command register 35, an address register 36, and a data register 43, respectively.

[0024] The control signal processing circuit 32 processes the control signal to the memory unit 12a. The control signal processing circuit 32 controls the above-mentioned allocation by the I / O signal processing circuit 31 based on the control signal to the memory unit 12a. The control signals input to the control signal processing circuit 32 are, for example, a CE (chip enable) signal, a CLE (command latch enable) signal, an ALE (address latch enable) signal, a WE (write enable) signal, a RE (read enable) signal, and a WP (write protect) signal. The control signal processing circuit 32 further transfers the control signal to the chip control circuit 33.

[0025] The chip control circuit 33 controls the memory unit 12a. The chip control circuit 33 controls the operation of the memory unit 12a based on the control signal transferred from the control signal processing circuit 32. The operation of the chip control circuit 33 changes, for example, when the state of the chip control circuit 33 transitions in response to the control signal.

[0026] The RY / BY generation circuit 34 outputs an RY (ready) signal and a BY (busy) signal. The RY / BY generation circuit 34 selectively outputs the RY signal and the BY signal under the control of the chip control circuit 33. The RY signal is output when the memory unit 12a is not in operation (ready state). The BY signal is output when the memory unit 12a is in operation (busy state).

[0027] The command register 35 is a circuit for storing commands. The commands stored in the command register 35 are read out by the chip control circuit 33.

[0028] The address register 36 is a circuit for storing an address. The address stored in the address register 36 is read by the chip control circuit 33, the row decoder 41, and the column decoder 42.

[0029] The row decoder 41 is a circuit that performs control related to the word lines of the memory cell array 45. The row decoder 41 applies a voltage to the word lines of the memory cell array 45 based on a row address read from the address register .

[0030] The column decoder 42 is a circuit that controls the latch circuits of the data register 43. The column decoder 42 selects a latch circuit of the data register 43 based on a column address read from the address register 36.

[0031] The data register 43 is a circuit for storing data. The data register 43 stores data from the I / O signal processing circuit 31 and data from the sense amplifier 44.

[0032] The sense amplifier 44 is a circuit that performs operations related to the bit lines of the memory cell array 45. The sense amplifier 44 detects data read out to the bit lines of the memory cell array 45. The row decoder 41, the column decoder 42, the data register 43, and the sense amplifier 44 function as an interface for read operations, write operations, and erase operations for the memory cell array 45.

[0033] The memory cell array 45 is a region in which a plurality of memory cells are arranged in an array. The memory cell array 45 is, for example, a three-dimensional memory in which memory cells are arranged in a three-dimensional array. The memory cell array 45 functions as a memory region capable of storing data. Further details of the memory cell array 45 will be described later.

[0034] FIG. 3 is a circuit diagram showing a configuration of a memory cell array 45 according to the first embodiment.

[0035] The memory cell array 45 includes a plurality of blocks. Fig. 3 shows a block BLK0 and a block BLK1 as examples of the plurality of blocks. Hereinafter, the configuration of the blocks in this embodiment will be described using the block BLK0. The other blocks including the block BLK1 have the same configuration as the block BLK0.

[0036] The block BLK0 includes a plurality of string units SU0 to SU3. Each of the string units SU0 to SU3 includes p bit lines BL0 to BLp-1, a cell source line CELSRC, and p NAND strings STR (p is an integer equal to or greater than 2). The NAND string STR includes memory cell transistors (memory cells) MT0 to MT15 on the word lines WL0 to WL15, respectively. The NAND string STR also includes selection transistors (selection gates) ST0 and DT0 on the selection lines SGSL0 and SGDL0, respectively. The selection line SGSL0 is called a source side selection line. The selection line SGDL0 is called a drain side selection line. The other NAND strings STR have a similar structure.

[0037] FIG. 4 is a block diagram showing the functional configuration of the CPU 11a according to the first embodiment.

[0038] The CPU 11a includes a main control unit 51, a patrol read execution unit 52, a setting table recording unit 53, and an interval parameter control unit 54. For example, firmware stored in the ROM 11c is expanded in the RAM 11b and executed by the CPU 11a to realize these functions. Also, some of these functions may be realized by dedicated hardware.

[0039] The main control unit 51 receives commands from the host device 2 and transmits the commands to the memory 12. The commands include, for example, program commands or read commands.

[0040] The patrol read execution unit 52 executes a patrol read process of the memory cells. The patrol read process is, for example, a data read process performed to grasp the fluctuation status of the threshold voltage distribution of the written data. The patrol read execution unit (error bit number measurement unit) 52 measures the number of error bits of the data read from the multiple memory cells by the patrol read process. The patrol read execution unit 52 stores the measured number of error bits in the RAM 11b.

[0041] The setting table recording unit 53 converts the measured number of error bits into an adjustment amount of the write distribution interval with reference to a parameter list 61 described later. The write distribution interval is the interval between two adjacent threshold voltage distributions. The threshold voltage indicates a certain data retention state for a plurality of memory cells. The interval between two threshold voltage distributions corresponds to the interval of the threshold voltage distribution between two different data retention states. The adjustment amount of the write distribution interval is an amount indicating the degree of change to the initial setting write distribution interval. The setting table recording unit 53 records the converted adjustment amount of the write distribution interval in a setting table 62 described later. The setting table recording unit (adjustment amount storage control unit) 53 generates an adjustment amount of the write distribution interval based on the measured number of error bits based on the parameter list 61, and records the generated adjustment amount in the setting table 62. The setting table recording unit 53 records the setting of the part where the write distribution interval needs to be adjusted in the setting table 62.

[0042] The interval parameter control unit (distribution interval control unit) 54 adjusts the write distribution interval in the threshold voltage distribution based on the measured number of error bits. The interval parameter control unit 54 also controls the write distribution interval based on the parameter list 61 and the measured number of error bits. The interval parameter control unit 54 sets the adjustment amount of the write distribution interval recorded in the setting table 62 in the memory 12. The write distribution interval is correlated with the reliability of the data stored in the memory cell array 45. The interval parameter control unit 54 sets the write distribution interval wider for a word line with a larger number of error bits. This can improve the reliability of the stored data.

[0043] FIG. 5 is a block diagram showing the contents stored in the ROM 11c according to the first embodiment.

[0044] The ROM 11c stores a parameter list 61 and a setting table 62.

[0045] The parameter list 61 is information including the correspondence between the number of error bits and the adjustment amount of the write distribution interval. The parameter list 61 is set in advance at least before the memory system 1 starts operating.

[0046] The setting table 62 is information for recording the points where the write distribution interval adjustment is performed and the amount of adjustment. The items of the setting table 62 are recorded by the setting table recording unit 53.

[0047] Fig. 6 is a diagram showing an example of threshold voltage distributions of memory cells according to the first embodiment. The vertical axis of Fig. 6 indicates the number of memory cells showing a certain bit value (data value). The horizontal axis of Fig. 6 indicates the threshold voltage of the memory cell. In Fig. 6, multiple threshold voltage distributions are shown so as not to overlap with each other.

[0048] When a memory cell operates in a triple-level cell (TLC) mode, the threshold voltage of the memory cell forms eight threshold voltage distributions. The eight threshold voltage distributions are called, for example, Er state, A state, B state, C state, D state, E state, F state, and G state in order from the lowest threshold voltage. In the TLC mode, each of the threshold voltage distributions of the Er state to the G state is assigned a different 3-bit data.

[0049] Fig. 7 is a diagram showing an example of the number of error bits in a memory cell according to the first embodiment. The vertical axis of Fig. 7 shows the number of memory cells showing a certain bit value (data value). The horizontal axis of Fig. 7 shows the threshold voltage of the memory cell. Fig. 7 shows how the threshold voltage distribution of the A state and the threshold voltage distribution of the B state overlap each other.

[0050] The threshold voltage distributions vary due to various factors and may overlap with each other. The area of ​​the overlapping shaded area determines the number of error bits. The number of error bits between the A state and the B state is determined by the FBC B The number of error bits between any state X and state Y that has a threshold voltage distribution higher than that of state X and is adjacent to the threshold voltage distribution of state X is called FBC. YThat is, the number of error bits between the Er state and the A state is called FBC A The number of error bits between the B and C states is called FBC C The number of error bits between the C and D states is called the FBC D The number of error bits between the D and E states is called the FBC E The number of error bits between the E and F states is called the FBC F The number of error bits between the F and G states is called the FBC G It is called.

[0051] FIG. 8 is a graph showing the number of error bits of memory cells for each word line according to the first embodiment. The vertical axis of FIG. 8 shows the measurement results of the average number of error bits. The horizontal axis of FIG. 8 shows the word line (WL). The ECC correction limit is the number of error bits that is the limit of the correction process by the ECC circuit 11d. In the example shown in FIG. 8, the number of error bits does not exceed the ECC correction limit. However, as shown in FIG. 8, the number of error bits varies from word line to word line.

[0052] Next, the operation of recording in the setting table 62 by the memory system 1 will be described.

[0053] Fig. 9 is a flowchart showing the operation of the memory system 1 according to the first embodiment. Fig. 9 shows the operation of recording in the setting table 62. In the first embodiment, the operation of recording in the setting table 62 starts in response to the execution of a read process for a written block (start).

[0054] An example of a read process for a written block is a patrol read process by the patrol read execution unit 52. The patrol read process is, for example, a data read process performed to grasp the fluctuation status of the threshold voltage distribution of written data. The patrol read process may be performed at regular intervals (for example, once a day). The patrol read process may also be performed each time the number of program / erase operations reaches a predetermined number (for example, 500 times). The frequency of execution of the patrol read process is determined taking into consideration the capacity of the memory 12 and the like. Another example of a read process for a written block is a read process based on a read request from the host device 2. The read process based on a read request from the host device 2 may be performed periodically, for example.

[0055] The patrol read execution unit 52 measures the number of error bits for each state (Er state to G state) for the written block (S10). The patrol read execution unit 52 stores the measured number of error bits in the RAM 11b.

[0056] After storing the measured number of error bits in the RAM 11b, the patrol read executing unit 52 transmits a signal to the setting table recording unit 53 (S20).

[0057] When the setting table recording unit 53 receives a signal from the patrol read executing unit 52, the setting table recording unit 53 reads the measured number of error bits from the RAM 11b (S30).

[0058] The setting table recording unit 53 takes statistics of the number of error bits that have been read out for each word line (S40). The setting table recording unit 53 stores the statistical value of the number of error bits in the RAM 11b.

[0059] After taking statistics on the number of error bits for each word line, the setting table recording unit 53 creates a word line group including multiple word lines (S50). A word line group is a group including multiple word lines having similar numbers of error bits. A word line group may be created in advance. A word line group may also be created by a read process based on a read request from the host device 2.

[0060] The setting table recording unit 53 acquires from the RAM 11b the statistical value of the number of error bits in each state (Er state to G state) for each created word line group (S60).

[0061] The setting table recording unit 53 checks the acquired statistical value of the number of error bits against the parameter list 61 (S70). The setting table recording unit 53 determines whether or not it is necessary to adjust the write distribution interval (S80).

[0062] If there is no need to adjust the write distribution interval (No in S80), the setting table recording unit 53 ends the series of processes in FIG. 9 (END).

[0063] If the write distribution interval needs to be adjusted (Yes in S80), the setting table recording unit 53 records the adjustment amount of the write distribution interval, which is recorded in advance in the parameter list 61, in the setting table 62 (S90). After the process S90, the setting table recording unit 53 ends the series of processes in FIG. 9 (END).

[0064] FIG. 10 is a diagram showing an example of the contents of the parameter list 61 according to the first embodiment.

[0065] FIG. 10 shows the measured number of error bits (bit / 4KB) and the adjustment amount Δ of the write distribution interval. The adjustment amount Δ is the amount of change from the initial setting write distribution interval before the write distribution interval adjustment is performed. A positive adjustment amount Δ indicates that the write distribution interval is widened from the initial setting write distribution interval. A negative adjustment amount Δ indicates that the write distribution interval is narrowed from the initial setting write distribution interval. Adjustment amount ΔVCG A indicates the adjustment amount of the write distribution interval between the Er state and the A state. Similarly, the adjustment amount Δ B indicates the adjustment amount of the write distribution interval between state A and state B. Adjustment amount Δ C indicates the adjustment amount of the write distribution interval between state B and state C. D indicates the adjustment amount of the write distribution interval between the C state and the D state. Adjustment amount Δ E indicates the adjustment amount of the write distribution interval between the D state and the E state. F indicates the adjustment amount of the write distribution interval between the E state and the F state. Adjustment amount Δ G indicates the adjustment amount of the write distribution interval between the F state and the G state.

[0066] Figure 10 shows the "FBC A ≧20" and "ΔVCG A = +0.01" pair is shown. This is the number of error bits FBC between the Er state and the A state. A is 20 bits or more, the write distribution interval is increased by 0.01.

[0067] Figure 10 shows the "FBC A ≧50" and "ΔVCG A = +0.02" pair is shown. This is the number of error bits FBC between the Er state and the A state. A If is 50 bits or more, the write distribution interval is increased by 0.02.

[0068] Figure 10 shows the "FBC A <10" and "ΔVCGA =-0.01" pair is shown. This is the number of error bits FBC between the Er state and the A state. A If is less than 10 bits, it indicates that the write distribution interval is reduced by 0.01.

[0069] FIG. 11 is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions among the threshold voltage distributions in the Er state to the G state according to the first embodiment is increased.

[0070] The memory system 1 can widen the interval between threshold voltage distributions when the number of error bits is large.

[0071] FIG. 12 is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions among the threshold voltage distributions in the Er state to the G state according to the first embodiment is reduced.

[0072] When the number of error bits is small, the memory system 1 can narrow the interval between the threshold voltage distributions.

[0073] FIG. 13 is a diagram showing the contents of the setting table 62 according to the first embodiment.

[0074] The setting table indicates the position of the die, the block, the word line (WL), and the adjustment amount Δ of the write distribution interval for each state (Er state to G state). The die indicates a plurality of memory chips (memory units 12a) that constitute the memory 12. The position of the die is expressed by specifying the parameters ch, ce, and lun. The symbol * in the block and word line indicates don't care (any value). The adjustment amount Δ is the adjustment amount ΔVCG A ~Adjustment amount ΔVCG G Includes.

[0075] The first row of the setting table 62 shown in FIG. 13 indicates that the adjustment amount Δ is applied to the entire block "2010." The second row of the setting table 62 shown in FIG. 13 indicates that the adjustment amount Δ is applied to word line group "54-57" of block "3673." The third row of the setting table 62 shown in FIG. 13 indicates that the adjustment amount Δ is applied to the entire die. The fourth row of the setting table 62 shown in FIG. 13 indicates that the adjustment amount Δ is applied to word line group "15-27."

[0076] Next, the operation of the memory system 1 during programming will be described.

[0077] Fig. 14 is a flowchart showing the operation of the memory system 1 according to the first embodiment. Fig. 14 shows the operation during programming.

[0078] When the main control unit 51 receives a write request from the host device 2 (S110), it initializes the word line to be programmed (S120). After the initialization, the word line to be programmed is word line "0".

[0079] After setting the access target, the interval parameter control unit 54 searches the setting table 62 for an entry for the access target (S130). The entry indicates an item recorded in the setting table 62.

[0080] When the entry to be accessed is found (Yes in S140), the interval parameter control unit 54 sets the parameter of the adjustment amount Δ of the entry to the write distribution interval of the word line to be accessed (S150). Setting the parameter of the adjustment amount Δ means updating the write distribution interval with the parameter.

[0081] After the parameter of the adjustment amount Δ is set, the main control unit 51 executes a program (S160).

[0082] If the entry to be accessed is not found (No in S140), the process proceeds to S160.

[0083] If the word line to be accessed is not the last word line (No in S170), the next word line obtained by incrementing the current word line by 1 is set as the access target, and the processes S130 to S160 are executed again.

[0084] If the word line to be accessed is the last word line (Yes in S170), the main control unit 51 and the interval parameter control unit 54 end the operation during programming (END).

[0085] 14, the interval parameter control unit 54 controls the write distribution interval based on the adjustment amount of the write distribution interval recorded in the setting table 62. The main control unit 51 executes programs of a plurality of memory cells at the controlled write distribution interval.

[0086] Next, the operation of the memory system 1 during reading will be described.

[0087] During a read operation, the read voltage Vth is corrected based on the adjustment amount Δ. The read voltage Vth is a voltage obtained by adding the adjustment amount Δ recorded in the setting table 62 to the read voltage before correction.

[0088] Fig. 15 is a flowchart showing the operation of the memory system 1 according to the first embodiment. Fig. 15 shows the operation during reading. Here, an example will be described in which data stored in a certain block is read sequentially starting from word line 0.

[0089] When the main control unit 51 receives a read request from the host device 2 (S210), it initializes the word line to be read (S220). After the initialization, the word line to be read is word line "0".

[0090] After setting the access target, the interval parameter control unit 54 searches the setting table 62 for an entry related to the access target (S230).

[0091] When the entry to be accessed is found (Yes in S240), the interval parameter control unit 54 corrects the read voltage Vth of the word line to be accessed based on the adjustment amount Δ of each state (Er state to G state) of the entry (S250).

[0092] After that, the main control unit 51 executes a read (S260).

[0093] If the entry to be accessed is not found (No in S240), the process proceeds to S260.

[0094] If the word line to be accessed is not the last word line (No in S270), the next word line obtained by incrementing the current word line by 1 is set as the access target, and the processes S230 to S260 are executed again.

[0095] If the word line to be accessed is the last word line (Yes in S270), the main control unit 51 and the interval parameter control unit 54 end the operation during reading (END).

[0096] As described above, according to the first embodiment, the patrol read execution unit 52 measures the number of error bits in the memory cells. The interval parameter control unit 54 controls the write distribution interval in the threshold voltage distribution of the memory cells based on the measured number of error bits. This allows the write distribution interval to be adjusted according to the quality variation of the memory 12. In addition, the memory system 1 according to the first embodiment can optimize the write distribution interval for each word line. For example, by widening the write distribution interval in a word line with a relatively low quality, the stress resistance can be improved. As a result, the reliability can be improved. In addition, by narrowing the write distribution voltage in a word line with a relatively high margin of reliability, further power saving can be achieved.

[0097] By creating a word line group, multiple word lines can be managed together. This reduces the required memory capacity and shortens the time required to refer to data. As a modified example, word lines may be managed one by one without creating word line groups.

[0098] Incidentally, the interval parameter control unit 54 may refer to the parameter list 61 after the patrol read process and immediately set the adjustment amount Δ and the read voltage Vth in the memory 12. As a result, when an appropriate adjustment amount Δ and read voltage Vth are found, the adjustment is performed immediately. In this case, the setting table 62 is not used.

[0099] Second embodiment 16 is a block diagram showing the configuration of a memory 12 according to the second embodiment. The second embodiment differs from the first embodiment in that the write distribution interval is adjusted for each die due to variations in die quality.

[0100] As shown in FIG. 16, multiple dies are arranged in series.

[0101] Fig. 17 is a flowchart showing the operation of the memory system 1 according to the second embodiment. Fig. 17 shows the operation of recording to the setting table 62. In the second embodiment, the operation of recording to the setting table 62 starts (starts) at any timing while the memory system 1 is in operation.

[0102] The main control unit 51 programs and reads the test block (S310). The test block is a block where test reading and writing are performed to check the quality of the die.

[0103] After the test block is programmed and read, the main control unit 51 measures the number of error bits for each state (Er state to G state) for the test block (S320). The measured number of error bits is stored in the RAM 11b.

[0104] The processes S310 and S320 are performed for all the dies in the test block.

[0105] In addition, in the processes S310 and S320, as a modified example, the same process as the process S10 shown in Fig. 9 may be performed during the patrol read process. In the processes S310 and S320 in which the patrol read process is performed, the test block is not used, and any written block is used.

[0106] After storing the measured number of error bits in the RAM 11b, the main control unit 51 or the patrol read executing unit 52 transmits a signal to the setting table recording unit 53 (S330).

[0107] When receiving a signal from the main control unit 51 or the patrol read executing unit 52, the setting table recording unit 53 reads the measured number of error bits from the RAM 11b (S340).

[0108] The setting table recording unit 53 takes statistics of the number of error bits in each read state for each die (S350). By taking statistics of the number of error bits, the worst number of error bits in each state for each die can be obtained.

[0109] The setting table recording unit 53 checks the worst error bit number for each state against the parameter list (S360). The setting table recording unit 53 determines whether or not it is necessary to adjust the write distribution interval (S370). Note that the process from step S370 onwards is the same as the process from step S80 onwards shown in FIG. 9.

[0110] FIG. 18 is a diagram showing the contents of the setting table 62 according to the second embodiment.

[0111] FIG. 18 shows the adjustment amount Δ of the write distribution interval for each state for the two dies, die “0” and die “1” shown in FIG.

[0112] Next, the operation of the memory system 1 during programming will be described.

[0113] Fig. 19 is a flowchart showing the operation of the memory system 1 according to the second embodiment. Fig. 19 shows the operation during programming.

[0114] When the main control unit 51 receives a write request from the host device 2 (S410), the interval parameter control unit 54 searches the setting table 62 for an entry regarding the access target (S420).

[0115] When an entry to be accessed is found (Yes in S430), the interval parameter control unit 54 sets the parameter of the adjustment amount Δ of that entry to the write distribution interval of the die to be accessed (S440).

[0116] After the parameter of the adjustment amount Δ is set, the main control unit 51 initializes the word line to be programmed (S450). Here, the word line to be programmed is, for example, word line "0".

[0117] If the entry to be accessed is not found (No in S430), the process proceeds to S450.

[0118] After initializing the word lines, main control unit 51 executes the program (S460).

[0119] If the word line to be accessed is not the last word line (No in S470), the next word line obtained by incrementing the current word line by 1 is set as the word line to be accessed, and the processes S420 to S460 are executed again.

[0120] If the word line to be accessed is the last word line (Yes in S470), main control unit 51 and interval parameter control unit 54 end the operation during programming (END).

[0121] Next, the operation of the memory system 1 during reading will be described.

[0122] Fig. 20 is a flowchart showing the operation of the memory system 1 according to the second embodiment. Fig. 20 shows the operation during reading. Here, an example will be described in which data stored in a certain block is read sequentially from word line 0.

[0123] When the main control unit 51 receives a read request from the host device 2 (S510), the interval parameter control unit 54 searches the setting table 62 for an entry regarding the access target (S520).

[0124] If the entry to be accessed is found (Yes in S530), the interval parameter control unit 54 corrects the read voltage Vth of the word line to be accessed based on the adjustment amount Δ of each state of the entry (S540).

[0125] After that, the main control unit 51 initializes the word line to be read (S550). Here, the word line to be read is word line "0".

[0126] If the entry to be accessed is not found (No in S530), the process proceeds to S560.

[0127] After initializing the word lines, the main control unit 51 executes a read (S560).

[0128] If the word line to be accessed is not the last word line (No in S570), the next word line obtained by incrementing the current word line by 1 is set as the access target, and the processes S520 to S560 are executed again.

[0129] If the word line to be accessed is the last word line (Yes in S570), the main control unit 51 and the interval parameter control unit 54 end the operation at the time of reading (END).

[0130] According to the second embodiment, the write distribution interval can be optimized for each die.

[0131] As in the second embodiment, the write distribution interval may be adjusted for each die due to variations in die quality. The memory system 1 of the second embodiment can obtain the same effects as the first embodiment.

[0132] The above-described embodiments are merely examples, and the scope of the invention is not limited thereto. For example, the component unit for which the write distribution interval is adjusted is not limited to the word line described in the first embodiment, or the memory chip (die) described in the second embodiment, but may be another component unit such as a block. [Explanation of symbols]

[0133] 1. Memory System 2 Host device 11 Memory Controller 11a CPU 11b RAM 11c ROM 11d ECC circuit 11e Memory I / F Controller 11f Host I / F Controller 12. Memory 12a Memory Unit 31 I / O signal processing circuit 32 Control signal processing circuit 33 Chip control circuit 34 RY / BY generation circuit 35 Command Register 36 Address Register 41 Row Decoder 42 Column Decoder 43 Data Register 44 Sense Amplifier 45 Memory Cell Array 51 Main control unit 52 Patrol Lead Execution Department 53 Setting table recorder 54 Interval Parameter Control Section 61 Parameter List 62 Setting Table

Claims

1. a memory device having a plurality of memory cells; Counting the number of error bits in the data read from the plurality of memory cells; controlling a write distribution interval in a threshold voltage distribution of the plurality of memory cells based on the measured number of error bits; A memory controller; A memory system comprising:

2. 2 . The memory system according to claim 1 , wherein the memory controller controls the write distribution interval based on a correspondence relationship between the number of error bits and an adjustment amount of the write distribution interval, and the measured number of error bits.

3. The memory controller includes: applying the measured number of error bits to the correspondence relationship to generate an adjustment amount for the write distribution interval and storing the adjustment amount in a storage unit; The memory system according to claim 2 , wherein the write distribution interval is controlled based on an adjustment amount of the write distribution interval stored in the storage unit.

4. The memory system according to claim 1 , wherein the memory controller controls the write distribution interval in a predetermined unit including the plurality of memory cells.

5. The memory system of claim 4 , wherein the predetermined unit includes a memory chip, a block, or a word line.

6. The memory system of claim 1 , wherein the memory controller causes programming of the plurality of memory cells at the controlled write distribution intervals.

7. The memory system according to claim 1 , wherein the memory controller controls a read voltage of the memory cell based on an adjustment amount of the write distribution interval.

8. 2. The memory system according to claim 1, wherein said memory controller measures the number of error bits by periodically performing a read process on said plurality of memory cells.

9. 1. A method for controlling a memory device having a plurality of memory cells, comprising: measuring the number of error bits in data read from the plurality of memory cells; Controlling a write distribution interval in a threshold voltage distribution of the plurality of memory cells based on the measured number of error bits; A control method comprising:

Images