Solar cell and manufacturing method for the same, and solar cell module

Abstract

To provide a solar cell and a manufacturing method for the same, and a solar cell module, in which an open circuit voltage of the solar cell can be improved, contact resistance of a metal electrode can be reduced, and conversion efficiency of the cell can be improved.SOLUTION: A solar cell includes a semiconductor substrate 10 having a first texture structure 12 on a rear surface and a second texture structure 11 on a front surface, a first passivation layer 20 existing on the second texture structure 11 on the front surface of the semiconductor substrate 10, a tunnel oxide layer 30 existing on the first texture structure 12 on a rear surface of the semiconductor substrate 10, a doped conductive layer 40 existing on a surface of the tunnel oxide layer 30, and a second passivation layer 50 existing on a surface of the doped conductive layer 40. The first texture structure 12 has a non-pyramidal microstructure and includes two or more first sub-structures with a step-like shape, and a top part surface of the first sub-structure is a polygonal plane.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the technical field of cells based on the photovoltaic effect, in particular to a solar cell and its manufacturing method, and a solar cell module. [Background technology]

[0002] N-type TOPCon (Tunnel Oxide Passivated Contact) batteries realize rear passivation contact by "tunnel effect". When manufacturing TOPCon batteries, after boron is diffused on the surface of the silicon piece, borosilicate glass is formed, and its cleaning and removal is more difficult than that of the phosphosilicate glass in ordinary PERC batteries. Usually, the borosilicate glass on the rear surface of N-type batteries is removed with an oxidizing mixed acid solution, and after the surface is washed and dried, rear polishing is performed with trough or chain acid additives. The rear surface of the silicon piece after polishing has a flat structure, and the structure of the rear surface after polishing can directly affect the manufacture of the tunnel oxide layer and polycrystalline silicon layer, and further affect the passivation performance of the battery and the conversion efficiency of the battery. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of the above, the present invention provides a solar cell, a manufacturing method thereof, and a solar cell module that are capable of improving the open circuit voltage of the solar cell, reducing the contact resistance of the metal electrodes, and improving the cell conversion efficiency by matching texture structures on the surface of a cell substrate. [Means for solving the problem]

[0004] According to a first aspect of the present invention, there is provided a solar cell.

[0005] The solar cell comprises: a semiconductor substrate having a first textured structure on a rear surface thereof; a first passivation layer located on a front side of the semiconductor substrate; a tunnel oxide layer located at a first textured structure on a rear surface of the semiconductor substrate; a doped conductive layer located on a surface of the tunnel oxide layer and having a doping element of the same conductivity type as the semiconductor substrate; a second passivation layer located on a surface of the doped conductive layer; the first texture structure at the rear surface of the semiconductor substrate comprises two or more first substructures at least partially stacked; The at least partially stacked two or more first substructures are characterized in that, in a direction away from and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure is 2 μm or less, and a linear dimension of the top surface of the outermost first substructure is 45 μm or less.

[0006] In one possible embodiment, the front surface of the semiconductor substrate has a second textured structure, the second textured structure having a pyramidal microstructure with an apex far away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate, the pyramidal microstructure having an apex-to-bottom distance of 5 μm or less in a direction far away from the front surface and perpendicular to the front surface.

[0007] In one possible embodiment, the at least partially stacked two or more first substructures are outermost in a direction away from and perpendicular to the rear surface. The distance between the top surface of a first substructure and the top surface of an adjacent first substructure is 0.3 μm to 1.2 μm.

[0008] In one possible embodiment, the average linear dimension of the top surface of said outermost first substructure is between 10 μm and 15 μm.

[0009] In one possible embodiment, the thickness of the tunnel oxide layer at the top surface of said outermost first substructure is smaller than the thickness of the tunnel oxide layer at the side surfaces of said outermost first substructure.

[0010] In one possible embodiment, the difference in thickness between the tunnel oxide layer at the top surface of said outermost first substructure and the tunnel oxide layer at the side surface of said outermost first substructure is less than or equal to 0.15 nm.

[0011] In one possible embodiment, the first texture structure further comprises two or more second substructures adjacent to each other but not stacked, and a first dimension of a top surface of the second substructures remote from the rear surface is less than or equal to 45 μm.

[0012] In one possible embodiment, the top surface of the first substructure and / or the second substructure is a polygonal plane.

[0013] In one possible embodiment, the polygonal planar shape includes at least one of a rhombus, a rectangle, a trapezoid, an approximate rhombus, an approximate rectangle, and an approximate trapezoid.

[0014] In one possible embodiment, the tunnel oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer, and the tunnel oxide layer has a thickness of 0.8 nm to 2 nm.

[0015] In one possible embodiment, the second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer, and the second passivation layer has a thickness of 70 nm to 120 nm.

[0016] In one possible embodiment, the first passivation layer comprises at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer.

[0017] In one possible embodiment, the semiconductor substrate is an N-type monocrystalline silicon substrate, the doped conductive layer is an N-type doped polycrystalline silicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer, and the thickness of the doped conductive layer is 60 nm to 200 nm.

[0018] According to a second aspect of the present invention, there is provided a solar cell module, the solar cell module comprising a plurality of solar cell strings, the solar cell strings comprising solar cells according to the first aspect.

[0019] According to a third aspect of the present invention, there is provided a method for manufacturing a solar cell, the method comprising the steps of: performing a texturing process on the semiconductor substrate to form a second texture structure including a pyramidal microstructure on a front surface of the semiconductor substrate; performing a doping process on the front side of the textured semiconductor substrate to form a doped layer; The rear surface of the semiconductor substrate is polished using an alkaline solution to form a polishing treatment on the semiconductor substrate. forming a first textured structure on a rear surface of the plate; forming a tunnel oxide layer on the first textured structure on the rear surface of the semiconductor substrate; depositing a polysilicon layer on a surface of the tunnel oxide layer, and performing a doping process on the polysilicon layer to form a doped conductive layer having a doping element of the same conductivity type as the semiconductor substrate; forming a first passivation layer on a front side of the semiconductor substrate; forming a second passivation layer on a surface of the doped conductive layer; the first texture structure comprises two or more first substructures at least partially stacked; The at least partially stacked two or more first substructures are characterized in that in a direction away from and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure is 2 μm or less, and a one-dimensional dimension of the top surface of the outermost first substructure is 45 μm or less.

[0020] In one possible embodiment, performing a polishing process on the rear surface of the semiconductor substrate using the alkaline solution includes: cleaning the rear surface of the semiconductor substrate with a 5% by mass to 15% by mass alkaline solution to remove porous silicon; Dropping minute droplets of the alkaline solution onto the rear surface of the semiconductor substrate by a spray method to perform a roughening treatment, and then pre-cleaning with 5% by mass to 10% by mass hydrofluoric acid; A polishing liquid is used to polish the rear surface of the semiconductor substrate, the polishing temperature is 70°C to 80°C, and the polishing time is less than 260 seconds, and the polishing liquid contains 1% by mass to 15% by mass of NaOH, 1% by mass to 15% by mass of KOH, and 0.5% by mass to 2.5% by mass of an additive; removing organic components contained in the polishing liquid using a mixed liquid containing 5% by mass to 15% by mass of potassium hydroxide and 15% by mass to 40% by mass of hydrogen peroxide; The polished semiconductor substrate is then washed with water and dried.

[0021] In one possible embodiment, the step of forming the tunnel oxide layer satisfies at least one of the following characteristics (1) to (5).

[0022] (1) depositing the tunnel oxide layer on the first textured structure on the rear surface of the semiconductor substrate by a variable temperature process and a chemical vapor deposition method; (2) During the process of depositing the tunnel oxide layer, the heating rate is controlled to be 0.5°C / min to 3°C / min, the deposition temperature is controlled to be 560°C to 620°C, and the deposition time is controlled to be 3 min to 10 min; (3) the deposition temperature of the tunnel oxide layer is lower than the deposition temperature of the polysilicon layer; (4) the tunnel oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer; (5) The tunnel oxide layer has a thickness of 0.8 nm to 2 nm. Effect of the Invention

[0023] The present invention has at least the following excellent effects.

[0024] By controlling the distance of the substructures in the first texture structure on the rear surface of the semiconductor substrate within a suitable range, it is possible to ensure that the roughness of the rear surface of the semiconductor substrate is within a suitable range, which is favorable for improving the uniformity of the tunnel oxide layer formed on the first texture structure, and the tunnel oxide layer formed has better performance, and furthermore, the local doped conductive layer can be formed. It is possible to suppress an increase in doping concentration, reduce the contact resistivity, improve the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency. [Brief description of the drawings]

[0025] In order to more clearly describe the embodiments of the present invention or the solutions of the prior art, the drawings necessary for the description of the embodiments or the solutions of the prior art are briefly described below. It is obvious to those skilled in the art that the drawings described below are only for illustrating some embodiments of the present invention, and other drawings can be obtained based on these drawings without any creative effort. [Figure 1] 1 is a structural schematic diagram of a solar cell manufacturing method according to one embodiment of the present application; [Diagram 2] 1 is an electron microscope photograph of a second texture structure on the front surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Diagram 3] 1 is an electron microscope photograph of a first texture structure on a rear surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Figure 4a] FIG. 2 is a structural schematic diagram of a first sub-structure in a first texture structure on a rear surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Figure 4b] FIG. 2 is a structural schematic diagram of another first sub-structure in a first texture structure on a rear surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Diagram 5] FIG. 2 is a structural schematic diagram of a sub-structure in a first texture structure on the rear surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Figure 6] 2 is a structural schematic diagram of a tunnel oxide layer on a first texture structure on a rear surface of a semiconductor substrate of a solar cell according to one embodiment of the present application. [Figure 7a] 1 is a structural schematic diagram of a solar cell module according to one embodiment of the present application. [Figure 7b] FIG. 1 is a top view of a solar cell module according to one embodiment of the present application. [Figure 8] FIG. 2 is a flow diagram of a method for manufacturing a solar cell according to one embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In order to make the present invention easier to understand, the following detailed description of the preferred embodiments of the present invention will be given with reference to the accompanying drawings.

[0027] It should be noted that the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. It is understood that all other embodiments that a person skilled in the art can obtain based on the embodiments of the present invention without requiring creative efforts fall within the scope of protection of the present application.

[0028] The terms used in the embodiments of the present invention are intended to describe specific embodiments and are not intended to be used to limit the present invention. The singular forms "said" and "the" used in the embodiments of the present invention and the appended claims are understood to include the plural meanings unless otherwise indicated by the context.

[0029] It should be noted that the term "and / or" used herein simply indicates a relational relationship describing related objects, and means that there are three possible relations. For example, A and / or B can indicate three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the sign " / " generally means that the related objects before and after are in an "or" relationship.

[0030] TOPCon cells achieve rear passivation by the "tunnel effect". The rear structure of conventional TOPCon cells is, from inside to outside, a semiconductor substrate, a tunnel oxide layer, a doped conductive layer, and a rear passivation layer. During the manufacture of N-type TOPCon cells (contact passivated cells), boron is diffused to form BSG borosilicate glass, which is more difficult to clean and remove than phosphosilicate glass. It is usually removed using an oxidizing mixed acid solution, and the surface is washed and dried, followed by rear polishing. Currently, semiconductor The post-polishing state of the rear surface of the semiconductor substrate can have a certain effect on the ultra-thin tunnel oxide layer having a nano-level thickness, which is likely to cause the contact resistivity between the tunnel oxide layer and the semiconductor substrate to be high, which is likely to cause instability in the fill factor of the solar cell, and can affect the photoelectric conversion efficiency of the cell.

[0031] Based on the above, according to a first aspect of the present invention there is provided a solar cell as shown in Figure 1, the solar cell comprising: A semiconductor substrate 10 having a first textured structure 12 on its rear surface and a second textured structure 11 on its front surface, which may include pyramidal microstructures; a first passivation layer 20 located on the front side of the semiconductor substrate 10; a tunnel oxide layer 30 located on the first textured structure on the rear surface of the semiconductor substrate 10; a doped conductive layer 40 located on the surface of the tunnel oxide layer 30 and having a doping element of the same conductivity type as the semiconductor substrate; a second passivation layer 50 located on a surface of the doped conductive layer 40; The first texture structure 12 comprises two or more first substructures at least partially stacked, The at least partially stacked two or more first substructures are characterized in that in a direction away from and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure is 2 μm or less, and a linear dimension of the top surface of the outermost first substructure is 45 μm or less.

[0032] The front surface of the semiconductor substrate 10 refers to the light-receiving surface, i.e., the surface that is irradiated by sunlight (light-receiving surface), and the back surface of the semiconductor substrate 10 refers to the surface opposite the front surface. In some embodiments, the formed solar cell may be single-sided, with the front surface being the light-receiving surface and the back surface being the non-light-receiving surface. In some embodiments, the formed solar cell may be double-sided, with both the front and back surfaces being light-receiving surfaces.

[0033] As an optional solution of the present invention, the semiconductor substrate 10 is an N-type crystalline silicon substrate (or silicon piece), and a P-type doped layer is formed on the front side of the semiconductor substrate by one or more processes of high temperature diffusion, paste doping, or ion implantation to form a PN junction in the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 may be one of a monocrystalline silicon substrate, a polycrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate.

[0034] In some embodiments, the P-type doped layer is a boron doped diffusion layer. The boron doped diffusion layer is a P-type doped layer (i.e., a P+ layer) formed by diffusing boron atoms to a certain depth on the front side through a diffusion process using a boron source. The boron source may be, for example, liquid boron tribromide.

[0035] In some embodiments, as shown in FIG. 2, the front surface of the semiconductor substrate 10 has a second texture structure 11 including a pyramidal microstructure 111. The pyramidal microstructure 111 may be a tetrahedron, a near-tetrahedron, a pentahedron, a near-pentahedron, or the like. The pyramidal microstructure 111 may be formed by performing a texturing process on the semiconductor substrate. The texturing process may be chemical etching, laser etching, mechanical etching, plasma etching, or the like. The pyramidal microstructure allows the microstructure to be better filled when the metal paste is used to form an electrode by screen printing, resulting in better electrode contact, effectively reducing the series electrical resistance of the battery, and improving the fill factor.

[0036] In some embodiments, the pyramidal microstructure 111 has an apex far away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate, and the pyramidal microstructure has a distance (or height) between the apex and the bottom in a direction far away from the front surface and perpendicular to the front surface, which is 5 μm or less, and preferably, the distance ranges from 2 μm to 5 μm. Specifically, it may be 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 4.8 μm, or 5 μm. When the distance range of the pyramidal microstructure 111 is controlled within 5 μm, for example, 2 μm to 5 μm, the pyramidal microstructure 111 has properties such as low reflectivity, low carrier recombination rate at the interface when in contact with a metal, and easy filling, thereby improving the photoelectric conversion efficiency of the battery.

[0037] As can be seen, the crystal orientation of the silicon crystal on the front surface is anisotropic, so the number of pyramidal microstructures formed on the front surface cannot be calculated or confirmed. Here, the distance of the pyramidal microstructures 111 may be the distance between the highest point of the protruding apex of the pyramidal microstructures 111 randomly selected in a specific region and the lowest point of the recess. For example, the distance of the pyramidal microstructures 111 can be confirmed by measuring the surface shape of the semiconductor substrate using an atomic force microscope (AFM). For example, a scanning range of about 40 μm×40 μm is selected on the front surface, and the front surface of the semiconductor substrate is scanned within the range selected by the atomic force microscope to measure the shape dimensions of the pyramidal microstructures on the front surface, and the height h is calculated and obtained. Specifically, if the highest point of the protruding apex of the pyramidal microstructure selected from the measured shape dimensions (AFM image) is ha, and the lowest point of the bottom corresponding to the apex is hb, then h=ha−hb. In another embodiment, a plurality of pyramidal microstructures in the second texture structure are randomly selected, their heights are measured, and the average value is calculated, and the average value is defined as the height of the pyramidal microstructures. For example, four pyramidal microstructures 111 are randomly selected, and their heights are denoted as h1, h2, h3, and h4, respectively, and the height of the pyramidal microstructure 111 is the value of (h1+h2+h3+h4) / 4. That is, the average distance of the plurality of pyramidal microstructures 111 can be regarded as the distance of the pyramidal microstructures on the front surface, and is used to represent the texture characteristics of the front surface.

[0038] As an optional technical solution of the present invention, the first passivation layer 20 includes a stacked structure consisting of at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.

[0039] In some embodiments, the thickness of the first passivation layer 20 is in the range of 10 nm to 120 nm, and may be specifically 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or 120 nm, etc., and of course may be other values ​​within the above range, and is not limited thereto.

[0040] Preferably, the first passivation layer 20 is a laminated passivation structure of an aluminum oxide layer and a silicon nitride layer. The aluminum oxide layer is provided on the front surface of the semiconductor substrate 10, and the silicon nitride layer is provided on the surface of the aluminum oxide layer. In some embodiments, the aluminum oxide layer has a thickness of 2 nm to 10 nm and a refractive index of 1.5 to 1.8, and the silicon nitride layer has a thickness of 50 nm to 110 nm and a refractive index of 1.65 to 2.25. The overall refractive index of the first passivation layer 20 is 1.9 to 2.0. In some embodiments, the aluminum oxide layer or the silicon nitride layer may include multiple sub-layers, for example, the silicon nitride layer is composed of 2 to 5 silicon nitride sub-layers.

[0041] Preferably, the first passivation layer is a layer of aluminum oxide deposited in sequence. The aluminum oxide layer has a thickness in the range of 2 nm to 10 nm and a refractive index in the range of 1.5 to 1.8, the silicon nitride layer has a thickness in the range of 40 nm to 80 nm and a refractive index in the range of 1.9 to 2.3, and the silicon oxynitride layer has a thickness in the range of 10 nm to 60 nm and a refractive index in the range of 1.5 to 1.75.

[0042] Furthermore, the rear surface of the semiconductor substrate 10 has a first texture structure 12. Specifically, the first texture structure 12 can be formed by an alkaline polishing process.

[0043] As an optional technical solution of the present invention, Fig. 3 is an electron microscope photograph of a first texture structure 12 on the rear surface of a semiconductor substrate provided in an embodiment of the present invention. As shown in Fig. 3, the first texture structure 12 includes two or more first sub-structures 121 that are at least partially stacked. The first texture structure 12 has a non-pyramidal microstructure shape. For example, the first texture structure has a substantially "staircase" shape, and the first sub-structure 121 can be regarded as one step of the "staircase".

[0044] FIG. 4a is a schematic diagram of an exemplary partially stacked three-layer first sub-structure, and FIG. 4b is a schematic diagram of an exemplary partially stacked two-layer first sub-structure.

[0045] The at least partially stacked two or more first substructures 121 have a distance H between the top surface 121a of the outermost first substructure and the top surface 121b of the adjacent first substructure in a direction (which may be understood as a stacking direction) far from the rear surface and perpendicular to the rear surface, which is 2 μm or less, and may be specifically 2 μm, 1.8 μm, 1.5 μm, 1.2 μm, 1.1 μm, 1.0 μm, 0.8 μm, 0.5 μm, 0.3 μm, 0.2 μm, or 0.1 μm, etc. If the distance H exceeds 2 μm, the roughness of the first texture structure is too large, and the thickness of the tunnel oxide layer 30 formed on the first texture structure becomes large, which is disadvantageous to the formation of a tunnel oxide layer having high density and high uniformity, and may further affect the tunnel effect and passivation effect of the tunnel oxide layer 30. Moreover, if the roughness of the first texture structure is too small, the thickness of the tunnel oxide layer formed on the first texture structure will be small, which is unfavorable for contact with the electrode paste.Preferably, in a direction far from the rear surface and perpendicular to the rear surface, a distance H between the top surface 121a of the outermost first substructure and the top surface 121b of the adjacent first substructure is in the range of 0.3 μm to 1.2 μm.

[0046] In the case of a three-layer first sub-structure arranged in layers, the distance H between the top surface 121a of any one layer of the first sub-structure and the top surface 121b of the adjacent layer of the first sub-structure is 2 μm or less.

[0047] As can be understood, by controlling the distance between the top surface 121a of the outermost first sub-structure and the top surface 121b of the adjacent first sub-structure to be 2 μm or less, the roughness of the first texture structure can be controlled within a desired range, which is beneficial to improving the uniformity of the tunnel oxide layer formed on the first texture structure. The performance of the formed tunnel oxide layer becomes better. Furthermore, it suppresses the excessive local phosphorus concentration due to the diffusion of phosphorus, reduces the contact resistivity, improves the open-circuit voltage of the solar cell, and can improve the fill factor and the photoelectric conversion efficiency.

[0048] The one-dimensional dimension L of the top surface 121a of the outermost first sub-structure is 45 μm or less, that is, 0 < L ≤ 45 μm. Preferably, the one-dimensional dimension L is in the range of 2 μm to 45 μm. Here, the one-dimensional dimension L of the top surface may specifically be the length of the vertical, horizontal, or diagonal of the surface, or the diameter in the case of a circle, etc., and is not limited herein. In some embodiments For example, in a predetermined range of the back surface of the substrate, the one-dimensional dimension may be the average value of the one-dimensional dimensions of the top surfaces of a plurality of outermost first sub-structures. Specifically, the average one-dimensional dimension of the top surface of the outermost first sub-structure may be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 42 μm, 40 μm, or 45 μm, etc. Preferably, the average one-dimensional dimension of the top surface of the outermost first sub-structure is in the range of 10 μm to 15 μm.

[0049] In one specific embodiment, as shown in FIG. 3, the first texture structure further includes two or more second sub-structures 122 that are arranged adjacent to each other without being stacked on top of each other. The top surface of the second sub-structure 122 that is far from the rear surface has a one-dimensional dimension L of 45 μm or less, that is, 0 < L ≤ 45 μm. Preferably, the one-dimensional dimension L of the second sub-structure 122 is 2 μm to 45 μm, specifically, it may be 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, or 45 μm, etc.

[0050] The top surface of the first sub-structure and / or the second sub-structure on the rear surface is a polygonal plane, which is different from the pyramidal micro-structure on the front surface. The shape of the polygonal plane includes at least one of a rhombus, a square, a trapezoid, a substantially rhombus, a substantially square, and a substantially trapezoid. As can be understood, during the actual manufacturing process, the shape of the top surface of the first sub-structure or the second sub-structure presents an irregular polygonal plane, but overall shows shape characteristics approximating a rhombus, a square, or a trapezoid.

[0051] In some embodiments, there may be a possibility of destroying the initial structures of the second texture structure and the first texture structure to a certain extent during the manufacturing of subsequent passivation film layers, such as the manufacturing of the first passivation layer 20, the tunnel oxide layer 30, the doped conductive layer 40, etc. For example, in mass-produced solar cells, there may be a small amount of non-pyramidal micro-structures in the second texture structure. The non-pyramidal micro-structures are formed by the destruction of the sharp tops of the pyramidal micro-structures.

[0052] In some embodiments, when measuring the dimensional feature of the texture representing the second texture structure or the first texture structure of the solar cell, for example, the one-dimensional dimension of the top surface of the first sub-structure or the distance between the surfaces of the adjacent first sub-structures can be directly measured and confirmed on the film layer surface by a test device (such as an optical microscope, an atomic force microscope, a scanning electron microscope, a transmission electron microscope, etc.). In one case, since the thickness of the film layer is at the nano-level, the value of the dimensional feature of the texture can be obtained directly by using the measurement data of the film layer corresponding to the second texture structure or the first texture structure, where the measurement data of the film layer is the sum of the film layer thickness and the value of the texture dimensional feature. In another case, the value of the dimensional feature of the texture can be obtained by subtracting the film layer thickness data from the measurement data of the film layer. The above measurement means are merely examples, and the present invention is not limited thereto.

[0053] As shown in FIG. 1 and FIG. 6, the tunnel oxide layer 30 is located on the first texture structure 12 on the rear surface of the semiconductor substrate 10, and may be a laminate structure including one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunnel oxide layer 30 may be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, etc. The thickness of the tunnel oxide layer 30 is 0.8 nm to 2 nm, and may be, for example, 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, or 2 nm. The thickness of the tunnel oxide layer 30 is the thickness of the tunnel oxide layer relative to the surface on which it is formed. The thickness of the tunnel oxide layer 30 formed on the first texture structure is obtained by observing and calculating a cross section when the normal direction of the slope of the substructure is the thickness direction. If the thickness of the tunnel oxide layer 30 is too large, it is disadvantageous to the reduction of the contact resistance of the tunnel oxide layer. Controlling the Thickness of the Tunnel Oxide Layer This makes it possible to suppress a decrease in the fill factor caused by contact resistance.

[0054] Specifically, the band gap width of the tunnel oxide layer 30 is greater than 3.0 eV. Although carriers are generally difficult to pass through the tunnel oxide layer 30 due to thermal radiation, when the tunnel oxide layer 30 is very thin, carriers can pass through the tunnel oxide layer 30 due to the tunnel effect, so a tunnel oxide layer with a thickness of 0.8 nm to 2 nm does not hinder the transport of majority carriers. As the thickness of the tunnel oxide layer gradually increases, the tunnel effect of majority carriers is affected, making it difficult for carriers to be transported and pass through the tunnel oxide layer 30, and the photoelectric conversion efficiency of the battery gradually decreases. However, if the thickness of the tunnel oxide layer is too small, it cannot play the role of passivation. Preferably, the tunnel oxide layer 30 is a silicon oxide layer with a thickness of 0.8 nm to 1.5 nm.

[0055] As an alternative technical solution of the present invention, as shown in Fig. 6, a thickness D1 of the tunnel oxide layer on the top surface of the outermost first sub-structure is smaller than a thickness D2 of the tunnel oxide layer formed on the side surface of the outermost first sub-structure. Specifically, the thickness difference (D2-D1) between the tunnel oxide layer on the top surface of the outermost first sub-structure and the tunnel oxide layer formed on the side surface of the outermost sub-structure is less than or equal to 0.15 nm. Specifically, the thickness difference may be 0.14 nm, 0.13 nm, 0.12 nm, 0.11 nm, 0.10 nm, 0.09 nm, 0.08 nm, 0.07 nm, 0.06 nm, 0.05 nm, 0.04 nm, etc. If the difference in thickness between the tunnel oxide layer on the top surface of the outermost first substructure and the tunnel oxide layer formed on the side surface of the outermost substructure is too large, the thickness uniformity of the tunnel oxide layer will be poor, the current density of the solar cell will be easily affected, and the open circuit voltage of the solar cell will be reduced.

[0056] In some embodiments, the front and rear surfaces of the semiconductor substrate are textured with different shapes, i.e., a pyramidal texture is formed on the front surface and a non-pyramidal texture is formed on the rear surface, so that the resulting cell has different light confinement structures on the front and rear surfaces and increases the effective contact area of ​​light. In addition, for the first texture formed on the rear surface, the distance between the top surface of the outermost first substructure and the top surface of the adjacent first substructure is controlled to be 2 μm or less, which is favorable for reducing the pinhole density in the tunnel oxide layer, and further improves the compactness and uniformity of the tunnel oxide layer, and further prevents the local doping concentration of the doped conductive layer on the surface of the tunnel oxide layer from becoming high, thereby reducing the contact resistivity, improving the open circuit voltage of the solar cell, and improving the fill factor and photoelectric conversion efficiency.

[0057] In some embodiments, the doped conductive layer 40 may be a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped amorphous silicon layer, and the doped conductive layer 40 includes a doping element of the same conductivity type as the semiconductor substrate.

[0058] When the semiconductor substrate 10 is an N-type single crystal silicon substrate, the doped conductive layer 40 is an N-type doped polycrystalline silicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer, and the doping element contained therein may be an N-type doping element such as phosphorus.

[0059] In some embodiments, the doped conductive layer 40 has a thickness in the range of 60 nm to 200 nm, for example an N-type doped polycrystalline silicon layer, and has a refractive index in the range of 3.5 to 4.5.

[0060] As an alternative technical solution of the present invention, the second passivation layer 50 can be a silicon nitride layer, The second passivation layer 50 includes at least one of a silicon oxide layer and a silicon oxynitride layer. The thickness of the second passivation layer 50 is 70 nm to 120 nm. For example, the second passivation layer 50 is a silicon nitride layer. The silicon nitride layer has a low silicon / nitrogen ratio and a refractive index in the range of 1.7 to 2.1, which may be 1.7, 1.8, 1.9, 2.0, or 2.1, and may of course be other values ​​within the above range, and is not limited thereto. By controlling the refractive index of the silicon nitride layer and lowering the silicon / nitrogen ratio contained in the silicon nitride layer, the contact resistivity can be reduced when the formed second passivation layer 50 is subjected to a metallization process, and the contact resistivity of the solar cell can be further reduced.

[0061] In some embodiments, when the second passivation layer 50 is a stack of silicon nitride and silicon oxide layers, or a stack of silicon nitride and silicon oxynitride layers, the silicon nitride layer is located on top of the doped conductive layer, and the silicon oxide layer or silicon oxynitride layer is located on top of the silicon nitride layer.

[0062] In addition, the solar cell further includes a first electrode 60 and a second electrode 70. The first electrode 60 penetrates the first passivation layer 20 to form an ohmic contact with a P-type doped layer (e.g., a boron-doped diffusion layer) on the front side of the semiconductor substrate 10, and the second electrode 70 penetrates the second passivation layer 50 to form an ohmic contact with the doped conductive layer 40, and the doped conductive layer 40 and the tunnel oxide layer 30 constitute a passivation contact structure. The first electrode 60 and the second electrode 70 can be formed by sintering a conductive metal paste applied to the surface of the first passivation layer and the second passivation layer. In some embodiments, the material of the first electrode 60 or the second electrode 70 includes a metal material such as silver, aluminum, copper, or nickel.

[0063] A solar cell formed as shown in FIG. 1, i.e., a second texture structure having a pyramidal microstructure is formed on the front surface of a semiconductor substrate 10, a first texture structure having a non-pyramidal microstructure is formed on the rear surface of the semiconductor substrate, a matching first passivation layer 20 (e.g., a stacked passivation structure of an aluminum oxide layer and a silicon nitride layer) is formed on the second texture structure, and a matching tunnel oxide layer 30, a doped conductive layer 40 and a second passivation layer 50 (e.g., a silicon nitride layer) are formed on the first texture structure, can exhibit high photoelectric conversion efficiency.

[0064] Regarding a second aspect of the present invention, in an embodiment of the present invention, there is provided a solar cell module including a plurality of solar cell strings.

[0065] As shown in FIGS. 7a and 7b, the solar cell module includes a first sheet 1, a first sealing adhesive layer 2, a solar cell string 3, a second sealing adhesive layer 4 and a second sheet 5.

[0066] The solar cell string 3 includes a plurality of solar cells (for example, the solar cells shown in FIG. 1) that are connected to each other by conductive ribbons (not shown). The solar cells may be connected to each other by shingling (for example, by partially stacking) or splicing.

[0067] The first sheet 1 and the second sheet 5 may be transparent or opaque sheets, for example, glass sheets or plastic sheets.

[0068] Both sides of the first sealing adhesive layer 2 are in contact with and bonded to the first sheet 1 and the sheet-like battery 3, respectively, and both sides of the second sealing adhesive layer 4 are in contact with and bonded to the second sheet 5 and the sheet-like battery 3, respectively. The adhesive film may be an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0069] The solar cell module may be sealed around all sides, i.e., the sealing tape may be used to completely cover and seal the sides of the solar cell module, thereby preventing the solar cell module from shifting during the lamination process.

[0070] Furthermore, the solar cell module (solar cell module 100 shown in FIG. 7b) further includes an edge sealing member 6 for sealing a part of the edge of the solar cell module. As shown in FIG. 7b, the edge sealing member 6 is fixed to an edge near a corner of the solar cell module to perform a sealing function. The edge sealing member 6 may be a high-temperature resistant tape. The high-temperature resistant tape has excellent high-temperature resistance properties and does not decompose or fall off during the lamination process, and can ensure that the solar cell module is reliably sealed. In addition, both ends of the high-temperature resistant tape are fixed to the second sheet 5 and the first sheet 1, respectively. Both ends of the high-temperature resistant tape may be bonded to the second sheet 5 and the first sheet 1, respectively, and the middle part of the tape can regulate the position of the side of the solar cell module, thereby preventing the solar cell module from being misaligned during the lamination process.

[0071] According to a third aspect of the present invention, there is further provided a method for producing the solar cell described above. As shown in FIG. 8, the method includes the following steps:

[0072] Step S10: performing a texturing process on the semiconductor substrate to form a second texture structure on the front surface of the semiconductor substrate, the second texture structure may include a pyramidal microstructure; Step S20: performing a doping process on the front surface of the semiconductor substrate after the texture is formed to form a doped layer; Step S30: performing a polishing process on the rear surface of the semiconductor substrate using an alkaline solution to form a first texture structure on the rear surface of the semiconductor substrate, the first texture structure including two or more first substructures at least partially stacked, and the two or more first substructures at least partially stacked have a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure that is 2 μm or less in a direction away from the rear surface and perpendicular to the rear surface, and a one-dimensional dimension of the top surface of the outermost first substructure is 45 μm or less; Step S40: forming a tunnel oxide layer on the first texture structure on the rear surface of the semiconductor substrate; Step S50: depositing a polycrystalline silicon layer on the surface of the tunnel oxide layer, and performing a doping process on the polycrystalline silicon layer to form a doped conductive layer having a doping element of the same conductivity type as the semiconductor substrate; Step S60: forming a first passivation layer on the front side of the semiconductor substrate; Step S70: Form a second passivation layer on the surface of the doped conductive layer.

[0073] In the above technical proposal, an alkaline solution is used to polish the rear surface of the semiconductor substrate, thereby forming texture structures of different shapes on the front and rear surfaces of the semiconductor substrate, i.e., forming a pyramidal texture structure on the front surface and a non-pyramidal texture structure on the rear surface, the front and rear surfaces of the formed cell can have different light confinement structures, and the effective contact area of ​​light can be increased. Furthermore, for the first texture structure formed on the rear surface, the distance between the top surface of the outermost first sub-structure and the top surface of the adjacent first sub-structure is controlled to be 2 μm or less, which is favorable for reducing the pinhole density in the tunnel oxide layer, and further improving the density and uniformity of the tunnel oxide layer, and further improving the tunnel oxide layer. This can prevent the local doping concentration of the doped conductive layer on the surface of the doped layer from becoming high, reduce the contact resistivity, improve the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0074] The present technical solution will be described in detail below.

[0075] In step S10, a texturing process is performed on the semiconductor substrate to form a second texture structure including pyramidal microstructures on the front side of the semiconductor substrate.

[0076] The semiconductor substrate may be a crystalline silicon substrate (silicon substrate), for example, one of a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, but the specific type of the semiconductor substrate is not limited in the embodiments of the present invention. In some embodiments, the semiconductor substrate is an N-type crystalline silicon substrate (or silicon piece) with a thickness of 60 μm to 240 μm, specifically, 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, or 240 μm, etc., but is not limited thereto. The doping element of the semiconductor substrate may be phosphorus, nitrogen, etc.

[0077] It should be noted that in the present invention, the specific operation method of texturing is not limited.For example, the wet texturing process can be selected to perform texturing on the N-type substrate, but is not limited to this operation method.When the N-type semiconductor substrate is an N-type single crystal silicon substrate, the texturing can be performed using an alkaline solution, such as a potassium hydroxide solution, and the corrosion of the NaOH solution shows anisotropy, so that a pyramidal microstructure can be produced.

[0078] As shown in FIG. 2, the front surface of the semiconductor substrate 10 has a second texture structure 11 including a pyramidal microstructure 111. The pyramidal microstructure 111 may be a tetrahedron, a roughly tetrahedron, a pentahedron, a roughly pentahedron, or the like structure. The pyramidal microstructure 111 can be formed by performing a texturing process on the semiconductor substrate. The texturing process can be performed in the form of chemical etching, laser etching, mechanical method, plasma etching, and the like. The pyramidal microstructure can be better filled into the microstructure when the electrode is formed by screen printing using a metal paste, and can obtain a better electrode contact, effectively reducing the series electrical resistance of the battery and improving the fill factor.

[0079] In step S20, a doping process is performed on the front surface of the textured semiconductor substrate to form a doped layer.

[0080] In one specific embodiment, if the semiconductor substrate 10 is an N-type substrate, a P-type doped layer may be formed on the front side of the semiconductor substrate by one or more of the following processes: high temperature diffusion, paste doping, or ion implantation, thereby forming a PN junction in the semiconductor substrate 10.

[0081] In some embodiments, the P-type doped layer is a boron doped diffusion layer. The boron doped diffusion layer is a P-type doped layer (i.e., a P+ layer) formed by diffusing boron atoms to a certain depth on the front surface by a diffusion process using a boron source. For example, the boron source may be liquid boron tribromide. The microcrystalline silicon phase in the boron-diffused substrate is transformed into a polycrystalline silicon phase. Due to the high concentration of boron on the surface of the semiconductor substrate, a borosilicate glass layer (BSG) is usually formed.

[0082] Furthermore, before performing a polishing process on the rear surface of the semiconductor substrate using an alkaline solution in step S30, the method for manufacturing a solar cell further includes the following steps.

[0083] The borosilicate glass layer on the rear surface of the semiconductor substrate is removed with the prepared mixed acid, which contains 0.1% by mass to 10% by mass of hydrogen fluoride, 10% by mass to 20% by mass of sulfuric acid, and 25% by mass to 50% by mass of nitric acid.

[0084] The rear surface of the semiconductor substrate after the acid washing is washed with water and dried.

[0085] As can be seen, during the boron diffusion process, some borosilicate glass is formed on the rear surface of the semiconductor substrate due to the wraparound effect, and this borosilicate glass must be removed. Note that after pickling, a porous structure is formed on the rear surface of the semiconductor substrate.

[0086] Specifically, the pickling time is 10s to 180s, and the pickling temperature is 7°C to 20°C, that is, the borosilicate glass on the rear surface of the semiconductor substrate is removed by pickling under room temperature to expose the semiconductor substrate body.

[0087] In step S30, a polishing process is performed on the rear surface of the semiconductor substrate using an alkaline solution, thereby forming a first texture structure on the rear surface of the semiconductor substrate.

[0088] Specifically, the rear surface of the semiconductor substrate is washed with an alkaline solution having a concentration of 5% by mass to 15% by mass to remove the porous silicon; Furthermore, a roughening treatment is performed by spraying minute droplets of an alkaline solution onto the rear surface of the semiconductor substrate, and then preliminary cleaning is performed with 5% by mass to 10% by mass hydrofluoric acid; A rear surface of a semiconductor substrate is polished using a polishing liquid, the polishing temperature is 70°C to 80°C, and the polishing time is less than 260 seconds, the polishing liquid contains 1% by mass to 15% by mass of NaOH, 1% by mass to 15% by mass of KOH, and 0.5% by mass to 2.5% by mass of an additive; The organic components contained in the etching solution are removed using a mixed solution containing 5% by mass to 15% by mass of potassium hydroxide and 15% by mass to 40% by mass of hydrogen peroxide; After polishing, the semiconductor substrate is washed with water and dried.

[0089] In some embodiments, the borosilicate glass layer on the front side of the semiconductor substrate needs to be protected during the backside polishing process, and may be protected, for example, by a mask.

[0090] In one embodiment, since the boron concentration at the rear surface of the semiconductor substrate is low, etching efficiency can be effectively improved by using an alkaline solution. The alkaline solution includes an organic base and / or an inorganic base, such as NaOH, KOH, Ga(OH), etc. 2 , N.H. 3 H 2 Examples of the organic base include triethylamine, nitrophenol, pyridine, quinine, and colchicine. The additive contained in the polishing liquid may be a buffer solution containing sodium sulfonate, maleic anhydride, alkyl glycoside, or the like.

[0091] Specifically, the polishing temperature may be 70°C, 72°C, 74°C, 75°C, 78°C, 79°C, 80°C, etc., and the polishing time may be 250 s, 240 s, 230 s, 220 s, 200 s, 180 s, 160 s, 140 s, 120 s, 100 s, 80 s, etc., but of course may be other values ​​within the above ranges.

[0092] In some embodiments, the polishing loss of the semiconductor substrate is less than 0.3 g.

[0093] By controlling the polishing time and polishing temperature, the shape of the substructures in the polished first texture structure can be adjusted so that, among two or more at least partially stacked first substructures, the distance between the top surface of the outermost first substructure and the top surface of the adjacent first substructure in a direction away from the rear surface and perpendicular to the rear surface is 2 μm or less, thereby increasing the roughness of the rear surface of the semiconductor substrate.

[0094] In some embodiments, the surface of the semiconductor substrate can be dried with hot air to form a first textured structure comprising non-pyramidal microstructures.

[0095] As an optional technical solution of the present invention, Fig. 3 is an electron microscope photograph of a first texture structure 12 on the rear surface of a semiconductor substrate provided in an embodiment of the present invention. As shown in Fig. 3, the first texture structure 12 includes two or more first sub-structures 121 that are at least partially stacked.

[0096] FIG. 4a is a schematic diagram of an exemplary partially stacked three-layer first sub-structure, and FIG. 4b is a schematic diagram of an exemplary partially stacked two-layer first sub-structure.

[0097] The at least partially stacked two or more first sub-structures 121 have a distance H between the top surface 121a of the outermost first sub-structure and the top surface 121b of the adjacent first sub-structure in a direction far from the rear surface and perpendicular to the rear surface, which is 2 μm or less, and may be 2 μm, 1.8 μm, 1.5 μm, 1.2 μm, 1.1 μm, 1.0 μm, 0.8 μm, 0.5 μm, 0.3 μm, 0.2 μm, 0.1 μm, etc. If the distance H exceeds 2 μm, the roughness of the first texture structure is too large, and the thickness of the tunnel oxide layer 30 formed on the first texture structure becomes large, which is disadvantageous to the formation of a tunnel oxide layer with high density and high uniformity, and may further affect the tunnel effect and passivation effect of the tunnel oxide layer 30. Moreover, if the roughness of the first texture structure is too small, the thickness of the tunnel oxide layer formed on the first texture structure will be small, which is unfavorable for contact with the electrode paste.Preferably, in a direction far from the rear surface and perpendicular to the rear surface, a distance H between the top surface 121a of the outermost first substructure and the top surface 121b of the adjacent first substructure is in the range of 0.3 μm to 1.2 μm.

[0098] In the case of a stack of three first sub-structures, the distance H between the top surface 121a of any one of the first sub-structures and the top surface 121b of the adjacent first sub-structure is 2 μm or less.

[0099] As can be seen, by controlling the distance between top surface 121a of the outermost first sub-structure and top surface 121b of the adjacent first sub-structure to be 2 μm or less, the roughness of the first textured structure can be controlled within a desired range, which is beneficial for improving the uniformity of the tunnel oxide layer formed on the first textured structure, the performance of the formed tunnel oxide layer can be improved, and the increase in local phosphorus concentration due to phosphorus diffusion can be suppressed, the contact resistivity can be reduced, the open circuit voltage of the solar cell can be improved, and the fill factor and photoelectric conversion efficiency can be improved.

[0100] The one-dimensional dimension L of the top surface 121a of the outermost first substructure is 45 μm or less, and preferably, the one-dimensional dimension L is 2 μm to 45 μm. Here, the one-dimensional dimension L of the top surface may specifically be the length, width, or diagonal length of the surface, or the diameter in the case of a circle, and is not limited thereto. In some embodiments, the one-dimensional dimension refers to the average value of the one-dimensional dimensions of the top surfaces of a plurality of outermost first substructures within a predetermined range of an area on the rear surface of the substrate. The average one-dimensional dimension of the top surfaces of the outermost first substructures is specifically Alternatively, the average linear dimension of the top surface of the outermost first substructure may be in the range of 2 μm, 5 μm, 8 μm, 12 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, 30 μm, 35 μm, 40 μm, 42 μm, 40 μm or 45 μm, etc. Preferably, the average linear dimension of the top surface of the outermost first substructure is in the range of 10 μm to 15 μm.

[0101] In one specific embodiment, as shown in Fig. 3, the first texture structure further includes two or more second sub-structures 122 arranged adjacent to each other without being stacked. The first dimension L of the top surface of the second sub-structure 122 farther from the rear surface is 45μm or less. Preferably, the first dimension L of the second sub-structure 122 is in the range of 2μm to 45μm, and specifically may be 2μm, 5μm, 8μm, 12μm, 15μm, 18μm, 20μm, 25μm, 28μm, 30μm, 32μm, 35μm, 45μm, etc.

[0102] The top surface of the first sub-structure and / or the second sub-structure on the rear surface is a polygonal plane, unlike the typical pyramidal microstructure on the front surface. The shape of the polygonal plane includes at least one of a rhombus, a square, a trapezoid, an approximate rhombus, an approximate square, and an approximate trapezoid. As can be understood, in an actual manufacturing process, the shape of the top surface of the first sub-structure or the second sub-structure will be an irregular polygonal plane, but it can be said that the overall shape is similar to a rhombus, a square, or a trapezoid.

[0103] In step S40, a tunnel oxide layer is formed on the first textured structure on the rear surface of the semiconductor substrate.

[0104] In some possible embodiments, the semiconductor substrate may be subjected to a backside etch followed by processing using ozone oxidation, high temperature thermal oxidation, nitric acid oxidation, chemical vapor deposition, or low pressure chemical vapor deposition to form the tunnel oxide layer 30.

[0105] In some embodiments, a variable temperature process and chemical vapor deposition can be used to deposit the tunnel oxide layer 30 on the backside of the semiconductor substrate. During the deposition process, the heating rate is controlled to be 0.5° C. / min to 3° C. / min, the deposition temperature is controlled to be 560° C. to 620° C., and the deposition time is controlled to be 3 min to 10 min.

[0106] Specifically, during the deposition process, the deposition temperature may be 560°C, 570°C, 580°C, 590°C, 600°C, 610°C, 615°C, or 620°C, etc., the deposition time may be 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min, or 10 min, etc., and the heating rate may be 0.5°C / min, 0.8°C / min, 1.0°C / min, 1.2°C / min, 1.5°C / min, 2.0°C / min, 2.5°C / min, or 3°C / min, etc., but of course may be other values ​​within the above ranges and are not limited here.

[0107] Preferably, the tunnel oxide layer 30 is deposited on the rear surface of the semiconductor substrate by low pressure chemical vapor deposition, which can reduce the influence of a high local doping concentration of the thin tunnel oxide layer 30 during a subsequent high temperature doping process, thereby reducing the instability of the open circuit voltage. In addition, the tunnel oxide layer 30 deposited by a variable temperature process and low pressure chemical vapor deposition can increase the open circuit voltage of the solar cell by 4mV to 6mV.

[0108] The tunnel oxide layer 30 may be a laminated structure of one or more of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer. In other embodiments, the tunnel oxide layer 30 may be an oxygen-containing silicon nitride layer, an oxygen-containing silicon carbide layer, etc. The thickness of the tunnel oxide layer 30 is 0.8 nm to 2 nm. In practice, the thickness of the tunnel oxide layer 30 may be 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, or 2 nm. The thickness of the tunnel oxide layer 30 is the thickness relative to the surface on which the tunnel oxide layer is formed. The thickness of the tunnel oxide layer 30 formed on the first texture structure is obtained by observing and calculating the cross section with the normal direction of the slope of the substructure as the thickness direction. If the thickness of the tunnel oxide layer 30 is too large, it is disadvantageous to the reduction of the contact resistance of the tunnel oxide layer. By controlling the thickness of the tunnel oxide layer, the reduction of the fill factor caused by the contact resistance can be suppressed.

[0109] Specifically, the band gap width of the tunnel oxide layer 30 is greater than 3.0 eV. Although carriers are generally difficult to be transported by thermal radiation and pass through the tunnel oxide layer 30, when the tunnel oxide layer 30 is very thin, carriers can pass through the tunnel oxide layer 30 by tunnel effect, so a tunnel oxide layer with a thickness of 0.8 nm to 2 nm does not hinder the transport of majority carriers. As the thickness of the tunnel oxide layer gradually increases, the tunnel effect of majority carriers is affected, so that carriers are difficult to be transported and pass through the tunnel oxide layer 30, and the photoelectric conversion efficiency of the battery gradually decreases. If the thickness of the tunnel oxide layer is too small, it cannot play the role of passivation. Preferably, the tunnel oxide layer 30 is a silicon oxide layer with a thickness of 0.8 nm to 1.5 nm.

[0110] As an optional technical solution of the present application, as shown in Fig. 6, a thickness D1 of the tunnel oxide layer on the top surface of the outermost first sub-structure is smaller than a thickness D2 of the tunnel oxide layer formed on the side surface of the outermost first sub-structure. Specifically, the thickness difference (D2-D1) between the tunnel oxide layer on the top surface of the outermost first sub-structure and the tunnel oxide layer formed on the side surface of the outermost sub-structure is less than or equal to 0.15 nm. Specifically, the thickness difference may be 0.14 nm, 0.13 nm, 0.12 nm, 0.11 nm, 0.10 nm, 0.09 nm, 0.08 nm, 0.07 nm, 0.06 nm, 0.05 nm, 0.04 nm, etc. If the difference in thickness between the tunnel oxide layer on the top surface of the outermost first substructure and the tunnel oxide layer formed on the side surface of the outermost substructure is too large, the thickness uniformity of the tunnel oxide layer will be poor, the current density of the solar cell will be easily affected, and the open circuit voltage of the solar cell will be reduced.

[0111] In step S50, a polysilicon layer is deposited on the surface of the tunnel oxide layer, and the polysilicon layer is doped to form a doped conductive layer, the conductivity type of which is the same as that of the semiconductor substrate.

[0112] In some possible embodiments, a polysilicon layer is deposited on the surface of the tunnel oxide layer by one of physical vapor deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, and atomic layer deposition, which may be low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition.

[0113] In one specific embodiment, the deposition of the tunnel oxide layer and the polysilicon layer, and the doping of the polysilicon layer are all formed in a low pressure chemical vapor deposition system.

[0114] Specifically, the process comprises: First, the semiconductor substrate after alkali polishing is placed in a deposition apparatus, 20 L to 60 L of an oxygen source (which may be, for example, oxygen, nitrous oxide, or ozone) is flowed, the temperature in the deposition apparatus is heated to 560°C to 620°C at a temperature increase rate of 0.5°C / min to 3°C / min, and the deposition time is set to 3 min to 10 min, thereby forming a tunnel oxide layer 30; After flowing oxygen, a constant temperature stage is entered, and then an appropriate amount of silane gas is flowed to form a polycrystalline silicon layer; and Finally, the polysilicon layer is in-situ doped to form a doped conductive layer 4 This includes forming a 0.

[0115] In some embodiments, the doped conductive layer 40 may be a doped polycrystalline silicon layer, with the doped conductive layer 40 and the semiconductor substrate containing doping elements of the same conductivity type.

[0116] In another embodiment, a microcrystalline silicon layer or an amorphous silicon layer can be deposited on the surface of the tunnel oxide layer 30 and in-situ doped to form the doped conductive layer 40, which is a doped microcrystalline silicon layer or a doped amorphous silicon layer.

[0117] When the semiconductor substrate 10 is an N-type single crystal silicon substrate, the doped conductive layer 40 is an N-type doped polycrystalline silicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer, and the doping element may be an N-type doping element such as phosphorus.

[0118] In some embodiments, the doped conductive layer 40 has a thickness in the range of 60 nm to 200 nm, for example an N-type doped polycrystalline silicon layer, and has a refractive index in the range of 3.5 to 4.5.

[0119] After step S50 and before step S60, the method for manufacturing a solar cell further includes depositing an in-situ doped polycrystalline silicon layer, followed by a high temperature annealing process and a cleaning process.

[0120] In the embodiment of the present invention, the specific operation manner of the high temperature annealing and cleaning is not limited. For example, the high temperature annealing is applied to the deposited polycrystalline silicon layer, which can better crystallize the polycrystalline silicon layer, and the annealing temperature range may be 700°C to 1000°C.

[0121] A high-temperature annealing process diffuses pentavalent phosphorus atoms to form a doped polycrystalline silicon layer, and after annealing, the microcrystalline silicon phase in the crystalline silicon is transformed into a polycrystalline silicon phase, and phosphorus is deposited on the surface of the semiconductor substrate to form phosphosilicate glass (PSG).

[0122] The cleaning process is to remove the phosphosilicate glass layer (PSG) formed during the phosphorus doping process. As can be understood, when diffusing phosphorus, a phosphosilicate glass layer (PSG) is usually formed on the surface of the semiconductor substrate due to the high concentration of phosphorus, which has a gettering effect and affects the normal operation of the solar cell, so it needs to be removed.

[0123] In one specific embodiment, the semiconductor substrate is placed in a chain pickling machine (the belt speed of the chain pickling machine is 1.0 m / min-2.0 m / min) so that the rear surface of the semiconductor substrate faces downward. The semiconductor substrate enters an acid bath, and the phosphosilicate glass (PSG) layer formed by phosphorus diffusion on the rear surface is removed by etching. A prepared mixed acid is poured into the acid bath, and the mixed acid contains 2% by mass-10% by mass of hydrogen fluoride and 2% by mass-10% by mass of hydrogen chloride, the pickling temperature is 15°C-25°C, and the pickling time is about 30s-60s. The front surface of the semiconductor substrate is covered with a water film, and the borosilicate glass (BSG) layer on the front surface of the semiconductor substrate can also function as a protective layer, which can avoid the reaction of the front surface of the semiconductor substrate with the mixed acid during the removal process of the phosphosilicate glass (PSG) layer.

[0124] After the acid washing, water washing is necessary. The water washing time may be 10 to 20 seconds and the water washing temperature may be 15° C. to 25° C. Of course, after the water washing, the semiconductor substrate may be dried.

[0125] In step S60, a first passivation layer is formed on the front side of the semiconductor substrate.

[0126] In some embodiments, the first passivation layer 20 can be deposited by plasma-enhanced chemical vapor deposition, although other methods, such as organic chemical vapor deposition, may of course be used. The embodiments of the present invention are not limited to a specific embodiment of the first passivation layer 20.

[0127] The first passivation layer 20 may include, but is not limited to, a single layer or a laminated structure such as a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer. Of course, other passivation layers may be used as the first passivation layer, and the present invention does not limit the specific material constituting the first passivation layer. For example, in another embodiment, the first passivation layer may be a laminated structure of silica and silicon nitride. The first passivation layer provides a good passivation effect to the semiconductor substrate and helps improve the conversion efficiency of the battery.

[0128] In step S70, a second passivation layer is formed on the surface of the doped conductive layer.

[0129] The second passivation layer 50 may be deposited by plasma-assisted chemical vapor deposition, but other methods, such as organic chemical vapor deposition, may also be used. In the embodiments of the present invention, the specific embodiment of the second passivation layer 50 is not limited.

[0130] As an optional technical solution of the present invention, the second passivation layer 50 includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The thickness of the second passivation layer 50 is 70 nm to 120 nm. For example, the second passivation layer 50 is a silicon nitride layer, and the silicon nitride layer has a low silicon / nitrogen ratio, and its refractive index ranges from 1.7 to 2.1, and may be specifically 1.7, 1.8, 1.9, 2.0, or 2.1, etc., and may of course be other values ​​within the above range, and is not limited here. By controlling the refractive index of the silicon nitride layer and making it have a low silicon / nitrogen ratio, the formed second passivation layer 50 has a low contact resistivity during metallization processing, and can further reduce the contact resistivity of the solar cell.

[0131] In some embodiments, when the second passivation layer 50 is a stack of silicon nitride and silicon oxide layers, or a stack of silicon nitride and silicon oxynitride layers, the silicon nitride layer is located on top of the doped conductive layer, and the silicon oxide layer or silicon oxynitride layer is located on top of the silicon nitride layer.

[0132] Furthermore, after step S70, the method for manufacturing a solar cell further includes screen printing and sintering the semiconductor substrate to form an electrode.

[0133] In some embodiments, the solar cell further includes a first electrode 60 and a second electrode 70. The first electrode 60 penetrates the first passivation layer 20 to form an ohmic contact with a P-type doped layer (e.g., a boron-doped diffusion layer) on the front side of the semiconductor substrate 10, and the second electrode 70 penetrates the second passivation layer 50 to form an ohmic contact with the doped conductive layer 40, and the doped conductive layer 40 and the tunnel oxide layer 30 form a passivation contact structure. The first electrode 60 and the second electrode 70 can be formed by sintering a conductive metal paste applied to the surface of the first passivation layer and the second passivation layer. In some embodiments, the material constituting the first electrode 60 or the second electrode 70 can be a metal material such as silver, aluminum, copper, or nickel.

[0134] Solar cells according to Examples 1 to 13 and Comparative Examples 1 to 4 were manufactured based on the above-mentioned method. Specific process parameters are shown in Table 1.

[0135] [Table 1]

[0136] Table 2 shows the tunnel oxide layer and its structure in the solar cells produced in each Example and Comparative Example. The deposition process parameters of the polysilicon layer above are shown. Specifically, the processed silicon substrate was loaded into an LPCVD low pressure diffusion equipment, evacuated and heated, and an oxygen source gas (e.g., oxygen gas) that had reached the "temperature at the time of introducing the oxygen source gas" was introduced into the equipment, and three stages of oxidation were performed at oxidation temperatures 1, 2, and 3 for 1.2 minutes, 1.3 minutes, and 1.5 minutes, respectively, to form a tunnel oxide layer on the silicon substrate. After that, the oxygen source gas in the equipment was sucked out and replaced with a nitrogen gas atmosphere, and then silane gas that had been heated to the preliminary deposition temperature in the equipment and reached the "temperature at the time of introducing the silane gas" was introduced, and the introduced silane gas was decomposed and deposited for 18 minutes on the tunnel oxide layer of the silicon substrate that had reached the "deposition temperature of the polysilicon layer", forming a polysilicon layer.

[0137] [Table 2]

[0138] [Table 3]

[0139] From Examples 1 to 13, by controlling the distance between the substructures in the first texture structure on the rear surface of the semiconductor substrate within an appropriate range, it is possible to ensure that the roughness of the rear surface of the semiconductor substrate is within an appropriate range, which is beneficial to improving the uniformity of the tunnel oxide layer formed on the first texture structure, and the performance of the formed tunnel oxide layer is improved. Furthermore, it is possible to suppress the local doping concentration of the doped conductive layer from becoming high, effectively reduce the contact resistivity, improve the open circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency.

[0140] In the first textured structure in the solar cell of Comparative Example 1, the distance between the top surface of the outermost first substructure and the top surface of the adjacent first substructure in a direction farther from and perpendicular to the rear surface was greater than 2 μm. Also, the smaller the linear dimension of the top surface of the outermost first substructure, the thicker the deposited tunnel oxide layer was and the less uniform the tunnel oxide layer was, which resulted in a higher local doping concentration of the doped conductive layer formed on the surface of the tunnel oxide layer and a higher contact resistivity than in Example 1, which resulted in a lower open circuit voltage of the solar cell, as well as a lower fill factor and photoelectric conversion efficiency.

[0141] The solar cell of Comparative Example 2 did not undergo alkaline polishing treatment after texturing, and the rear surface had a pyramidal microstructure. The uniformity of the tunnel oxide layer deposited on the pyramidal microstructure was reduced, which tended to increase the local doping concentration of the doped conductive layer formed on the surface of the tunnel oxide layer, and the contact resistivity was higher than that of Example 1. As a result, the open circuit voltage of the solar cell was reduced, and the fill factor and photoelectric conversion efficiency were also reduced.

[0142] In the solar cell of Comparative Example 3, the process of forming the substructures in the first texture structure was able to suppress the local doping concentration of the doped conductive layer from becoming high, but the use of a silicon nitride layer with a high silicon / nitrogen ratio further reduced the contact resistivity during the metallization process. Compared with Example 1, by controlling the distance between the substructures in the first texture structure on the rear surface of the semiconductor substrate and controlling the refractive index of the second passivation layer, the two can exert a synergistic effect, which can better reduce the contact resistivity and improve the open circuit voltage, fill factor and photoelectric conversion efficiency of the solar cell.

[0143] In the solar cell of Comparative Example 4, the process of forming the substructure of the first texture structure was able to suppress high local doping concentrations in the doped conductive layer, but the contact resistivity was improved during the metallization process because a combination of an aluminum oxide layer and a silicon nitride layer with a low overall refractive index was used as the first passivation layer.

[0144] Although the preferred embodiment of the present invention has been disclosed as above, it is not intended to limit the scope of the claims. A person skilled in the art can make various changes and modifications without departing from the spirit of the present application, and therefore the scope of protection of the present application should be based on the scope defined in the appended claims.

Claims

1. A semiconductor substrate (10) having a first textured structure (12) on its rear surface and a second textured structure (11) on its front surface; a first passivation layer (20) located on the second textured structure (11) on the front side of the semiconductor substrate (10); a tunnel oxide layer (30) located on the first textured structure (12) at the rear surface of the semiconductor substrate (10); a doped conductive layer (40) located on the surface of said tunnel oxide layer (30); a second passivation layer (50) located on a surface of the doped conductive layer (40), The first texture structure (12) has a non-pyramidal microstructure and comprises two or more stepped first substructures (121), the top surface of the first substructures (121) being a polygonal plane; The second texture structure (11) includes a pyramidal microstructure having an apex far away from the front surface of the semiconductor substrate (10) and a bottom close to the front surface of the semiconductor substrate (10), and the distance between the apex and the bottom of the pyramidal microstructure in a direction far away from the front surface and perpendicular to the front surface is 5 μm or less.

2. 2. The solar cell of claim 1, wherein the two or more first substructures (121) have a distance between a top surface of an outermost first substructure (121) and a top surface of an adjacent first substructure (121) in a direction away from the rear surface and perpendicular to the rear surface, the distance being 2 μm or less.

3. 3. The solar cell of claim 1, wherein the thickness of the tunnel oxide layer (30) on the top surface of the outermost first substructure (121) is smaller than the thickness of the tunnel oxide layer (30) on the side surfaces of the outermost first substructure (121).

4. the tunnel oxide layer (30) comprises at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer; The solar cell according to any one of claims 1 to 3, wherein the tunnel oxide layer (30) has a thickness of between 0.8 nm and 2 nm.

5. the second passivation layer (50) comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer; The solar cell according to any one of the preceding claims, wherein the second passivation layer (50) has a thickness of 70 to 120 nm.

6. The solar cell according to any one of claims 1 to 5, wherein the first passivation layer (20) comprises at least one of a silicon oxide layer, a silicon nitride layer, an aluminium oxide layer, a silicon oxynitride layer.

7. The first passivation layer (20) has a laminated structure of an aluminum oxide layer and a silicon nitride layer, The solar cell according to any one of claims 1 to 6, wherein the aluminum oxide layer has a thickness of 2 nm to 10 nm, and the silicon nitride layer has a thickness of 50 nm to 110 nm.

8. The first passivation layer (20) has a sequentially stacked structure of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer, The solar cell according to any one of claims 1 to 7, wherein the aluminum oxide layer has a thickness range of 2 nm to 10 nm, the silicon nitride layer has a thickness range of 40 nm to 80 nm, and the silicon oxynitride layer has a thickness range of 10 nm to 60 nm.

9. The solar cell according to any one of the preceding claims, wherein the doped conductive layer (40) and the semiconductor substrate (10) comprise doping elements of the same conductivity type.

10. The semiconductor substrate (10) is an N-type single crystal silicon substrate, The solar cell according to any one of claims 1 to 9, wherein the doped conductive layer (40) is an N-type doped polycrystalline silicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped amorphous silicon layer.

11. The solar cell according to any one of the preceding claims, wherein the doped conductive layer (40) has a thickness of between 60 nm and 200 nm.

12. performing a texturing process on the semiconductor substrate to form a second texture structure on a front side of the semiconductor substrate; performing a doping process on the front surface of the semiconductor substrate after the texturing process to form a doped layer; performing a polishing process on the rear surface of the semiconductor substrate using an alkaline solution to form a first texture structure on the rear surface of the semiconductor substrate; forming a tunnel oxide layer on the first textured structure at the rear surface of the semiconductor substrate; forming a doped conductive layer on a surface of the tunnel oxide layer; forming a first passivation layer on the second textured structure on the front side of the semiconductor substrate; and 1. A method for manufacturing a solar cell, comprising forming a second passivation layer on a surface of the doped conductive layer, The second texture structure includes a pyramidal microstructure having an apex far away from the front surface of the semiconductor substrate and a bottom close to the front surface of the semiconductor substrate, and a distance between the apex and the bottom of the pyramidal microstructure in a direction far away from the front surface and perpendicular to the front surface is 5 μm or less; The method of manufacturing, wherein the first texture structure has a non-pyramidal microstructure and includes two or more stepped first substructures, the top surfaces of the first substructures being polygonal planes.

13. The polishing treatment of the rear surface of the semiconductor substrate using the alkaline solution includes: cleaning the rear surface of the semiconductor substrate with a 5% to 15% by weight alkaline solution to remove porous silicon; A roughening treatment is performed by dropping minute droplets of the alkaline solution onto the rear surface of the semiconductor substrate by a spray method, and then a preliminary cleaning is performed with 5% by mass to 10% by mass hydrofluoric acid; polishing the rear surface of the semiconductor substrate using a polishing solution containing 1% by mass to 15% by mass of NaOH, 1% by mass to 15% by mass of KOH, and 0.5% by mass to 2.5% by mass of an additive under conditions of a polishing temperature of 70° C. to 80° C. and a polishing time of less than 260 s; removing organic components contained in the polishing liquid using a mixed liquid containing 5% by mass to 15% by mass of potassium hydroxide and 15% by mass to 40% by mass of hydrogen peroxide; The method according to claim 12, further comprising washing the polished semiconductor substrate with water and drying the same.

14. The method according to claim 12 or 13, wherein the step of forming the tunnel oxide layer satisfies at least one of the following characteristics (1) to (4): (1) depositing the tunnel oxide layer on a first textured structure on a rear surface of the semiconductor substrate by a variable temperature process and a chemical vapor deposition method; (2) during the process of depositing the tunnel oxide layer, the heating rate is controlled to be 0.5°C / min to 3°C / min, the deposition temperature is controlled to be 560°C to 620°C, and the deposition time is controlled to be 3 min to 10 min; (3) the tunnel oxide layer includes at least one of a silicon oxide layer, an aluminum oxide layer, a silicon oxynitride layer, a molybdenum oxide layer, and a hafnium oxide layer; (4) The thickness of the tunnel oxide layer is 0.8 nm to 2 nm.

15. A solar cell module comprising a plurality of solar cell strings each including a plurality of solar cells according to any one of claims 1 to 11.

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