Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a rate of occurrence of SEB.SOLUTION: According to one embodiment, a semiconductor device 1 includes a semiconductor substrate 150 having an upper surface 151 and a lower surface 152, and emitter wiring 141. When viewed from the upper surface side 151, the semiconductor substrate 150 has an active region ACT including a plurality of IGBTs, a termination region TER, and a main junction region CON. The semiconductor substrate 150 of the main junction region CON has an N-type drift layer 153 and a P-type junction impurity layer 170. The semiconductor substrate 150 of the termination region TER has an N-type drift layer 153 and a P-type floating layer 190. At least the main junction region CON has a trench electrode 260 provided inside the trench, and a trench insulating film 265 provided between the trench electrode 260 and the semiconductor substrate 150. The trench electrode 260 and the P-type junction impurity layer 170 are connected to the emitter wiring 141.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, for example, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode), and a semiconductor device including an RC-IGBT (Reverse Conducting-IGBT). [Background technology]

[0002] Patent Document 1 describes a semiconductor device having an IGBT. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-079308 A Summary of the Invention [Problem to be solved by the invention]

[0004] Electric field concentration in a semiconductor device causes the occurrence of single event burn-out (hereinafter referred to as SEB) in the semiconductor device. There is a demand for a semiconductor device that can alleviate electric field concentration and reduce the occurrence rate of SEB.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, an emitter wiring provided on the first main surface via an insulating film, and a collector wiring provided on the second main surface, and when viewed from the first main surface side, the semiconductor substrate has an active region including a plurality of IGBTs formed in the semiconductor substrate, a termination region arranged to surround the active region, and a main junction region arranged between the active region and the termination region, and the semiconductor substrate in the main junction region has the drift layer of a first conductivity type and a collector wiring of a second conductivity type provided on the first main surface side of the drift layer. the semiconductor substrate in the termination region has the drift layer and the second conductivity type floating layer provided on the first main surface side of the drift layer, and at least the main junction region of the semiconductor substrate has a trench electrode provided inside a trench formed in the first main surface, and a trench insulating film provided between the trench electrode and the semiconductor substrate, and when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the active region toward the termination region, and the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region.

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, an emitter wiring provided on the first main surface via an insulating film, and a collector wiring provided on the second main surface, wherein when viewed from the first main surface side, the semiconductor substrate has an active region including a plurality of IGBTs formed in the semiconductor substrate, a termination region arranged to surround the active region, and a main junction region arranged between the active region and the termination region, the semiconductor substrate in the main junction region has the drift layer of a first conductivity type and a junction impurity layer of a second conductivity type provided on the first main surface side relative to the drift layer, the semiconductor substrate in the termination region has the drift layer and the floating layer of the second conductivity type provided on the first main surface side relative to the drift layer, and at least the main junction region of the semiconductor substrate is connected to a trench electrode provided inside a trench formed in the first main surface. and a trench insulating film provided between the trench electrode and the semiconductor substrate, wherein when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the active region toward the termination region, and the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region, and the IGBT includes the drift layer, the barrier layer of the first conductivity type provided on the first main surface side of the drift layer, the channel layer of the second conductivity type provided on the first main surface side of the barrier layer, the emitter layer of the first conductivity type provided on the first main surface side of the channel layer, gate trench electrodes provided to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in another direction intersecting the one direction in a plane parallel to the first main surface, and a gate trench insulating film provided between the gate trench electrode, the drift layer, the barrier layer, the channel layer, and the emitter layer. Effect of the Invention

[0008] According to the embodiment, it is possible to provide a semiconductor device capable of reducing the SEB occurrence rate. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device according to a reference example. [Diagram 2] 2 is a cross-sectional view illustrating a semiconductor device according to a reference example, taken along line II in FIG. [Diagram 3] 11 is a schematic diagram illustrating a simulation result of an electric field strength distribution when a reverse bias is applied to a collector in a semiconductor device according to a comparative example. FIG. [Figure 4] 4 is a schematic diagram illustrating a simulation result of an electric field strength distribution when a reverse bias is applied to a collector in a semiconductor device according to a comparative example, and is an enlarged view of a portion IV in FIG. [Diagram 5] 1 is a graph illustrating the electric field strength distribution when a reverse bias is applied to the collector in a semiconductor device of a comparative example, where the horizontal axis indicates the position in the direction from the active region to the termination region of the semiconductor device, and the vertical axis indicates the electric field strength. [Figure 6] 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Figure 7] 7 is a plan view illustrating a semiconductor device according to a comparative example, showing an enlarged view illustrating a portion VII of FIG. 6. [Figure 8] 8 is a cross-sectional view illustrating a main junction region and a termination region of a semiconductor device according to a comparative example, taken along line VIII-VIII in FIG. 7. [Figure 9] 8 is a cross-sectional view illustrating an IGBT formed on a semiconductor substrate in the semiconductor device according to Comparative Example 1, taken along line IX-IX in FIG. 7. [Figure 10] 7 is a plan view illustrating the semiconductor device according to the first embodiment, and is an enlarged view illustrating a portion X in FIG. 6. [Figure 11] 11 is a cross-sectional view illustrating the semiconductor device according to the first embodiment, taken along line XI-XI of FIG. [Figure 12] 12 is a cross-sectional view illustrating the semiconductor device according to the first embodiment, taken along line XII-XII in FIG. [Figure 13] 1 is a plan view illustrating a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 14] 14 is a cross-sectional view illustrating a semiconductor device according to Modification 1 of Embodiment 1, taken along line XIV-XIV of FIG. 13. [Figure 15] 11 is a plan view illustrating a semiconductor device according to Modification 2 of Embodiment 1. FIG. [Figure 16] 13 is a plan view illustrating a semiconductor device according to another example of Modification 2 of Embodiment 1. FIG. [Figure 17] 11 is a plan view illustrating a semiconductor device according to a third modified example of the first embodiment. FIG. [Figure 18] 11 is a plan view illustrating a simulation result of an electric field strength distribution at a boundary portion between a main junction region and a termination region in a semiconductor device according to a comparative example. FIG. [Figure 19] 4 is a plan view illustrating a simulation result of the electric field strength distribution at the boundary between the main junction region and the termination region in the semiconductor device according to the first embodiment. FIG. [Figure 20] 19 is a perspective view illustrating a simulation result of an electric field strength distribution at a boundary portion between a main junction region and a termination region in a semiconductor device according to a comparative example, showing a cross-sectional perspective view taken along line XX-XX in FIG. 18. [Figure 21] 20 is a perspective view illustrating a simulation result of an electric field strength distribution at a boundary portion between a main junction region and a termination region in the semiconductor device according to the first embodiment, showing a cross-sectional perspective view taken along line XXI-XXI in FIG. 19. [Figure 22] 11 is a cross-sectional view illustrating a simulation result of an electric field strength distribution at a boundary portion between a main junction region and a termination region in a semiconductor device according to a comparative example. [Figure 23] 4 is a cross-sectional view illustrating a simulation result of an electric field intensity distribution at a boundary portion between a main junction region and a termination region in the semiconductor device according to the first embodiment. FIG. [Figure 24]4 is a graph illustrating the electric field strength distribution of a semiconductor device according to a comparative example and a semiconductor device according to embodiment 1, in which the horizontal axis indicates the position at the boundary between a main junction region and a termination region, and the vertical axis indicates the electric field strength. [Diagram 25] 4 is a graph illustrating the collector breakdown voltage of the semiconductor device according to the comparative example and the semiconductor device according to the first embodiment, where the horizontal axis indicates the collector voltage and the vertical axis indicates the leakage current. [Figure 26] FIG. 11 is a plan view illustrating a semiconductor device according to a second embodiment. [Figure 27] 27 is a cross-sectional view illustrating the semiconductor device according to the second embodiment taken along line XXVII-XXVII of FIG. 26. [Figure 28] FIG. 11 is a plan view illustrating a semiconductor device 3 according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to clarify the explanation, the following description and drawings are omitted and simplified as appropriate. In addition, in the drawings, hatching and the like may be omitted even in cross sections when it would be too complicated or when the distinction from voids is clear. In addition, the same elements are given the same reference numerals in each drawing, and duplicate explanations are omitted as necessary. In addition, reference numerals are omitted as appropriate to avoid the drawings becoming too complicated.

[0011] First, in <Cosmic ray resistance>, the cosmic ray resistance of the semiconductor device with respect to the occurrence of SEB is described. In <Reference Example>, the semiconductor device according to the Reference Example is described. In <Problems newly found by the inventors>, the semiconductor device of the Comparative Example is described, and then the problems newly found by the inventors with respect to the semiconductor device of the Comparative Example are described. In <Embodiment 1>, the semiconductor device according to the Embodiment 1 is described. In this regard, the comparative example in <Semiconductor device of Comparative Example> is compared with the embodiment in <Semiconductor device of Embodiment 1>. After that, in <Embodiment 2> and <Embodiment 3>, the semiconductor device of each embodiment is described. Note that the cosmic ray resistance, the semiconductor devices according to the Reference Example and Comparative Example, and the problems newly found by the inventors are also within the scope of the technical ideas of the embodiments.

[0012] <Cosmic ray resistance> Power devices including IGBTs and diodes are required to have resistance to cosmic rays (also called cosmic radiation). For example, industrial and automotive products are required to have strict cosmic ray resistance of a few FIT / chip or less. Cosmic ray resistance is a probabilistic resistance to neutron rays.

[0013] When cosmic rays reach the Earth, they react with oxygen, nitrogen, etc. in the atmosphere, generating secondary particles. The secondary particles generated are still highly energetic and further react with oxygen, nitrogen, etc. in the atmosphere. This cascade reaction causes neutron rays to rain down on the Earth. Neutron rays can cause errors that cause semiconductor devices to malfunction.

[0014] For example, an error occurs in a semiconductor device due to the interaction between the semiconductor device and a high-energy neutron beam as shown below. That is, first, a high-energy neutron beam is incident on the semiconductor device. This causes a nuclear reaction between the neutron beam and the atoms that make up the semiconductor. Secondary particles are then generated. The generated secondary particles are incident on a sensitive region. This causes a single event phenomenon. The single event phenomenon is a general term for phenomena such as malfunction and damage caused by a single particle, including a proton or a heavy ion such as a He ion or Fe ion, being incident on a semiconductor element.

[0015] Such single event phenomena cause soft errors and hard errors. The main problem with power devices including IGBTs and diodes is hard errors including single event burn-out (hereinafter referred to as SEB). In short, cosmic rays are converted into high-energy neutron rays and then enter the semiconductor chip (neutron rays cannot be shielded). Then, the neutron rays that enter the high electric field region in the semiconductor chip generate secondary particles, which cause hard errors due to single event phenomena.

[0016] As the miniaturization of the manufacturing process of semiconductor devices progresses, the cosmic ray resistance of the semiconductor devices decreases, and therefore, one of the challenges is to improve the cosmic ray resistance against malfunctions caused by such neutron rays.

[0017] To improve the cosmic ray resistance, for example, there is a method of reducing the electric field strength by increasing the thickness of the n-type drift layer in the semiconductor chip. However, increasing the thickness of the semiconductor chip deteriorates the performance such as the collector-emitter saturation voltage VCE(sat) and switching (SW) loss. Therefore, there is a trade-off between the cosmic ray resistance and the performance of the power device.

[0018] <Reference example> A semiconductor device according to a reference example will be described. FIG. 1 is a plan view illustrating a semiconductor device 100 according to a reference example. FIG. 2 is a cross-sectional view illustrating the semiconductor device 100 according to the reference example, showing a cross section along line II in FIG. 1. As shown in FIGS. 1 and 2, the semiconductor device 100 of the reference example is formed in a semiconductor chip CP. The semiconductor chip CP includes, for example, a rectangular plate-shaped semiconductor substrate 150. The semiconductor substrate 150 has two plate surfaces and a chip end 150E. For convenience, the two plate surfaces are called an upper surface 151 and a lower surface 152.

[0019] Here, for convenience of explanation of the semiconductor device 100, etc., an XYZ Cartesian coordinate system is introduced. The direction perpendicular to the upper surface 151 is defined as the Z-axis direction, and the two directions perpendicular to the Z-axis direction are defined as the X-axis direction and the Y-axis direction. The direction from the lower surface 152 toward the upper surface 151 is defined as the +Z-axis direction. For convenience, the +Z-axis direction is defined as the upward direction, and the -Z-axis direction is defined as the downward direction. Note that the upward and downward directions are provided for convenience of explanation, and do not indicate the directions when the semiconductor device 100 is actually used.

[0020] The four sides of the rectangular plate form chip ends 150E of the semiconductor chip CP. When the semiconductor device 100 is viewed from the top surface 151 side, the semiconductor device 100 includes an active region ACT and a termination region TER. In the semiconductor device 100 of the reference example, the active region ACT is also called an active cell region. The semiconductor device 100 further has a gate pad GPD and an emitter pad EPD on the top surface 151.

[0021] The active area ACT is disposed in the center of the upper surface 151 of the semiconductor chip CP. The active area ACT includes semiconductor elements such as a plurality of IGBTs. In the active area ACT, the plurality of IGBTs are disposed in a matrix. The gates of the plurality of IGBTs are connected to a gate pass line GPL extending from a gate pad GPD. The emitters of the plurality of IGBTs are connected to an emitter pad EPD.

[0022] The termination region TER is disposed so as to surround the active region ACT. The termination region TER is disposed between the active region ACT and the chip end 150E.

[0023] As shown in FIG. 2, the semiconductor substrate 150 in the termination region TER has an FLR (Field Limiting Ring). Specifically, for example, the semiconductor substrate 150 in the termination region TER includes an N-type drift layer 153 including an N-epi layer, an N+ type field stop layer 157 including an N+ substrate, and a P++ type collector layer 158. The semiconductor substrate 150 in the termination region TER also has a plurality of FLRs on the N-type drift layer 153. The FLR includes a P-type floating layer. The P-type floating layer includes a P-type impurity layer. For example, the semiconductor device 100 includes seven FLRs consisting of seven P-type floating layers p1 to p7 in the termination region TER. By adding the FLR, the semiconductor device 100 can promote the extension of the depletion layer and maintain a high breakdown voltage. As a result, the semiconductor device 100 such as a power MOS often uses an FLR structure that allows a relatively easy high breakdown voltage even with a shallow junction.

[0024] <New problem discovered by the inventor> FIG. 3 is a schematic diagram illustrating a simulation result of an electric field strength distribution when a reverse bias is applied to the collector in the semiconductor device 101 according to the comparative example. FIG. 4 is a schematic diagram illustrating a simulation result of an electric field strength distribution when a reverse bias is applied to the collector in the semiconductor device 101 according to the comparative example, and is an enlarged view of a portion IV in FIG. 3. As shown in FIGS. 3 and 4 and FIGS. 7 and 8 described later, when the semiconductor device 101 according to the comparative example is viewed from the upper surface 151 side, the semiconductor substrate 150 has an active region ACT, a main junction region CON, and a termination region TER. As described later, the main junction region CON is disposed between the active region ACT and the termination region TER. The main junction region CON has a junction impurity layer connected to the emitter wiring.

[0025] 5 is a graph illustrating the electric field strength distribution when a reverse bias is applied to the collector in the semiconductor device 101 according to the comparative example, where the horizontal axis indicates the position in the X-axis direction from the active region ACT to the termination region TER of the semiconductor device 101, and the vertical axis indicates the electric field strength. As shown in FIGS. 3 to 5, the electric field strength in the semiconductor device 101 of the comparative example tends to be stronger in the main junction region CON and the termination region TER than in the active region ACT. The portions surrounded by the dotted line V in FIGS. 4 and 5 indicate the portions where the electric field strength is particularly high. When there is a path connected to the emitter wiring, such as the main junction region CON, the incidence of SEB may be high at such a location after the incidence of neutron rays.

[0026] Until now, it was believed that SEB occurred only in the active region ACT. However, SEB may also occur in the outermost periphery of the main junction region CON. This is believed to be because a path to the emitter wiring exists, which forms a high electric field region. The following embodiment solves at least one of the problems expected in the semiconductor device 101 of the comparative example.

[0027] <Embodiment 1> Next, a semiconductor device according to the first embodiment will be described. Fig. 6 is a plan view illustrating the semiconductor device 1 according to the first embodiment. As shown in Fig. 6, the semiconductor device 1 of this embodiment includes a semiconductor substrate 150 having an upper surface 151 (first main surface) and a lower surface 152 (second main surface). The upper surface 151 is the surface opposite to the lower surface 152. Note that Fig. 6 is used in the description of the semiconductor device 101 of the comparative example.

[0028] When the semiconductor device 1 is viewed from the top surface 151 side, the semiconductor substrate 150 has an active region ACT, a main junction region CON, and a termination region TER. The active region ACT includes a plurality of semiconductor elements such as IGBTs formed on the semiconductor substrate 150. The main junction region CON is disposed between the active region ACT and the termination region TER. The main junction region CON is disposed so as to surround the active region ACT. The termination region TER is disposed so as to surround the active region ACT and the main junction region CON.

[0029] Roughly speaking, the main junction region CON has a rectangular frame shape. The shape of the main junction region CON is not limited to a rectangular frame shape and may be changed according to the outer shape of the semiconductor device 1. In the following description, the shape of the main junction region CON is described as a rectangular frame shape. When viewed from the top surface 151 side, the main junction region CON includes a region 121, a region 122, a region 123, and a region 124.

[0030] Region 121 is a portion on the +Y-axis direction side of active region ACT. Region 121 extends in the X-axis direction. Region 121 is disposed between the end of active region ACT on the +Y-axis direction side in the Y-axis direction and termination region TER. Region 121 separates active region ACT and termination region TER in the Y-axis direction. Region 122 is a portion on the +X-axis direction side of active region ACT. Region 122 extends in the Y-axis direction. Region 122 is disposed between the end of active region ACT on the +X-axis direction side in the X-axis direction and termination region TER. Region 122 separates active region ACT and termination region TER in the X-axis direction.

[0031] The region 123 is a portion on the -Y-axis direction side of the active region ACT. The region 123 extends in the X-axis direction. The region 123 is disposed between the end of the active region ACT on the -Y-axis direction side in the Y-axis direction and the termination region TER. The region 123 separates the active region ACT and the termination region TER in the Y-axis direction. The region 124 is a portion on the -X-axis direction side of the active region ACT. The region 124 extends in the Y-axis direction. The region 124 is disposed between the end of the active region ACT on the -X-axis direction side in the X-axis direction and the termination region TER. The region 124 separates the active region ACT and the termination region TER in the X-axis direction. The regions 121 and 123 extending in the X-axis direction are called the first main junction portion, and the regions 122 and 124 extending in the Y-axis direction are called the second main junction portion.

[0032] Further, the main bonding region CON includes a corner 125 (third main bonding portion). The corner 125 includes a connection portion where the region 121 and the region 122 are connected, a connection portion where the region 122 and the region 123 are connected, a connection portion where the region 123 and the region 124 are connected, and a connection portion where the region 124 and the region 121 are connected. The corner 125 may be appropriately rounded with a corner R.

[0033] The termination region TER has a rectangular frame shape. The shape of the termination region TER is not limited to a rectangular frame shape, and may be changed according to the outer shapes of the semiconductor device 1 and the main junction region CON, etc. In the following, the shape of the termination region TER will be described as a rectangular frame shape. When viewed from the top surface 151 side, the termination region TER includes a region 131, a region 132, a region 133, and a region 134.

[0034] Region 131 is a portion on the +Y-axis direction side of region 121. Region 131 extends in the X-axis direction. Region 131 sandwiches region 121 between it and active region ACT in the Y-axis direction. Region 132 is a portion on the +X-axis direction side of region 122. Region 132 extends in the Y-axis direction. Region 132 sandwiches region 122 between it and active region ACT in the X-axis direction.

[0035] Region 133 is a portion on the -Y-axis direction side of region 123. Region 133 extends in the X-axis direction. Region 133 sandwiches region 123 between it and active region ACT in the Y-axis direction. Region 134 is a portion on the -X-axis direction side of region 124. Region 134 extends in the Y-axis direction. Region 134 sandwiches region 124 between it and active region ACT in the X-axis direction. Regions 131 and 133 extending in the X-axis direction are called a first termination portion, and regions 132 and 134 extending in the Y-axis direction are called a second termination portion.

[0036] Further, the termination region TER includes a corner 135 (third termination portion). The corner 135 includes a connection portion where the region 131 and the region 132 are connected, a connection portion where the region 132 and the region 133 are connected, a connection portion where the region 133 and the region 134 are connected, and a connection portion where the region 134 and the region 131 are connected. The corner 135 may be appropriately rounded with a corner R.

[0037] In the semiconductor device 1 of this embodiment, a main junction region CON is arranged in a region surrounding an active region ACT so as to be connected to a termination region TER.

[0038] Next, the configuration of the semiconductor device 1 according to this embodiment will be described in comparison with the configuration of a semiconductor device 101 according to a comparative example. First, the configuration of the semiconductor device 101 according to the comparative example will be described.

[0039] <Semiconductor device of comparative example> Fig. 7 is a plan view illustrating a semiconductor device 101 according to a comparative example, and shows an enlarged view illustrating part VII of Fig. 6. Fig. 8 is a cross-sectional view illustrating a main junction region CON and a termination region TER of the semiconductor device 101 according to the comparative example, and shows a cross-section along line VIII-VIII of Fig. 7. Fig. 9 is a cross-sectional view illustrating an IGBT 10a in an active region ACT of the semiconductor device 101 according to the comparative example, and shows a cross-section along line IX-IX of Fig. 7.

[0040] 7 to 9, the semiconductor device 101 of the comparative example has an active region ACT, a main junction region CON, and a termination region when viewed from above. The semiconductor device 101 includes an emitter wiring 141, a gate wiring 147, and a termination wiring 181 provided on an upper surface 151 of a semiconductor substrate 150 via an insulating film 164. The emitter wiring 141, the gate wiring 147, and the termination wiring 181 may be aluminum wiring containing aluminum (Al).

[0041] <Active area> For example, a plurality of IGBTs 10a are formed in the semiconductor substrate 150 of the active region ACT. In the active region ACT of FIG. 7, the gate trench electrodes 160 of the plurality of IGBTs 10a are shown in a simplified schematic manner. As shown in FIG. 9, for example, the IGBT 10a has an N-type drift layer 153, an N+ type barrier layer 154, a P type channel layer 155, an N+ type emitter layer 156, a gate trench electrode 160, a gate trench insulating film 165, an N+ type field stop layer 157, a P++ type collector layer 158, and a P type floating layer 159. Note that the IGBT 10a may further include other members in addition to these members, or some of these members may be omitted. To avoid complication of the figure, the gate trench insulating film 165 and the insulating film 164 on the semiconductor substrate 150 are shown by thick lines. The P type floating layer 159 may be called an IGBT floating layer.

[0042] In addition, N++ type and P++ type respectively indicate low resistance N conductivity type and P conductivity type. N+ type and P+ type respectively indicate higher resistance than N++ type and P++ type, but lower resistance than N type and P type. P- type and N- type respectively indicate higher resistance N conductivity type and P conductivity type than N type and P type. Therefore, N type and P type respectively indicate N conductivity type and P conductivity type of resistance between N+ type and P+ type and P- type and N- type. N+ type and P+ type respectively indicate N conductivity type and P conductivity type of resistance between N++ type and P++ type and P type and N type. Hereinafter, the same meaning is shown unless otherwise specified. N conductivity type may be called the first conductivity type, and P conductivity type may be called the second conductivity type.

[0043] The N-type conductivity may be the second conductivity type, and the P-type conductivity may be the first conductivity type. A semiconductor device in which the conductivity types of the configurations of the present disclosure are reversed is also included in the scope of the technical concept of the present disclosure. Furthermore, the resistances of the N++, N+, N, and N-type semiconductor layers are examples. They may be larger than the resistances shown in the present disclosure, or may be smaller than the resistances shown in the present disclosure. Similarly, the resistances of the P++, P+, P, and P-type semiconductor layers are examples. The magnitude relationship of the resistances of the semiconductor layers may be reversed in some cases.

[0044] The N- type drift layer 153 is provided on the upper surface 151 side of the N+ type field stop layer 157. The N- type drift layer 153 is provided across the active region ACT, the main junction region CON, and the termination region TER.

[0045] The N+ type barrier layer 154 is provided closer to the upper surface 151 than the N- type drift layer 153. The N+ type barrier layer 154 extends, for example, in the Y-axis direction when viewed from the upper surface 151 side. The N+ type barrier layer 154 is sandwiched between the gate trench electrodes 160 from both sides in the X-axis direction. That is, the N+ type barrier layer 154 is disposed inside the gate trench electrodes 160.

[0046] The P-type channel layer 155 is provided on the upper surface 151 side of the N+ type barrier layer 154. The P-type channel layer 155 is sandwiched between gate trench electrodes 160 on both sides in the X-axis direction. The P-type channel layer 155 is connected to the emitter wiring 141 filled in a through hole penetrating the insulating film 164 and the N+ type emitter layer 156.

[0047] The N+ type emitter layer 156 is provided on the upper surface 151 side of the P type channel layer 155. The N+ type emitter layer 156 is disposed inside the gate trench electrode 160. The N+ type emitter layer 156 is connected to an emitter wiring 141 filled in a through hole penetrating the insulating film 164.

[0048] The pair of gate trench electrodes 160 are provided to sandwich the N+ type barrier layer 154, the P type channel layer 155, and the N+ type emitter layer 156 from both sides in the X-axis direction. Each gate trench electrode 160 includes, for example, a portion extending in the Y-axis direction when viewed from the upper surface 151 side. For example, of the pair of gate trench electrodes 160, the gate trench electrode 160 on the -X-axis direction side is referred to as the gate trench electrode 161, and the gate trench electrode 160 on the +X-axis direction side is referred to as the gate trench electrode 162. Thus, the pair of gate trench electrodes 160 of the IGBT 10a includes the gate trench electrode 161 and the gate trench electrode 162.

[0049] The gate trench electrode 161 is connected to, for example, the gate wiring 147. The gate trench electrode 162 is connected to the emitter wiring 141 filled in a through hole penetrating the insulating film 164. Thus, the N+ type emitter layer 156, the P type channel layer 155, and the gate trench electrode 162 are connected to the emitter wiring 141. The structure between a pair of gate trench electrodes 160 is called an inter-trench structure. For example, the inter-trench structure of the IGBT 10a includes the N+ type barrier layer 154, the P type channel layer 155, and the N+ type emitter layer 156. The inter-trench structure of the IGBT 10a may include other members such as a contact layer.

[0050] The P-type floating layer 159 is provided between adjacent IGBTs 10a among the multiple IGBTs 10a. For example, the P-type floating layer 159 is provided between a gate trench electrode 162 of the IGBT 10a on the −X-axis direction side and a gate trench electrode 161 of the IGBT 10a on the +X-axis direction side among the adjacent IGBTs 10a. The P-type floating layer 159 is provided on the opposite side of the gate trench electrode 160 to the N+ type barrier layer 154, the P-type channel layer 155, and the N+ type emitter layer 156.

[0051] The P-type floating layer 159 is provided closer to the upper surface 151 than the N-type drift layer 153. Thus, on the N-type drift layer 153, from the -X-axis direction side, the P-type floating layer 159, the gate trench electrode 161 (covered with a gate trench insulating film 165), the trench-to-trench structure, the gate trench electrode 162 (covered with a gate trench insulating film 165), and the P-type floating layer 159 are arranged along the X-axis direction. In the active region ACT, such a configuration is arranged so as to be repeated in the X-axis direction.

[0052] The P-type floating layer 159 between the P-type floating layer 159 at the end of the active region ACT in the +X-axis direction in the X-axis direction and the P-type floating layer 159 at the end of the active region ACT in the -X-axis direction in the X-axis direction is in contact with the gate trench electrode 161 and the gate trench electrode 162. In other words, the P-type floating layer 159 is formed between adjacent IGBTs 10a in the areas other than the end of the active region ACT in the X-axis direction.

[0053] The gate trench insulating film 165 is provided between the gate trench electrode 160 and the semiconductor substrate 150. Specifically, the gate trench insulating film 165 is provided between the gate trench electrode 160 and the N- type drift layer 153, the N+ type barrier layer 154, the P type channel layer 155, the N+ type emitter layer 156, and the P type floating layer 159.

[0054] The N+ type field stop layer 157 is provided closer to the lower surface 152 than the N- type drift layer 153. The P++ type collector layer 158 is provided closer to the lower surface 152 than the N+ type field stop layer 157. The P++ type collector layer 158 is connected to a collector wiring. Note that the collector wiring is omitted to avoid complicating the drawing.

[0055] <Main joint area> The semiconductor substrate 150 of the main junction region CON has an N-type drift layer 153, an N+ type field stop layer 157, a P++ type collector layer 158, and a P type junction impurity layer 170. The semiconductor substrate 150 of the main junction region CON may further include other members in addition to these members, or some of these members may be omitted. The P type junction impurity layer 170 is provided on the upper surface 151 side of the N- type drift layer 153. The N+ type field stop layer 157 is provided on the lower surface 152 side of the N- type drift layer 153. The P++ type collector layer 158 is provided on the lower surface 152 side of the N+ type field stop layer 157.

[0056] The P-type junction impurity layer 170 is connected to the emitter wiring 141 in the main junction region CON. The emitter wiring 141 has, for example, a main body portion 142 and a contact 143. The contact 143 is a portion of the emitter wiring 141 that is connected to the P-type junction impurity layer 170. The P-type junction impurity layer 170 is connected to the emitter wiring 141 via the contact 143. Note that, although the contact 143 in FIGS. 7 and 8 is composed of three portions, the present invention is not limited thereto and may be composed of one portion or a plurality of portions other than three.

[0057] <Termination area> The semiconductor substrate 150 in the termination region TER has an N-type drift layer 153, an N+ type field stop layer 157, a P++ type collector layer 158, and a plurality of P type floating layers 190. The plurality of P type floating layers 190 are provided on the upper surface 151 side of the N- type drift layer 153. The N+ type field stop layer 157 is provided on the lower surface 152 side of the N- type drift layer 153. The P++ type collector layer 158 is provided on the lower surface 152 side of the N+ type field stop layer 157. The plurality of P type floating layers 190 form an FLR.

[0058] The P-type floating layer 190 is connected to the termination wiring 181 in the termination region TER. The termination wiring 181 has, for example, a main body 182 and a contact 183. The contact 183 is a portion of the termination wiring 181 that connects to the P-type floating layer 190. The P-type floating layer 190 is connected to the termination wiring 181 via the contact 183.

[0059] The P-type floating layer 190a closest to the main junction region CON in the termination region TER is called the first ring layer p1. The second P-type floating layer 190b from the main junction region CON in the termination region TER is called the second ring layer p2. Similarly, the k-th P-type floating layer 190 from the main junction region CON in the termination region TER is called the k-th ring layer pk.

[0060] The termination wiring 181 is not formed on the first ring layer p1, i.e., on the P-type floating layer 190a. Therefore, the P-type floating layer 190a constituting the first ring layer p1 is not connected to the termination wiring 181. On the other hand, the termination wiring 181 is formed on the second ring layer p2 (P-type floating layer 190b), the third ring layer p3, and the kth ring layer pk. The P-type floating layers 190 other than the P-type floating layer 190a are connected to the termination wiring 181 via contacts 183.

[0061] The termination wiring 181 is not connected to the emitter wiring 141 and is in a floating state. Therefore, the P-type floating layer 190 constituting the FLR is in a floating state. In this manner, the P-type floating layer 190 is not connected to the emitter wiring 141 in the termination region TER.

[0062] <Semiconductor device according to embodiment 1> Next, the semiconductor device of the first embodiment will be described. Fig. 10 is a plan view illustrating the semiconductor device 1 according to the first embodiment, and an enlarged view illustrating the X portion of Fig. 6. Fig. 11 is a cross-sectional view illustrating the semiconductor device 1 according to the first embodiment, and shows a cross section taken along line XI-XI in Fig. 10. Fig. 12 is a cross-sectional view illustrating the semiconductor device 1 according to the first embodiment, and shows a cross section taken along line XII-XII in Fig. 10. Figs. 10 and 11 also show enlarged views of a portion of the main junction region CON.

[0063] As shown in FIG. 10, the semiconductor device 1 of this embodiment has an active region ACT, a main junction region CON, and a termination region as seen from above, similar to the semiconductor device 101 of the comparative example. In the semiconductor device 1 of this embodiment, at least the main junction region CON of the semiconductor substrate 150 has a trench electrode 260 and a trench insulating film 265. In FIG. 10, the trench electrode 260 and the trench insulating film 265 are shown by lines so as not to make the drawing complicated. One line indicates the trench electrode 260 and the trench insulating film 265. Therefore, in the drawing, the trench electrode 260 is a rectangular ring. That is, when viewed from the top surface 151 side, the trench electrode 260 is, for example, a ring in which both ends of two parts extending in the X-axis direction are connected.

[0064] In the figure, the trench electrode 260 is formed in the region 122 and the region 132 on the +X-axis direction side of the active region ACT, but it may be formed in the region 124 and the region 134 on the -X-axis direction side of the active region ACT.

[0065] <Trench electrode> As shown in FIGS. 10 to 12, the trench electrode 260 is provided inside a trench formed on the upper surface 151 of the semiconductor substrate 150. The trench insulating film 265 is provided between the trench electrode 260 and the semiconductor substrate 150. When viewed from the upper surface 151 side, the trench electrode 260 includes a portion extending in the X-axis direction from the main junction region CON toward the termination region TER. Specifically, one end of the trench electrode 260 in the X-axis direction is located in the main junction region CON, and the other end is located in the termination region TER. For example, the end of the trench electrode 260 on the −X-axis direction side is located in the P-type junction impurity layer 170 of the main junction region CON, and the end of the trench electrode 260 on the +X-axis direction side is located in the P-type floating layer 190a of the termination region TER. The cross-sectional shapes of the trench electrode 260 in FIGS. 11 and 12 are both schematic diagrams.

[0066] The termination region TER has a plurality of P-type floating layers 190 including a portion extending in the Y-axis direction. As described above, among the plurality of P-type floating layers 190 in the termination region TER, the P-type floating layer 190a closest to the main junction region CON is defined as the first P-type floating layer. The P-type floating layer 190b adjacent to the first P-type floating layer is defined as the second P-type floating layer. In this case, the end of the trench electrode 260 on the termination region TER side is located in the first P-type floating layer (190a).

[0067] 11 and 12, the lower end of the trench electrode 260, i.e., the end of the trench electrode 260 on the −Z axis direction side, is located in the P-type junction impurity layer 170 and the P-type floating layer 190a. The lower end of the trench electrode 260 may be located in the N-type drift layer 153.

[0068] The trench electrode 260 is connected to the emitter wiring 141 in the main junction region CON. The emitter wiring 141 further has a contact 144. The contact 144 may include a first contact 145 and a second contact 146. The contact 144 may be called an emitter contact. The first contact 145 and the second contact 146 may be called a first emitter contact and a second emitter contact, respectively. The first contact 145 is connected to the P-type junction impurity layer 170 and the trench electrode 260 inside the annular trench electrode 260. The second contact 146 is connected to the P-type junction impurity layer 170 between the annular trench electrodes 260 adjacent to each other in the Y-axis direction.

[0069] The first contact 145 and the second contact 146 are formed within the range of the main junction region CON. The first contact 145 and the second contact 146 are not formed in the P-type floating layer 190a in the termination region TER.

[0070] The semiconductor substrate 150 in the main junction region CON may have a P-type contact layer 174 provided on the upper surface 151 side of the P-type junction impurity layer 170. The P-type contact layer 174 contains a higher concentration of P-type impurities than the P-type junction impurity layer 170. The P-type contact layer 174 may include a first contact layer 175 and a second contact layer 176. The P-type contact layer 174 may be referred to as an emitter contact layer. The first contact layer 175 and the second contact layer 176 may be referred to as a first emitter contact layer and a second emitter contact layer, respectively.

[0071] The first contact layer 175 is disposed inside the annular trench electrode 260. The second contact layer 176 is disposed between the annular trench electrodes 260 adjacent to each other in the Y-axis direction. The first contact 145 is connected to the P-type junction impurity layer 170 via the first contact layer 175. The second contact 146 is connected to the P-type junction impurity layer 170 via the second contact layer 176. The upper end of the trench electrode 260 on the +Z-axis direction side has a step with respect to the lower end of the first contact 145 on the -Z-axis direction side. The trench electrode 260 is connected to the emitter wiring via the step. This allows the trench electrode 260 to have a large contact area with the emitter wiring 141.

[0072] The contact 144 is connected to the P-type junction impurity layer 170 and also to the trench electrode 260. As a result, the trench electrode 260 is connected to the emitter wiring 141. In this way, the semiconductor device 1 of this embodiment has the trench electrode 260 of the emitter potential connected to the emitter wiring 141 at least in the main junction region CON. The semiconductor device 1 has the contact 144 for fixing the trench electrode 260 to the emitter potential. The semiconductor device 1 also has the contact 144 for enhancing hole discharge at the time of turn-off. In this way, the semiconductor device 1 can suppress the occurrence of SEB due to electric field relaxation by forming the contact 144 connected to the emitter wiring 141. This can improve the cosmic ray resistance, as well as the collector breakdown voltage and hole discharge effect. In this way, the semiconductor device 1 can suppress current concentration and improve the breakdown resistance (Reverse Bias Safe Operating Area, hereinafter referred to as RBSOA).

[0073] <Variation 1> Fig. 13 is a plan view illustrating a semiconductor device 1a according to Modification 1 of Embodiment 1. Fig. 14 is a cross-sectional view illustrating the semiconductor device 1a according to Modification 1 of Embodiment 1, taken along line XIV-XIV in Fig. 13. Fig. 14 also shows an enlarged view of a portion of the main junction region CON.

[0074] As shown in FIGS. 13 and 14, in the semiconductor device 1a according to the first modification, the contact 144 is formed across a plurality of annular trench electrodes 260 arranged in the Y-axis direction and the P-type junction impurity layer 170. The upper end of the trench electrode 260 is formed flat so as to coincide with the upper surface 151 of the semiconductor substrate 150. As a result, the contact 144 is connected to the P-type junction impurity layer 170 via the first contact layer 175 and the second contact layer 176. The upper end of the trench electrode 260 on the +Z-axis direction side is connected to the lower end of the contact 144. By arranging the contact 144 formed across the plurality of annular trench electrodes 260 and the P-type junction impurity layer 170, the contact area can be increased and the manufacturing process can be facilitated.

[0075] <Variation 2> Fig. 15 is a plan view illustrating a semiconductor device 1b according to Modification 2 of the first embodiment. As shown in Fig. 15, in the semiconductor device 1b of Modification 2, a trench electrode 260 is formed in a region 121 and a region 131 arranged on the +Y-axis direction side of the active region ACT. The trench electrode 260 includes a portion extending in the Y-axis direction from the active region ACT toward the termination region TER. The trench electrode 260 may be formed in a region 123 and a region 133 arranged on the -Y-axis direction side of the active region ACT.

[0076] In this modification, when viewed from the top surface 151 side, the trench electrode 260 includes a portion extending in a direction from the main junction region CON toward the termination region TER, but the trench electrode 260 extends in the Y-axis direction. Specifically, one end of the trench electrode 260 in the Y-axis direction is located in the main junction region CON, and the other end is located in the termination region TER. For example, the end of the trench electrode 260 on the -Y-axis direction side is located in the P-type junction impurity layer 170 of the main junction region CON, and the end of the trench electrode 260 on the +Y-axis direction side is located in the P-type floating layer 190a of the termination region TER.

[0077] In the region 131, the termination region TER has a plurality of P-type floating layers 190 including a portion extending in the X-axis direction. Of the plurality of P-type floating layers 190 in the termination region TER, the P-type floating layer 190a closest to the main junction region CON is defined as a first P-type floating layer. When the P-type floating layer 190b adjacent to the first P-type floating layer is defined as a second P-type floating layer, the end of the trench electrode 260 on the termination region TER side is located in the first P-type floating layer.

[0078] When viewed from the top surface 151 side, the semiconductor substrate 150 has a gate wiring region GAT disposed between the main junction region CON and the active region ACT in the Y-axis direction. In the gate wiring region GAT, a gate wiring 147 is disposed on the top surface 151 of the semiconductor substrate 150 via an insulating film 164. The gate trench electrode 161 of the IGBT 10a is connected to the gate wiring 147 in the gate wiring region GAT.

[0079] The trench electrode 260 may extend to the gate wiring region GAT in the Y-axis direction or to the termination region TER, as long as it is disposed at least in the main junction region CON. The trench electrode 260 may also be disposed only in the main junction region CON.

[0080] In the semiconductor device 1b of the second modification, the contact 144 of the emitter wiring 141 may also have a first contact 145 and a second contact 146. The contact 144 may also be connected to a plurality of annular trench electrodes 260 and a P-type junction impurity layer 170.

[0081] FIG. 16 is a plan view illustrating a semiconductor device 1bb according to another example of the second modification of the first embodiment. As shown in FIG. 16, the semiconductor device 1bb may not include the contact 144. Since the semiconductor device 1bb has the gate wiring 147, a current flows through a path as shown by the arrow XV in the figure. If such a current causes an effect of potential fluctuation, the contact 144 of the emitter wiring 141 may be reduced. Although the carrier extraction effect is reduced, the dynamic avalanche is suppressed by the electric field relaxation effect. Therefore, the RBSOA resistance can be improved compared to the semiconductor device 101 of the comparative example.

[0082] <Modification 3> FIG. 17 is a plan view illustrating a semiconductor device 1c according to Modification 3 of the first embodiment. As shown in FIG. 17, in the semiconductor device 1c of Modification 3, the trench electrode 260 is formed at the corner 125. The trench electrode 260 includes a portion extending in the X-axis direction or the Y-axis direction at the corner 125. The trench electrode 260 may include a portion extending from the corner 125 to the corner 135. The trench electrode 260 may also include a portion extending from the corner 125 to the gate wiring region GAT. By disposing the trench electrode 260 at the corner 125, the electric field at the corner 125 of the semiconductor device 1c can be alleviated.

[0083] If there is a possibility that the shape of the FLR in the termination region TER may be affected, it is desirable to optimize the structures of the trench electrode 260 and the FLR. Furthermore, the trench electrode 260 is not limited to a shape including a portion extending in the X-axis direction or the Y-axis direction, and may be curved to match the shape of the FLR.

[0084] Next, the effects of this embodiment will be described. In the semiconductor devices 1, 1a, 1b, 1bb, and 1c (hereinafter referred to as semiconductor device 1) of this embodiment, the trench electrode 260 and the P-type junction impurity layer 170 in the main junction region CON are connected to the emitter wiring 141. As a result, the semiconductor device 1 can form a hole discharge path in the main junction region CON and improve the hole discharge effect. Therefore, local current concentration can be suppressed and the RBSOA resistance can be improved. The semiconductor device 1 of this embodiment has an electric field relaxation effect in the highest electric field region shown in, for example, the above-mentioned FIGS. 3 to 5. As a result, the breakdown voltage can be improved by the relaxation effect against the critical electric field.

[0085] 18 and 19 are plan views illustrating simulation results of the electric field intensity distribution at the boundary between the main junction region CON and the termination region TER in the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, respectively. Fig. 20 and Fig. 21 are perspective views illustrating simulation results of the electric field intensity distribution at the boundary between the main junction region CON and the termination region TER in the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, respectively, and show a cross-sectional perspective view taken along the line XX-XX in Fig. 18 and a cross-sectional perspective view taken along the line XXI-XXI in Fig. 19. Fig. 22 and Fig. 23 are cross-sectional views illustrating simulation results of the electric field intensity distribution at the boundary between the main junction region CON and the termination region TER in the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, respectively.

[0086] 18, 20, and 22, in the P-type junction impurity layer 170 of the main junction region CON of the semiconductor device 101 according to the comparative example, a plurality of contact grooves connected to the contacts 143 of the emitter wiring 141 are high electric field regions. On the other hand, as shown in Fig. 19, 21, and 23, the semiconductor device 1 according to this embodiment has a trench electrode 260 connected to the emitter wiring 141 in addition to a plurality of contact grooves connected to the contacts 144 of the emitter wiring 141 in the P-type junction impurity layer 170 of the main junction region CON. This makes it possible to relax the electric field in the P-type junction impurity layer 170 of the main junction region CON.

[0087] 24 is a graph illustrating the electric field intensity distribution of the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the embodiment 1, where the horizontal axis indicates the position at the boundary between the main junction region CON and the termination region TER, and the vertical axis indicates the electric field intensity. As shown in FIG. 24, in the semiconductor device 101 of the comparative example, the electric field intensity in the main junction region CON is much higher than that in the termination region TER.

[0088] In contrast, in the semiconductor device 101 of the first embodiment, the electric field strength in the main junction region CON is reduced compared to the comparative example, and the electric field strength in the termination region TER is higher than the comparative example. As a result, the difference in electric field strength between the main junction region CON and the termination region TER of the semiconductor device 1 of the first embodiment is reduced. In this way, the semiconductor device 1 of the first embodiment can alleviate the electric field concentration in the main junction region CON.

[0089] 25 is a graph illustrating the collector breakdown voltage of the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the embodiment 1, where the horizontal axis indicates the collector voltage VC and the vertical axis indicates the leakage current ICES. As shown in FIG. 25, the collector breakdown voltage of the semiconductor device 1 according to the embodiment 1 can be significantly improved compared to the semiconductor device 101 according to the comparative example.

[0090] In the semiconductor device 1 of this embodiment, the electric field relaxation structure is due to the emitter potential trench electrode 260. Therefore, even if hot carriers are generated, there is no influence on the fluctuation of the characteristics of the emitter potential trench electrode 260.

[0091] <Embodiment 2> Next, a semiconductor device according to a second embodiment will be described. FIG. 26 is a plan view illustrating a semiconductor device 2 according to the second embodiment. FIG. 27 is a cross-sectional view illustrating a semiconductor device 2 according to the second embodiment, taken along the line XXVII-XXVII in FIG. 26. FIGS. 26 and 27 also show enlarged views of a portion of the termination region TER. As shown in FIGS. 26 and 27, in the semiconductor device 2, the end of the trench electrode 260 on the termination region TER side is located in the second P-type floating layer 190b from the main junction region CON side.

[0092] The P-type floating layer 190b is connected to the termination wiring 181 via a contact 184. The contact 184 includes a first contact 185 and a second contact 186. The first contact 185 is connected to the P-type floating layer 190b inside the annular trench electrode 260. The second contact 186 is connected to the P-type floating layer 190b between adjacent annular trench electrodes 260.

[0093] The first contact 185 is not connected to the trench electrode 260. The trench electrode 260 is connected to the first contact 145 or the contact 144 in the main junction region CON. On the other hand, the trench electrode 260 is not connected to the first contact 185 in the termination region TER. Therefore, the trench electrode 260 can maintain the emitter potential. Also, the termination wiring 181 including the first contact 185 can be maintained floating.

[0094] In the semiconductor device 2, the contact 184 including the first contact 185 and the second contact 186 extends in the X-axis direction in which the trench electrode 260 extends. This prevents the P-type floating layer 190b from being connected to the trench electrode 260, and prevents the P-type floating layer 190b from becoming at the emitter potential.

[0095] The semiconductor substrate 150 in the termination region TER may have a P-type contact layer 194 provided on the upper surface 151 side of the P-type floating layer 190b. The P-type contact layer 194 contains a higher concentration of P-type impurities than the P-type floating layer 190b. The P-type contact layer 194 includes a first contact layer 195 and a second contact layer 196. The first contact layer 195 is disposed inside the annular trench electrode 260. The second contact layer 196 is disposed between the adjacent annular trench electrodes 260. The first contact 185 is connected to the P-type floating layer 190b via the first contact layer 195. The second contact 186 is connected to the P-type floating layer 190b via the second contact layer 196.

[0096] According to the semiconductor device 2 of this embodiment, the trench electrode 260 extends to the P-type floating layer 190b, so that the electric field relaxation region can be extended to the second FLR in the termination region TER. The closer to the outer periphery of the semiconductor device 2, the wider the FLR interval may be. In that case, it is considered that the electric field strength for the trench electrode 260 becomes high. Therefore, by setting the trench electrode 260 to the emitter potential, the electric field can be relaxed, the collector breakdown voltage can be improved, and shrink can be made possible. Therefore, the relaxation of the electric field by the trench electrode 260 can be optimized by setting the FLR interval accordingly. When the FLR interval is fixed, the range of the ring layer p0 to the ring layer p1 or the ring layer p2 becomes a high electric field. Therefore, by extending the trench electrode 260 to such a high electric field range, the electric field concentration can be relaxed.

[0097] <Embodiment 3> A semiconductor device according to a second embodiment will be described. FIG. 28 is a plan view illustrating a semiconductor device 3 according to a third embodiment. As shown in FIG. 28, in the semiconductor device 3 of this embodiment, the end of the trench electrode 260 on the termination region TER side is located in the P-type junction impurity layer 170 in the main junction region CON. Therefore, both ends of the trench electrode 260 in the X-axis direction are located in the main junction region CON. The contact 144 may include a first contact 145 and a second contact 146. The contact 144 is connected to the trench electrode 260 and the P-type junction impurity layer 170. Even with this configuration, electric field concentration can be alleviated.

[0098] The disclosure made by the present inventor has been specifically described above based on the embodiments, but the present disclosure is not limited to the above-mentioned embodiments and modifications, and can be modified in various ways without departing from the spirit of the disclosure. For example, appropriate combinations of the configurations of the first to third embodiments and the first to third modifications are also within the scope of the technical idea of ​​the embodiments. In addition, the following configurations are also within the scope of the technical idea of ​​the embodiments.

[0099] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; an emitter wiring provided on the first main surface via an insulating film; Equipped with When viewed from the first main surface side, the semiconductor substrate has an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination area disposed to surround the active area; a primary junction region disposed between the active area and the termination area; having The semiconductor substrate in the primary junction region is A drift layer of a first conductivity type; a second conductivity type junction impurity layer provided closer to the first main surface than the drift layer; having The semiconductor substrate in the termination region is The drift layer; the second conductive type floating layer provided on the first main surface side relative to the drift layer; having At least the main junction region of the semiconductor substrate is a trench electrode provided inside a trench formed in the first main surface; a trench insulating film provided between the trench electrode and the semiconductor substrate; having When viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the active region toward the termination region, the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region; The IGBT is The drift layer; a barrier layer of the first conductivity type provided on the first main surface side of the drift layer; the second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of the first conductivity type provided on the first main surface side of the channel layer; a gate trench electrode provided to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in another direction intersecting the one direction in a plane parallel to the first main surface; a gate trench insulating film provided between the gate trench electrode, the drift layer, the barrier layer, the channel layer, and the emitter layer; having Semiconductor device. (Appendix 2) a gate wiring provided on the first main surface via the insulating film; Further equipped with When viewed from the first main surface side, the semiconductor substrate has a gate wiring region disposed between the main junction region and the active region in the one direction; and The gate trench electrode is connected to the gate wiring in the gate wiring region. 2. The semiconductor device according to claim 1. (Appendix 3) When viewed from the first main surface side, the trench electrode includes a portion extending from the gate wiring region to the termination region, One end of the trench electrode in the one direction is located in the gate wiring region, and the other end is located in the termination region. 3. The semiconductor device according to claim 2. (Appendix 4) When viewed from the first main surface side, the trench electrode includes a portion extending from the gate wiring region to the main junction region, One end of the trench electrode in the one direction is located in the gate wiring region, and the other end is located in the main junction region. 3. The semiconductor device according to claim 2. [Explanation of symbols]

[0100] 1, 1a, 1b, 1bb, 1c, 2, 3 Semiconductor device 10a IGBT 100, 101 Semiconductor device 121, 122, 123, 124 area 125 Corner 131, 132, 133, 134 area 135 Corner 141 Emitter wiring 142 Main body 143, 144 Contact 145 First Contact 146 Second Contact 147 Gate wiring 150 Semiconductor Substrate 150E Tip End 151 Top surface 152 Bottom surface 153 N-type drift layer 154 N+ type barrier layer 155 P-type channel layer 156 N+ type emitter layer 157 N+ type field stop layer 158 P++ type collector layer 159 P-type floating layer 160, 161, 162 Gate trench electrode 164 Insulating Film 165 Gate trench insulating film 170 P-type junction impurity layer 174 P-type contact layer 175 First Contact Layer 176 Second Contact Layer 181 Termination wiring 182 Main body 183, 184 Contact 185 First Contact 186 Second Contact 190, 190a, 190b P-type floating layer 194 P-type contact layer 195 First Contact Layer 196 Second Contact Layer 260 Trench Electrode 265 Trench insulating film ACT Active Area CON Main junction area CP Semiconductor Chip EPD emitter pad GAT Gate wiring area GPD Gate Pad GPL Gate Pass Line TER Termination area

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; an emitter wiring provided on the first main surface via an insulating film; Equipped with When viewed from the first main surface side, the semiconductor substrate has an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination area disposed to surround the active area; a primary junction region disposed between the active area and the termination area; having The semiconductor substrate in the primary junction region is A drift layer of a first conductivity type; a junction impurity layer of a second conductivity type provided closer to the first main surface than the drift layer; having The semiconductor substrate in the termination region is The drift layer; the second conductivity type floating layer provided on the first main surface side relative to the drift layer; having At least the main junction region of the semiconductor substrate is a trench electrode provided inside a trench formed in the first main surface; a trench insulating film provided between the trench electrode and the semiconductor substrate; having When viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main junction region toward the termination region, the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region; Semiconductor device.

2. When viewed from the first main surface side, both ends of the trench electrode in the one direction are located in the main junction region. The semiconductor device according to claim 1 .

3. When viewed from the first principal surface side, the trench electrode includes a portion extending from the main junction region to the termination region, One end of the trench electrode in the one direction is located in the main junction region, and the other end is located in the termination region. The semiconductor device according to claim 1 .

4. the termination region has a plurality of the floating layers including portions extending in another direction intersecting the one direction, The plurality of floating layers include a first floating layer closest to the main junction region; a second floating layer adjacent to the first floating layer; Including, The other end is located on the first floating layer. The semiconductor device according to claim 3 .

5. the termination region has a plurality of the floating layers including portions extending in another direction intersecting the one direction, The plurality of floating layers include a first floating layer closest to the main junction region; a second floating layer adjacent to the first floating layer; Including, The other end is located on the second floating layer. The semiconductor device according to claim 3 .

6. The floating layer is not connected to the emitter wiring in the termination region. The semiconductor device according to claim 1 .

7. The emitter wiring is A main body portion, an emitter contact connected to the junction impurity layer; having the junction impurity layer is connected to the emitter wiring via the emitter contact; The semiconductor device according to claim 1 .

8. When viewed from the first main surface side, the trench electrode has an annular shape in which both ends of the two portions extending in one direction are connected to each other, The emitter contact is a first emitter contact connected to the junction impurity layer inside the annular trench electrode; a second emitter contact connected to the junction impurity layer between adjacent ones of the annular trench electrodes; Including, The semiconductor device according to claim 7.

9. the semiconductor substrate in the main junction region further includes an emitter contact layer of the second conductivity type provided closer to the first main surface than the junction impurity layer, the emitter contact layer containing an impurity of the second conductivity type at a higher concentration than the junction impurity layer; The emitter contact layer is a first emitter contact layer disposed inside the annular trench electrode; a second emitter contact layer disposed between adjacent ones of the annular trench electrodes; Including, the first emitter contact is connected to the junction impurity layer via the first emitter contact layer; the second emitter contact is connected to the junction impurity layer via the second emitter contact layer; The semiconductor device according to claim 8.

10. an upper end of the trench electrode on the first main surface side has a step with respect to a lower end of the first emitter contact on the second main surface side; The trench electrode is connected to the emitter wiring via the step. The semiconductor device according to claim 9.

11. When viewed from the first main surface side, the trench electrode has an annular shape in which both ends of the two portions extending in one direction are connected to each other, the emitter contact is formed across the plurality of annular trench electrodes and the junction impurity layer; The semiconductor device according to claim 7.

12. the semiconductor substrate in the main junction region further includes an emitter contact layer of a second conductivity type provided closer to the first main surface than the junction impurity layer, the emitter contact layer containing an impurity of the second conductivity type at a higher concentration than the junction impurity layer; The emitter contact layer is a first emitter contact layer disposed inside the annular trench electrode; a second emitter contact layer disposed between adjacent ones of the annular trench electrodes; Including, the emitter contact is connected to the junction impurity layer via the first emitter contact layer and the second emitter contact layer; The semiconductor device according to claim 11.

13. An upper end of the trench electrode on the first main surface side is connected to a lower end of the emitter contact. The semiconductor device according to claim 12.

14. The IGBT includes: The drift layer; a barrier layer of the first conductivity type provided on the first main surface side of the drift layer; the second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of the first conductivity type provided on the first major surface side of the channel layer; gate trench electrodes provided to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in the one direction in a plane parallel to the first main surface; a gate trench insulating film provided between the gate trench electrode and the semiconductor substrate; the second conductivity type IGBT floating layer provided on the opposite side of the barrier layer, the channel layer, and the emitter layer with the gate trench electrode interposed therebetween; having The semiconductor device according to claim 1 .

15. When viewed from the first main surface side, the main junction region is a first main joint portion extending in one direction; A second main joint portion extending in another direction intersecting the one direction; a third main joint portion at a corner where the first main joint portion and the second main joint portion are connected; Including, the trench electrode includes a portion extending in the one direction or the other direction in the third main junction portion; The semiconductor device according to claim 1 .

16. When viewed from the first main surface side, the termination region has a first termination portion extending in one direction; a second termination portion extending in the other direction; and a third termination portion at a corner where the first termination portion and the second termination portion are connected; Including, the trench electrode includes a portion extending from the third main junction portion to the third termination portion; The semiconductor device according to claim 15.

17. a termination wiring provided on the first main surface via an insulating film in the termination region; The termination wiring is A main body portion, a termination contact at a portion connected to the second floating layer; having the second floating layer is connected to the termination wiring via the termination contact; The semiconductor device according to claim 5 .

18. When viewed from the first main surface side, the trench electrode has an annular shape in which both ends of the two portions extending in one direction are connected to each other, The termination contact comprises: a first termination contact connected to the second floating layer within the annular trench electrode; a second termination contact connected to the second floating layer between adjacent annular trench electrodes; Including, The semiconductor device according to claim 17.

19. the semiconductor substrate in the termination region further includes a termination contact layer of the second conductivity type provided closer to the first main surface than the second floating layer, the termination contact layer including a higher concentration of impurities of the second conductivity type than the second floating layer; The termination contact layer comprises: a first termination contact layer disposed within the annular trench electrode; a second termination contact layer disposed between adjacent ones of the annular trench electrodes; Including, the first termination contact is connected to the second floating layer via the first termination contact layer; the second termination contact is connected to the second floating layer via the second termination contact layer; The semiconductor device according to claim 18.

20. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; an emitter wiring provided on the first main surface via an insulating film; Equipped with When viewed from the first main surface side, the semiconductor substrate has an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination area disposed to surround the active area; a primary junction region disposed between the active area and the termination area; having The semiconductor substrate in the primary junction region is A drift layer of a first conductivity type; a junction impurity layer of a second conductivity type provided closer to the first main surface than the drift layer; having The semiconductor substrate in the termination region is The drift layer; the second conductivity type floating layer provided on the first main surface side relative to the drift layer; having At least the main junction region of the semiconductor substrate is a trench electrode provided inside a trench formed in the first main surface; a trench insulating film provided between the trench electrode and the semiconductor substrate; having When viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main junction region toward the termination region, the trench electrode and the junction impurity layer are connected to the emitter wiring in the main junction region; The IGBT includes: The drift layer; a barrier layer of the first conductivity type provided on the first main surface side of the drift layer; the second conductivity type channel layer provided on the first main surface side of the barrier layer; an emitter layer of the first conductivity type provided on the first major surface side of the channel layer; a gate trench electrode provided to sandwich the barrier layer, the channel layer, and the emitter layer from both sides in another direction intersecting the one direction in a plane parallel to the first main surface; a gate trench insulating film provided between the gate trench electrode, the drift layer, the barrier layer, the channel layer, and the emitter layer; the second conductivity type IGBT floating layer provided on the opposite side of the barrier layer, the channel layer, and the emitter layer with the gate trench electrode interposed therebetween; having Semiconductor device.

Images