Semiconductor memory device, memory system and control method

Abstract

To provide a semiconductor memory device which can suppress deterioration of a memory cell.SOLUTION: A control circuit of a semiconductor memory device determines whether or not a first threshold voltage possessed by a memory cell which is an object to be written is higher than a second threshold determined on the basis of data stored in the memory cell which is the object to be written. When the first threshold voltage is higher than the second threshold voltage, the control circuit executes erase operation of lowering a threshold voltage possessed by the memory cell which is the object to be written using an erase voltage, so that the memory cell which is the object to be written stores the data to be stored.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor memory device, a memory system, and a control method. [Background technology]

[0002] 2. Description of the Related Art In recent years, semiconductor memory devices, which are non-volatile memories, have become widespread. As one type of memory system equipped with such semiconductor memory devices, a solid-state drive (SSD) equipped with a NAND flash memory is known.

[0003] A semiconductor memory device such as a NAND flash memory includes a number of memory cells each storing data. The data stored in a memory cell corresponds to the amount of charge stored in the charge storage layer of the memory cell. Before a program operation to store data in a memory cell, an erase operation to erase the data stored in the memory cell is performed. In a semiconductor memory device, the memory cell deteriorates as the erase and program operations are repeated on the memory cell.

[0004] For this reason, a technique capable of suppressing degradation of memory cells is required. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2023-65351 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor memory device, a memory system, and a control method that can suppress deterioration of memory cells. [Means for solving the problem]

[0007] According to an embodiment, a semiconductor memory device includes a plurality of memory cells and a control circuit. The plurality of memory cells are configured to store data corresponding to a threshold voltage range to which each of the memory cells belongs. The control circuit is configured to control the plurality of memory cells. The control circuit determines whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined based on data to be stored in the memory cell to be written. When the first threshold voltage is higher than the second threshold voltage, the control circuit generates an erase voltage to be applied to the memory cell to be written. The control circuit executes an erase operation to lower the threshold voltage of the memory cell to be written using the erase voltage so that the memory cell to be written stores the data to be stored. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment. [Diagram 2] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to an embodiment. [Diagram 3] 2 is a diagram showing an example of the configuration of each of a plurality of blocks included in a memory cell array of the semiconductor memory device according to the embodiment. [Figure 4] 2 is a diagram showing an example of a circuit configuration of each of a plurality of blocks included in a memory cell array of the semiconductor memory device according to the embodiment. [Diagram 5] 1 is a diagram showing an example of threshold voltage distributions of a plurality of memory cells included in a semiconductor memory device according to an embodiment; [Figure 6] 1 is a diagram showing an example of the relationship between the threshold voltage distribution of a plurality of memory cells included in a semiconductor memory device according to an embodiment and an erase voltage. [Figure 7] 1 is a diagram showing an example of one memory cell selected as a target for an erase operation in a semiconductor memory device according to an embodiment. [Figure 8]11A and 11B are diagrams showing examples of the relationship between data of a memory cell to be written and data to be written to the memory cell to be written in the semiconductor memory device according to the embodiment and the semiconductor memory device according to the comparative example. [Figure 9] FIG. 2 is a block diagram showing a first example of the flow of a write process executed in the semiconductor memory device according to the embodiment. [Figure 10] 11 is a diagram showing the relationship between a current value read from a memory cell included in the semiconductor memory device according to the embodiment and a threshold voltage. [Figure 11] 1 is a flowchart showing a first example of a procedure of a write process executed in a semiconductor memory device according to the embodiment. [Figure 12A] 4 is a diagram showing a first example of a change in threshold voltage due to a program operation executed in the semiconductor memory device according to the embodiment. [Figure 12B] 11 is a diagram showing a second example of a change in threshold voltage due to a program operation executed in the semiconductor memory device according to the embodiment. FIG. [Figure 12C] 11 is a diagram showing a third example of changes in threshold voltage due to a program operation executed in the semiconductor memory device according to the embodiment. FIG. [Figure 12D] 11 is a diagram showing a fourth example of a change in threshold voltage due to a program operation executed in the semiconductor memory device according to the embodiment. FIG. [Figure 13A] 4 is a diagram showing a first example of a change in threshold voltage due to an erase operation executed in the semiconductor memory device according to the embodiment. [Figure 13B] 11 is a diagram showing a second example of a change in threshold voltage due to an erase operation executed in the semiconductor memory device according to the embodiment. [Figure 14] FIG. 11 is a block diagram showing a second example of the flow of a write process executed in the semiconductor memory device according to the embodiment. [Figure 15] 11 is a flowchart showing a second example of the procedure of a write process executed in the semiconductor memory device according to the embodiment. [Figure 16]1 is a diagram showing the correspondence relationship between a write process and a combination of an original state and a state after writing of a memory cell to be written that is included in a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] In the following, it is assumed that the semiconductor memory device according to the embodiment is realized as a NAND type flash memory, which will be simply referred to as a NAND memory.

[0011] 1 is a block diagram showing a configuration example of a memory system 3 including a semiconductor memory device according to an embodiment. The memory system 3 is included in an information processing system 1. The information processing system 1 further includes a host (host device) 2. The host 2 and the memory system 3 can be connected to each other via a bus 10.

[0012] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile device. The host 2 accesses the memory system 3. Specifically, the host 2 transmits an input / output (I / O) command to the memory system 3. The I / O command is a command for writing data to the NAND memory 5 or reading data from the NAND memory 5. The I / O command is, for example, a write command or a read command.

[0013] The memory system 3 is a storage device connectable to the host 2. The memory system 3 is, for example, a solid state drive (SSD) or a universal flash storage (UFS) device. The memory system 3 includes a NAND memory 5 which is a semiconductor storage device.

[0014] The communication between the memory system 3 and the host 2 is performed via a bus 10. The bus 10 is a communication path that connects the host 2 and the memory system 3. The bus 10 is, for example, a PCI express TM (PCIe TM ) standard, or Mobile Industry Processor Interface TM (MIPI TM The bus 10 is used for transmitting data and I / O commands from the host 2 to the memory system 3, and for transmitting data and responses from the memory system 3 to the host 2.

[0015] As a standard of a logical interface for connecting the host 2 and the memory system 3, for example, NVM express TM (NVMe TM ) standard may be used.

[0016] Next, we will explain the configuration of the host 2. The host 2 includes a processor 21 and a memory 22. The processor 21 and the memory 22 are connected to each other via an internal bus 20.

[0017] The processor 21 is, for example, a central processing unit (CPU). The processor 21 executes software (host software) that is loaded into the memory 22 from the memory system 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and application programs.

[0018] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM).

[0019] Next, the configuration of the memory system 3 will be described.

[0020] The memory system 3 includes a controller 4 and a NAND memory 5. The memory system 3 further includes a random access memory (RAM), for example, a DRAM 6. The DRAM 6 may be built into the controller 4.

[0021] The controller 4 is a circuit that functions as a memory controller. The controller 4 is, for example, a semiconductor device such as a system-on-a-chip (SoC). The controller 4 is electrically connected to the NAND memory 5. The controller 4 executes a write process and a read process based on each I / O command received from the host 2. The write process is a process for writing data to the NAND memory 5. The read process is a process for reading data from the NAND memory 5. In the write process, the controller 4 transmits a write request (program request) to the NAND memory 5. In the read process, the controller 4 transmits a read request to the NAND memory 5. For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a standard for an interface that electrically connects the controller 4 and the NAND memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

[0022] The NAND memory 5 is a semiconductor storage device. Based on a write request received from the controller 4, the NAND memory 5 writes data associated with the write request. Based on a read request received from the controller 4, the NAND memory 5 reads data associated with the read request.

[0023] The NAND memory 5 includes a plurality of blocks. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages is a unit of each of a write operation (specifically, a program operation) and a read operation.

[0024] The DRAM 6 is a volatile memory. The DRAM 6 includes a storage area for storing, for example, a logical-to-physical address translation table (L2P table) 61.

[0025] The L2P table 61 is a table that stores mapping information. The mapping information is information that indicates the mapping between each logical address and each physical address of the NAND memory 5 in a unit of a predetermined management size. The logical address is an address used by the host 2 to access the memory system 3. As the logical address, for example, a logical block address (LBA) is used. The physical address is an address that indicates a storage location (physical storage location) in the NAND memory 5.

[0026] Next, the internal configuration of the controller 4 will be described. The controller 4 includes, for example, a host interface (host I / F) 41, a static RAM (SRAM) 42, a CPU 43, a direct memory access controller (DMAC) 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. The host interface 41, SRAM 42, CPU 43, DMAC 44, error correction circuit 45, NAND interface 46, and DRAM interface 47 are interconnected via an internal bus 40. The controller 4 is configured as an electronic circuit having these components.

[0027] The host interface 41 is an interface circuit that executes communication with the host 2. The host interface 41 executes, for example, a process of fetching each I / O command (write command, read command) from the memory 22 of the host 2, a process of acquiring write data associated with each fetched write command from the memory 22 of the host 2, a process of transferring data read from the NAND memory 5 based on each fetched read command to the memory 22 of the host 2, and a process of transmitting a completion response corresponding to each fetched I / O command to the host 2.

[0028] The SRAM 42 is a volatile memory. The storage area of ​​the SRAM 42 is used, for example, as a working area of ​​the CPU 43. A part of the storage area of ​​the SRAM 42 may be used as a write buffer for temporarily storing write data received from the host 2. Furthermore, a part of the storage area of ​​the DRAM 6 may be used as the write buffer.

[0029] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the NAND memory 5 or a ROM (not shown) into the SRAM 42. The CPU 43 executes the firmware to perform various processes. The firmware may be loaded into the DRAM 6.

[0030] The CPU 43, for example, as a flash translation layer (FTL), manages data stored in the NAND memory 5 and manages blocks included in the NAND memory 5. The management of data stored in the NAND memory 5 includes, for example, management of mapping information. The CPU 43 uses, for example, the mapping information of the L2P table 61 to manage the mapping between each logical address and each physical address in units of a predetermined management size.

[0031] In the NAND memory 5, the controller 4 writes updated data corresponding to a logical address to a different physical storage location, not to the physical storage location where the previous data corresponding to the logical address is stored. The controller 4 then updates the L2P table 61 to associate the logical address with a physical address indicating the different physical storage location, and treats the previous data as invalid data.

[0032] Among the blocks included in the NAND memory 5, blocks that contain at least valid data are managed as active blocks. Blocks that do not contain valid data and store only invalid data are managed as free blocks. Valid data means data stored in a physical memory location associated with a logical address in the L2P table 61 (i.e., data associated with a logical address as the latest data). Valid data may be read by the host 2 later. Invalid data means data that is not associated with any logical address. Data that is not associated with any logical address is data that may no longer be read by the host 2.

[0033] The DMAC 44 is a circuit that executes direct memory access (DMA) and executes data transfer between the memory 22 of the host 2 and the SRAM 42 (or the DRAM 6).

[0034] The error correction circuit 45 performs an encoding process when data is written to the NAND memory 5. In the encoding process, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND memory 5. In the decoding process, the error correction circuit 45 performs an error detection and error correction of the data read from the NAND memory 5, using the ECC added to the data.

[0035] The NAND interface 46 is a memory interface circuit that controls the NAND memory 5. The NAND interface 46 transmits a program request for writing data, which is transmitted by the controller 4, to the NAND memory 5. In addition, the NAND interface 46 transmits a read request for reading data, which is transmitted by the controller 4, to the NAND memory 5.

[0036] The DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6. In addition, the DRAM interface 47 reads the data stored in the DRAM 6.

[0037] Next, a description will be given of the internal configuration of the NAND memory 5. The NAND memory 5 includes a peripheral circuit 51 and a memory cell array 52. ​​The NAND memory 5 may include a memory cell array 52 having a two-dimensional structure, or may include a memory cell array 52 having a three-dimensional structure.

[0038] The peripheral circuit 51 is a circuit that controls the memory cell array 52. ​​The peripheral circuit 51 is also referred to as a control circuit. In response to receiving a program request from the NAND interface 46, the peripheral circuit 51 executes an operation for writing data associated with the received program request to the memory cell array 52. ​​For example, the peripheral circuit 51 executes at least one of a program operation, a read operation, and an erase operation to write data to the memory cell array 52. ​​In addition, in response to receiving a read request from the NAND interface 46, the peripheral circuit 51 executes an operation for reading data specified by the received read request from the memory cell array 52.

[0039] The memory cell array 52 includes a plurality of non-volatile memory cell transistors (hereinafter, simply referred to as memory cells). Each of the plurality of memory cells has a certain threshold voltage, thereby storing data corresponding to a threshold voltage range to which the threshold voltage belongs. The memory cell array 52 also includes a plurality of blocks. Each block is a collection of a plurality of memory cells. Each block includes a plurality of memory cell groups. A memory cell group is also referred to as a string unit. Each string unit is a collection of memory cells. Each memory cell group includes a plurality of NAND strings (hereinafter, simply referred to as strings). Each string is a collection of memory cells connected in series.

[0040] The memory cell group may be used as a unit of write and read operations. For example, the program request includes information specifying the memory cell group to be programmed. The peripheral circuit 51 executes a process for writing a portion of data associated with the program request to each of a plurality of memory cells included in the memory cell group to be programmed. The read request includes information specifying the memory cell group to be read. The peripheral circuit 51 executes a process for reading data from each of a plurality of memory cells included in the memory cell group to be read.

[0041] One memory cell can store at least one bit of data. For example, the memory cell array 52 may be used in a single level cell (SLC) mode in which one bit of data is written per memory cell. Alternatively, the memory cell array 52 may be used in a mode in which two or more bits of data are written per memory cell. The mode in which two bits of data are written per memory cell is called a multi-level cell (MLC) mode. The mode in which three bits of data are written per memory cell is called a triple level cell (TLC) mode. The mode in which four bits of data are written per memory cell is called a quad level cell (QLC) mode.

[0042] The larger the number of bits of data written per memory cell, the more data can be stored even with the same hardware configuration, and therefore the NAND memory 5 can be used efficiently. However, the larger the number of bits of data written per memory cell, the longer the time required to write the data, and therefore the performance of the memory system 3 may decrease.

[0043] The multiple blocks included in the memory cell array 52 may include blocks to which data is written in different modes. For example, some of the multiple blocks may be blocks to which data is written in the SLC mode, and other of the multiple blocks may be blocks to which data is written in the QLC mode.

[0044] Next, a functional configuration of the CPU 43 will be described. In addition to the components that function as an FTL, the CPU 43 includes a write processing unit 431 and a read processing unit 432. A part or the whole of each of the write processing unit 431 and the read processing unit 432 may be realized by dedicated hardware of the controller 4.

[0045] The write processing unit 431 executes the write processing by processing each write command received from the host 2. The write processing includes, for example, a process of acquiring write data associated with the write command from the memory 22 of the host 2, a process of writing the write data to a storage location in the NAND memory 5, and a process of updating the L2P table 61 to map (associate) a physical address indicating the storage location to which the write data has been written to a logical address specified by the write command. The write processing also includes a process of sending a completion response indicating the completion of the processing of the write command to the host 2. The completion response indicating the completion of the processing of the write command is sent to the host 2 in response to, for example, the transfer of the write data associated with this write command from the memory 22 of the host 2 to the SRAM 42.

[0046] In a process of writing write data to a storage location in the NAND memory 5, the NAND interface 46 instructs the NAND memory 5 to execute a program operation by transferring a program request and write data associated with the program request to the NAND memory 5. The program request includes, for example, information specifying a storage area to which the write data is to be written. The storage area specified by the program request corresponds, for example, to a memory cell group. The program operation is an operation of writing the write data transferred to the NAND memory 5 to a memory cell of the memory cell array 52. ​​The program operation is executed by the peripheral circuit 51 that receives the program request.

[0047] The read processing unit 432 executes a read process by processing each read command received from the host 2. The read process includes a process of reading data corresponding to a logical address designated by the read command from the NAND memory 5, a process of transferring the read data to the memory 22 of the host 2, and a process of sending a completion response indicating completion of the processing of the read command to the host 2. In the process of reading data from the NAND memory 5, specifically, the read processing unit 432 converts the logical address designated by the read command into a physical address by referring to the L2P table 61, and reads the data from the storage location of the NAND memory 5 indicated by the physical address.

[0048] In the process of reading data from a storage location of the read target NAND memory 5, the NAND interface 46 instructs the peripheral circuit 51 to execute a read operation (also referred to as a sense operation or a read operation) by sending a read request to the NAND memory 5. The read operation is an operation of reading data from the memory cell array 52. ​​The read operation is executed by the peripheral circuit 51. Then, the NAND interface 46 executes a data output operation for transferring the read data from the NAND memory 5 to the controller 4.

[0049] Next, an example of the internal configuration of the NAND memory 5 will be described. Fig. 2 is a block diagram showing an example of the configuration of the NAND memory 5 according to the embodiment. In the example of Fig. 2, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to these.

[0050] The NAND memory 5 is connected to the controller 4. The NAND memory 5 operates based on instructions from the controller 4.

[0051] The NAND memory 5 includes a peripheral circuit 51 and a memory cell array 52. ​​The NAND memory 5 also includes a plurality of planes PLN. The peripheral circuit 51 includes an input / output circuit 5101, a logic control circuit 5102, an address register 5103, a command register 5104, a status register 5105, a sequencer 5106, a ready / busy circuit 5107, a voltage generation circuit 5108, a comparison circuit 5109, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113. Each of the components of the peripheral circuit 51 may be realized by dedicated hardware or may be realized by the function of the peripheral circuit 51. The memory cell array 52 is included in each of the plurality of planes PLN. Some of the components of the peripheral circuit 51 may be included in each of the plurality of planes PLN. In FIG. 2, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113 are included in each of the multiple planes PLN (PLN0 to PLN3).

[0052] The input / output circuit 5101 is a circuit that inputs and outputs a signal DQ. The input / output circuit 5101 is connected to the controller 4. The input / output circuit 5101 is also connected to an address register 5103, a command register 5104, a status register 5105, and a data register 5112 of each plane PLN. The signal DQ is, for example, an 8-bit signal DQ<7:0>. The signal DQ<7:0> includes, for example, data DAT, an address ADD, and a command CMD. When the input signal DQ is data DAT (for example, data to be written to the memory cell array 52), the input / output circuit 5101 receives the input signal DQ based on the strobe signals DQS and DQSn. Then, the input / output circuit 5101 transmits the data DAT to the data register 5112 of the corresponding plane PLN. Furthermore, the input / output circuit 5101 outputs data DAT (e.g., data read from the memory cell array 52) and status information STS together with strobe signals DQS and DQSn to the controller 4. When the input signal DQ is an address ADD (e.g., a physical address), the input / output circuit 5101 transmits the address ADD to an address register 5103. When the input signal DQ is a command CMD (e.g., a program request or a read request), the input / output circuit 5101 transmits the command CMD to a command register 5104.

[0053] The logic control circuit 5102 is a circuit that performs logic control based on a control signal. The logic control circuit 5102 is connected to the controller 4. The logic control circuit 5102 is also connected to the input / output circuit 5101 and the sequencer 5106. The logic control circuit 5102 receives various control signals from the controller 4. The logic control circuit 5102 controls the input / output circuit 5101 and the sequencer 5106 based on the received control signals.

[0054] The address register 5103 is a register that temporarily stores an address ADD received from the input / output circuit 5101. The address register 5103 is connected to the row decoder 5110 and the column decoder 5113 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 5103 transmits the row address RA to the row decoder 5110. In addition, the address register 5103 transmits the column address CA to the column decoder 5113.

[0055] The command register 5104 is a register that temporarily stores the command CMD received from the input / output circuit 5101. The command register 5104 is connected to the sequencer 5106. The command register 5104 transmits the command CMD to the sequencer 5106.

[0056] The status register 5105 is a register that temporarily stores the status information STS. The status register 5105 is connected to the sequencer 5106. The status register 5105 temporarily stores the status information STS in a program operation, a read operation, an erase operation, etc. The status information STS is transmitted to the controller 4 via the input / output circuit 5101.

[0057] The sequencer 5106 controls the operation of the entire NAND memory 5. More specifically, the sequencer 5106 controls the ready / busy circuit 5107, the voltage generating circuit 5108, the row decoder 5110, the sense amplifier module 5111, the data register 5112, the column decoder 5113, and the like. The sequencer 5106 executes a program operation, a read operation, and an erase operation based on a command CMD stored in the command register 5104. At this time, the sequencer 5106 controls the voltage generating circuit 5108 so as to generate a voltage used when executing various operations. In addition, the sequencer 5106 may execute a program operation, a read operation, and an erase operation based on a comparison result received from the comparison circuit 5109. The sequencer 5106 transmits status information STS to the status register 5105.

[0058] For example, the sequencer 5106 executes a read operation on the memory cell group to be programmed based on a program request. The sequencer 5106 determines whether to execute a program operation and whether to execute an erase operation on the memory cell to be programmed based on a threshold voltage of a memory cell to be programmed among a plurality of memory cells included in the memory cell group to be programmed and a threshold voltage corresponding to data to be stored in the memory cell to be programmed. The sequencer 5106 also executes a read operation on the memory cell group to be read based on a read request.

[0059] The ready / busy circuit 5107 is a circuit that transmits a ready / busy signal RBn. The ready / busy circuit 5107 transmits a ready / busy signal RBn according to the operation status of the sequencer 5106 to the controller 4.

[0060] The voltage generating circuit 5108 generates a voltage used to control the NAND memory 5. The voltage generating circuit 5108 generates a voltage based on, for example, the control of the sequencer 5106. The voltage generating circuit 5108 supplies the generated voltage to the comparison circuit 5109, the memory cell array 52 of each plane PLN, the row decoder 5110, the data register 5112, the column decoder 5113, and the like. The voltages generated by the voltage generating circuit 5108 include a program voltage Vpg, a read voltage Vrv, an erase voltage Ver, and a target threshold voltage Vref. The program voltage Vpg is a voltage applied to a memory cell group to be programmed during a program operation. The read voltage Vrv is a voltage applied to a word line of a memory cell group to be read during a read operation. The erase voltage Ver is a voltage applied to a memory cell to be erased during an erase operation. The target threshold voltage Vref is a voltage used by the comparison circuit 5109. The target threshold voltage Vref is a voltage determined based on data to be written to a memory cell to be written. Further, the voltage generating circuit 5108 generates, as the target threshold voltage Vref, a first voltage Vref max indicating the upper limit of a target threshold voltage range determined based on data to be written in the memory cell to be written, and a second voltage Vref min indicating the lower limit of this target threshold voltage range, based on the control of the sequencer 5106. Alternatively, the voltage generating circuit 5108 generates, as the target threshold voltage Vref, one voltage (a third voltage Vref) determined based on data to be written in the memory cell to be written, based on the control of the sequencer 5106. The third voltage Vref is, for example, the median of the target threshold voltage range determined based on data to be written in the memory cell to be written.

[0061] The comparison circuit 5109 compares the threshold voltage of a memory cell to be written, which is included in the memory cell array 52, with the target threshold voltage generated by the voltage generation circuit 5108. Then, the comparison circuit 5109 outputs the comparison result to the sequencer 5106.

[0062] For example, when the target threshold voltage includes a first voltage Vref max and a second voltage Vref min, the comparison circuit 5109 outputs to the sequencer 5106 a comparison result indicating one of the following: the threshold voltage of the memory cell to be written is greater than the first voltage Vref max, the threshold voltage of the memory cell to be written is less than the first voltage Vref max and greater than the second voltage Vref min, or the threshold voltage of the memory cell to be written is less than the second voltage Vref min.

[0063] For example, when the target threshold voltage is the third voltage Vref, the comparison circuit 5109 outputs a comparison result indicating either that the threshold voltage of the memory cell to be written is greater than the third voltage Vref or that the threshold voltage of the memory cell to be written is equal to or less than the third voltage Vref to the sequencer 5106. However, instead of determining whether the threshold voltage of the memory cell to be written is equal to or less than the third voltage Vref, the comparison circuit 5109 may determine whether the threshold voltage of the memory cell to be written is equal to or more than the third voltage Vref.

[0064] The plane PLN is a unit that performs data write and read operations. In the example of FIG. 2, the NAND memory 5 includes four planes PLN0, PLN1, PLN2, and PLN3. The number of planes PLN is not limited to four. The number of planes PLN may be one or a number other than four. The planes PLN0 to PLN3 can operate independently of each other. Also, the planes PLN0 to PLN3 can operate in parallel.

[0065] Next, the internal configuration of the plane PLN will be described. In the following, a case where the planes PLN0 to PLN3 have the same configuration will be described. Note that the configuration of each plane PLN may be different. In the following, when there is no limitation on any of the planes PLN0 to PLN3, they will be referred to as the plane PLN. The plane PLN includes a memory cell array 52, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113.

[0066] The memory cell array 52 includes a plurality of blocks BLK. In the example of Fig. 2, the memory cell array 52 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 52 included in a certain plane PLN is arbitrary.

[0067] The row decoder 5110 is a decode circuit for the row address RA. Based on the decoded result, the row decoder 5110 selects one of the blocks BLK in the memory cell array 52. ​​The row decoder 5110 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0068] The sense amplifier module 5111 is a circuit that mainly reads out a signal corresponding to the data DAT. The sense amplifier module 5111 is connected to the memory cell array 52. ​​During a read operation, the sense amplifier module 5111 reads out a voltage corresponding to the data DAT from the memory cell array 52. ​​The sense amplifier module 5111 amplifies the voltage read out from the memory cell array 52.

[0069] The data register 5112 is a register that temporarily stores data DAT. The data register 5112 is connected to the sense amplifier module 5111. The data register 5112 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0070] The column decoder 5113 is a circuit that decodes a column address CA. The column decoder 5113 receives the column address CA from the address register 5103. The column decoder 5113 selects a latch circuit in the data register 5112 based on the result of decoding the column address CA.

[0071] Next, a configuration example of a block will be described below. Fig. 3 is a diagram showing a configuration example of each of a plurality of blocks included in the memory cell array 52 of the NAND memory 5 according to the embodiment.

[0072] In FIG. 3, the configuration of the blocks will be described with a focus on the block BLK0. The other blocks have the same configuration as the block BLK0. The block BLK0 includes four string units (SU0, SU1, SU2, and SU3). The four string units (SU0, SU1, SU2, and SU3) are arranged in a direction (horizontal direction) perpendicular to the direction (vertical direction) in which the word lines WL0 to WL7 are stacked. Each string unit SU includes a plurality of strings NS. One end of each string NS is connected to a corresponding bit line among the plurality of bit lines (BL0 to BLn). Each string NS extends in the vertical direction. The control gates of the memory cell transistors included in each string NS are connected to the plurality of word lines (WL0, WL1, ..., WL7), respectively.

[0073] Next, the circuit configuration of the block will be described. Fig. 4 is a diagram showing an example of the circuit configuration of a block of the NAND memory 5 included in the memory system 3 according to the embodiment. Fig. 4 shows a plan view of the example of the configuration of the block shown in Fig. 3.

[0074] 4, the circuit configuration of the block will be described with a focus on the block BLK0. The block BLK0 includes, for example, four string units SU0 to SU3. Note that the number of string units SU included in each block BLK is arbitrary.

[0075] A string unit SU is, for example, a set of multiple strings NS that are collectively selected in a program operation or a read operation. Each string unit SU includes multiple strings NS.

[0076] Each string NS is a set of multiple memory cells MC connected in series. The multiple strings NS in the string unit SU are connected to any of bit lines BL0 to BLn (n is an integer equal to or greater than 1). The string NS includes multiple memory cells MC and selection transistors ST1 and ST2. In the example of FIG. 4, the string NS includes eight memory cells MC0 to MC7 and two selection transistors ST1 and ST2. The number of memory cells MC in the string NS is not limited to eight.

[0077] The memory cell MC is a memory element that stores data in a non-volatile manner. The memory cell MC includes a control gate and a charge storage layer. The memory cell MC may be of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductive layer for the charge storage layer.

[0078] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0079] The gates of the select transistors ST1 of the string unit SU0 are connected to the select gate line SGD0 corresponding to the string unit SU0. The gates of the select transistors ST1 of the string unit SU1 are connected to the select gate line SGD1 corresponding to the string unit SU1. The gates of the select transistors ST1 of the string unit SU2 are connected to the select gate line SGD2 corresponding to the string unit SU2. The gates of the select transistors ST1 of the string unit SU3 are connected to the select gate line SGD3 corresponding to the string unit SU3. In contrast, the gates of the select transistors ST2 of the string units SU0 to SU3 are commonly connected to the select gate line SGS. The gates of the select transistors ST2 of the string units SU0 to SU3 may be connected to different select gate lines for each string unit. The control gates of the memory cells MC0 to MC7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively.

[0080] The program operation and read operation by the peripheral circuit 51 can be performed collectively on a plurality of memory cells MC connected to one word line in one string unit SU. A set of memory cells MC selected collectively during the program operation and read operation is called a memory cell group MG. The memory cell group MG is the unit of the program operation and read operation and is treated as a storage location. When each memory cell MC is configured to store 1 bit of data (SLC mode), the size of data stored per memory cell group MG is called a page. When each memory cell MC is configured to store 4 bits of data (QLC mode), the size of data stored per memory cell group MG is 4 pages.

[0081] Next, a description will be given of threshold voltage distributions of a plurality of memory cells configured to store 4 bits of data per memory cell. Here, it is assumed that data is written in the QLC mode to each of a plurality of blocks included in the NAND memory 5. FIG. 5 is a diagram showing an example of threshold voltage distributions of a plurality of memory cells included in the NAND memory 5 according to the embodiment.

[0082] The threshold voltage Vth of each memory cell varies according to the amount of charge stored in the charge storage layer of the memory cell. In the NAND memory 5, each of the 16 types of 4-bit data that can be stored in each memory cell corresponds to one of the 16 threshold voltage ranges represented by the threshold voltage Vth of the memory cell. Thus, each memory cell stores data corresponding to the threshold voltage range to which the threshold voltage Vth of the memory cell belongs.

[0083] In the QLC mode, the threshold voltage that each memory cell can have is divided into 16 threshold voltage ranges. In Fig. 5, the 16 threshold voltage ranges are called Er state, A state, B state, C state, ..., O state in order of decreasing threshold voltage. The threshold voltage Vth of each memory cell is controlled to belong to one of the threshold voltage ranges by the program operation and the erase operation.

[0084] These 16 states correspond to different 4-bit data. For example, the threshold voltage Vth of a memory cell programmed with 4-bit data corresponding to the A state is set in the threshold voltage range from Vr1 to Vr2. Similarly, the threshold voltage Vth of a memory cell programmed with 4-bit data corresponding to the B state is set in the threshold voltage range from Vr2 to Vr3. Similarly, the threshold voltage Vth of a memory cell programmed with 4-bit data corresponding to the O state is set in the threshold voltage range from Vr15 to Vr16. The same applies to the other states.

[0085] Here, we have described the case where 4 bits of data are written to each memory cell (QLC mode), but the data written to each memory cell may be 1 bit of data (SLC mode), 2 bits of data (MLC mode), 3 bits of data (TLC mode), or 5 bits or more of data.

[0086] In SLC mode, the possible threshold voltages of each memory cell are divided into two threshold voltage ranges, in MLC mode, they are divided into four threshold voltage ranges, and in TLC mode, they are divided into eight threshold voltage ranges.

[0087] Next, the erase operation will be described.

[0088] First, the decrease in the threshold voltage Vth of a memory cell due to an erase operation will be described.

[0089] In an erase operation, an erase voltage Ver is applied to a memory cell in which data has been written (i.e., a memory cell in which a program operation has been executed), thereby removing charge from the charge storage layer. In a memory cell to which a program voltage Vpg has been applied by a program operation, the amount of charge stored in the charge storage layer is increased. As a result, the threshold voltage Vth of the memory cell in which data has been written becomes a value greater than the threshold voltage range of the erased state, and belongs to a threshold voltage range corresponding to another state. As the amount of charge stored in the charge storage layer decreases, the threshold voltage Vth of the erased memory cell is reduced to the threshold voltage range of the erased state.

[0090] Here, the amount of reduction in the threshold voltage Vth of the memory cell due to the erase operation depends on the magnitude of the erase voltage Ver used in the erase operation, the length of time for which the erase voltage Ver is applied, and the number of times the erase voltage Ver is applied. Fig. 6 is a diagram showing an example of the relationship between the threshold voltage distribution of multiple memory cells included in the NAND memory 5 according to the embodiment and the erase voltage Ver.

[0091] FIG. 6 shows five graphs. The horizontal axis of each graph indicates the threshold voltage Vth of each of the multiple memory cells. The vertical axis of each graph indicates the number of memory cells. The dashed line graph indicates the relationship between the threshold voltage Vth of each memory cell before application of the erase voltage Ver and the number of memory cells. The solid line graph indicates the relationship between the threshold voltage Vth of each memory cell after application of the erase voltage Ver and the number of memory cells.

[0092] In each graph, the multiple threshold voltage ranges correspond to the O state, N state, . . . , Er state, in order from the threshold voltage range having a peak corresponding to a larger threshold voltage.

[0093] The top graph of the five graphs shows the case where the erase voltage Ver is the smallest, the time for applying the erase voltage Ver is the shortest, and the number of times the erase voltage Ver is applied is the smallest. In this case, the change in the threshold voltage Vth of each of the memory cells before and after the erase operation is performed is the smallest. For example, when focusing on a specific memory cell (target cell TC) that belongs to the O state before the erase operation is performed, the target cell TC remains in the O state even after the erase operation is performed.

[0094] From the top graph to the bottom graph, the erase voltage Ver becomes larger, the time for applying the erase voltage Ver becomes longer, or the number of times the erase voltage Ver is applied becomes larger. Therefore, from the bottom graph to the top graph, the change in the threshold voltage Vth of each of the multiple memory cells before and after the erase operation becomes larger. For example, in the second graph from the top, the target cell TC remains in the O state before and after the erase operation, but in the fourth graph from the top, the target cell TC transitions from the O state to the N state before and after the erase operation.

[0095] In addition, the bottom graph of the five graphs shows the case where the erase voltage Ver is the largest, the time for applying the erase voltage Ver is the longest, and the number of times the erase voltage Ver is applied is the largest. In this case, the threshold voltage distribution of multiple memory cells is significantly shifted in the direction in which the threshold voltage Vth becomes smaller before and after the erase operation is performed. For example, when a target cell TC that is in the O state before the erase operation is performed is focused on, the target cell TC has a threshold voltage Vth that belongs to the M state after the erase operation is performed.

[0096] Therefore, the peripheral circuit 51 can control the amount of decrease in the threshold voltage Vth before and after the erase operation by controlling the parameters of the erase operation. The parameters include the value of the erase voltage Ver, the time for which the erase voltage Ver is applied, or the number of times the erase voltage Ver is applied.

[0097] For example, the peripheral circuit 51 can increase the amount of decrease in the threshold voltage Vth by increasing the erase voltage Ver. Also, the peripheral circuit 51 can increase the amount of decrease in the threshold voltage Vth by lengthening the time for which the erase voltage Ver is applied. Furthermore, the peripheral circuit 51 can increase the amount of decrease in the threshold voltage Vth by increasing the number of times the erase voltage Ver is applied.

[0098] On the other hand, the peripheral circuit 51 can reduce the amount of decrease in the threshold voltage Vth by setting the erase voltage Ver to a smaller value. Also, the peripheral circuit 51 can reduce the amount of decrease in the threshold voltage by shortening the time during which the erase voltage Ver is applied. Furthermore, the peripheral circuit 51 can reduce the amount of decrease in the threshold voltage by reducing the number of times the erase voltage Ver is applied.

[0099] Next, an erase operation on a specific memory cell will be described. Fig. 7 is a diagram showing an example of one memory cell selected as a target for an erase operation in the NAND memory 5 according to the embodiment.

[0100] The peripheral circuit 51 selects one select gate line SGD, one word line WL, and one bit line BL included in a certain block. This allows the peripheral circuit 51 to select one memory cell included in the string unit SU corresponding to the selected select gate line SGD and connected to the selected word line WL and the selected bit line BL from among the multiple memory cells included in this block. The peripheral circuit 51 then applies the erase voltage Ver only to the selected memory cell. This allows the peripheral circuit 51 to perform an erase operation on only a specific memory cell from among the multiple memory cells included in this block.

[0101] 7 shows a case where the peripheral circuit 51 selects the select gate line SGD1, the word line WL6, and the bit line BL0. The peripheral circuit 51 selects a memory cell MC connected to the word line WL6 and the bit line BL0 among a plurality of memory cells MC included in the string unit SU corresponding to the select gate line SGD1. The peripheral circuit 51 then applies the erase voltage Ver only to the selected memory cell to perform the erase operation.

[0102] This allows the peripheral circuit 51 to select one specific memory cell from among a plurality of memory cells included in a certain block, and to execute an erase operation on only the selected memory cell.

[0103] As described above, the peripheral circuit 51 can control the amount of decrease in the threshold voltage Vth of the memory cell by controlling the erase operation, and can execute the erase operation only on a specific memory cell included in a certain block. Therefore, the peripheral circuit 51 can select only a specific memory cell and execute an erase operation that adjusts the threshold voltage of the selected memory cell in a decreasing direction.

[0104] Next, a write process using an erase operation will be described. Fig. 8 is a diagram showing an example of the relationship between the data of a target cell and the data to be written to the target cell in the NAND memory 5 according to the embodiment and the NAND memory according to the comparative example. Fig. 8 assumes a case where data is written to each of a plurality of memory cells in the MLC mode.

[0105] The left side of FIG. 8 shows the correspondence between the threshold voltage distributions of multiple memory cells and the data (hereinafter also referred to as cell data) stored in each memory cell. Here, the threshold voltage range C1 with the highest peak threshold voltage corresponds to cell data (0, 1). The threshold voltage range B1 with the second highest peak threshold voltage corresponds to cell data (0, 0). The threshold voltage range A1 with the third highest peak threshold voltage corresponds to cell data (1, 0). The threshold voltage range Er1 with the lowest peak threshold voltage corresponds to cell data (1, 1) indicating the erased state.

[0106] That is, the amount of charge stored in the charge storage layer of the memory cell storing cell data (0, 1) is greater than the amount of charge stored in the charge storage layer of the memory cell storing other cell data. The amount of charge stored in the charge storage layer of the memory cell storing cell data (0, 0) is less than the amount of charge stored in the charge storage layer of the memory cell storing cell data (0, 1), and is greater than the amount of charge stored in the charge storage layer of the memory cell storing cell data (1, 0) or (1, 1). The amount of charge stored in the charge storage layer of the memory cell storing cell data (1, 0) is less than the amount of charge stored in the charge storage layer of the memory cell storing cell data (0, 1) or (0, 0), and is greater than the amount of charge stored in the charge storage layer of the memory cell storing cell data (1, 1). The amount of charge stored in the charge storage layer of the memory cell storing cell data (1, 1) is less than the amount of charge stored in the charge storage layer of the memory cell storing other cell data.

[0107] Here, it is assumed that a write process is executed to write new cell data (0, 0) to a memory cell (target cell) that is a write target and stores cell data (0, 1).

[0108] First, the write process in the comparative example will be described. In the write process in the comparative example, when a new block including a target cell is selected as a write destination block, the peripheral circuit executes an erase operation on this write destination block ((1-1) in FIG. 8). This erase operation puts all memory cells in the write destination block into an erased state. In other words, all of the multiple memory cells in the write destination block are in a state where they store cell data (1, 1). As a result, the cell data stored in the target cell changes from cell data (0, 1) to (1, 1).

[0109] Next, a program operation is performed on the memory cell group including the target cell ((1-2) in FIG. 8). In the program operation, a program voltage Vpg is applied to each of the memory cells included in the memory cell group via a word line. The threshold voltage Vth of the memory cell to which the program voltage Vpg is applied rises. The peripheral circuit determines whether or not each of the threshold voltages Vth of the memory cells included in the memory cell group to be programmed belongs to the target threshold voltage range corresponding to each memory cell every time the program voltage Vpg is applied. Then, among the multiple memory cells included in the memory cell group, memory cells having a threshold voltage Vth that belongs to the target threshold voltage range corresponding to the data to be written are set to a program completion state (inhibit). An operation including determining whether or not each of the threshold voltages Vth of the memory cells belongs to the target threshold voltage range corresponding to each memory cell and setting each memory cell having a threshold voltage Vth that belongs to the target threshold voltage range to a program completion state is also called a verify operation. Then, the peripheral circuit repeatedly performs an operation of applying the program voltage Vpg to memory cells not set to a program completion state among the multiple memory cells included in the memory cell group, and a verify operation. As a result, the threshold voltage Vth of the target cell included in the memory cell group to be programmed increases, the cell data stored in the target cell changes from cell data (1, 1) to cell data (0, 0), and the target cell is set to a programmed state.

[0110] As described above, in the write process in the comparative example, the target cell goes through an erase state and then new data is written.

[0111] Next, the write process in this embodiment will be described. In the write process in this embodiment, when a new block including a target cell is selected as a write destination block, an erase operation is not performed on the entire write destination block. Therefore, the target cell included in the write destination block does not necessarily become in an erased state (a state in which cell data (1, 1) is stored).

[0112] The peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell is greater than the target threshold voltage Vref corresponding to the data (cell data (0, 0)) to be newly written to the target cell. Here, the current threshold voltage Vth of the target cell corresponds to the cell data (0, 1). As a result, the peripheral circuit 51 determines whether the data stored in the target cell can be set to cell data (0, 0) by performing an erase operation on the target cell. Here, the target threshold voltage Vref corresponding to the cell data (0, 0) may be a first voltage Vref max indicating the upper limit of the threshold voltage range corresponding to the cell data (0, 0), or may be a third voltage Vref indicating one voltage belonging to the threshold voltage range corresponding to the cell data (0, 0).

[0113] Here, since the threshold voltage Vth of the target cell is greater than the target threshold voltage Vref corresponding to the cell data (0, 0), the peripheral circuit 51 executes an erase operation on the target cell ((2-1) in FIG. 8). Through this erase operation, the peripheral circuit 51 reduces the threshold voltage Vth of the target cell so that it falls within the threshold voltage range corresponding to the cell data (0, 0). In other words, the peripheral circuit 51 executes an erase operation so that the target cell stores data to be written to the target cell. At this time, the peripheral circuit 51 determines at least one of the magnitude of the erase voltage Ver, the length of time for applying the erase voltage Ver, and the number of times for applying the erase voltage Ver, which are used in the erase operation, based on the threshold voltage corresponding to the cell data (0, 1) and the threshold voltage corresponding to the cell data (0, 0).

[0114] Then, the peripheral circuit 51 reads data from the target cell and determines whether the read data matches the data to be written to the target cell. If the data read from the target cell matches the data to be written to the target cell, the peripheral circuit 51 completes the write to the target cell. The peripheral circuit 51 sets the target cell in which writing has been completed to a program complete state (inhibit). The target cell set to the program complete state does not have the program voltage or erase voltage Ver applied thereto during a program operation on other memory cells in the memory cell group including the target cell. Therefore, the target cell can maintain the data to be written.

[0115] Thus, in the write process of the present embodiment, new data is written to the target cell only by the erase operation without passing through the erase state. For this reason, in the write process of the present embodiment, the amount of charge discharged from the charge storage layer of the target cell is the difference between the amount of charge stored in the charge storage layer of the memory cell in which the cell data (0, 1) is stored and the amount of charge stored in the charge storage layer of the memory cell in which the cell data (0, 0) is stored. On the other hand, in the write process of the comparative example, since the target cell passes through the erase state once, the amount of charge discharged from the charge storage layer of the target cell is the difference between the amount of charge stored in the charge storage layer of the memory cell in which the cell data (0, 1) is stored and the amount of charge stored in the charge storage layer of the memory cell in which the cell data (1, 1) is stored. In other words, in the write process of the present embodiment, the amount of charge discharged from the charge storage layer is reduced by the amount of charge stored in the charge storage layer of the memory cell in which the cell data (0, 0) is stored and the amount of charge stored in the charge storage layer of the memory cell in which the cell data (1, 1) is stored, compared to the write process of the comparative example.

[0116] Here, the case has been described where an erase operation is performed on the target cell so that the target cell stores data to be newly written (e.g., cell data (0, 0)). However, the peripheral circuit 51 may also perform an erase operation so that the target cell is in a state other than the erased state and stores data corresponding to a threshold voltage range lower than the target threshold voltage range corresponding to the newly written data (e.g., cell data (1, 0)). When such a rough erase operation is performed, the peripheral circuit 51 does not set the target cell to a program complete state in this state. Thereafter, the target cell is set to a program complete state in response to the threshold voltage being raised to a state in which cell data (0, 0) is stored by a program operation on a memory cell group including the target cell.

[0117] Therefore, in the write process of the embodiment, when writing new data to the target cell, the amount of charge discharged from the charge storage layer of the target cell can be reduced. The deterioration of the memory cell progresses according to the amount of charge discharged from the charge storage layer. Therefore, the write process of the embodiment can suppress the progress of deterioration of the memory cell.

[0118] When performing the write process of the embodiment, the peripheral circuit 51 compares the threshold voltage Vth of the target cell with a target threshold voltage Vref corresponding to new data to be written to the target cell. At this time, the peripheral circuit 51 uses, as the target threshold voltage Vref, either a first method using a first voltage Vref max indicating the upper limit of a threshold voltage range corresponding to the new data and a second voltage Vref min indicating the lower limit of the threshold voltage range, or a second method using a third voltage Vref indicating a voltage determined based on the new data.

[0119] First, the write process using the first method will be described.

[0120] 9 is a block diagram showing a first example of the flow of a write process executed in the NAND memory 5 according to the embodiment. First, the controller 4 transmits a program request to the NAND memory 5 via the NAND interface 46 in response to receiving a write command from the host 2. The controller 4 may transmit a program request to the NAND memory 5 autonomously, instead of using the write command received from the host 2. The program request includes information specifying a memory cell group to be programmed. The program request is also associated with data to be written to each memory cell included in the memory cell group to be programmed.

[0121] S1: The sequencer 5106 receives a program request from the NAND interface 46. The sequencer 5106 selects a target cell from among a plurality of memory cells included in a memory cell group to be programmed that is specified in the program request.

[0122] S2: The sequencer 5106 transmits a read instruction to the voltage generating circuit 5108 to generate a read voltage Vrv for acquiring the threshold voltage Vth of the selected target cell. The sequencer 5106 also transmits information for specifying the selected target cell to other components of the peripheral circuit 51, thereby specifying the target cell TC included in the memory cell array 52. ​​The sequencer 5106 outputs, for example, information for specifying the word line WL, the bit line BL, and the select gate lines SGD, SGS, and source line SL corresponding to the target cell TC, to which the target cell TC is connected.

[0123] S3: The voltage generating circuit 5108 generates a read voltage Vrv based on the received read instruction, and outputs the generated read voltage Vrv to the memory cell array 52.

[0124] S4: The memory cell array 52 controls a read operation for the target cell TC using the read voltage Vrv generated by the voltage generating circuit 5108. The sense amplifier module 5111 acquires the threshold voltage Vth of the target cell TC by the read operation. For example, in a state where a predetermined voltage value is applied to the bit line corresponding to the target cell TC, the read voltage Vrv is applied to the word line connected to the memory cell group including the target cell TC, whereby the sense amplifier module 5111 acquires the threshold voltage Vth.

[0125] S5: The sense amplifier module 5111 outputs the acquired threshold voltage Vth to the comparison circuit 5109.

[0126] S6: The sequencer 5106 instructs the voltage generating circuit 5108 to generate a first voltage Vref max indicating the upper limit and a second voltage Vref min indicating the lower limit of the target threshold voltage range corresponding to the data to be newly written to the target cell TC.

[0127] S7: The voltage generating circuit 5108 outputs the first voltage Vref max and the second voltage Vref min generated based on an instruction from the sequencer 5106 to the comparing circuit 5109. Here, the processes of S6-S7 do not necessarily have to be executed after S5, and may be executed in parallel with or independently of the processes of S2-S5.

[0128] S8: The comparison circuit 5109 determines which is larger between the threshold voltage Vth input from the sense amplifier module 5111 and the first voltage Vref max and the second voltage Vref min input from the voltage generation circuit 5108, and outputs the determination result to the sequencer 5106.

[0129] If the determination result output in S8 indicates that the threshold voltage Vth is greater than the first voltage Vref max, the peripheral circuit 51 executes the processes of S9-S10.

[0130] S9: The sequencer 5106 transmits an erase instruction to the voltage generating circuit 5108 to generate an erase voltage Ver used in an erase operation on the target cell TC. The erase instruction may include information specifying the magnitude of the erase voltage Ver, the time to apply the erase voltage Ver, or the number of times to apply the erase voltage Ver, determined based on the difference between the current threshold voltage Vth of the target cell TC and the target threshold voltage range. The sequencer 5106 also transmits information for specifying the selected target cell to other components of the peripheral circuit 51, thereby specifying the target cell TC included in the memory cell array 52. ​​The sequencer 5106 outputs information specifying, for example, the word line WL, the bit line BL, and the select gate lines SGD, SGS, and source line SL to which the target cell TC is connected, and the select gate lines SGD, SGS, and source line SL corresponding to the target cell TC.

[0131] S10: The voltage generation circuit 5108 outputs the erase voltage Ver generated based on the received erase instruction to the memory cell array 52. ​​The memory cell array 52 controls the erase operation on the target cell TC using the erase voltage Ver generated by the voltage generation circuit 5108. For example, the erase operation is controlled by applying the erase voltage Ver to a word line connected to a memory cell group including the target cell TC while a predetermined voltage value is applied to a bit line corresponding to the target cell TC.

[0132] After S10 is completed, the peripheral circuit 51 may execute the processes of S2 to S8 again. Specifically, the peripheral circuit 51 repeatedly executes the erase operation until the threshold voltage Vth of the target cell TC becomes equal to or lower than the first voltage Vref max.

[0133] Furthermore, when the determination result output in S8 indicates that the threshold voltage Vth is equal to or lower than the first voltage Vref max and equal to or higher than the second voltage Vref min, the peripheral circuit 51 executes the process of S11.

[0134] S11: The sequencer 5106 sets the target cell TC to a program completion state (inhibit). This prevents the program voltage Vpg from being applied to the target cell TC when a program operation is performed on other memory cells in the memory cell group including the target cell TC. After that, the sequencer 5106 selects the next target cell TC from the memory cell group to be programmed, and executes the process from S2 onwards again.

[0135] Furthermore, if the comparison result output in S8 indicates that the threshold voltage Vth is equal to or lower than the second voltage Vref min, the peripheral circuit 51 does nothing to the target cell TC. That is, the target cell TC is not set to the program completion state (inhibit). The next target cell TC is selected from the memory cell group to be programmed, and the process from S2 onward is executed again.

[0136] When the memory cells included in the memory cell group to be programmed have been selected as the target cells TC, if there are one or more memory cells among the memory cells included in the memory cell group to be programmed whose threshold voltage Vth is equal to or lower than the second voltage Vref min and which do not store data to be written, the peripheral circuit 51 executes the process of S12-S13. The one or more memory cells are memory cells that are not set to the program completion state (inhibit).

[0137] S12: The sequencer 5106 transmits a program instruction to the voltage generating circuit 5108 to generate a program voltage Vpg used in a program operation for the destination memory cell group. The sequencer 5106 also transmits information for specifying the destination memory cell group to other components of the peripheral circuit 51, thereby specifying the destination memory cell group included in the memory cell array 52. ​​The sequencer 5106 outputs, for example, information specifying the word line WL to which the destination memory cell group is connected.

[0138] S13: The voltage generating circuit 5108 outputs the program voltage Vpg generated based on the received program instruction to the memory cell array 52. ​​The memory cell array 52 uses the program voltage Vpg generated by the voltage generating circuit 5108 to control the program operation for the memory cell group to which the data is to be written. For example, the program operation is controlled by applying the program voltage Vpg to the word line to which the memory cell group to be programmed is connected while a predetermined voltage value is applied to each bit line corresponding to each memory cell not set to a program completion state among the memory cells included in the memory cell group to be programmed. Note that the target cell TC whose threshold voltage Vth is equal to or lower than the second voltage Vref min in the comparison result output in S8 is included in the target of the program operation in S13.

[0139] Next, the relationship between the current value read from a memory cell and the threshold voltage Vth of the memory cell will be described. For example, as in S4 of FIG. 9, when a read voltage Vrv is applied to the memory cell, the peripheral circuit 51 acquires the threshold voltage of the memory cell based on the current value output from the memory cell. FIG. 10 is a diagram showing the relationship between the current value read from the memory cell included in the NAND memory 5 according to the embodiment and the threshold voltage.

[0140] The vertical axis indicates the current value output from a memory cell to which a read voltage Vrv is applied, and the horizontal axis indicates the threshold voltage of the memory cell.

[0141] The curve Cu in Fig. 10 shows the relationship between the current value output from each memory cell and the threshold voltage of that memory cell. In other words, the threshold voltage of a certain memory cell can be determined based on the current value of the current output from that memory cell.

[0142] Specifically, the sense amplifier module 5111 obtains a current value Ith indicating the amount of current output from the memory cell by applying a read voltage Vrv to the word line of the memory cell and applying a predetermined voltage to the bit line of the memory cell. By referring to the correspondence between the current value Ith and the threshold voltage Vth for this memory cell, the peripheral circuit 51 can obtain the threshold voltage Vth based on the obtained current value Ith.

[0143] Therefore, for the sake of simplicity, it is described that the sense amplifier module 5111 obtains the threshold voltage Vth from the memory cell to be read by the read operation.

[0144] Next, a procedure of a write process using the first method will be described. Fig. 11 is a flowchart showing a first example of a procedure of a write process executed in the NAND memory 5 according to the embodiment. In response to receiving a program request from the controller 4, the peripheral circuit 51 starts the write process.

[0145] The peripheral circuit 51 selects a memory cell group to be programmed based on the received program request (S101).

[0146] The peripheral circuit 51 selects a memory cell to be written (target cell) from among the multiple memory cells included in the memory cell group selected in S101 (S102).

[0147] The peripheral circuit 51 determines a target threshold voltage range for the target cell based on data associated with the program request (S103). The target threshold voltage range is a threshold voltage range corresponding to data to be newly written to the target cell. The peripheral circuit 51 determines, for example, a first voltage Vref max indicating an upper limit of the target threshold voltage range and a second voltage Vref min indicating a lower limit of the target threshold voltage range.

[0148] The peripheral circuit 51 applies a read voltage Vrv to the target cell and obtains the current threshold voltage Vth of the target cell (S104).

[0149] The peripheral circuit 51 determines whether the threshold voltage Vth of the target cell obtained in S104 is within the target threshold voltage range determined in S103 (S105). That is, the peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell obtained in S104 is equal to or lower than the first voltage Vref max and equal to or higher than the second voltage Vref min determined in S103.

[0150] If the threshold voltage Vth of the target cell acquired in S104 is within the target threshold voltage range determined in S103 (Yes in S105), the peripheral circuit 51 sets the target cell to a program complete state (inhibit) (S106).

[0151] Furthermore, if the threshold voltage Vth of the target cell acquired in S104 is not within the target threshold voltage range determined in S103 (No in S105), the peripheral circuit 51 determines whether the threshold voltage Vth of the target cell is lower than the target threshold voltage range (S107). Specifically, the peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell acquired in S104 is lower than the second voltage Vref min or higher than the first voltage Vref max.

[0152] If the threshold voltage Vth of the target cell is higher than the target threshold voltage range, that is, if the current threshold voltage Vth of the target cell is higher than the first voltage Vref max (No in S107), the peripheral circuit 51 applies the erase voltage Ver to the target cell (S108). The peripheral circuit 51 may determine the magnitude of the erase voltage Ver to be applied based on the difference between the threshold voltage Vth of the target cell and the target threshold voltage range. The peripheral circuit 51 may also determine not only the magnitude of the erase voltage Ver but also the time and number of times the erase voltage Ver is applied. Then, the peripheral circuit 51 returns to S104, obtains the threshold voltage Vth of the target cell again, and determines whether the threshold voltage Vth of the target cell has dropped to the target threshold voltage range.

[0153] After S106, or if the threshold voltage Vth of the target cell is lower than the target threshold voltage range (Yes in S107), the peripheral circuit 51 determines whether all memory cells included in the memory cell group to be programmed have been selected as target cells (S109).

[0154] If there is a memory cell that has not yet been selected among the memory cells included in the memory cell group to be programmed (No in S109), the peripheral circuit 51 returns to S102 and selects the next target cell from among the multiple memory cells included in the memory cell group to be programmed that have not yet been selected as a target cell.

[0155] If all memory cells included in the memory cell group to be programmed have been selected (Yes in S109), the peripheral circuit 51 executes a program operation on the memory cell group to be programmed (S110).

[0156] Thus, in the write process using the first method, the peripheral circuit 51 including the sequencer 5106, the voltage generating circuit 5108, the comparator circuit 5109, and the sense amplifier module 5111 controls the read operation, the erase operation, and the program operation for the target cell based on the magnitude relationship between the current threshold voltage Vth of the target cell and the target threshold voltage range determined based on the data to be written to the target cell. Then, the peripheral circuit 51 sets the memory cell whose threshold voltage Vth belongs to the target threshold voltage range to a program complete state.

[0157] Thereby, when the current threshold voltage Vth of the target cell is greater than the first voltage Vref max indicating the upper limit of the target threshold voltage range, the peripheral circuit 51 can set the target cell to the program complete state without passing through the erase state by only lowering the threshold voltage Vth by the erase operation. Also, when the current threshold voltage Vth of the target cell is less than the second voltage Vref min indicating the lower limit of the target threshold voltage range, the peripheral circuit 51 can set the target cell to the program complete state by only raising the threshold voltage Vth by the program operation without passing through the erase state.

[0158] Next, the write process using the second method will be described. In the write process using the second method, a third voltage Vref indicating one voltage value determined based on data to be newly written to the memory cell to be written is used as the target threshold voltage Vref. Here, the third voltage Vref is less than a value (first voltage Vref max) indicating the upper limit of the target threshold voltage range and greater than a value (second voltage Vref min) indicating the lower limit of the target threshold voltage range. In addition, the peripheral circuit 51 sets the magnitude of the program voltage Vpg so that the amount of change in the threshold voltage Vth of the memory cell, which changes every time the program voltage Vpg is applied to the memory cell, is smaller than the difference between the third voltage Vref and the value indicating the upper limit of the target threshold voltage range and the difference between the third voltage Vref and the value indicating the lower limit of the target threshold voltage. Furthermore, the peripheral circuit 51 sets the magnitude of the erase voltage Ver so that the amount of change in the threshold voltage Vth of a memory cell to be written, which changes each time the erase voltage Ver is applied to the memory cell, is smaller than the difference between the third voltage Vref and a value indicating the upper limit of the target threshold voltage range and the difference between the third voltage Vref and a value indicating the lower limit of the target threshold voltage range.

[0159] First, the program operation will be described. The peripheral circuit 51 executes the program operation on the memory cell group to be programmed, which is designated by the program request. The peripheral circuit 51 applies the program voltage Vpg to each of the memory cells not set to the program completion state among the plurality of memory cells included in the memory cell group to be programmed. At this time, the peripheral circuit 51 determines whether or not each of the threshold voltages Vth of the memory cells included in the memory cell group to be programmed reaches the third voltage Vref corresponding to each memory cell, every time the peripheral circuit 51 applies the program voltage Vpg to each of the memory cells not set to the program completion state among the memory cell group to be programmed. Then, the peripheral circuit 51 sets each of the memory cells having the threshold voltage Vth that reaches the third voltage Vref to the program completion state. An operation including determining whether or not each of the threshold voltages Vth of the memory cells reaches the third voltage Vref corresponding to each memory cell, and setting each of the memory cells having the threshold voltage Vth that reaches the third voltage Vref to the program completion state is also called a verify operation. The peripheral circuit 51 sets each of the memory cells included in the memory cell group to be programmed to the program completion state by repeatedly executing the operation of applying the program voltage Vpg and the verify operation.

[0160] Here, a description will be given focusing on one memory cell (target cell) included in the memory cell group to be programmed. Each of Figures 12A to 12D is a diagram showing an example of change in threshold voltage due to a program operation executed in the NAND memory 5 according to the embodiment.

[0161] 12A to 12D, the vertical axis represents the current value read from each memory cell to which a read voltage Vrv is applied, and the horizontal axis represents the threshold voltage of each memory cell.

[0162] The target threshold voltage Vref indicates a voltage (third voltage Vref) determined based on data to be written to the target cell, where the third voltage Vref is less than the upper limit of the target threshold voltage range and greater than the lower limit of the target threshold voltage range. The threshold voltage Vth indicates the current threshold voltage value of the target cell.

[0163] 12A shows the threshold voltage Vth of the target cell before the application of the program voltage and the change amount ΔVpg of the threshold voltage Vth due to the application of the program voltage Vpg in the first program operation. For example, the peripheral circuit 51 determines whether the threshold voltage Vth of each memory cell has become equal to or higher than the third voltage Vref every time the program voltage Vpg is applied to each memory cell. Since the threshold voltage Vth of the target cell after the first application of the program voltage Vpg is still less than the third voltage Vref, the peripheral circuit 51 does not yet set the target cell to the program complete state.

[0164] 12B and 12C each show the threshold voltage Vth of the target cell before the application of the program voltage Vpg and the change amount ΔVpg of the threshold voltage due to the application of the program voltage Vpg in the second and third program operations. After each program operation, the peripheral circuit 51 determines whether the threshold voltage Vth of each memory cell has become equal to or higher than the third voltage Vref. In either case after the second or third application of the program voltage Vpg, the threshold voltage Vth of the target cell is less than the third voltage Vref, so the peripheral circuit 51 does not set the memory cell to be written to the program complete state.

[0165] 12D shows the threshold voltage Vth of the target cell before the application of the program voltage Vpg and the change amount ΔVpg of the threshold voltage Vth due to the application of the program voltage Vpg in the fourth program operation. As the threshold voltage Vth increases by ΔVpg, the threshold voltage Vth of the target cell becomes greater than the third voltage Vref. Then, the peripheral circuit 51 sets the target cell to a program complete state in response to the threshold voltage Vth of the target cell becoming greater than the third voltage Vref.

[0166] At this time, ΔVpg is set to be smaller than the difference between the third voltage Vref and the first voltage Vref max and the difference between the third voltage Vref and the second voltage Vref min. Therefore, if the threshold voltage Vth does not reach the third voltage Vref when the third program voltage Vpg is applied and the threshold voltage Vth reaches the third voltage Vref when the fourth program voltage Vpg is applied, the threshold voltage Vth of the target cell immediately after the fourth program voltage Vpg is applied belongs to the target threshold voltage range. That is, the target cell is in a state where the data to be written is stored.

[0167] Next, the erase operation will be described. The peripheral circuit 51 selects a memory cell to be written from a memory cell group to be programmed, and judges whether or not the threshold voltage Vth of the memory cell to be written is greater than the target threshold voltage Vref of the memory cell to be written. If the threshold voltage Vth of the memory cell to be written is greater than the target threshold voltage Vref, the peripheral circuit 51 executes an erase operation on the selected memory cell to be written. That is, the peripheral circuit 51 executes an erase operation to apply the erase voltage Ver only to the memory cell to be written. In the write process using the second method, the peripheral circuit 51 judges whether or not the threshold voltage Vth of the memory cell to be written has become equal to or less than the target threshold voltage Vref every time the peripheral circuit 51 applies the erase voltage Ver to the memory cell to be written. Then, when the threshold voltage Vth becomes equal to or less than the target threshold voltage Vref, the peripheral circuit 51 sets the memory cell to be written to a program completion state. The peripheral circuit 51 repeatedly performs an operation of applying an erase voltage Ver to the memory cell to be written to and an operation of determining whether the threshold voltage Vth of the memory cell to be written to has become equal to or lower than the target threshold voltage Vref, thereby putting the memory cell to be written into a program complete state.

[0168] Here, it is assumed that an erase operation is being performed on a memory cell to be written to. Figures 13A and 13B are diagrams showing an example of a change in threshold voltage Vth due to an erase operation performed in the NAND memory 5 according to the embodiment.

[0169] 13A and 13B, the vertical axis indicates the current value read from each memory cell to which a read voltage Vrv is applied, and the horizontal axis indicates the threshold voltage Vth of each memory cell.

[0170] The target threshold voltage Vref indicates a voltage (third voltage) determined based on data to be written to the memory cell to be written. Here, the third voltage Vref is less than a value indicating an upper limit of the target threshold voltage range and greater than a value indicating a lower limit of the target threshold voltage range. The threshold voltage Vth indicates a current threshold voltage value of the memory cell to be written.

[0171] 13A shows the threshold voltage Vth of the target cell before the application of the erase voltage Ver and the change in threshold voltage ΔVer due to the application of the erase voltage Ver in the first erase operation. For example, the peripheral circuit 51 determines whether the threshold voltage Vth of the target cell has become equal to or lower than the third voltage Vref every time the erase voltage Ver is applied to the target cell. Since the threshold voltage Vth of the target cell after the first application of the erase voltage Ver is still greater than the third voltage Vref, the peripheral circuit 51 does not yet set the target cell to the program complete state.

[0172] 13B shows the threshold voltage Vth of the target cell before the erase operation is applied and the change in threshold voltage ΔVer caused by the application of the erase voltage Ver in the second erase operation. The threshold voltage Vth of the target cell decreases by ΔVer, so that the threshold voltage Vth becomes less than the third voltage Vref. Then, the peripheral circuit 51 sets the target cell to a program complete state in response to the threshold voltage Vth of the target cell becoming less than the third voltage Vref.

[0173] At this time, ΔVer is set to be smaller than the difference between the third voltage Vref and the first voltage Vref max and the difference between the third voltage Vref and the second voltage Vref min. Therefore, if the threshold voltage Vth does not reach the third voltage Vref in the first application of the erase voltage and the threshold voltage Vth falls below the third voltage Vref in the second application of the erase voltage Ver, the threshold voltage Vth of the target cell immediately after the second application of the erase voltage Ver is executed belongs to the target threshold voltage range. That is, the target cell is in a state where the data to be written is stored.

[0174] 14 is a block diagram showing a second example of the flow of a write process executed in the NAND memory 5 according to the embodiment. First, in response to receiving a write command from the host 2, the controller 4 transmits a program request to the NAND memory 5 via the NAND interface 46. The controller 4 may transmit a program request to the NAND memory 5 spontaneously, instead of as a write command received from the host 2.

[0175] In steps S21 to S25, the peripheral circuit 51 executes the same processes as the processes S1 to S5 described with reference to FIG.

[0176] S26: The sequencer 5106 instructs the voltage generating circuit 5108 to generate a target threshold voltage Vref (for example, a third voltage Vref) corresponding to the data to be newly written to the target cell TC. The target threshold voltage Vref is, for example, the median value of the target threshold voltage range.

[0177] S27: The voltage generating circuit 5108 outputs the target threshold voltage Vref generated based on an instruction from the sequencer 5106 to the comparing circuit 5109. Here, the processes of S26-S27 do not necessarily have to be executed after S25, and may be executed in parallel with or independently of the processes of S22-S25.

[0178] S28: The comparison circuit 5109 judges whether the threshold voltage Vth input from the sense amplifier module 5111 is larger than the target threshold voltage Vref, and outputs the judgment result to the sequencer 5106.

[0179] If the determination result output in S28 indicates that the threshold voltage Vth is greater than the target threshold voltage Vref, the peripheral circuit 51 executes the processes of S29-30.

[0180] S29: The sequencer 5106 transmits an erase instruction to the voltage generating circuit 5108 to generate an erase voltage Ver used in an erase operation on the target cell TC. The erase instruction may include information specifying, for example, a predetermined magnitude of the erase voltage Ver, a time for applying the erase voltage Ver, or a number of times for applying the erase voltage Ver. The sequencer 5106 also transmits information for specifying the selected target cell to other components of the peripheral circuit 51, thereby specifying the target cell TC included in the memory cell array 52. ​​The sequencer 5106 outputs, for example, information specifying the word line WL, the bit line BL, and the select gate lines SGD, SGS, and source line SL corresponding to the target cell TC, to which the target cell TC is connected.

[0181] S30: The voltage generation circuit 5108 outputs the erase voltage Ver generated based on the received erase instruction to the memory cell array 52. ​​The memory cell array 52 controls the erase operation on the target cell TC using the erase voltage Ver generated by the voltage generation circuit 5108. For example, the erase operation is controlled by applying the erase voltage Ver to a word line connected to a memory cell group including the target cell TC while a predetermined voltage value is applied to a bit line corresponding to the target cell TC.

[0182] After S30 is completed, the peripheral circuit 51 executes the processes of S22-28 again, whereby the peripheral circuit 51 repeatedly executes the erase operation until the threshold voltage Vth of the target cell TC becomes equal to or lower than the target threshold voltage Vref.

[0183] S31: After S30, if a determination result is received indicating that the threshold voltage Vth of the target cell TC is equal to or lower than the target threshold voltage Vref, the sequencer 5106 sets the target cell TC to a program completion state (inhibit). This prevents the program voltage Vpg from being applied to the target cell TC when a program operation is performed on other memory cells in the memory cell group including the target cell TC. After that, the sequencer 5106 selects the next target cell TC from the memory cell group to be programmed, and executes the process from S22 onwards again.

[0184] Furthermore, if the judgment result output in S28 for the first time after the target cell TC is selected indicates that the threshold voltage Vth is equal to or lower than the target threshold voltage Vref, the peripheral circuit 51 does not do anything to the target cell TC, but selects the next target cell TC from the memory cell group to be programmed, and re-executes the processing from S22 onwards.

[0185] After the selection of each of the memory cells included in the memory cell group to be programmed as the target cell TC is completed, the peripheral circuit 51 executes the process of S32-33. The process of S32-33 is similar to the process of S12-S13 described with reference to FIG.

[0186] Next, a procedure of a write process using the second method will be described. Fig. 15 is a flowchart showing a second example of the procedure of a write process executed in the NAND memory 5 according to the embodiment. In response to receiving a program request from the controller 4, the peripheral circuit 51 starts the write process.

[0187] The peripheral circuit 51 selects a memory cell group to be programmed based on the received program request (S201).

[0188] The peripheral circuit 51 selects a memory cell to be written (target cell) from among the multiple memory cells included in the memory cell group selected in S201 (S202).

[0189] The peripheral circuit 51 determines a target threshold voltage Vref of the target cell based on data associated with the program request (S203). The target threshold voltage Vref is a voltage (third voltage Vref) that belongs to a threshold voltage range corresponding to data to be newly written to the target cell. Here, the target threshold voltage Vref is less than a value indicating an upper limit of the target threshold voltage range and greater than a value indicating a lower limit of the target threshold voltage range. For example, the target threshold voltage Vref is a median value of the target threshold voltage range.

[0190] The peripheral circuit 51 executes a read operation on the target cell using the read voltage Vrv, and obtains the current threshold voltage Vth of the target cell (S204).

[0191] The peripheral circuit 51 determines whether the threshold voltage Vth of the target cell obtained in S204 is equal to or lower than the target threshold voltage Vref determined in S203 (S205).

[0192] If the threshold voltage Vth of the target cell acquired in S204 is greater than the target threshold voltage Vref determined in S203 (No in S205), the peripheral circuit 51 applies the erase voltage Ver to the target cell (S206). The peripheral circuit 51 determines the magnitude of the erase voltage Ver to be applied so that the magnitude of the threshold voltage Vth that varies with one application of the erase voltage Ver is smaller than the difference between the target threshold voltage Vref and the value indicating the upper limit of the target threshold voltage range and the difference between the target threshold voltage Vref and the value indicating the lower limit of the target threshold voltage range. The peripheral circuit 51 may determine not only the magnitude of the erase voltage Ver but also the time and number of times the erase voltage Ver is applied.

[0193] The peripheral circuit 51 executes a read operation on the target cell using the read voltage Vrv, and obtains the current threshold voltage Vth of the target cell again (S207).

[0194] The peripheral circuit 51 determines whether the threshold voltage Vth of the target cell is equal to or lower than the target threshold voltage Vref (S208).

[0195] If the threshold voltage Vth of the target cell is still greater than the target threshold voltage Vref even after application of the erase voltage Ver (No in S208), the peripheral circuit 51 returns to S206 and applies the erase voltage Ver to the target cell again.

[0196] If the threshold voltage Vth of the target cell becomes equal to or lower than the target threshold voltage Vref (Yes in S208), the peripheral circuit 51 sets the target cell to a program complete state (inhibit) (S209).

[0197] If the threshold voltage Vth of the target cell is equal to or lower than the target threshold voltage Vref (Yes in S205), or after completing the processing of S209, the peripheral circuit 51 determines whether all memory cells included in the memory cell group to be programmed have been selected as target cells (S210).

[0198] If there is a memory cell that has not yet been selected among the memory cells included in the memory cell group to be programmed (No in S210), the peripheral circuit 51 returns to S202 and selects the next target cell from among the multiple memory cells included in the memory cell group to be programmed that have not yet been selected as a target cell.

[0199] If all memory cells included in the memory cell group to be programmed have been selected (Yes in S210), the peripheral circuit 51 executes a program operation on the memory cell group to be programmed (S211).

[0200] Thus, in a write process using the second method, the peripheral circuit 51 including the sequencer 5106, the voltage generation circuit 5108, the comparison circuit 5109, and the sense amplifier module 5111 controls the read operation, the erase operation, and the program operation for the target cell based on the magnitude relationship between the current threshold voltage Vth of the target cell and the target threshold voltage Vref determined based on the data to be written to the target cell.

[0201] As a result, in the write process using the second method, similarly to the case where the first method is used, if the current threshold voltage Vth of the target cell is higher than the target threshold voltage Vref, the peripheral circuit 51 can set the target cell to a program complete state by only lowering the threshold voltage Vth through an erase operation, without passing through an erase state. Also, if the current threshold voltage Vth of the target cell is equal to or lower than the target threshold voltage Vref, the peripheral circuit 51 can set the target cell to a program complete state by only raising the threshold voltage Vth through a program operation, without passing through an erase state.

[0202] Next, the correspondence relationship between the combination of the original state of the memory cell to be written and the state after data is written, and the operation performed on the memory cell to be written in the write process will be described. FIG. 16 is a diagram showing the correspondence relationship between the combination of the original state of the memory cell to be written included in the NAND memory 5 according to the embodiment and the state after writing, and the write process. Here, it is assumed that the write process is performed using the first method. Also, it is assumed that data is written to the memory cell in the MLC mode.

[0203] For example, if the current threshold voltage Vth of the target cell is within the target threshold voltage range, the peripheral circuit 51 does not perform a program operation or an erase operation in the write process. Also, if the current threshold voltage Vth of the target cell is greater than a value indicating the upper limit of the target threshold voltage range, the peripheral circuit 51 performs only an erase operation on the target cell. Furthermore, if the current threshold voltage Vth of the target cell is less than a value indicating the lower limit of the target threshold voltage range, the peripheral circuit 51 performs only a program operation on the target cell. That is, the peripheral circuit 51 controls the operation to be performed on the target cell in the write process based on the combination between the data currently stored in the target cell (the state of the memory cell before the write process is executed) and the data to be written to the target cell (the state of the memory cell after the write process is executed).

[0204] The following provides specific examples of combinations of the original state of the target cell and the state after writing to the target cell, and operations executed on the target cell.

[0205] Also, in FIG. 16, as in the case of FIG. 8, the threshold voltage range with the highest peak threshold voltage corresponds to cell data (0, 1), the threshold voltage range with the second highest peak threshold voltage corresponds to cell data (0, 0), the threshold voltage range with the third highest peak threshold voltage corresponds to cell data (1, 0), and the threshold voltage range with the lowest peak threshold voltage corresponds to cell data (1, 1) indicating the erased state.

[0206] If the original state is a state in which cell data (1, 1) is stored and the state after writing is a state in which cell data (0, 1) is stored, the peripheral circuit 51 performs only a program operation on the target cell because the threshold voltage range corresponding to the cell data (1, 1) is lower than the threshold voltage range corresponding to the cell data (0, 1).

[0207] If the original state is a state in which cell data (1, 1) is stored and the state after writing is a state in which cell data (0, 0) is stored, the peripheral circuit 51 performs only a program operation on the target cell because the threshold voltage range corresponding to the cell data (1, 1) is lower than the threshold voltage range corresponding to the cell data (0, 0).

[0208] If the original state is a state in which cell data (1, 1) is stored and the state after writing is a state in which cell data (1, 0) is stored, the peripheral circuit 51 performs only a program operation on the target cell because the threshold voltage range corresponding to the cell data (1, 1) is lower than the threshold voltage range corresponding to the cell data (1, 0).

[0209] If the original state is a state in which cell data (1, 1) is stored and the post-write state is a state in which cell data (1, 1) is stored, the peripheral circuit 51 performs neither a program operation nor an erase operation on the target cell.

[0210] If the original state is a state in which cell data (1, 0) is stored and the post-write state is a state in which cell data (0, 1) is stored, the threshold voltage range corresponding to cell data (1, 0) is lower than the threshold voltage range corresponding to cell data (0, 1), so the peripheral circuit 51 executes only the program operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes an erase operation until the target cell enters a state in which cell data (1, 1) is stored (erased state) and then executes a program operation.

[0211] If the original state is a state in which cell data (1, 0) is stored and the state after writing is a state in which cell data (0, 0) is stored, the threshold voltage range corresponding to cell data (1, 0) is lower than the threshold voltage range corresponding to cell data (0, 0), so the peripheral circuit 51 executes only the program operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes the erase operation until the target cell is in the erased state and then executes the program operation.

[0212] When the original state is a state in which cell data (1, 0) is stored and the post-write state is a state in which cell data (1, 0) is stored, the peripheral circuit 51 does not execute either a program operation or an erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes an erase operation until the target cell is in the erased state and then executes a program operation.

[0213] If the original state is a state in which cell data (1, 0) is stored and the state after writing is a state in which cell data (1, 1) is stored, the peripheral circuit 51 performs only an erase operation on the target cell, since the threshold voltage range corresponding to the cell data (1, 0) is higher than the threshold voltage range corresponding to the cell data (1, 1).

[0214] If the original state is a state in which cell data (0, 0) is stored and the state after writing is a state in which cell data (0, 1) is stored, the threshold voltage range corresponding to cell data (0, 0) is lower than the threshold voltage range corresponding to cell data (0, 1), so the peripheral circuit 51 executes only the program operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes the erase operation until the target cell is in the erased state and then executes the program operation.

[0215] When the original state is a state in which cell data (0, 0) is stored and the post-write state is a state in which cell data (0, 0) is stored, the peripheral circuit 51 does not execute either a program operation or an erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case in which the peripheral circuit 51 executes an erase operation until the target cell is in the erased state and then executes a program operation.

[0216] If the original state is a state in which cell data (0, 0) is stored and the state after writing is a state in which cell data (1, 0) is stored, the threshold voltage range corresponding to cell data (0, 0) is higher than the threshold voltage range corresponding to cell data (1, 0), so the peripheral circuit 51 executes only the erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case in which the erase operation is executed until the target cell is in the erased state, and then the program operation is executed.

[0217] If the original state is a state in which cell data (0, 0) is stored and the state after writing is a state in which cell data (1, 1) is stored, the peripheral circuit 51 performs only an erase operation on the target cell, since the threshold voltage range corresponding to the cell data (0, 0) is higher than the threshold voltage range corresponding to the cell data (1, 1).

[0218] When the original state is a state in which cell data (0, 1) is stored and the post-write state is a state in which cell data (0, 1) is stored, the peripheral circuit 51 does not execute either a program operation or an erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes an erase operation until the target cell is in the erased state and then executes a program operation.

[0219] If the original state is a state in which cell data (0, 1) is stored and the state after writing is a state in which cell data (0, 0) is stored, the threshold voltage range corresponding to cell data (0, 1) is higher than the threshold voltage range corresponding to cell data (0, 0), so the peripheral circuit 51 executes only the erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case where the peripheral circuit 51 executes the erase operation until the target cell is in the erased state and then executes the program operation.

[0220] If the original state is a state in which cell data (0, 1) is stored and the post-write state is a state in which cell data (1, 0) is stored, the threshold voltage range corresponding to cell data (0, 1) is higher than the threshold voltage range corresponding to cell data (1, 0), so the peripheral circuit 51 executes only the erase operation on the target cell. In this case, the peripheral circuit 51 can reduce the amount of charge discharged from the charge storage layer of the target cell compared to the case in which the peripheral circuit 51 executes the erase operation until the target cell is in the erased state and then executes the program operation.

[0221] If the original state is a state in which cell data (0, 1) is stored and the state after writing is a state in which cell data (1, 1) is stored, the peripheral circuit 51 performs only an erase operation on the target cell, since the threshold voltage range corresponding to the cell data (0, 1) is higher than the threshold voltage range corresponding to the cell data (1, 1).

[0222] As described above, in the NAND memory 5 according to the present embodiment, when the threshold voltage Vth of the target cell is greater than the target threshold voltage Vref, the peripheral circuit 51 executes an erase operation on the target cell so that data to be written in the target cell is stored. Then, the peripheral circuit 51 sets the target cell to a program complete state. At this time, the amount of charge discharged from the charge storage layer of the target cell is less than that in the case where a program operation is executed after the target cell is once put into an erase state. This allows the peripheral circuit 51 to execute data writing to the target cell while suppressing deterioration of the memory cell.

[0223] Furthermore, when the peripheral circuit 51 receives a program request and information specifying the write process of the embodiment, the peripheral circuit 51 may execute the write process using the first method or the second method. When the controller 4 does not specify the write process of the embodiment or specifies the write process of the comparative example, the peripheral circuit 51 may execute the write process of the comparative example, which executes an erase operation to put each memory cell of the entire block to be written into an erased state, and then executes a program operation on each page. In this way, the peripheral circuit 51 can selectively execute the write process of the embodiment and the write process of the comparative example.

[0224] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0225] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 21...processor, 22...memory, 41...host interface, 42...SRAM, 43...CPU, 44...DMAC, 45...error correction circuit, 46...NAND interface, 47...DRAM interface, 51...peripheral circuit, 52...memory cell array, 61...L2P table, 431...write processing unit, 432...read processing unit, 5101...input / output circuit, 5102...logic control circuit, 5103...address register, 5104...command register, 5105...status register, 5106...sequencer, 5107...ready / busy circuit, 5108...voltage generation circuit, 5109...comparison circuit, 5110...row decoder, 5111...sense amplifier module, 5112...data register, 5113...column decoder.

Claims

1. A plurality of memory cells configured to store data corresponding to a threshold voltage range to which each of the memory cells has a threshold voltage; a control circuit configured to control the plurality of memory cells; The control circuit determines whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined based on data to be stored in the memory cell to be written; generating an erase voltage to be applied to the memory cell to be programmed if the first threshold voltage is higher than the second threshold voltage; performing an erase operation using the erase voltage to lower a threshold voltage of the memory cell to be written so that the memory cell to be written stores the data to be stored; It is configured as follows: Semiconductor memory device.

2. The control circuit includes: a sequencer that controls program and erase operations performed on the plurality of memory cells; a voltage generating circuit that generates a voltage applied to each of the plurality of memory cells and the second threshold voltage; a comparison circuit that compares the threshold voltage of the memory cell to be written and the second threshold voltage generated by the voltage generation circuit to determine which is larger.

2. The semiconductor memory device according to claim 1.

3. the plurality of memory cells includes a plurality of memory cell groups; The control circuit includes: A write request is received, selecting a memory cell group to be written from the plurality of memory cell groups based on the write request; and selecting each of the memory cells included in the memory cell group to be written as the memory cell to be written.

2. The semiconductor memory device according to claim 1.

4. the second threshold voltage is a first voltage indicating an upper limit of a threshold voltage range determined based on data to be stored in the memory cell to be written, among data associated with the write request; The control circuit includes: generating the first voltage and a second voltage indicating a lower limit of the threshold voltage range; comparing the first threshold voltage to the first voltage and the second voltage; If the first threshold voltage is equal to or lower than the first voltage and equal to or higher than the second voltage, completing the write to the memory cell to be written; generating a program voltage to be applied to one or more memory cells when the threshold voltage is less than the second voltage and the data to be stored is not stored in the memory cell group to be written; performing a program operation on each of the one or more memory cells using the program voltage until a threshold voltage of each of the one or more memory cells is less than the first voltage and greater than or equal to the second voltage corresponding to each of the one or more memory cells; It is configured as follows:

4. The semiconductor memory device according to claim 3.

5. the second threshold voltage is a third voltage that is determined based on data associated with the write request; The control circuit includes: generating the erase voltage when the first threshold voltage is greater than the third voltage; Repeating a process including: performing the erase operation using the generated erase voltage; and determining whether or not a threshold voltage of the memory cell to be written has become equal to or lower than the third voltage; After the threshold voltage of the memory cell to be programmed becomes equal to or lower than the third voltage, the erase operation on the memory cell to be programmed is completed; generating a program voltage to be applied to one or more memory cells when the threshold voltage is lower than the third voltage and the data to be stored is not stored in the one or more memory cells included in the memory cell group to be written; performing a program operation on each of the one or more memory cells using the program voltage until a threshold voltage of each of the one or more memory cells becomes equal to or greater than the third voltage corresponding to each of the one or more memory cells; It is configured as follows:

4. The semiconductor memory device according to claim 3.

6. The control circuit includes: When the erase operation is performed, determining at least one of the magnitude of the erase voltage, the time for applying the erase voltage, and the number of times the erase voltage is applied, based on the data currently stored in the memory cell to be written and the data to be stored in the memory cell to be written; It is configured as follows:

2. The semiconductor memory device according to claim 1.

7. A semiconductor memory device according to any one of claims 1 to 6, A controller configured to control the semiconductor memory device. Memory system.

8. The controller: transmitting a write request to the semiconductor memory device, the write request specifying a memory cell in which invalid data is stored, among memory cells included in the semiconductor memory device, as a memory cell to which next data is to be written; It is configured as follows:

8. The memory system of claim 7.

9. 1. A method of controlling a plurality of memory cells configured to store data corresponding to a threshold voltage range each having a threshold voltage, the method comprising: Determining whether a first threshold voltage of a memory cell to be programmed is higher than a second threshold voltage determined based on data to be stored in the memory cell to be programmed; generating an erase voltage to be applied to the memory cell to be programmed if the first threshold voltage is higher than the second threshold voltage; performing an erase operation to lower a threshold voltage of the memory cell to be programmed using the erase voltage so that the memory cell to be programmed stores the data to be stored; Equipped with Control methods.

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