Memory device

Abstract

To provide a memory device to improve reliability.SOLUTION: A memory device of the embodiment includes a memory cell array including first to ninth areas, first and second column switching circuits, and first and second row switching circuits. When the first area is selected, the first and second column switching circuits and the first and second row switching circuits are activated, when any one of the second to fifth areas is selected, one of the first and second column switching circuits and one of the first and second row switching circuits are activated, when any one of the sixth and eighth areas is selected, both of the first and second column switching circuits and one of the first and second row switching circuits are activated, and when any one of the seventh to the ninth areas is selected, one of the first and second column switching circuits and both of the first and second row switching circuits are activated.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to memory devices. [Background technology]

[0002] Variable resistance element (e.g., magnetoresistive effect element) 2. Description of the Related Art Memory devices using a semiconductor laser as a memory element are known. In order to improve the characteristics of memory devices, research and development of various technologies relating to memory devices is being carried out. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2012 / 0069627A1 [Patent Document 2] US Patent Application Publication No. 2011 / 0044090A1 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the reliability of a memory device. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each connected to one of the plurality of bit lines and one of the plurality of word lines, and having first to ninth areas set therein; a first column switch circuit connected to the plurality of bit lines and provided at one end of the memory cell array in a first direction; a second column switch circuit connected to the plurality of bit lines and provided at the other end of the memory cell array in the first direction; a first row switch circuit connected to the plurality of word lines and provided at one end of the memory cell array in a second direction; and a second row switch circuit connected to the plurality of word lines and provided at the other end of the memory cell array in the second direction. When a memory cell in the first area is selected, the first and second column switch circuits and the first and second row switch circuits are activated, and when a memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated. when a memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated; when a memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated; when a memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated; when a memory cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated; when a memory cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated; when a memory cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated; and when a memory cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a block diagram showing an example of the configuration of a memory device according to the first embodiment. [Diagram 2] 1 is a circuit diagram showing an example of the configuration of a memory cell array in a memory device according to a first embodiment. [Diagram 3] 1 is a bird's-eye view showing a configuration example of a memory cell array of a memory device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a configuration example of a memory cell array of a memory device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a configuration example of a memory cell array of a memory device according to a first embodiment. [Figure 6] FIG. 2 is a schematic diagram showing a configuration example of a memory cell of the memory device according to the first embodiment; [Figure 7] FIG. 2 is a diagram showing a circuit configuration in the vicinity of a memory cell array of the memory device according to the first embodiment. [Figure 8] FIG. 4 is a schematic diagram showing an operating state of a column switch circuit of the memory device according to the first embodiment. [Figure 9] 4 is a schematic diagram showing an operating state of a row switch circuit of the memory device according to the first embodiment; FIG. [Figure 10] 2 is a diagram for explaining areas in a memory cell array of the memory device according to the first embodiment; [Figure 11] FIG. 4 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 12] FIG. 4 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 13] FIG. 4 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 14] FIG. 4 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 15] FIG. 4 is a diagram showing characteristics of the memory device according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, elements having the same functions and configurations are denoted by the same reference numerals. In the following embodiments, for multiple identical components (e.g., circuits, wiring, various voltages and signals, etc.), a distinguishing number / letter may be added to the end of the reference symbol. When components having a reference symbol with a distinguishing number / letter at the end are not required to be distinguished from each other, a description (reference symbol) with the number / letter at the end omitted is used.

[0008] (1) First embodiment A memory device 100 according to an embodiment will be described with reference to FIGS.

[0009] (a) Configuration example An example of the configuration of a memory device according to a first embodiment will be described with reference to FIGS.

[0010] (a-1) Overall configuration FIG. 1 is a diagram showing an example of the configuration of a memory device 100 according to the present embodiment.

[0011] As shown in FIG. 1, a memory device 100 of this embodiment is connected to a device 900 external to the memory device 100 (hereinafter, referred to as an external device).

[0012] The external device 900 sends a command CMD, an address ADR, and a control signal CNT to the memory device 100. Data DT is transferred between the memory device 100 and the external device 900. During a write operation, the external device 900 sends data to be written in the memory device 100 (hereinafter referred to as write data) to the memory device 100. During a read operation, the external device 900 receives data read from the memory device 100 (hereinafter referred to as read data) from the memory device 100.

[0013] The memory device 100 of this embodiment includes a memory cell array 110, a column control circuit 120, a row control circuit 130, a write circuit 140, a read circuit 150, a voltage generation circuit 160, an input / output circuit 170, and a control circuit 180.

[0014] The memory cell array 110 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0015] The memory cells MC correspond to a plurality of rows and a plurality of columns in the memory cell array 110. Each memory cell MC is connected to a corresponding one of a plurality of word lines WL. Each memory cell MC is connected to a corresponding one of a plurality of bit lines BL.

[0016] The column control circuit 120 controls the columns of the memory cell array 110. The column control circuit 120 is connected to the memory cell array 110 via bit lines BL. The column control circuit 120 receives a column address (or a decoded result of the column address) of the memory cell array 110 at an address ADR. The column control circuit 120 controls a plurality of bit lines BL based on the decoded result of the column address. As a result, the column control circuit 120 sets each of the plurality of bit lines BL (a plurality of columns) to a selected state or a non-selected state. In the following, the bit line BL set to the selected state is called a selected bit line BL, and the bit lines BL other than the selected bit line BL are called non-selected bit lines BL. The column control circuit 120 includes a plurality of column switch circuits 121. Each column switch circuit 121 controls a connection between a selected bit line BL and a global wiring described later.

[0017] The row control circuit 130 controls the rows of the memory cell array 110. The row control circuit 130 is connected to the memory cell array 110 via word lines WL. The row control circuit 130 receives a row address (or a decoded result of the row address) of the memory cell array 110 at an address ADR. The row control circuit 130 controls a plurality of word lines WL based on the decoded result of the row address. As a result, the row control circuit 130 sets each of the plurality of word lines WL (a plurality of rows) to a selected state or a non-selected state. In the following, a word line WL set to a selected state is called a selected word line WL, and word lines WL other than the selected word line WL are called non-selected word lines WL. The row control circuit 130 includes a plurality of row switch circuits 131. Each row switch circuit 131 controls a connection between a selected word line WL and a global wiring described later.

[0018] The write circuit 140 writes data to the memory cell MC. The write circuit 140 supplies a voltage (or current) for writing data to each of the selected word line WL and the selected bit line BL via global wiring. This causes a certain write voltage (or write current) to be supplied to the selected memory cell MC. The write circuit 140 can supply one of a plurality of write voltages according to the write data to the selected memory cell MC. For example, each of the plurality of write voltages has a polarity (bias direction) according to the write data. For example, the write circuit 140 includes a write driver (not shown) and a write sink (not shown).

[0019] The read circuit 150 reads data from the memory cell MC. The read circuit 150 amplifies a signal output from the selected memory cell MC to a selected bit line BL. The read circuit 150 determines the data in the memory cell MC based on the amplified signal. For example, the read circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a read driver (not shown), and a read sink (not shown).

[0020] The voltage generation circuit 160 generates voltages for various operations of the memory cell array 110 using a power supply voltage provided by the external device 900. For example, the voltage generation circuit 160 generates various voltages used in a write operation. The voltage generation circuit 160 outputs the generated voltages to the write circuit 140. For example, the voltage generation circuit 160 generates various voltages used in a read operation. The voltage generation circuit 160 outputs the generated voltages to the read circuit 150.

[0021] The input / output circuit 170 functions as an interface circuit for various signals ADR, CMD, CNT, and DT between the memory device 100 and the external device 900. The input / output circuit 170 transfers an address ADR from the external device 900 to the control circuit 180. The input / output circuit 170 transfers a command CMD from the external device 900 to the control circuit 180. The input / output circuit 170 transfers various control signals CNT between the external device 900 and the control circuit 180. The input / output circuit 170 transfers write data DT from the external device 900 to the write circuit 140. The input / output circuit 170 transfers data DT from the read circuit 150 to the external device 900 as read data.

[0022] The control circuit 180 (also called a sequencer, state machine, or internal controller) decodes the command CMD. The control circuit 180 controls the operations of the column control circuit 120, row control circuit 130, write circuit 140, read circuit 150, voltage generation circuit 160, and input / output circuit 170 in the memory device 100 based on the decoded result of the command CMD and the control signal CNT. The control circuit 180 decodes the address ADR. The control circuit 180 sends the decoded result of the address ADR to the column control circuit 120, row control circuit 130, and the like. For example, the control circuit 180 includes a register circuit (not shown) that temporarily stores the command CMD and the address ADR. Note that the register circuit, a circuit (command decoder) for decoding the command CMD, and a circuit (address decoder) for decoding the address ADR may be provided in the memory device 100 outside the control circuit 180.

[0023] (a-2) Memory cell array A configuration example of the memory cell array 110 in the memory device 100 of this embodiment will be described with reference to FIGS.

[0024] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array 110 of the memory device 100 of this embodiment.

[0025] 2, a plurality of memory cells MC are arranged in a matrix in the memory cell array 110. Each memory cell MC is connected to a plurality of bit lines BL (BL <0> ,BL <1> , ,BL <n>) and a plurality of word lines WL (WL <0> , W.L. <1> ,···,WL <m>), where M and N are integers of 1 or greater.

[0026] Each memory cell MC includes a memory element 1 and a switching element 2.

[0027] The memory element 1 is, for example, a variable resistance element. The resistance state of the memory element 1 changes to one of a plurality of resistance states (for example, a low resistance state and a high resistance state) depending on a supplied voltage (or current). The memory element 1 can store data by associating the resistance state of the element 1 with data (for example, data "0" and data "1").

[0028] The switching element (also called a selector element or simply a selector) 2 functions as a selection element for the memory cell MC. The switching element 2 has a function of controlling the supply of a voltage (or a current) to the corresponding memory element 1 when writing data to the corresponding memory element 1 and when reading data from the corresponding memory element 1.

[0029] For example, when a voltage applied to a certain memory cell MC is lower than the threshold voltage of the switching element 2 in that memory cell MC, the switching element 2 is set to the OFF state (high resistance state, non-conducting state). In this case, the switching element 2 cuts off the voltage (or current) to the memory element 1. When a voltage applied to a certain memory cell MC is equal to or higher than the threshold voltage of the switching element 2 in that memory cell MC, the switching element 2 is set to the ON state (low resistance state, conducting state). In this case, the switching element 2 supplies a voltage (or current) to the memory element 1.

[0030] The switching element 2 can switch whether to allow a current to flow through the memory cell MC or not depending on the magnitude of the voltage applied to the memory cell MC, regardless of the direction of the current flow in the memory cell MC.

[0031] For example, the switching element 2 is a two-terminal element. In the example of Fig. 2, one end of the switching element 2 is connected to a word line WL. The other end of the switching element 2 is connected to one end of the memory element 1. The other end of the memory element 1 is connected to a bit line BL.

[0032] 3 to 5 are diagrams for explaining a configuration example of the memory cell array 110 of the memory device 100 of this embodiment. FIG. 3 is a bird's-eye view for explaining a configuration example of the memory cell array 110. FIG. 4 is a schematic cross-sectional view showing a cross-sectional structure along a first direction (axis) of the memory cell array 110. FIG. 5 is a schematic cross-sectional view showing a cross-sectional structure along a second direction (axis) of the memory cell array 110. In the examples of FIGS. 3 to 5, the first direction corresponds to the X direction, and the second direction corresponds to the Y direction.

[0033] As shown in FIGS. 3 to 5, the memory cell array 110 is provided above the upper surface of the substrate 90. The X direction is a direction parallel to the upper surface of the substrate 90. The Y direction is a direction parallel to the upper surface of the substrate 90 and intersects with the X direction. Hereinafter, a plane parallel to the upper surface of the substrate 90 is called the XY plane. A direction (axis) perpendicular to the XY plane is the Z direction (Z axis). A plane parallel to the plane consisting of the X and Z directions is called the XZ plane. A plane parallel to the plane consisting of the Y and Z directions is called the YZ plane.

[0034] A plurality of wirings (conductive layers) 50 are provided above the upper surface of the substrate 90 in the Z direction, with an insulating layer 91 interposed therebetween. The plurality of wirings 50 are aligned along the X direction. Each of the wirings 50 extends along the Y direction. The plurality of wirings 50 function as, for example, word lines WL.

[0035] The multiple wirings (conductive layers) 51 are provided above the multiple wirings 50 in the Z direction. The multiple wirings 51 are lined up along the Y direction. Each wiring 51 extends along the X direction. The multiple wirings 51 function as, for example, bit lines BL.

[0036] A plurality of memory cells MC are provided between a plurality of wirings 50 and a plurality of wirings 51. The plurality of memory cells MC are arranged in a matrix in the XY plane.

[0037] A plurality of memory cells MC aligned in the Y direction are provided above one wiring 50. Two memory cells MC aligned in the Y direction are adjacent to each other with a predetermined interval therebetween. Each of the plurality of memory cells MC aligned in the Y direction is connected to a common wiring 50 (word line WL) via a corresponding one of contacts 52. A plurality of contacts 52 are provided on one wiring 50.

[0038] A plurality of memory cells MC aligned in the X direction are provided below one wiring 51. Two memory cells MC aligned in the X direction are adjacent to each other with a predetermined interval therebetween. Each of the plurality of memory cells MC aligned in the X direction is connected to a common wiring 51 (bit line BL) via a corresponding one of contacts 53. The plurality of contacts 53 are provided below one of the wirings 51.

[0039] 2, the switching element 2 is provided below the memory element 1 in the Z direction. The switching element 2 is provided between the memory element 1 and a wiring 50 (word line WL). The memory element 1 is provided between a wiring 51 (bit line BL) and the switching element 2.

[0040] In this manner, each memory cell MC is a stack of the memory element 1 and the switching element 2. Due to the memory cells MC, the memory cell array 110 has a stacked type configuration.

[0041] Depending on the process (eg, etching method) used to form the memory cell array 110, the memory cells MC may have a tapered cross-sectional shape.

[0042] An insulating layer 60 is provided above the substrate 90. The insulating layer 60 covers the memory cells MC, the wirings 50 and 51, and the contacts 52 and 53. An insulating layer 62 is provided on the insulating layer 60 and the wirings 51.

[0043] 4 and 5 show an example in which an insulating layer 91 is provided between the plurality of wirings 50 and the substrate 90. When the substrate 90 is a semiconductor substrate, one or more field effect transistors (not shown) may be provided on a semiconductor region on the upper surface of the substrate 90. The field effect transistors are covered with the insulating layer 91 including a multi-layer wiring structure. The field effect transistors on the substrate 90 are components of circuits such as the column control circuit 120. The field effect transistors are connected to the memory cell array 110 via contact plugs (not shown) and wirings (not shown) in the insulating layer 91. In this way, a circuit for controlling the operation of the memory cell array 110 may be provided below the memory cell array 110 in the Z direction. If the substrate 90 is an insulating substrate, the plurality of wirings 50 may be provided directly on the upper surface of the substrate 90 without the insulating layer 91.

[0044] The circuit configuration and structure of the stacked memory cell array 110 are not limited to the examples shown in Figures 2 to 5. The circuit configuration and structure of the memory cell array 110 may be modified as appropriate depending on the connection relationship of the memory elements 1 and the switching elements 2 to the bit lines BL and word lines WL. For example, the structure of the memory cell array 110 having the circuit configuration of Figure 2 is not limited to the examples of Figures 3 to 5. For example, the switching elements 2 may be provided above the memory elements 1 in the Z direction. In this case, the wiring 50 is used as the bit lines BL, and the wiring 51 is used as the word lines WL.

[0045] (a-3) Memory cell FIG. 6 is a cross-sectional view showing an example of the configuration of a memory cell MC in the memory device 100 of the present embodiment.

[0046] 6, in a memory cell MC of a stack, a memory element 1 and a switching element 2 are aligned in the Z direction. In this example, the memory element 1 is provided on the switching element 2 in the Z direction.

[0047] For example, the variable resistance element serving as the memory element 1 is a magnetoresistive effect element. In this case, the memory device 100 of the present embodiment is a magnetic memory such as an MRAM (Magnetoresistive Random Access Memory).

[0048] <Configuration example of magnetoresistance effect element> For example, the magnetoresistance effect element 1 includes at least two magnetic layers 11 and 13 and a nonmagnetic layer 12. The nonmagnetic layer 12 is provided between the two magnetic layers 11 and 13 in the Z direction. In the example of Fig. 6, multiple layers 11, 12, and 13 are arranged in the Z direction in the order of the magnetic layer 11, the nonmagnetic layer 12, and the magnetic layer 13 from the word line WL (wiring 50) side toward the bit line BL (wiring 51) side.

[0049] The two magnetic layers 11 and 13 and the non-magnetic layer 12 form a magnetic tunnel junction. Hereinafter, the magnetoresistance effect element 1 including the magnetic tunnel junction is called an MTJ (Magnetic Tunnel Junction) element 1. The non-magnetic layer 12 in the MTJ element 1 is called a tunnel barrier layer.

[0050] The magnetic layers 11 and 13 are ferromagnetic layers containing, for example, cobalt (Co), iron (Fe) and / or boron (B). The magnetic layers 11 and 13 may be single-layer films (for example, alloy films) or multi-layer films (for example, artificial lattice films). The tunnel barrier layer 12 is, for example, an insulating layer containing magnesium oxide. The tunnel barrier layer 12 may be single-layer films or multi-layer films.

[0051] When the MTJ element 1 is a perpendicular magnetization type magnetoresistance effect element, each of the magnetic layers 11, 13 has perpendicular magnetic anisotropy. The magnetization easy axis direction of each of the magnetic layers 11, 13 is perpendicular to the layer surface (film surface) of the magnetic layers 11, 13. Each of the magnetic layers 11, 13 has magnetization perpendicular to the layer surface of the magnetic layers 11, 13. The magnetization direction of each of the magnetic layers 11, 13 is parallel to the arrangement direction (Z direction) of the magnetic layers 11, 13.

[0052] Of the two magnetic layers 11 and 13, one magnetic layer has a variable magnetization direction, and the other magnetic layer has an invariable magnetization direction. The MTJ element 1 can have a plurality of resistance states (resistance values) according to the relative relationship (magnetization arrangement) between the magnetization direction of one magnetic layer and the magnetization direction of the other magnetic layer.

[0053] For example, the magnetization direction of the magnetic layer 13 is variable. The magnetization direction of the magnetic layer 11 is invariable (fixed state). Hereinafter, the magnetic layer 13 whose magnetization direction is variable is called a memory layer. Hereinafter, the magnetic layer 11 whose magnetization direction is invariable (fixed state) is called a reference layer. The memory layer 13 may also be called a free layer, a magnetization free layer, or a magnetization variable layer. The reference layer 11 may also be called a pinned layer, a pinned layer, a magnetization invariable layer, or a magnetization fixed layer.

[0054] In this embodiment, "the magnetization direction of the reference layer (magnetic layer) is unchanging" or "the magnetization direction of the reference layer (magnetic layer) is fixed" means that when a current or voltage for changing the magnetization direction of the memory layer 13 is supplied to the MTJ element 1, the magnetization direction of the reference layer 11 does not change before or after the supply of the current / voltage due to the supplied current or voltage.

[0055] When the magnetization direction of the memory layer 13 is the same as that of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is the parallel arrangement state), the resistance state of the MTJ element 1 is a first resistance state. When the magnetization direction of the memory layer 13 is different from that of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is the antiparallel arrangement state), the resistance state of the MTJ element 1 is a second resistance state different from the first resistance state. The resistance value of the MTJ element 1 in the second resistance state (antiparallel arrangement state) is higher than the resistance value of the MTJ element 1 in the first resistance state (parallel arrangement state).

[0056] In the following, regarding the magnetization alignment state of the MTJ element 1, the parallel alignment state is also referred to as the P state, and the antiparallel alignment state is also referred to as the AP state.

[0057] For example, the MTJ element 1 is connected to two electrodes 31 and 32. The magnetic layers 11 and 13 and the tunnel barrier layer 12 are provided between the two electrodes 31 and 32 in the Z direction. The reference layer 11 is provided between the electrode (called an intermediate electrode) 31 and the tunnel barrier layer 12. The memory layer 13 is provided between the electrode (called an upper electrode) 32 and the tunnel barrier layer 12.

[0058] For example, the shift cancellation layer 14 may be provided in the MTJ element 1. In this case, the shift cancellation layer 14 is provided between the reference layer 11 and the intermediate electrode 31. The shift cancellation layer 14 is a magnetic layer for reducing the influence of the leakage magnetic field of the reference layer 11. When the MTJ element 1 includes the shift cancellation layer 14, a nonmagnetic layer 15 is provided between the shift cancellation layer 14 and the reference layer 11. The nonmagnetic layer 15 is, for example, a metal layer such as a ruthenium (Ru) layer. The shift cancellation layer 14 is antiferromagnetically coupled to the reference layer 11 via the nonmagnetic layer 15. As a result, the stack including the reference layer 11 and the shift cancellation layer 14 forms a SAF (synthetic antiferromagnetic) structure. In the SAF structure, the magnetization direction of the shift cancellation layer 14 is opposite to the magnetization direction of the reference layer 11. The SAF structure allows the magnetization direction of the reference layer 11 to be more stably fixed. The set of the two magnetic layers 11 and 14 and the nonmagnetic layer 15 that form the SAF structure may be called a reference layer.

[0059] For example, the MTJ element 1 may include at least one of an underlayer (not shown) and a cap layer (not shown). The underlayer is provided between the magnetic layer (here, a shift cancellation layer) 14 and the intermediate electrode 31. The underlayer is a nonmagnetic layer (e.g., a conductive layer). The underlayer is a layer for improving the characteristics (e.g., crystallinity and / or magnetic properties) of the magnetic layer 14 in contact with the underlayer. The cap layer is provided between the magnetic layer (here, a storage layer) 13 and the upper electrode 32. The cap layer is a nonmagnetic layer (e.g., a conductive layer). The cap layer is a layer for improving the characteristics (e.g., crystallinity and / or magnetic properties) of the magnetic layer 13 in contact with the cap layer. Each of the underlayer and the cap layer may be regarded as a component of the electrodes 31 and 32.

[0060] <Example of switching element configuration> 6, when the switching element 2 is a two-terminal type element, the switching element 2 includes at least one variable resistance layer (also called a switching layer or a selector layer) 20. The variable resistance layer 20 is provided between two electrodes 30 and 31 in the Z direction. The variable resistance layer 20 can be in a plurality of resistance states.

[0061] An electrode (called a lower electrode) 30 is provided below the variable resistance layer 20 in the Z direction, and an intermediate electrode 31 is provided above the variable resistance layer 20 in the Z direction. For example, the lower electrode 30 is provided between the wiring 50 and the variable resistance layer 20. The electrode 31 is provided between the variable resistance layer 20 and the MTJ element 1.

[0062] The variable resistance layer 20 is connected to the wiring 50 via the lower electrode 30 and the contact 52. The variable resistance layer 20 is connected to the MTJ element 1 via the intermediate electrode 31.

[0063] Depending on the voltage applied to the switching element 2 (memory cell MC), the resistance state of the variable resistance layer 20 becomes a high resistance state (non-conductive state) or a low resistance state (conductive state). When the resistance state of the variable resistance layer 20 is the high resistance state, the switching element 2 is off. When the resistance state of the variable resistance layer 20 is the low resistance state, the switching element 2 is on.

[0064] When the memory cell MC is set to a selected state, the switching element 2 is turned on, and the resistance state of the variable resistance layer 20 is a low resistance state. When the memory cell MC is set to a non-selected state, the switching element 2 is turned off, and the resistance state of the variable resistance layer 20 is a high resistance state.

[0065] Depending on the material of the variable resistance layer 20, the change in the resistance state of the variable resistance layer 20 may depend on the current (for example, the magnitude of the current) flowing in the switching element 2 (memory cell MC).

[0066] For example, the lower electrode 30 and the upper electrode 32 are conductive layers made of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), etc. The intermediate electrode 31 is a conductive layer made of carbon (C) or carbon nitride (CN).

[0067] The memory cell array 110 having the structure of FIGS. 3 to 6 can be formed using well-known techniques.

[0068] (a-4) Configuration near the memory cell array FIG. 7 is a diagram for explaining the configuration of the MRAM 100 of the present embodiment in the vicinity of the memory cell array 110. In FIG.

[0069] As shown in FIG. 7, the memory cell array 110 has a rectangular layout when viewed in the Z direction.

[0070] M word lines WL <1> ,W.L. <2> ,···,WL <x>···,WL <m-1>,WL <m>are arranged in the memory cell array 110 at predetermined intervals in the X direction. <1> ,BL <2> , ,BL <y>···,BL <n-1>,BL <n>are arranged in the Y direction at predetermined intervals in the memory cell array 110. The bit lines BL are arranged above the word lines WL in the Z direction.

[0071] For example, the memory cell MCa is arranged at coordinates indicated by (x, y) in the memory cell array 110. The memory cell MCa is connected to the word line WL <x>and bit line BL <y>and M intersect. x is an integer of 1 or more and M or less. y is an integer of 1 or more and N or less.

[0072] In this embodiment, the value of "M" is equal to the value of "N". The interval between memory cells MC in the X direction is equal to the interval between memory cells MC in the Y direction. The memory cell array 110 has a square layout (planar structure) when viewed from the Z direction.

[0073] When multiple memory cells MC are arranged at a predetermined interval in the X direction, the resistance between two memory cells MC adjacent in the X direction has a resistance value of "Rs_x". When the address of the bit line BL changes by one, the wiring resistance applied to the memory cells MC changes by "Rs_x". When multiple memory cells MC are arranged at a predetermined interval in the Y direction, the resistance between two memory cells MC adjacent in the Y direction has a resistance value of "Rs_y". When the address of the word line WL changes by one, the wiring resistance applied to the memory cells MC changes by "Rs_y".

[0074] For example, in this embodiment, the value of "Rs_x" is equal to the value of "Rs_y." In the following, the resistance between memory cells MC is represented as "Rs."

[0075] In the MRAM 100 of this embodiment, the column control circuit 120 includes two column switch circuits 121-1 and 121-2.

[0076] Of the two column switch circuits 121-1 and 121-2, the column switch circuit 121-1 is provided at one end in the X direction of the memory cell array 110. Of the two column switch circuits 121-1 and 121-2, the other column switch circuit 121-2 is provided at the other end in the X direction of the memory cell array 110. The memory cell array 110 is provided between the two column switch circuits 121-1 and 121-2 in the X direction.

[0077] The two column switch circuits 121-1 and 121-2 are connected to a common global bit line GBL. The global bit line GBL is connected to a write circuit 140 and a read circuit 150.

[0078] Each of the column switch circuits 121-1 and 121-2 includes a plurality of column switches SWC. The column switches SWC are, for example, field effect transistors. One end of each of the column switches SWC is electrically connected to a corresponding one of the plurality of bit lines BL. The other end of each of the column switches SWC is electrically connected to a global bit line GBL.

[0079] In the column switch circuits 121-1 and 121-2, each column switch SWC is set to an on or off state according to the supplied address ADR. Depending on the on / off state of the multiple column switches SWC in the column switch circuits 121-1 and 121-2, one bit line BL is electrically connected to the global bit line GBL via the column switch SWC in the on state.

[0080] Here, the distance between the end memory cell MC in the X direction of the memory cell array 110 and the column switch circuit 121 is set to half the distance between adjacent memory cells MC in the X direction. Therefore, the resistance between the column switch circuit 121 and the end memory cell MC in the X direction is "0.5×Rs".

[0081] The wiring resistance between the memory cell MCa at the coordinates (x, y) and the column switch circuit 121-1 is "(x-0.5) x Rs". The wiring resistance between the memory cell MCa at the coordinates (x, y) and the column switch circuit 121-2 is "(M-x+0.5) x Rs".

[0082] In this way, the distance of memory cell MCa to a voltage / current supply source (e.g., write circuit 140 or read circuit 150) used for various operations of MRAM 100 varies depending on the coordinates of memory cell MCa in memory cell array 110. As a result, during operation of MRAM 100, the magnitude of the wiring resistance applied to memory cell MCa varies depending on the coordinates of memory cell MCa.

[0083] In this embodiment, when a read operation and a write operation are performed on the memory cell array 110, both of the two column switch circuits 121-1 and 121-2 or either one of the two column switch circuits 121-1 and 121-2 is turned on (activated).

[0084] As shown in FIG. 7, in the MRAM of this embodiment, the row control circuit 130 includes two row switch circuits 131-1 and 131-2.

[0085] Of the two row switch circuits 131-1 and 131-2, the row switch circuit 131-1 is provided at one end in the Y direction of the memory cell array 110. Of the two row switch circuits 131-1 and 131-2, the other row switch circuit 131-2 is provided at the other end in the Y direction of the memory cell array 110. The memory cell array 110 is provided between the two row switch circuits 131-1 and 131-2 in the Y direction.

[0086] The two row switch circuits 131-1 and 131-2 are connected to a common global word line GWL. The global word line GWL is connected to a write circuit 140 and a read circuit 150.

[0087] Each of the row switch circuits 131-1 and 131-2 includes a plurality of row switches SWR. The row switches SWR are, for example, field effect transistors. One end of each row switch SWR is electrically connected to a corresponding one of the plurality of word lines WL. The other end of each row switch SWR is electrically connected to a global word line GWL.

[0088] In the row switch circuits 131-1 and 131-2, each row switch SWR is set to an on state or an off state according to the supplied address ADR. According to the on / off state of the row switches SWR in the row switch circuits 131-1 and 131-2, one word line WL is electrically connected to the global word line GWL via the row switch SWR in the on state.

[0089] Here, the distance between the end memory cell MC in the Y direction of the memory cell array 110 and the row switch circuit 131 is set to half the distance between adjacent memory cells MC in the Y direction. Therefore, the wiring resistance between the row switch circuit 131 and the end memory cell MC in the Y direction is "0.5×Rs".

[0090] The wiring resistance between the memory cell MCa at the coordinates (x, y) and the row switch circuit 131-1 is "(y-0.5) x Rs". The wiring resistance between the memory cell MCa at the coordinates (x, y) and the row switch circuit 131-2 is "(N-y+0.5) x Rs".

[0091] In this way, the magnitude of the wiring resistance added to the memory cell MCa changes depending on the y coordinate of the memory cell MCa in the memory cell array 110.

[0092] In this embodiment, when a read operation and a write operation are performed on the memory cell array 110, both of the two row switch circuits 131-1 and 131-2 or either one of the two row switch circuits 131-1 and 131-2 is turned on (activated).

[0093] In the MRAM 1 of this embodiment, the operations (on / off state) of the two column switch circuits 121-1 and 121-2 and the operations (on / off state) of the two row switch circuits 131-1 and 131-2 are controlled according to the coordinates of a memory cell MC to be operated in the memory cell array 110. Hereinafter, the memory cell to be operated is called a selected cell.

[0094] (a-5) Relationship between the operating state of the switch circuit and wiring resistance The relationship between the operating states of the column and row switch circuits 121, 131 and the wiring resistance applied to the memory cells MC in the MRAM 100 of this embodiment will be described with reference to FIGS.

[0095] FIG. 8 is a schematic diagram for explaining the relationship between the operating state of the column switch circuit 121 and the wiring resistance applied to the selected cell MCa in the MRAM 100 of this embodiment.

[0096] As shown in FIG. 8, when a selected cell MCa is connected to a global bit line GBL using either or both of two column switch circuits 121-1 and 121-2, the magnitude of the wiring resistance between the memory cell MC and the global bit line GBL changes depending on the path formed by the column switch circuit 121 in the on state.

[0097] FIG. 8(a) is a diagram illustrating the wiring resistance between the selected cell MCa and the global bit line GBL when the two column switch circuits 121-1 and 121-2 are set to the on state (activated state).

[0098] 8(a), two column switch circuits 121-1 and 121-2 are set to the ON state. A resistor RX1 is present on the connection path between the memory cell MC and the global bit line GBL via the ON-state column switch circuit 121-1. A resistor RX2 is present on the connection path between the selected cell MCa and the global bit line GBL via the ON-state column switch circuit 121-2.

[0099] Resistor RX1 is "(x-0.5) x Rs". Resistor RX2 is "(M-x+0.5) x Rs".

[0100] When the selected cell MCa is connected to the global bit line GBL by both of the two column switch circuits 121-1 and 121-2, two resistors RX1 and RX2 are connected in parallel between the memory cell MCa and the global bit line GBL. In this case, the wiring resistance between the selected cell MCa and the global bit line GBL is "RX1×RX2 / (RX1+RX2)". Therefore, the wiring resistance of the bit line BL can be expressed as "Rs×(x-0.5)×(M-x+0.5) / M".

[0101] FIG. 8B is a diagram illustrating the wiring resistance between the selected cell MCa and the global bit line GBL when only one column switch circuit 121-1 is set to the on state.

[0102] 8B, one column switch circuit 121-1 is set to an ON state, and the other column switch circuit 121-2 is set to an OFF state (inactive state), so that the resistor RX2 is electrically isolated from the global bit line GBL.

[0103] When the selected cell MCa is connected to the global bit line GBL by one of the column switch circuits 121-1, a resistor RX1 is connected between the selected cell MCa and the global bit line GBL. In this case, the wiring resistance between the selected cell MCa and the global bit line GBL can be expressed as "(x-0.5)×Rs".

[0104] FIG. 8C is a diagram illustrating the wiring resistance between the selected cell MCa and the global bit line GBL when only the other column switch circuit 121-2 is set to the on state.

[0105] 8(c), one column switch circuit 121-1 is set to an off state, and the other column switch circuit 121-2 is set to an on state, so that the resistor RX1 is electrically isolated from the global bit line GBL.

[0106] When the selected cell MCa is connected to the global bit line GBL by the other column switch circuit 121-2, a resistor RX2 is connected between the selected cell MCa and the global bit line GBL. In this case, the wiring resistance between the selected cell MCa and the global bit line GBL can be expressed as "(M-x+0.5)×Rs".

[0107] 8, the operation of the column switch circuit 121 for selecting a column of the memory cell array 110 can be controlled in three different ways. Accordingly, for the column of the memory cell array 110, one of three different wiring resistances is applied to the selected cell MCa according to the operation of the column switch circuit 121.

[0108] FIG. 9 is a schematic diagram for explaining the relationship between the operating state of the row switch circuit 131 and the wiring resistance of the selected cell MCa in the MRAM 100 of this embodiment.

[0109] As shown in FIG. 9, when a selected cell MCa is connected to a global word line GWL using either or both of two row switch circuits 131-1 and 131-2, the magnitude of the wiring resistance between the memory cell MC and the global word line GWL changes depending on the path formed by the row switch circuit 131 in the on state.

[0110] FIG. 9(a) is a diagram illustrating the wiring resistance between a selected cell MCa and a global word line GWL when two row switch circuits 131-1 and 131-2 are set to an on state (activated state).

[0111] 9A, two row switch circuits 131-1 and 131-2 are set to the ON state. A resistor RY1 is present on the connection path between the selected cell MCa and the global word line GWL via the ON-state row switch circuit 131-1. A resistor RY2 is present on the connection path between the selected cell MCa and the global word line GWL via the ON-state row switch circuit 131-2.

[0112] Resistor RY1 is "(y-0.5) x Rs". Resistor RY2 is "(N-y+0.5) x Rs".

[0113] When the selected cell MCa is connected to the global word line GWL by both of the two row switch circuits 131-1 and 131-2, two resistors RY1 and RY2 are connected in parallel between the selected cell MCa and the global word line GWL. In this case, the wiring resistance between the selected cell MCa and the global word line GWL is "RY1×RY2 / (RY1+RY2)". Therefore, the wiring resistance of the word line WL can be expressed as "Rs×(y-0.5)×(M-y+0.5) / N".

[0114] FIG. 9B is a diagram illustrating the wiring resistance between the selected cell MCa and the global word line GWL when one row switch circuit 131-1 is set to the on state.

[0115] 9B, one row switch circuit 131-1 is set to an ON state, and the other row switch circuit 131-2 is set to an OFF state (inactive state), so that the resistor RY2 is electrically isolated from the global word line GWL.

[0116] When the selected cell MCa is connected to the global word line GWL by one row switch circuit 131-1, a resistor RY1 is connected between the selected cell MCa and the global word line GWL. In this case, the wiring resistance between the selected cell MCa and the global word line GWL can be expressed as "(y-0.5)×Rs".

[0117] FIG. 9C is a diagram illustrating the wiring resistance between the selected cell MCa and the global word line GWL when the other row switch circuit 131-2 is set to the on state.

[0118] 9(c), one row switch circuit 131-1 is set to an off state, and the other row switch circuit 131-2 is set to an on state, so that the resistor RY1 is electrically isolated from the global word line GWL.

[0119] When the other row switch circuit 131-2 connects the selected cell MCa to the global word line GWL, a resistor RY2 is connected between the selected cell MCa and the global word line GWL. In this case, the wiring resistance between the selected cell MCa and the global word line GWL can be expressed as "(N-y+0.5)×Rs".

[0120] 9, the operation of the row switch circuit 131 for selecting a row of the memory cell array 110 can be controlled in three different ways. Accordingly, for a row of the memory cell array 110, one of three different wiring resistances is applied to the selected cell MCa depending on the operation of the row switch circuit 131.

[0121] As shown in Figures 8 and 9, in this embodiment, memory cells MC in the memory cell array 110 can be selected in a 3 x 3 (9) selection manner by control of two column switch circuits 121-1, 121-2 and two row switch circuits 131-1, 131-2.

[0122] In the MRAM 100 of this embodiment, when the MRAM is in operation, one of nine selection methods is used based on the address ADR of the memory cell MC to be operated, thereby reducing the influence of differences in wiring resistance according to the coordinates of the memory cell MC in the memory cell array 110.

[0123] For example, in this embodiment, the magnitude of the wiring resistance applied to the memory cell MC is controlled by the operation of the switch circuits 121, 131 so that the magnitude of the wiring resistance applied to the memory cell MC located in an area close to the switch circuits 121, 131 is close to the magnitude of the wiring resistance applied to the memory cell MC located in an area far from the switch circuits 121, 131.

[0124] (a-6) Area in the memory cell array A plurality of areas set in the memory cell array 110 in the MRAM 100 of this embodiment will be described with reference to FIG.

[0125] The memory cell array 110 includes nine areas A1, A2, . . . , A9 that are divided according to nine selection methods (access methods) of the memory cells in the memory cell array 110 by the column switch circuit 121 and the row switch circuit 131.

[0126] When a write operation or a read operation of the MRAM 100 is performed, one of a plurality of selection methods of the memory cells MC by the column switch circuits 121-1, 121-2 and the row switch circuits 131-1, 131-2 is determined based on the address (coordinates) of the memory cells MC.

[0127] Here, when the coordinates of the memory cell array 110 are associated with directions, the first row switch circuit 131-1 side corresponds to the north direction, the second row switch circuit side 131-2 corresponds to the south direction, the first column switch circuit 121-1 side corresponds to the west direction, and the second column switch circuit 121-2 side corresponds to the east direction.

[0128] The first area A1 is a region in the center of the memory cell array 110.

[0129] The memory cells MC in the first area A1 are arranged at a position far from the voltage / current supply source with respect to the columns of the memory cell array 110. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the Y direction, the memory cells MC in the first area A1 are far from both of the column switch circuits 121. The memory cells MC in the first area A1 are arranged at a position far from the voltage / current supply source with respect to the rows of the memory cell array 110. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the X direction, the memory cells MC in the first area A1 are far from both of the row switch circuits 131.

[0130] The first area A1 is accessed by two column switch circuits 121-1 and 121-2 in the ON state and two row switch circuits 131-1 and 131-2 in the ON state.

[0131] As shown in (a) of Fig. 8, the memory cells MC in the first area A1 are electrically connected to the global bit line GBL by two column switch circuits 121-1 and 121-2 in the ON state. As shown in (a) of Fig. 9, the memory cells MC in the first area A1 are electrically connected to the global word line GWL by two row switch circuits 131-1 and 131-2 in the ON state.

[0132] The second area A2 is an area located in the northwest corner area of ​​the memory cell array 110. The second area A2 is adjacent to the first column switch circuit 121-1 and the first row switch circuit 131-1.

[0133] The memory cells MC in the second area A2 are arranged in a position close to a voltage / current supply source with respect to the columns of the memory cell array 110. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the Y direction, the memory cells MC in the second area A2 are close to the first column switch circuit 121-1 and far from the second column switch circuit 121-2. The memory cells MC in the second area A2 are arranged in a position close to a voltage / current supply source with respect to the rows of the memory cell array 110. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the X direction, the memory cells MC in the second area A2 are close to the first row switch circuit 131-1 and far from the second row switch circuit 131-2.

[0134] The second area A2 is accessed by the first column switch circuit 121-1 in the ON state and the first row switch circuit 131-1 in the ON state.

[0135] As shown in Fig. 8(b), the memory cells MC in the second area A2 are connected to the global bit line GBL by the first column switch circuit 121-1 in the on state. As shown in Fig. 9(b), the memory cells MC in the second area A2 are connected to the global word line GWL by the first row switch circuit 131-1 in the on state.

[0136] When a memory cell MC in the second area A2 is selected as an operation target, the second column switch circuit 121-2 and the second row switch circuit 131-2 are set to the off state.

[0137] The third area A3 is an area located in the northeast corner area of ​​the memory cell array 110. The third area A3 is adjacent to the second column switch circuit 121-2 and the first row switch circuit 131-1.

[0138] The memory cells MC in the third area A3 are arranged in a position close to a voltage / current supply source with respect to the columns of the memory cell array 110. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the Y direction, the memory cells MC in the third area A3 are far from the first column switch circuit 121-1 and close to the second column switch circuit 121-2. The memory cells MC in the third area A3 are arranged in a position close to a voltage / current supply source with respect to the rows of the memory cell array 110. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the X direction, the memory cells MC in the third area A3 are close to the first row switch circuit 131-1 and far from the second row switch circuit 131-2.

[0139] The third area A3 is accessed by the second column switch circuit 121-2 in the ON state and the first row switch circuit 131-1 in the ON state.

[0140] As shown in Fig. 8(c), the memory cells MC in the third area A3 are connected to the global bit line GBL by the second column switch circuit 121-2 in the ON state. As shown in Fig. 9(b), the memory cells MC in the third area A3 are connected to the global word line GWL by the first row switch circuit 131-1 in the ON state.

[0141] When a memory cell MC in the third area A3 is selected as an operation target, the first column switch circuit 121-1 and the second row switch circuit 131-2 are set to the off state.

[0142] The fourth area A4 is an area located in the southeast corner area of ​​the memory cell array 110. The fourth area A4 is adjacent to the second column switch circuit 121-2 and the second row switch circuit 131-2.

[0143] The memory cells MC in the fourth area A4 are arranged in a position close to a voltage / current supply source with respect to the columns of the memory cell array 110. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the Y direction, the memory cells MC in the fourth area A4 are far from the first column switch circuit 121-1 and close to the second column switch circuit 121-2. The memory cells MC in the fourth area A4 are arranged in a position close to a voltage / current supply source with respect to the rows of the memory cell array 110. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the X direction, the memory cells MC in the fourth area A4 are far from the first row switch circuit 131-1 and close to the second row switch circuit 131-2.

[0144] The fourth area A4 is accessed by the second column switch circuit 121-2 in the ON state and the second row switch circuit 131-2 in the ON state.

[0145] As shown in Fig. 8(c), the memory cells MC in the fourth area A4 are connected to the global bit line GBL by the second column switch circuit 121-2 in the on state. As shown in Fig. 9(c), the memory cells MC in the fourth area A4 are connected to the global word line GWL by the second row switch circuit 131-2 in the on state.

[0146] When a memory cell MC in the fourth area A4 is selected as an operation target, the first column switch circuit 121-1 and the first row switch circuit 131-1 are set to the off state.

[0147] The fifth area A5 is an area located in the southwest corner area of ​​the memory cell array 110. The fifth area A5 is adjacent to the first column switch circuit 121-1 and the second row switch circuit 131-2.

[0148] The memory cells MC in the fifth area A5 are arranged in a position close to a voltage / current supply source with respect to the columns of the memory cell array 110. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the Y direction, the memory cells MC in the fifth area A5 are close to the first column switch circuit 121-1 and far from the second column switch circuit 121-2. The memory cells MC in the fifth area A5 are arranged in a position close to a voltage / current supply source with respect to the rows of the memory cell array 110. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the X direction, the memory cells MC in the fifth area A5 are far from the first row switch circuit 131-1 and close to the second row switch circuit 131-2.

[0149] The fifth area A5 is accessed by the first column switch circuit 121-1 in the ON state and the second row switch circuit 131-2 in the ON state.

[0150] As shown in Fig. 8(b), the memory cells MC in the fifth area A5 are connected to the global bit line GBL by the first column switch circuit 121-1 in the ON state, and as shown in Fig. 9(c), the memory cells MC in the fifth area A5 are connected to the global word line GWL by the second row switch circuit 131-2 in the ON state.

[0151] When a memory cell MC in the fifth area A5 is selected as an operation target, the second column switch circuit 121-2 and the first row switch circuit 131-1 are set to the off state.

[0152] The sixth area A6 (A6-1, A6-2, A6-3) is an area between the second area A2 and the third area A3, and is an area on the north side (the first row switch circuit 131-1 side) of the first area A1. The sixth area A6 is surrounded by the first, second and third areas A1, A2 and A3.

[0153] The sixth area A6 includes an area A6-1 between the first area A1 and the first row switch circuit 131-1, an area A6-2 between the second area A2 and a ninth area A9 (A9-1, A9-3) described later, and an area A6-3 between the third area A3 and a seventh area A7 (A7-1, A7-2) described later. The area A6-1 is surrounded by the three areas A1, A2, and A3. The area A6-1 is adjacent to the first area A1 and areas A7-2 and A9-3 described later.

[0154] The sixth area A6 is accessed by the two column switch circuits 121-1 and 121-2 in the on state and the first row switch circuit 131-1 in the on state.

[0155] As shown in Fig. 8(a), the memory cells MC in the sixth area A6 are connected to the global bit line GBL via the first and second column switch circuits 121-1 and 121-2 in the ON state. As shown in Fig. 9(b), the memory cells MC in the sixth area A6 are connected to the global word line GWL via the first row switch circuit 131-1 in the ON state.

[0156] When the memory cell MC in the sixth area A6 is selected as the operation target, the second row switch circuit 131-2 is set to the off state.

[0157] The seventh area A7 (A7-1, A7-2, A7-3) is an area between the third area A3 and the fourth area A4, and is an area on the east side (the second column switch circuit 121-2 side) of the first area A1. The seventh area A7 is surrounded by the first, third and fourth areas A1, A3 and A4.

[0158] The seventh area A7 includes an area A7-1 between the first area A1 and the second column switch circuit 121-2, an area A7-2 between the third area A3 and the sixth area A6 (A6-1, A6-2), and an area A7-3 between the fourth area A4 and an eighth area A8 (A8-1, A8-2) described below. The area A7-1 is surrounded by the three areas A1, A3, and A4. The area A7-1 is adjacent to the first area A1, the area A6-3, and the area A8-2 described below.

[0159] The seventh area A7 is accessed by the second column switch circuit 121-2 in the on state and the two row switch circuits 131-1 and 131-2 in the on state.

[0160] As shown in Fig. 8(c), the memory cells MC in the seventh area A7 are connected to the global bit line GBL via the second column switch circuit 121-2 in the ON state. As shown in Fig. 9(a), the memory cells MC in the seventh area A7 are connected to the global word line GWL via the first and second row switch circuits 131-1 and 131-2 in the ON state.

[0161] When the memory cell MC in the seventh area A7 is selected as the operation target, the first column switch circuit 121-1 is set to the off state.

[0162] The eighth area A8 is an area between the fourth area A4 and the fifth area A5, and is an area on the south side (the second row switch circuit 131-2 side) of the first area A1. The eighth area A8 is surrounded by the first, fourth and fifth areas A1, A4 and A5.

[0163] The eighth area A8 includes an area A8-1 between the first area A1 and the second row switch circuit 131-2, an area A8-2 between the fourth area A4 and the seventh area A7 (A7-1, A7-3), and an area A8-3 between the fifth area A5 and a ninth area A9 (A9-1, A9-2) described later. The area A8-1 is surrounded by the three areas A1, A4, and A5. The area A8-1 is adjacent to the first area A1, the area A7-3, and the area A9-2 described later.

[0164] The eighth area A8 is accessed by the two column switch circuits 121-1 and 121-2 in the on state and the second row switch circuit 131-2 in the on state.

[0165] As shown in Fig. 8(a), the memory cells MC in the sixth area A6 are connected to the global bit line GBL via the first and second column switch circuits 121-1 and 121-2 in the ON state. As shown in Fig. 9(c), the memory cells MC in the sixth area A6 are connected to the global word line GWL via the second row switch circuit 131-2 in the ON state.

[0166] When the memory cell MC in the eighth area A8 is selected as the operation target, the first row switch circuit 131-1 is set to the off state.

[0167] The ninth area A9 (A9-1, A9-2, A9-3) is an area between the second area A2 and the fifth area A5, and is an area on the west side (the first column switch circuit 121-1 side) of the first area A1. The ninth area A9 is surrounded by the first, second and fifth areas A1, A2 and A5.

[0168] The ninth area A9 includes an area A9-1 between the first area A1 and the first column switch circuit 121-1, an area A9-2 between the fifth area A5 and the eighth area A8 (A8-1, A8-3), and an area A9-3 between the second area A2 and the sixth area A6 (A6-1, A6-2). The area A9-1 is surrounded by the three areas A1, A2, and A5. The area A9-1 is adjacent to the first area A1, the area A6-2, and the area A8-3.

[0169] The ninth area A9 is accessed by the first column switch circuit 121-1 in the on state and the two row switch circuits 131-1 and 131-2 in the on state.

[0170] As shown in Fig. 8(b), the memory cells MC in the ninth area A9 are connected to the global bit line GBL via the first column switch circuit 121-1 in the ON state. As shown in Fig. 9(a), the memory cells MC in the ninth area A9 are connected to the global word line GWL via the first and second row switch circuits 131-1 and 131-2 in the ON state.

[0171] When the memory cell MC in the ninth area A9 is selected as the operation target, the second column switch circuit 121-2 is set to the off state.

[0172] As described above, in the MRAM 100 of this embodiment, nine areas A1, . . . , A9 are defined in the memory cell array 110.

[0173] The tendency of the wiring resistance applied to the memory cells MC in each of the areas A1, ..., A9 is that the wiring resistance applied to the memory cells MC in each of the areas A6, A7, A8, A9 is higher than the wiring resistance applied to the memory cells MC in each of the areas A2, A3, A4, A5, and lower than the wiring resistance applied to the memory cells MC in the area A1.

[0174] In this embodiment, the areas A1,...,A9 including the memory cells MC to be operated are identified based on the address ADR provided to the MRAM 100. Based on the identification result of the areas A1,...,A9, the column switch circuit 121 to be activated and the row switch circuit 131 to be activated are determined.

[0175] (a-7) Conditions for memory cell allocation in each area The conditions under which each memory cell MC is assigned to each of the above-mentioned areas A1, . . . , A9 will be described.

[0176] Here, when the memory cell array 110 has a square array size, "M" is equal to "N." Also, the magnitude of the resistance between memory cells MC adjacent to each other in the X direction is equal to the magnitude of the resistance between memory cells MC adjacent to each other in the Y direction.

[0177] The wiring resistance between the memory cells MC in the first area A1 and the global bit lines GBL is Rs×(x-0.5)(N-x+0.5) / N. The wiring resistance between the memory cells MC in the first area A1 and the global word lines GWL is Rs×(y-0.5)(N-y+0.5) / N.

[0178] The memory cells MC allocated to the first area A1 satisfy the following conditional expressions (Formula 1a), (Formula 1b), (Formula 1c), and (Formula 1d).

[0179] (xN) 2 + (yN / 2) 2 ≦ N 2 / 2 ···(Equation 1a) x 2 + (yN / 2) 2 ≦ N 2 / 2...(Equation 1b) (xN / 2) 2 + (yN) 2 ≦ N 2 / 2...(Equation 1c) (xN / 2) 2 + y 2 ≦ N 2 / 2...(Formula 1d) The wiring resistance between the memory cells MC in the second area A2 and the global bit lines GBL is Rs×(x-0.5). The wiring resistance between the memory cells MC in the second area A2 and the global word lines GWL is Rs×(y-0.5).

[0180] The memory cells MC allocated to the second area A2 satisfy the conditional expression shown in the following (Equation 2).

[0181] x + y ≦ N / 2 (Eq. 2) The wiring resistance between the memory cells MC in the third area A3 and the global bit lines GBL is Rs×(N-x+0.5). The wiring resistance between the memory cells MC in the third area A3 and the global word lines GWL is Rs×(y-0.5).

[0182] The memory cells MC allocated to the third area A3 satisfy the conditional expression shown in the following (Equation 3).

[0183] (Nx) + y ≦ N / 2 (Equation 3) The wiring resistance between the memory cells MC in the fourth area A4 and the global bit lines GBL is Rs×(N-x+0.5). The wiring resistance between the memory cells MC in the fourth area A4 and the global word lines GWL is Rs×(N-y+0.5).

[0184] The memory cells MC allocated to the fourth area A4 satisfy the conditional expression shown in the following (Equation 4).

[0185] (Nx) + (Ny) ≦ N / 2 (Formula 4) The wiring resistance between the memory cells MC in the fifth area A5 and the global bit lines GBL is Rs×(x-0.5). The wiring resistance between the memory cells MC in the fifth area A5 and the global word lines GWL is Rs×(N-y+0.5).

[0186] The memory cells MC allocated to the fifth area A5 satisfy the conditional expression shown in the following (Equation 5).

[0187] x + (Ny) ≦ N / 2 (Eq. 5) The wiring resistance between the memory cells MC in the sixth area A6 and the global bit lines GBL is Rs×(x−0.5)(N−x+0.5) / N. The wiring resistance between the memory cells MC in the sixth area A6 and the global word lines GWL is Rs×(y−0.5).

[0188] The memory cells MC allocated to the sixth area A6 satisfy the following conditional expressions (Formula 6a), (Formula 6b), and (Formula 6c).

[0189] (xN) 2 +(yN / 2) 2 ≧N 2 / 2 AND (xN / 2) 2 +(yN) 2 ≦N 2 / 2 AND (xN / 2) 2 +y 2 ≦N 2 / 2...(Equation 6a) (xN) 2 +(yN / 2) 2 ≧N 2 / 2 AND x+y≧N / 2 AND x+(Ny)≦N (Equation 6b) (xN) 2 +(yN / 2) 2 ≧N 2 / 2 AND (Nx)+y≧N / 2 AND (Nx)+(Ny)≦N (Formula 6c) The wiring resistance between the memory cells MC in the seventh area A7 and the global bit lines GBL is Rs×(N-x+0.5) / N. The wiring resistance between the memory cells MC in the seventh area A7 and the global word lines GWL is Rs×(y-0.5)(N-y+0.5) / N.

[0190] The memory cells MC allocated to the seventh area A7 satisfy the following conditional expressions (Formula 7a), (Formula 7b), and (Formula 7c).

[0191] x 2 +(yN) 2 ≧N 2 / 2 AND (xN) 2 +(yN / 2) 2 ≦N 2 / 2 AND x 2 +(yN / 2) 2 ≦N 2 / 2...(Equation 7a) x 2 +(yN) 2 ≧N 2 / 2 AND (Nx)+y≧N / 2 AND x+y≦N (Formula 7b) x 2 +(yN) 2 ≧N 2 / 2 AND (Nx)+(Ny)≧N / 2 AND x+(Ny)≦N (Equation 7c) The wiring resistance between the memory cells MC in the eighth area A8 and the global bit lines GBL is Rs×(x−0.5)(N−x+0.5) / N. The wiring resistance between the memory cells MC in the eighth area A8 and the global word lines GWL is Rs×(N−y+0.5).

[0192] The memory cells MC allocated to the eighth area A8 satisfy the following conditional expressions (Equation 8a), (Equation 8b), and (Equation 8c).

[0193] x 2 +(yN / 2) 2 ≧N 2 / 2 AND (xN / 2) 2 +(yN) 2 ≦N 2 / 2 AND (xN / 2) 2 +y 2 ≦N 2 / 2...(Equation 8a) x 2 +(yN / 2) 2 ≧N 2 / 2 AND x+(Ny)≧N / 2 AND x+y≦N (Equation 8b) x 2 +(yN / 2) 2 ≧N 2 / 2 AND (Nx)+(Ny)≧N / 2 AND (Nx)+y≦N (Formula 8c) The wiring resistance between the memory cells MC in the ninth area A9 and the global bit lines GBL is Rs×(x−0.5). The wiring resistance between the memory cells MC in the ninth area A9 and the global word lines GWL is Rs×(y−0.5)(N−y+0.5).

[0194] The memory cells MC allocated to the ninth area A9 satisfy the following conditional expressions (Formula 9a), (Formula 9b), and (Formula 9c).

[0195] (xN / 2) 2 +(yN) 2 ≧N 2 / 2 AND (xN) 2 +(yN / 2) 2 ≦N 2 / 2 AND x 2 +(yN / 2) 2 ≦N 2 / 2...(Formula 9a) (xN / 2) 2 +(yN) 2 ≧N 2 / 2 AND x+y≧N / 2 AND (Nx)+y≦N (Equation 9b) (xN / 2) 2 +(yN) 2 ≧N 2 / 2 AND x+(Ny)≧N / 2 AND (Nx)+(Ny)≦N (Equation 9c) As described above, the wiring resistance applied to the memory cell MC (the wiring resistance between the memory cell MC and the global wirings GBL, GWL) depends on the coordinates of the memory cell MC in the memory cell array 110. Therefore, the memory cell MC can be assigned to areas A1, A2, ..., A9 set in the memory cell array based on the coordinates of the memory cell MC in the memory cell array 110.

[0196] Depending on the coordinates (x, y) of the memory cell MC, the memory cell MC existing at the boundary (or near the boundary) between the multiple areas A (A1 to A9) may meet the allocation conditions of the multiple areas A. In this case, one memory cell MC may be allocated to multiple areas A. A memory cell existing at the boundary between the multiple areas A may be allocated to either area A as long as it meets the allocation conditions of each area A. It is desirable to design the operation of the column switch circuit 121 and / or the operation of the row switch circuit 131 so that a memory cell MC existing at the boundary between the multiple areas and meeting the multiple allocation conditions is allocated to one of the areas A. As a result, malfunction of the memory cell MC at the boundary between the multiple areas A can be prevented.

[0197] (b) Example of operation An example of the operation of the memory device (MRAM) 100 of this embodiment will be described with reference to FIGS.

[0198] The MRAM 100 of this embodiment receives a command CMD, an address ADR, and various control signals CNT from an external device 900. When the command CMD to be executed is a write operation, the MRAM 100 of this embodiment further receives write data DT from the external device 900.

[0199] The MRAM 100 of this embodiment starts a commanded operation (write operation or read operation) based on the command CMD, the address ADR, and various control signals CNT.

[0200] The control circuit 180 performs various controls according to the operation to be executed based on the command CMD and various control signals CNT. The control circuit 180 decodes the address ADR.

[0201] The column control circuit 120 and the row control circuit 130 activate the column switch circuit 121 and the row switch circuit 131 based on the decoded result of the address ADR.

[0202] In this embodiment, one or two column switch circuits 121-1, 121-2 and one or two row switch circuits 131-1, 131-2 are activated based on the coordinates (address ADR) of the memory cell MC to be operated.

[0203] A memory cell (selected cell) MC indicated by an address ADR is accessed by one or two activated column switch circuits 121-1, 121-2 and one or two activated row switch circuits 131-1, 131-2. Voltages and currents used for the operation to be performed are supplied to the selected cell MC via bit lines BL and word lines WL.

[0204] 11 is a schematic diagram showing a voltage and current supply path when a memory cell MC in a first area A1 is selected as an operation target, and shows an example in which a current Ia flows from a global bit line GBL to a global word line GWL.

[0205] As shown in FIG. 11, when a memory cell MC in the first area A1 is selected, two column switch circuits 121-1 and 121-2 are set to the ON state, and two row switch circuits 131-1 and 131-2 are set to the ON state.

[0206] The current Ia flows from the column switch circuit 121-1 to the selected cell MC via a resistor (wiring resistance) RX1 (=(x-0.5)×Rs), and from the column switch circuit 121-2 to the selected cell via a resistor (wiring resistance) RX2 (=(M-x+0.5)×Rs).

[0207] Current Ia flows from the selected cell MC to the row switch circuit 131-1 via resistance (wiring resistance) RY1 (=(y-0.5)×Rs), and from the selected cell MC to the row switch circuit 131-2 via resistance (wiring resistance) RY2 (=(N-y+0.5)×Rs).

[0208] In this way, in a write operation or a read operation of the MRAM 100, a voltage and a current are supplied to a selected cell MC in the first area A1 via the two column switch circuits 121-1 and 121-2 and the two row switch circuits 131-1 and 131-2.

[0209] 12 is a schematic diagram showing a voltage and current supply path when a memory cell MC in the second area A2 is selected as an operation target, and shows an example in which a current Ia flows from a global bit line GBL to a global word line GWL.

[0210] As shown in FIG. 12, when a memory cell MC in the second area A2 is selected, one column switch circuit 121-1 is set to the ON state, and one row switch circuit 131-1 is set to the ON state.

[0211] The current Ia flows from the column switch circuit 121-1 to the selected cell MC via the resistor RX1.

[0212] The current Ia flows from the selected cell MC to the row switch circuit 131-1 via the resistor RY1.

[0213] In this way, in a write operation or a read operation of the MRAM 100, a voltage and a current are supplied to a selected cell MC in the second area A2 via one column switch circuit 121-1 and one row switch circuit 131-1.

[0214] Similar to the selected cell MC in the second area A2, the current Ia is supplied to the selected cell MC in the third, fourth and fifth areas A3, A4 and A5 via one of the two column switch circuits 121 and one of the two row switch circuits 131.

[0215] 13 is a schematic diagram showing a voltage and current supply path when a memory cell MC in a sixth area A6 is selected as an operation target, in which an example is shown in which a current Ia flows from a global bit line GBL to a global word line GWL.

[0216] As shown in FIG. 13, when a memory cell MC in the sixth area A6 is selected, two column switch circuits 121-1 are set to the ON state, and one row switch circuit 131-1 is set to the ON state.

[0217] The current Ia flows from the column switch circuit 121-1 to the selected cell MC via the resistor RX1, and from the column switch circuit 121-2 to the selected cell MC via the resistor RX2.

[0218] The current Ia flows from the selected cell MC to the row switch circuit 131-1 via the resistor RY1.

[0219] In this way, in a write operation or a read operation of the MRAM 100, a voltage and a current are supplied to a selected cell MC in the sixth area A6 via two column switch circuits 121-1 and 121-2 and one row switch circuit 131-1.

[0220] Substantially the same as the selected cell MC in the sixth area A6, the current Ia is supplied to the selected cell MC in the eighth area A8 via two column switch circuits 121-1 and 121-2 and one row switch circuit 131-2.

[0221] 14 is a schematic diagram showing a voltage and current supply path when a memory cell MC in a seventh area A7 is selected as an operation target, in which an example is shown in which a current Ia flows from a global bit line GBL to a global word line GWL.

[0222] As shown in FIG. 14, when a memory cell MC in the seventh area A7 is selected, one column switch circuit 121-2 is set to the ON state, and two row switch circuits 131-1 and 131-2 are set to the ON state.

[0223] The current Ia flows from the column switch circuit 121-2 to the selected cell MC via the resistor RX1.

[0224] The current Ia flows from the selected cell MC to the row switch circuit 131-1 via the resistor RY1, and from the selected cell MC to the row switch circuit 131-2 via the resistor RY2.

[0225] In this way, in a write operation or a read operation of the MRAM 100, a voltage and a current are supplied to a selected cell MC in the seventh area A7 via one column switch circuit 121-2 and two row switch circuits 131-1 and 131-2.

[0226] Substantially the same as the selected cell MC in the seventh area A7, the current Ia is supplied to the selected cell MC in the ninth area A9 via one column switch circuit 121-1 and two row switch circuits 131-1 and 131-2.

[0227] As described above, when various operations of the MRAM 100 of this embodiment are performed, at least one of the two column switch circuits 121 and at least one of the two row switch circuits 131 are activated according to the coordinates of the memory cell MC corresponding to the supplied address ADR.

[0228] As a result, the MRAM 100 of this embodiment can mitigate the influence of the difference in wiring resistance applied to the memory cells MC due to the position of the memory cells MC in the memory cell array 110.

[0229] (c) Experiment The characteristics of the MRAM 100 of this embodiment will be described with reference to FIG.

[0230] FIG. 15 is a graph showing the results of an experiment on the MRAM 100 of the present embodiment.

[0231] The horizontal axis of the graph in Fig. 15 corresponds to the wiring resistance applied to the memory cell, and the vertical axis of the graph in Fig. 15 corresponds to the Z value related to the operation failure.

[0232] In FIG. 15, a characteristic P1 consisting of a set of square plots indicates the experimental results of the MRAM of the comparative example, and a characteristic P2 consisting of a set of cross plots indicates the experimental results of the MRAM 100 of this embodiment. In the comparative MRAM, two column switch circuits and two row switch circuits are activated to access a selected memory cell, regardless of the coordinates of the memory cell in the memory cell array.

[0233] 15, any of the memory cells MC in the first area A1 has the highest wiring resistance Rfar. Any of the memory cells MC in each of the second to fifth areas A2, A3, A4, and A5 has the lowest wiring resistance Rnear. Any of the memory cells MC in each of the sixth to ninth areas A6, A7, A8, and A9 has a wiring resistance R1.

[0234] As shown in FIG. 15, the Z value relating to the operational malfunction of the MRAM 100 of this embodiment is lower than the Z value relating to the operational malfunction of the MRAM 100 of the comparative example.

[0235] For example, in the MRAM of the comparative example, 38% of memory cells having a resistance value equal to or less than the wiring resistance R1 may malfunction. In contrast, in the MRAM 100 of the present embodiment, the memory cells having a resistance value equal to or less than the wiring resistance R1 may malfunction in only 16% of the memory cells.

[0236] In this way, the MRAM 1 of this embodiment can reduce the percentage of memory cells that may have operational defects due to the coordinates (wiring resistance) of the memory cells.

[0237] (d) Summary In the MRAM 100 of this embodiment, the memory cell array 110 includes nine areas A1, . . . , A9 that are set based on the coordinates of the memory cells MC.

[0238] The MRAM 100 of this embodiment activates one or two of the two column switch circuits 121 and activates one or two of the two row switch circuits 131 according to the coordinates of the memory cell MC to be operated.

[0239] A bit line BL connected to a selected memory cell MC is connected to a global bit line GBL via one or two column switch circuits 121 depending on the coordinates of the memory cell MC. A word line WL connected to a selected memory cell MC is connected to a global word line GWL via one or two row switch circuits 131 depending on the coordinates of the memory cell MC.

[0240] As a result, the MRAM 100 of this embodiment can reduce the difference in wiring resistance applied to the memory cells MC caused by the coordinates of the memory cells MC.

[0241] As a result, the MRAM 100 of this embodiment can reduce malfunctions of the memory cells MC.

[0242] As described above, the reliability of the memory device of this embodiment can be improved.

[0243] (2) Second embodiment A memory device according to a second embodiment will be described below with reference to Figures 1 to 14 as appropriate.

[0244] A memory cell array 110 of a memory device such as the MRAM 100 may have different sizes for the columns of the memory cell array 110 and the rows of the memory cell array 110.

[0245] 7 and 10, when the size of the columns of the memory cell array 110 is different from the size of the rows of the memory cell array 110, the value of "M" is different from the value of "N." In this case, the memory cell array 110 has a rectangular layout when viewed from the Z direction.

[0246] Furthermore, the magnitude of the resistance (Rs_X) between two memory cells MC adjacent in the X direction may be different from the magnitude of the resistance (Rs_Y) between two memory cells MC adjacent in the Y direction.

[0247] In this embodiment, similarly to FIG. 7 described above, nine areas A1, . . . , A9 are set in a rectangular memory cell array 110 according to the coordinates and wiring resistance of memory cells MC.

[0248] The following wiring resistance is applied to each of the memory cells MC in each of the areas A1, . . . , A9.

[0249] For columns in the first area A1, a wiring resistance of Rs_x×M / ((x-0.5)(M-x+0.5)) is applied to memory cells MC in the first area A1 by two column switch circuits 121-1 and 121-2. For rows in the first area A1, a wiring resistance of Rs_y×N / ((y-0.5)(N-y+0.5)) is applied to memory cells MC in the first area A1 by two row switch circuits 131-1 and 131-2.

[0250] For columns in the second area A2, a wiring resistance of Rs_x×(x−0.5) is applied to memory cells MC in the second area A2 by the first column switch circuit 121-1. For rows in the second area A2, a wiring resistance of Rs_y×(y−0.5) is applied to memory cells MC in the second area A2 by the first row switch circuit 131-1.

[0251] For columns in the third area A3, a wiring resistance of Rs_x×(M−x+0.5) is applied to memory cells MC in the third area A3 by the second column switch circuit 121-2. For rows in the third area A3, a wiring resistance of Rs_y×(y−0.5) is applied to memory cells MC in the third area A3 by the first row switch circuit 131-1.

[0252] For columns in the fourth area A4, a wiring resistance of Rs_x×(M−x+0.5) is applied to memory cells MC in the fourth area A4 by the second column switch circuit 121-2. For rows in the fourth area A4, a wiring resistance of Rs_y×(N−y+0.5) is applied by the second row switch circuit 131-2.

[0253] For the columns of the fifth area A5, a wiring resistance of Rs_x×(x−0.5) is applied to the memory cells MC in the fifth area A5 by the first column switch circuit 121-1. For the rows of the fifth area A5, a wiring resistance of Rs_y×(N−y+0.5) is applied to the memory cells MC in the fifth area A5 by the two row switch circuits 131-1 and 131-2.

[0254] For columns in the sixth area A6, a wiring resistance of Rs_x×M / ((x−0.5)(M−x+0.5)) is applied to memory cells MC in the sixth area A6 by the two column switch circuits 121-1 and 121-2. For rows in the sixth area A6, a wiring resistance of Rs_y×(y−0.5) is applied to memory cells MC in the sixth area A6 by the first row switch circuit 131-1.

[0255] For the columns of the seventh area A7, a wiring resistance of Rs_x×(M−x+0.5) is applied to the memory cells MC in the seventh area A7 by the second column switch circuit 121-2. For the rows of the seventh area A7, a wiring resistance of Rs_y×N / ((y−0.5)(N−y+0.5)) is applied to the memory cells MC in the seventh area A7 by the two row switch circuits 131-1 and 131-2.

[0256] For the columns in the eighth area A8, a wiring resistance of Rs_x×M / ((x-0.5)(M-x+0.5)) is applied to the memory cells MC in the eighth area A8 by the two column switch circuits 121-1 and 121-2. For the columns in the eighth area A8, a wiring resistance of Rs_y×(N-y+0.5) is applied to the memory cells MC in the eighth area A8 by the second row switch circuit 131-2.

[0257] For the columns of the ninth area A9, a wiring resistance of Rs_x×(x−0.5) is applied to the memory cells MC in the ninth area A9 by the first column switch circuit 121-1. For the rows of the ninth area A9, a wiring resistance of Rs_y×N / ((y−0.5)(N−y+0.5)) is applied to the memory cells MC in the ninth area A9 by the two row switch circuits 131-1 and 131-2.

[0258] As described above, the MRAM 100 of this embodiment can reduce the difference in wiring resistance according to the coordinates of the memory cells MC by controlling the column switch circuit 121 and the row switch circuit 131.

[0259] Therefore, the memory device of this embodiment can obtain the same effects as those of the first embodiment.

[0260] (3)Other In the memory device 100 of the above embodiment, nine areas A1,..., A9 are set in the memory cell array 110. The number of areas set in the memory cell array 110 is not limited to nine. The number of areas set in the memory cell array 110 may be less than nine or more than nine. For example, five areas may be set in the memory cell array 110 such that areas are set in the center and four corner regions of the rectangular memory cell array 110.

[0261] In the above-described embodiment, an MRAM is exemplified as the memory device 100 of the present embodiment. However, the memory device 100 of the present embodiment may be a memory device other than an MRAM.

[0262] For example, the memory device 100 of this embodiment may be a memory device using a transition metal oxide element having variable resistance characteristics as a memory element (e.g., a resistance change memory such as ReRAM (Resistive Random Access Memory)), a memory device using a phase change element as a memory element (e.g., a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device using a ferroelectric element as a memory element (e.g., a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0263] Even if the memory device 100 of this embodiment is a memory device other than an MRAM, it can obtain the effects described in the above embodiments.

[0264] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0265] 100: memory device, 110: memory cell array, 120: column control circuit, 121-1, 121-2: column switch circuit, 130: row control circuit, 131-1, 131-2: row switch circuit, MC, MCa: memory cell, 1: memory element, 2: switching element.< / y> < / x> < / n> < / y> < / m> < / x> < / m> < / n>

Claims

1. a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each connected to one of the plurality of bit lines and one of the plurality of word lines, the memory cell array having first to ninth areas; a first column switch circuit connected to the plurality of bit lines and provided at one end of the memory cell array in a first direction; a second column switch circuit connected to the plurality of bit lines and provided on the other end side of the memory cell array in the first direction; a first row switch circuit connected to the plurality of word lines and provided at one end of the memory cell array in a second direction; a second row switch circuit connected to the plurality of word lines and provided on the other end side of the memory cell array in the second direction; Equipped with When a memory cell in the first area is selected, the first and second column switch circuits and the first and second row switch circuits are activated; When a memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated; When a memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated; When a memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated; When a memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated; When a memory cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated; When a memory cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated; When a memory cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated; When a memory cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated. Memory device.

2. the memory cell array has a rectangular layout; the first area is disposed in a central region of the memory cell array; the second area is disposed within a first corner region of the memory cell array; the third area is disposed in a second corner region of the memory cell array; the fourth area is disposed in a third corner region of the memory cell array; the fifth area is disposed in a fourth corner region of the memory cell array; the sixth area is disposed between the first, second and third areas; the seventh area is disposed between the first, third and fourth areas; the eighth area is disposed between the first, fourth and fifth areas; the ninth area is disposed between the first, second and fifth areas; The memory device of claim 1 .

3. the sixth area includes a first region, a second region, and a third region; the seventh area includes a fourth region, a fifth region, and a sixth region; the eighth area includes a seventh region, an eighth region, and a ninth region, the ninth area includes a tenth region, an eleventh region, and a twelfth region; the first region is provided between the first area, the second area, and the third area; The second region is provided between the second area and the tenth region, the third region is provided between the third area and the fourth region, the fourth region is provided between the first area, the third area, and the fourth area, the fifth region is provided between the third area and the first region, the sixth region is provided between the fourth area and the seventh area, the seventh region is provided between the first area, the fourth area, and the fifth area, the eighth region is provided between the fourth area and the fourth region, the ninth region is provided between the fifth area and the tenth area, the tenth region is provided between the first area, the second area, and the fifth area, the eleventh region is provided between the fifth area and the seventh area, The twelfth region is provided between the second area and the first region. The memory device of claim 2 .

4. a global bit line connected to the first and second column switch circuits; a global word line connected to the first and second row switch circuits; The memory device of claim 1 further comprising:

5. When a memory cell in the sixth area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and to the global word line via the first row switch circuit; When a memory cell in the seventh area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the first and second row switch circuits; When a memory cell in the eighth area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and to the global word line via the second row switch circuit; When a memory cell in the ninth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the first and second row switch circuits. The memory device of claim 4.

6. When a memory cell in the first area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and connected to the global word line via the first and second row switch circuits; When a memory cell in the second area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the first row switch circuit; When a memory cell in the third area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the first row switch circuit; When a memory cell in the fourth area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the second row switch circuit; When a memory cell in the fifth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the second row switch circuit. The memory device of claim 5 .

7. A wiring resistance applied to each of the memory cells in the sixth, seventh, eighth and ninth areas is higher than a wiring resistance applied to each of the memory cells in the second, third, fourth and fifth areas and is lower than a wiring resistance applied to a memory cell in the first area. The memory device of claim 1 .

8. one or both of the first and second column switch circuits are activated, and one or both of the first and second row switch circuits are activated, depending on an address of a memory cell to be operated among the plurality of memory cells. The memory device of claim 1 .

9. Each of the plurality of memory cells A memory element; A switching element connected in series to the memory element; Including, The memory device of claim 1 .

10. The memory element is a magnetoresistance effect element. The memory device of claim 9.

11. a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each connected to one of the plurality of bit lines and one of the plurality of word lines, the memory cell array having first to ninth areas; a first column switch circuit connected to the plurality of bit lines and provided at one end of the memory cell array in a first direction; a second column switch circuit connected to the plurality of bit lines and provided on the other end side of the memory cell array in the first direction; a first row switch circuit connected to the plurality of word lines and provided at one end of the memory cell array in a second direction; a second row switch circuit connected to the plurality of word lines and provided on the other end side of the memory cell array in the second direction; Equipped with one or both of the first and second column switch circuits are activated, and one or both of the first and second row switch circuits are activated, depending on an address of a memory cell to be operated among the plurality of memory cells. Memory device.

12. the memory cell array has a rectangular layout; the first area is disposed in a central region of the memory cell array; the second area is disposed within a first corner region of the memory cell array; the third area is disposed in a second corner region of the memory cell array; the fourth area is disposed in a third corner region of the memory cell array; the fifth area is disposed in a fourth corner region of the memory cell array; the sixth area is disposed between the first, second and third areas; the seventh area is disposed between the first, third and fourth areas; the eighth area is disposed between the first, fourth and fifth areas; the ninth area is disposed between the first, second and fifth areas; The memory device of claim 11.

13. the sixth area includes a first region, a second region, and a third region; the seventh area includes a fourth region, a fifth region, and a sixth region; the eighth area includes a seventh region, an eighth region, and a ninth region, the ninth area includes a tenth region, an eleventh region, and a twelfth region; the first region is provided between the first area, the second area, and the third area; The second region is provided between the second area and the tenth region, the third region is provided between the third area and the fourth region, the fourth region is provided between the first area, the third area, and the fourth area, the fifth region is provided between the third area and the first region, the sixth region is provided between the fourth area and the seventh area, the seventh region is provided between the first area, the fourth area, and the fifth area, the eighth region is provided between the fourth area and the fourth region, the ninth region is provided between the fifth area and the tenth area, the tenth region is provided between the first area, the second area, and the fifth area, the eleventh region is provided between the fifth area and the seventh area, The twelfth region is provided between the second area and the first region. The memory device of claim 12.

14. a global bit line connected to the first and second column switch circuits; a global word line connected to the first and second row switch circuits; The memory device of claim 11 further comprising:

15. When a memory cell in the sixth area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and to the global word line via the first row switch circuit; When a memory cell in the seventh area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the first and second row switch circuits; When a memory cell in the eighth area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and to the global word line via the second row switch circuit; When a memory cell in the ninth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the first and second row switch circuits. The memory device of claim 14.

16. When a memory cell in the first area is selected, the selected memory cell is connected to the global bit line via the first and second column switch circuits and connected to the global word line via the first and second row switch circuits; When a memory cell in the second area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the first row switch circuit; When a memory cell in the third area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the first row switch circuit; When a memory cell in the fourth area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and to the global word line via the second row switch circuit; When a memory cell in the fifth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and to the global word line via the second row switch circuit.

16. The memory device of claim 15.

17. A wiring resistance applied to each of the memory cells in the sixth, seventh, eighth and ninth areas is higher than a wiring resistance applied to each of the memory cells in the second, third, fourth and fifth areas and is lower than a wiring resistance applied to a memory cell in the first area. The memory device of claim 11.

18. Each of the plurality of memory cells A memory element; A switching element connected in series to the memory element; Including, The memory device of claim 11.

19. The memory element is a magnetoresistance effect element.

20. The memory device of claim 18.

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