Information processing apparatus

Abstract

To provide an information processing apparatus capable of receiving electric power from a UPS until a plurality of motherboards shut down when a power outage occurs.SOLUTION: An information processing apparatus according to an embodiment includes a first acquisition unit, a power outage detection unit, and a switch unit. The first acquisition unit acquires from each of a plurality of motherboards an activation notification signal indicating an activation state of the motherboard. The power outage detection unit detects a power outage. When the power outage is detected by the power outage detection unit and any of the activation notification signals acquired by the first acquisition unit indicates that the motherboard is activated, the switch unit passes electric power supplied from an uninterruptible power supply device to the motherboard.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to an information processing device. [Background technology]

[0002] Conventionally, information processing devices such as server devices have a motherboard equipped with a microcomputer. The information processing device has a UPS (Uninterruptible Power Supply) to prevent damage to the hardware mounted on the motherboard and data stored on the motherboard in the event of a power outage. For example, in the event of a power outage, the UPS supplies power until the motherboard safely shuts down.

[0003] However, when an information processing device is equipped with a plurality of motherboards, the UPS may stop supplying power if any of the motherboards shuts down. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide an information processing device that can receive power supply from a UPS until a plurality of motherboards are shut down in the event of a power outage. [Means for solving the problem]

[0005] An information processing device according to an embodiment includes a first acquisition unit, a power outage detection unit, and a switch unit. The first acquisition unit acquires, from each of a plurality of motherboards, a startup notification signal indicating the startup state of the motherboard. The power outage detection unit detects a power outage. When a power outage is detected by the power outage detection unit and any of the startup notification signals acquired by the first acquisition unit indicates that the motherboard is starting up, the switch unit passes power supplied from an uninterruptible power supply to the motherboard. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating an example of an information processing device according to the present embodiment. [Diagram 2] FIG. 2 is a flowchart showing the flow of the power supply process executed by the information processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of an information processing device will be described in detail with reference to the accompanying drawings. Note that the embodiment described below is one embodiment of an information processing device, and is not intended to limit the configuration, specifications, and the like of the information processing device.

[0008] 1 is a diagram showing an example of an information processing device 1 according to the present embodiment. The information processing device 1 is a computer such as a server device or a personal computer. The information processing device 1 includes a first motherboard 10, a second motherboard 20, a first conversion circuit 30, a UPS 40, and a baseboard 50.

[0009] The first motherboard 10 and the second motherboard 20 are boards that control the information processing device 1. The first motherboard 10 and the second motherboard 20 may provide different functions, or may provide the same function through parallel processing. Furthermore, the information processing device 1 is not limited to two motherboards, the first motherboard 10 and the second motherboard 20, and may have three or more motherboards.

[0010] The first motherboard 10 has a first microcomputer 101 and a first power supply circuit 102. The first microcomputer 101 is a microcomputer that controls at least a part of the information processing device 1. The first microcomputer 101 has a storage medium such as a register that stores settings. The storage medium stores a UPS setting that indicates whether or not to receive power supply from the UPS 40 during a power outage. When the UPS setting indicates that power is being supplied, the first microcomputer 101 receives power supplied by the UPS 40 during a power outage. On the other hand, when the UPS setting indicates that power is not being supplied, the first microcomputer 101 does not receive power from the UPS 40 even if a power outage occurs.

[0011] Also, the first microcomputer 101 outputs a first UPS setting signal indicating the UPS setting. That is, the first microcomputer 101 outputs a first UPS setting signal indicating whether or not to receive power supply from the UPS 40 during a power outage. Also, the first UPS setting signal becomes a Low state when the setting is to receive power supply from the UPS 40 during a power outage.

[0012] The first power supply circuit 102 is a circuit that starts up the first motherboard 10. The first power supply circuit 102 also outputs a first startup notification signal that notifies the startup state of the first motherboard 10. That is, the first power supply circuit 102 outputs the first startup notification signal that indicates whether the first motherboard 10 is starting up or not.

[0013] The second motherboard 20 has a second microcomputer 201 and a second power supply circuit 202. The second microcomputer 201 is a microcomputer that controls at least a part of the information processing device 1. The second microcomputer 201 has a storage medium such as a register that stores settings. The storage medium stores a UPS setting of whether or not power is supplied from the UPS 40 during a power outage. When the UPS setting is for power supply, the second microcomputer 201 receives power supplied by the UPS 40 during a power outage. On the other hand, when the UPS setting is for no power supply, the second microcomputer 201 does not receive power from the UPS 40 even if a power outage occurs.

[0014] Also, the second microcomputer 201 outputs a second UPS setting signal indicating the UPS setting. That is, the second microcomputer 201 outputs a second UPS setting signal indicating whether or not to receive power supply from the UPS 40 during a power outage. Also, the second UPS setting signal becomes a Low state when the setting is to receive power supply from the UPS 40 during a power outage.

[0015] The second power supply circuit 202 is a circuit that starts up the second motherboard 20. In addition, the second power supply circuit 202 outputs a second startup notification signal that notifies the startup state of the second motherboard 20. That is, the second power supply circuit 202 outputs the second startup notification signal that indicates whether the second motherboard 20 is starting up or not.

[0016] The first conversion circuit 30 is a circuit having an AC (Alternating Current)-DC (Direct Current) converter that converts AC current into DC current. The first conversion circuit 30 is, for example, an AC adapter. The first conversion circuit 30 converts the AC current supplied from the AC power source 2 into DC current and outputs it to the base board 50.

[0017] The UPS 40 is an uninterruptible power supply device that supplies power during a power outage. More specifically, the UPS 40 supplies power to each unit of the information processing device 1 when no AC current is supplied from the AC power source 2. For example, the UPS 40 supplies power to the first motherboard 10 and the second motherboard 20 via the baseboard 50.

[0018] The baseboard 50 is a board to which multiple motherboards are connected. When a power outage is detected, the baseboard 50 receives power from the UPS 40. The baseboard 50 outputs the power supplied from the UPS 40 to the first motherboard 10 and the second motherboard 20.

[0019] The base board 50 includes a logical sum circuit 501, a logical product circuit 502, a second conversion circuit 503, a power outage monitoring circuit 504, a first buffer circuit 505, a second buffer circuit 506, a switch circuit 507, a first rectifier circuit 508, a second rectifier circuit 509, a constant voltage circuit 510, and a third conversion circuit 511.

[0020] The OR circuit 501 acquires a startup notification signal indicating the startup state of each of the multiple motherboards from each of the multiple motherboards. The OR circuit 501 is an example of a first acquisition unit. Then, the OR circuit 501 outputs an aggregated startup notification signal indicating whether or not any of the multiple motherboards included in the information processing device 1 is running.

[0021] More specifically, the OR circuit 501 receives a first start-up notification signal from the first power supply circuit 102 of the first motherboard 10. In addition, the OR circuit 501 receives a second start-up notification signal from the second power supply circuit 202 of the second motherboard 20.

[0022] The logical sum circuit 501 outputs an aggregated startup notification signal indicating that any of the motherboards is starting up when at least one of the first startup notification signal of the first power supply circuit 102 and the second startup notification signal of the second power supply circuit 202 indicates starting up. On the other hand, the logical sum circuit 501 outputs an aggregated startup notification signal indicating that all of the motherboards are not starting up when both the first startup notification signal of the first power supply circuit 102 and the second startup notification signal of the second power supply circuit 202 indicate not starting up.

[0023] The AND circuit 502 acquires a UPS setting signal indicating whether or not each of the motherboards is set to receive power from the UPS 40 during a power outage. The AND circuit 502 is an example of a second acquisition unit. The AND circuit 502 outputs an aggregated UPS setting signal indicating whether or not any of the motherboards included in the information processing device 1 is set to receive power from the UPS 40.

[0024] More specifically, the AND circuit 502 acquires a first UPS setting signal from the first microcomputer 101 of the first motherboard 10. In addition, the AND circuit 502 acquires a second UPS setting signal from the second microcomputer 201 of the second motherboard 20.

[0025] The AND circuit 502 outputs an aggregate UPS setting signal indicating that the UPS setting is set to "with power supply" in any of the motherboards when at least one of the first UPS setting signal of the first microcomputer 101 and the second UPS setting signal of the second microcomputer 201 indicates that power is being supplied. On the other hand, the AND circuit 502 outputs an aggregate UPS setting signal indicating that the UPS setting is set to "without power supply" in all of the motherboards when both the first UPS setting signal of the first microcomputer 101 and the second UPS setting signal of the second microcomputer 201 indicate that power is not being supplied.

[0026] Here, the first UPS setting signal and the second UPS setting signal are in a Low state when the setting is made to receive power supply from the UPS 40 during a power outage. Therefore, the AND circuit 502 outputs an aggregated UPS setting signal in a Low state when the UPS setting is set to supply power in any of the motherboards.

[0027] The second conversion circuit 503 is a circuit having a DC-DC converter that converts into a DC voltage suitable for the base board 50. More specifically, the second conversion circuit 503 receives an input of a DC current output from the first conversion circuit 30. In addition, the second conversion circuit 503 converts the voltage of the DC current input from the first conversion circuit 30 into a DC voltage suitable for the base board 50 and outputs it.

[0028] The power failure monitoring circuit 504 is a circuit that detects a power failure. The power failure monitoring circuit 504 is an example of a power failure detection unit. In other words, the power failure monitoring circuit 504 is a circuit that monitors the stop of power supply from the AC power source 2. For example, the power failure monitoring circuit 504 determines that a power failure has occurred when the DC voltage output from the second conversion circuit 503 becomes less than a threshold value. In other words, the power failure monitoring circuit 504 determines that the power supply from the AC power source 2 has stopped.

[0029] The first buffer circuit 505 is a circuit having a three-state buffer that switches whether to output a power failure detection signal based on the aggregated startup notification signal from the logical sum circuit 501. When the first buffer circuit 505 acquires from the logical sum circuit 501 an aggregated startup notification signal indicating that the motherboard is starting up, the first buffer circuit 505 outputs a power failure detection signal indicating that a power failure has been detected by the power failure monitoring circuit 504 to the switch circuit 507. The first buffer circuit 505 is an example of a first connection unit. In addition, the first buffer circuit 505 cuts off the power failure detection signal when the condition is not satisfied.

[0030] More specifically, when an aggregated startup notification signal indicating that any of the motherboards is activated is input from the OR circuit 501, the first buffer circuit 505 outputs the power failure detection signal input from the power failure monitoring circuit 504. On the other hand, when an aggregated startup notification signal indicating that all of the motherboards are not activated is input from the OR circuit 501, the first buffer circuit 505 does not output the power failure detection signal input from the power failure monitoring circuit 504. In other words, the first buffer circuit 505 cuts off the connection between the power failure monitoring circuit 504 and the second buffer circuit 506.

[0031] The second buffer circuit 506 is a circuit having a three-state buffer that switches whether to output a power failure detection signal based on the aggregated UPS setting signal from the AND circuit 502. When the second buffer circuit 506 acquires from the AND circuit 502 an aggregated UPS setting signal indicating that power is supplied from the UPS 40 during a power failure, the second buffer circuit 506 outputs a power failure detection signal to the switch circuit 507. The second buffer circuit 506 is an example of a second connection unit. Moreover, the second buffer circuit 506 cuts off the power failure detection signal when the condition is not satisfied.

[0032] More specifically, when an aggregate UPS setting signal indicating that the UPS setting is valid in any of the motherboards is input from the AND circuit 502, the second buffer circuit 506 outputs the power failure detection signal input from the first buffer circuit 505. That is, when an aggregate UPS setting signal indicating that the UPS setting is invalid in all the motherboards is input from the OR circuit 501, the second buffer circuit 506 does not output the power failure detection signal input from the power failure monitoring circuit 504. In other words, the second buffer circuit 506 cuts off the connection between the first buffer circuit 505 and the switch circuit 507.

[0033] The switch circuit 507 is a circuit that switches whether or not to receive power supply from the UPS 40, based on the power failure detection signal output from the second buffer circuit 506. For example, the switch circuit 507 has a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0034] The switch circuit 507 passes the power supplied from the UPS 40 to the first motherboard 10 and the second motherboard 20 when a power outage is detected by the power outage monitoring circuit 504 and either the first startup notification signal or the second startup notification signal acquired by the logical sum circuit 501 indicates that the motherboard is starting up. The switch circuit 507 is an example of a switch unit. In addition, when a power outage is detected by the power outage monitoring circuit 504, either the first UPS setting signal or the second UPS setting signal acquired by the logical sum circuit 502 indicates that the motherboard is starting up, and either the first startup notification signal or the second startup notification signal acquired by the logical sum circuit 501 indicates that the setting is to receive power supply from the UPS 40, the switch circuit 507 passes the power supplied from the UPS 40 to the motherboard.

[0035] The switch circuit 507 passes the current supplied from the UPS 40 when a power outage detection signal indicating that a power outage has occurred is input from the second buffer circuit 506. For example, when a power outage detection signal is input to the gate terminal of the switch circuit 507, a channel is formed between the source terminal and the drain terminal. This causes the switch circuit 507 to pass the power supplied from the UPS 40 to the second rectifier circuit 509. On the other hand, when a power outage detection signal indicating that a power outage has occurred is not input from the second buffer circuit 506, the switch circuit 507 stops the current supplied from the UPS 40. In other words, the switch circuit 507 does not pass the power supplied from the UPS 40 to the second rectifier circuit 509.

[0036] The first rectifier circuit 508 is a circuit having a diode that rectifies the direct current output from the second conversion circuit 503. In other words, the first rectifier circuit 508 prevents a current from flowing in the reverse direction.

[0037] The second rectifier circuit 509 is a circuit having a diode that rectifies the direct current output from the switch circuit 507. In other words, the second rectifier circuit 509 prevents the current from flowing in the reverse direction.

[0038] The constant voltage circuit 510 is a circuit that outputs a DC current of a constant voltage to the third conversion circuit 511. The constant voltage circuit 510 realizes the constant voltage by, for example, a Zener diode. More specifically, the constant voltage circuit 510 outputs the DC current supplied from the first rectifier circuit 508 or the second rectifier circuit 509 to the third conversion circuit 511 at a constant voltage.

[0039] The third conversion circuit 511 is a circuit that converts a DC voltage suitable for a supply destination. More specifically, the third conversion circuit 511 converts the DC current output from the constant voltage circuit 510 into a DC voltage suitable for a supply destination of the information processing device 1. Then, the third conversion circuit 511 outputs the converted DC voltage to each supply destination of the information processing device 1. For example, the third conversion circuit 511 outputs the converted DC voltage to the first motherboard 10 and the second motherboard 20.

[0040] Next, a description will be given of the operation of the information processing device 1. Note that the description will be given of a case where at least one of the first motherboard 10 and the second motherboard 20 is activated and the UPS setting is enabled.

[0041] The first conversion circuit 30 converts the AC current supplied from the AC power supply 2 into a DC current and outputs the DC current. The second conversion circuit 503 converts the DC current output from the first conversion circuit 30 into a DC voltage suitable for the base board 50 and outputs the DC voltage.

[0042] The first rectifier circuit 508 rectifies the direct current output from the second conversion circuit 503. The constant voltage circuit 510 outputs the direct current output from the first rectifier circuit 508 to the third conversion circuit 511 at a constant voltage.

[0043] The third conversion circuit 511 converts the voltage into a DC voltage suitable for the first motherboard 10 and the second motherboard 20 and outputs the converted voltage.

[0044] The power failure monitoring circuit 504 detects a power failure, in other words, a stop of the power supply from the AC power supply 2, based on the voltage of the current voltage output from the second conversion circuit 503. When a stop of the power supply from the AC power supply 2 is detected, the power failure monitoring circuit 504 outputs a power failure detection signal indicating that a power failure has occurred.

[0045] The first buffer circuit 505 outputs the power failure detection signal input from the power failure monitoring circuit 504 since the aggregated startup notification signal indicating that the first motherboard 10 or the second motherboard 20 is starting up is input.

[0046] The second buffer circuit 506 outputs the power outage detection signal input from the first buffer circuit 505 because an aggregated UPS setting signal indicating that power supply is set to be on in the first motherboard 10 or the second motherboard 20 has been input.

[0047] Since the power failure detection signal is input from the second buffer circuit 506 , the switch circuit 507 passes the power supplied from the UPS 40 to the first rectifier circuit 508 .

[0048] The third conversion circuit 511 converts the power input via the first rectification circuit 508 and the constant voltage circuit 510 into a DC voltage suitable for the first motherboard 10 and the second motherboard 20, and outputs the DC voltage.

[0049] Next, a power supply process executed by the information processing device 1 according to this embodiment will be described below.

[0050] The power failure monitoring circuit 504 determines whether or not a power failure has been detected (step S1). If a power failure has not been detected (step S1; No), the power failure monitoring circuit 504 waits.

[0051] When a power outage is detected (step S1; Yes), the first buffer circuit 505 judges whether the first motherboard 10 or the second motherboard 20 is booting up (step S2). When the first motherboard 10 and the second motherboard 20 are not booting up (step S2; No), the information processing device 1 proceeds to step S1.

[0052] When the first motherboard 10 or the second motherboard 20 is booting (step S2; Yes), the second buffer circuit 506 determines whether or not the UPS setting is enabled on the first motherboard 10 or the second motherboard 20 (step S3). When the UPS setting is not enabled (step S3; No), the information processing device 1 ends the power supply process.

[0053] When the UPS setting is enabled (step S3; Yes), the switch circuit 507 supplies the power supplied from the UPS 40 to each unit via the third conversion circuit 511 (step S4).

[0054] With the above, the information processing device 1 ends the power supply process.

[0055] As described above, the OR circuit 501 of the information processing device 1 according to the present embodiment acquires the first startup notification signal and the second startup notification signal indicating the startup states of the first motherboard 10 and the second motherboard 20, respectively. In addition, the information processing device 1 detects a power outage of the AC power source 2. Then, when a power outage is detected by the power outage monitoring circuit 504 and the first startup notification signal and the second startup notification signal acquired by the OR circuit 501 indicate that the first motherboard 10 or the second motherboard 20 is starting up, the switch circuit 507 passes the power supplied from the UPS 40 to the first motherboard 10 and the second motherboard 20 via the third conversion circuit 511. Therefore, the information processing device 1 can receive power from the UPS 40 until the multiple motherboards are shut down in the event of a power outage.

[0056] (Variation 1) The first microcomputer 101 according to this embodiment is mounted on the first motherboard 10. However, the first microcomputer 101 may be mounted on another board, not limited to the first motherboard 10. For example, the first microcomputer 101 may be mounted on the baseboard 50, or on a board not shown in FIG. 1.

[0057] The second microcomputer 201 according to this embodiment is mounted on the second motherboard 20. However, the second microcomputer 201 may be mounted on another board, not limited to the second motherboard 20. For example, the second microcomputer 201 may be mounted on the baseboard 50, or on a board not shown in FIG.

[0058] (Variation 2) The base board 50 according to this embodiment receives a first UPS setting signal and a second UPS setting signal from the first microcomputer 101 and the second microcomputer 201. However, when power is always supplied from the UPS 40 during a power outage, the base board 50 always receives the first UPS setting signal and the second UPS setting signal with power supply, so the base board 50 does not need to receive the first UPS setting signal and the second UPS setting signal. In this case, the base board 50 does not need to have the AND circuit 502 and the second buffer circuit 506. In addition, the first buffer circuit 505 may output a power outage detection signal to the switch circuit 507.

[0059] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0060] 1. Information processing device 2 AC power supply 10 First Motherboard 20 Second Motherboard 30 First conversion circuit 40 UPS(Uninterruptible Power Supply) 50 Baseboard 101 First Microcomputer 102 1st power supply circuit 201 Second Microcomputer 202 2nd power supply circuit 501 OR circuit 502 AND Circuit 503 Second conversion circuit 504 Power failure monitoring circuit 505 First Buffer Circuit 506 Second Buffer Circuit 507 Switch Circuit 508 1st rectifier circuit 509 2nd rectifier circuit 510 Constant voltage circuit 511 Third conversion circuit [Prior art documents] [Patent documents]

[0061] [Patent Document 1] Japanese Patent Application Publication No. 07-295688

Claims

1. a first acquisition unit that acquires, from each of a plurality of motherboards, a startup notification signal that indicates a startup state of the motherboard; A power outage detection unit that detects a power outage; a switch unit that flows power supplied from an uninterruptible power supply to the motherboard when a power outage is detected by the power outage detection unit and any of the startup notification signals acquired by the first acquisition unit indicates that the motherboard is starting up; An information processing device comprising:

2. a second acquisition unit that acquires, for each of the plurality of motherboards, a setting signal indicating a setting as to whether to receive power supply from the uninterruptible power supply device in the event of a power outage; the switch unit, when a power outage is detected by the power outage detection unit, any of the startup notification signals acquired by the first acquisition unit indicates that the motherboard is starting up, and any of the startup notification signals acquired by the second acquisition unit indicates that a setting is made to receive power supply from the uninterruptible power supply, causes the power supplied from the uninterruptible power supply to flow to the motherboard; The information processing device according to claim 1 .

3. A first connection unit outputs a power failure detection signal indicating that a power failure has been detected by the power failure detection unit to the switch unit when a signal indicating that the motherboard is booting is acquired from the first acquisition unit, The information processing device according to claim 2 .

4. A second connection unit that outputs the power failure detection signal to the switch unit when a signal indicating that the uninterruptible power supply is set to be supplied with power during a power failure is acquired from the second acquisition unit, The information processing device according to claim 3 .

5. The first connection unit and the second connection unit have a three-state buffer that blocks the power failure detection signal when a condition is not satisfied. The information processing device according to claim 4.

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