Planar antenna and antenna device

Abstract

To provide a planar antenna in which variation in characteristic impedance at a signal line is suppressed.SOLUTION: A planar antenna 1 includes: a thin film transistor substrate 120 where a phase shift layer 130 is formed, the phase shift layer including an antenna array in which a plurality of patch antennas P are disposed in an array form two dimensionally, a phase shifter 131 to deal with each of the patch antennas P, and a wire 135 used to control the phase shifter 131; signal lines LS1 and LS2 formed on the same surface as the antenna array, through which signals to be communicated propagate; and a ground layer 141 disposed between the phase shifter layer 130 and the signal lines LS1 and LS2 and having a slot St formed between at least the signal lines LS1 and LS2 and the phase shifter 131.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a planar antenna and an antenna device. [Background technology]

[0002] Patent Document 1 discloses a phased array antenna device having a plurality of radiating elements. The device of Patent Document 1 has a multi-layer structure formed by a plurality of radiating elements, a plurality of phase shifters, a phase-shift control circuit, and a power supply unit. The phase shifter is coupled to any one of the radiating elements and shifts the phase of a power supply signal supplied to the radiating element for each bit. The phase-shift control circuit controls the phase shift of the plurality of phase shifters. The power supply unit is arranged to be coupled to the radiating element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-074717 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the configuration of Patent Document 1, the antenna gain can be improved by increasing the number of elements. However, when the number of elements is increased to 10,000, there are cases where the wiring used for selecting the phase shifter or writing data crosses the signal line, which may cause mutual interference. If the wiring used for selecting the phase shifter or writing data interferes with the signal line, the characteristic impedance of the signal line may fluctuate.

[0005] An object of the present disclosure is to provide a planar antenna and an antenna device in which fluctuations in characteristic impedance in a signal line are suppressed. [Means for solving the problem]

[0006] A planar antenna according to one embodiment of the present disclosure comprises an antenna array in which a plurality of patch antennas are arranged in a two-dimensional array, a substrate on which a phase shifter layer is formed, the phase shifter layer including phase shifters corresponding to each of the plurality of patch antennas and wiring used to control the phase shifters, a signal line formed on the same surface as the antenna array and through which a signal to be communicated propagates, and a ground layer disposed between the phase shifter layer and the signal line, with a slot formed at least between the signal line and the phase shifter. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a planar antenna and an antenna device in which fluctuations in characteristic impedance in a signal line are suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Diagram 2] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Diagram 3] 1 is a conceptual diagram for explaining an example of a phase shifter memory included in a planar antenna in the present disclosure. FIG. [Figure 4] 1 is a conceptual diagram for explaining an example of a switch included in a planar antenna in the present disclosure. [Diagram 5] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Figure 6] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Figure 7] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Figure 8] 10 is a conceptual diagram for explaining an example of a planar antenna in a comparative example. FIG. [Figure 9] 10 is a conceptual diagram for explaining an example of a planar antenna in a comparative example. FIG. [Figure 10] FIG. 13 is a conceptual diagram showing an example of the configuration of a planar antenna in a comparative example. [Figure 11] 1 is a conceptual diagram illustrating an example of an antenna device according to the present disclosure. [Figure 12] 1 is a block diagram showing an example of a configuration of an antenna device according to the present disclosure. [Figure 13] FIG. 1 is a conceptual diagram illustrating an example of the configuration of a planar antenna in the present disclosure. [Figure 14] FIG. 2 is a block diagram showing an example of a hardware configuration for executing control and processing in each embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments for carrying out the present disclosure will be described with reference to the drawings. In this disclosure, the drawings used in the description of each embodiment relate to one or more embodiments. In addition, the elements included in each drawing may apply to one or more embodiments. The embodiments described below are limited in a manner that is technically preferable for carrying out the present disclosure, but the scope of the disclosure is not limited to the following. In all the drawings used in the description of the following embodiments, the same reference numerals are used for similar parts unless otherwise specified. In the following embodiments, repeated description of similar configurations and operations may be omitted.

[0010] (First embodiment) First, the planar antenna according to the first embodiment will be described with reference to the drawings. The planar antenna of this embodiment includes a patch antenna, which is a type of planar antenna. In the following, a transmitter that transmits radio waves from the planar antenna and a receiver that receives radio waves received by the planar antenna will not be described. For example, the planar antenna of this embodiment is used for transmitting and receiving electromagnetic waves in a high frequency band that is expected to be applied to mobile communications of B5G (Beyond 5 Generation) following 5G (5 Generation). For example, the planar antenna of this embodiment is used for transmitting and receiving millimeter wave and terahertz wave signals. Note that the planar antenna of this embodiment may be used for transmitting and receiving signals other than millimeter wave and terahertz wave.

[0011] For example, the planar antenna of this embodiment includes a phase shift element formed using a manufacturing process technology of a micro LED (Light-Emitting Diode) display. The planar antenna of this embodiment also includes a switching element formed using a manufacturing process technology of a thin film transistor (TFT). In manufacturing the planar antenna of this embodiment, a manufacturing process technology of a micro LED display (micro LED process technology) and a manufacturing process technology of a thin film transistor (TFT process technology) are combined. Note that the planar antenna of this embodiment may be manufactured using a technology other than the micro LED process technology and the TFT process technology.

[0012] (composition) FIG. 1 is a cross-sectional view showing a cross section of a portion of a planar antenna according to the present disclosure. The planar antenna 1 of this embodiment includes a patch antenna P, a first insulating layer 111, a second insulating layer 112, a TFT substrate 120, a phase shifter layer 130, a ground layer 141, and a ground layer 142. The phase shifter layer 130 is formed with a phase shifter 131 and a TFT wiring 135. The TFT wiring 135 includes wiring such as a selection line and a data line used to control the phase shifter. The planar antenna 1 includes a signal line (signal line L) connected to a signal source (not shown). S1 , signal line L S1 ) is included. Signal line L S1 and signal line L S1 is formed in the same layer as the patch antenna P. In other words, the planar antenna 1 is a coplanar type planar antenna in which the patch antenna P and the signal line are formed on the same plane.

[0013] The first insulating layer 111 is formed on the surface of the planar antenna 1. A patch antenna array is disposed on the upper surface of the first insulating layer 111. The patch antenna array is composed of a plurality of patch antennas P. Although a single patch antenna P is illustrated in FIG. 1, the planar antenna 1 includes a plurality of patch antennas P. The plurality of patch antennas P are arranged in a lattice pattern along two directions perpendicular to each other. The plurality of patch antennas P are formed into a phased array. The patch antenna P is a plate-shaped radiating element. For example, the patch antenna P is rectangular. The shape of the patch antenna P is not limited to rectangular, and may be circular or another shape.

[0014] In addition, the signal line L is provided on the upper surface of the first insulating layer 111. S1 and signal line L S1 The signal line L S1 The first signal line is a signal line through which a signal before phase shifting supplied from a signal source is transmitted. S1 The first end of the signal line L is connected to a signal source. S1 The second end of the signal line L is disposed above the first end of the phase shifter 131. S1 The second end of the signal line L functions as an open end of the microstrip line. S1 The second end of the phase shifter slot S t The signal line L is connected to a first end of the phase shifter 131 by electromagnetic coupling EC (Electromagnetic Coupling) via the signal line L S1 Between the phase shifter 131 and the first insulating layer 111, a phase shifter slot S t A capacitance is formed according to the air space in this portion and the dielectric constant of second insulating layer 112.

[0015] Signal line L S2 The second signal line is a signal line through which the signal after the phase shift by the phase shifter 131 is transmitted to the patch antenna P. S2 The signal line L may be formed integrally with the patch antenna P. S2 The first end of the signal line L is disposed above the second end of the phase shifter 131. S2The first end of the signal line L functions as an open end of the microstrip line. S2 The first end of the phase shifter slot S t The signal line L is connected to the second end of the phase shifter 131 by electromagnetic coupling EC via the signal line L. S2 Between the phase shifter 131 and the first insulating layer 111, a phase shifter slot S t A capacitance is formed according to the air layer in this portion and the dielectric constant of the second insulating layer 112. S2 The second end of the antenna is connected to a patch antenna P.

[0016] The signal supplied from the signal source is fed into the phase shifter slot S t The electromagnetic coupling EC via the signal line L S1 The signal propagated to the phase shifter 131 is phase-shifted. The signal whose phase has been shifted by the phase shifter 131 is then propagated to the phase shifter slot S t The electromagnetic coupling EC from the phase shifter 131 to the signal line L S2 The signal whose phase has been shifted by the phase shifter is propagated to the signal line L S2 The signal propagates through the antenna and is transmitted to a patch antenna P. The signal propagated to the patch antenna P is transmitted as a radio signal from a phased array antenna formed by multiple patch antennas P.

[0017] The first insulating layer 111 is laminated on the upper surface of the ground layer 141. For example, the material of the first insulating layer 111 is glass, glass epoxy, or a resin such as tetrafluoroethylene or epoxy. The first insulating layer 111 may be made of a material other than glass, glass epoxy, or a resin such as tetrafluoroethylene or epoxy, as long as it is capable of transmitting and receiving radio waves for communication.

[0018] The ground layer 141 is disposed on the lower surface of the first insulating layer 111. The ground layer 141 blocks electromagnetic coupling above and below the ground layer 141. The ground layer 141 is made of a conductor. For example, the material of the ground layer 141 is a metal (including an alloy) such as copper, aluminum, or chromium. The potential of the ground layer 141 is ground potential. The lower surface of the ground layer 141 contacts the upper surface of the ground layer 141.

[0019] A plurality of openings are formed in the ground layer 141. The openings formed in the ground layer 141 are called slots. The slots are called phase shifter slots S. t Includes phase shifter slot S t are formed between the phase shifter layer 130 and the signal line. In the example of FIG. 1, one type of phase shifter slot S t is formed in the ground layer 141. The phase shifter slot S t is formed above a phase shifter 131 formed in a phase shifter layer 130.

[0020] The second insulating layer 112 is formed under the ground layer 141. The TFT substrate 120 is disposed under the second insulating layer 112. The upper surface of the second insulating layer 112 is in contact with the lower surface of the ground layer 141. A part of the upper surface of the second insulating layer 112 is in contact with the slot S for the phase shifter formed in the ground layer 141. t The second insulating layer 112 faces a part of the lower surface of the first insulating layer 111 via the TFT wiring 135. The lower surface of the second insulating layer 112 contacts the TFT wiring 135 formed on the upper surface of the TFT substrate 120 and the phase shifter layer 130. For example, the material of the second insulating layer 112 is glass, glass epoxy, or a resin such as tetrafluoroethylene or epoxy. The second insulating layer 112 may be made of a material other than glass, glass epoxy, or a resin such as tetrafluoroethylene or epoxy, as long as it is capable of transmitting and receiving radio waves for communication.

[0021] The TFT substrate 120 is disposed below the second insulating layer 112. For example, the material of the TFT substrate 120 is a dielectric material such as glass. On the upper surface of the TFT substrate 120, a TFT wiring 135 and a phase shifter layer 130 are formed. The TFT wiring 135 includes a plurality of selection lines used to select a phase shifter and a plurality of data lines used to write phase shift data to the phase shifter. On the upper surface of the TFT substrate 120, a matrix circuit is formed. The matrix circuit has a structure in which a plurality of thin film transistors (TFTs) are arranged in a two-dimensional array. For example, the TFTs included in the matrix circuit are formed using a TFT process technology. In addition, a signal layer is formed above the matrix circuit. In the signal layer, wiring constituting the phase shift element, a switch group including a plurality of switching elements, and wiring for connecting the wiring and switch group constituting the phase shift element are formed. For example, the switching element is formed using a micro LED process technology. For example, the material of the TFT substrate 120 is glass, glass epoxy, or a resin such as tetrafluoroethylene or epoxy. The TFT substrate 120 may be made of a material other than resin, such as glass, glass epoxy, tetrafluoroethylene, or epoxy, as long as it is capable of transmitting and receiving radio waves for communication.

[0022] The ground layer 142 (second ground layer) is disposed on the lower surface of the TFT substrate 120. The ground layer 142 is also called a ground plate. The ground layer 142 is made of a conductor. The characteristic impedance of the phase shifter 131 is ensured between the phase shifter 131 and the ground layer 141. For example, the material of the ground layer 142 is a metal (including an alloy) such as copper, aluminum, or chromium. The potential of the ground layer 142 is the ground potential.

[0023] The patch antenna P is connected to a signal line L arranged on the same plane. S2 Power is supplied through the signal line L S2 The patch antenna P is excited by power supply through the patch antenna P. The resonant frequency of the patch antenna P is an integer multiple of 1 / 2 the wavelength, which corresponds to the length of one side of the patch antenna P. The size of the patch antenna P is set according to the wavelength of the radio wave to be transmitted.

[0024] It is preferable that the patch antenna P easily radiates signals (radio waves) into space. In contrast, it is preferable that the internal wiring such as signal lines and wiring does not easily radiate signals. In other words, the smaller the dielectric constant required around the patch antenna P, the better, and the larger the dielectric constant required around the internal wiring, the better. For this reason, it is preferable that different manufacturing processes are applied to the structure around the patch antenna P and the structure around the internal wiring. For example, the structure of the planar antenna 1 of this embodiment can be realized by applying a method in which the structure around the patch antenna P is formed by a liquid crystal process and the structure around the internal wiring is formed by a thin film process.

[0025] 2 is a plan view of a portion of the planar antenna in the present disclosure. In FIG. 2, the first insulating layer 111, the second insulating layer 112, the TFT substrate 120, the ground layer 141, and the ground layer 142 are omitted. In FIG. 2, the patch antenna P, the phase shifter 131 formed in the phase shifter layer 130, and the signal line L are shown. S The positional relationship of the selection line L PS , data line L PD , and a phase shifter memory 150.

[0026] As shown in Figure 2, the signal line L S1 and signal line L S2 is the selection line L PS and data line L PD In the example of Figure 2, the signal line L S1 The signal line L has a first end that is branched into four. S1 The first end of the phase shifter slot S t The signal line L passes under the phase shifter 131. S1 is the phase shifter slot S t The signal line L is electromagnetically coupled to the phase shifter 131 via the signal line L. S2 is electrically connected to the patch antenna P.

[0027] FIG. 3 is a conceptual diagram for explaining the phase shifter memory 150. The phase shifter memory 150 includes memories M, the number of which corresponds to the number of bits. In the example of FIG. 3, the phase shifter memory 150 is 4 bits. The phase shifter memory 150 includes four memories M (M1, M2, M3, M4). FIG. 3 shows a memory selection line L for making the memories M included in the phase shifter memory 150 writable. MS Also, a data line L for writing data to the memory M is shown. D In the example of FIG. 3, four data lines L are arranged corresponding to each of the multiple memories M. D Shows.

[0028] The phase shifter 13 is provided with a plurality of switch groups SW (SW1, SW2, SW3, SW4) each associated with a plurality of memories M. For example, if the phase shifter 131 is a 4-bit line switching type, the switch group SW includes four switches per bit (16 in total). The switch group SW1 is connected to the memory M1. The switch group SW2 is connected to the memory M2. The switch group SW3 is connected to the memory M3. The switch group SW4 is connected to the memory M4. For example, the switch group SW is composed of a switching element including a thin film of vanadium dioxide VO2.

[0029] FIG. 4 is a conceptual diagram for explaining the configuration of a switch group SW composed of switching elements including a thin film of vanadium dioxide VO2. FIG. 4 shows an example in which a transmission line R1 and a transmission line R2 are electrically connected via the switch group SW. A heating wire H is thermally connected to the switch group SW. A first end of the heating wire H is connected to a power line L. P Connected to the power line L P The second end of the TFT is connected to the drain d of the TFT. The source of the TFT is connected to the ground line L G When a gate voltage is applied to the gate g of the TFT, a power line L P Current is supplied from the power line L PA current from is supplied to the TFT via the heating wire H. When a current flows through the heating wire H, the heating wire H generates heat. When the temperature of the switch group SW in contact with the heating wire H exceeds the phase transition temperature of vanadium dioxide VO2, the switch group SW transitions to the ON state. When the switch group SW transitions to the ON state, the transmission line R1 and the transmission line R2 are electrically connected. In this embodiment, the transmission line R1 is connected to the memory M, and the transmission line R2 is connected to the phase shifter 131.

[0030] The phase shifter 131 is formed by a TFT process. For example, as shown in the examples of Figs. 3 and 4, the phase shifter 131 is provided with a switch group SW made of vanadium dioxide VO2. For example, a signal line that provides a phase level to a plurality of phase shifters 131 arranged in a matrix and a memory M that stores data for each phase shifter 131 are formed as a TFT circuit. Therefore, inside the planar antenna 1, internal wiring such as a signal line and a selection line are arranged in a matrix. The intersection of these internal wirings is separated by a ground layer 141. Therefore, in the planar antenna 1 of this embodiment, the dielectric constant around the patch antenna P and the dielectric constant around the internal wiring can be set to completely different values. That is, according to this embodiment, the dielectric constant around the patch antenna P and the dielectric constant around the internal wiring can be set to values ​​according to their respective requirements.

[0031] (Modification) Next, modified examples of the planar antenna 1 of this embodiment will be described with reference to the drawings. In the following description, the matters that have been described so far may be omitted. The following modified examples are merely examples and do not limit the configuration of the planar antenna 1 of this embodiment.

[0032] [Variation 1] Fig. 5 is a cross-sectional view showing a cross section of a portion of the planar antenna in the present disclosure. Fig. 6 is a plan view showing the upper surface of a portion of the planar antenna in the present disclosure. The planar antenna 1-1 of the first modification has a configuration in which a single ground layer is used in the planar antenna 1 (Fig. 1).

[0033] The phase shifter layer 130-1 is formed with a phase shifter 132 and a TFT wiring 135. The phase shifter 132 extends to a region below the patch antenna P. The ground layer 141 is provided with two types of slots S for the phase shifter. t (Phase shifter slot S t1 , phase shifter slot S t2 ) is formed. Phase shifter slot S t1 is a signal line L S1 The phase shifter slot S is formed between the first end and the second end of the phase shifter. t2 is a part of the upper surface of the phase shifter 132 and the signal line L S2 A first end of the first plate is formed between the first plate and the second plate.

[0034] In the planar antenna 1-1, the phase shifter slot S t1 Through the signal line L S1 and the phase shifter 132 are connected by electromagnetic coupling EC. In addition, in the planar antenna 1-1, the phase shifter slot S t2 Through the signal line L S2 and the phase shifter 132 are connected by electromagnetic coupling EC. According to this modification, the phase shifter 132 can be extended to below the patch antenna P, so there is a greater degree of freedom in the shape and size of the phase shifter 132 compared to the planar antenna 1 (FIG. 1). The configuration of this modification makes it possible to apply a phase shifter having multiple lines or a phase shifter with a long line length. Furthermore, according to this modification, the characteristic impedance can be secured between the phase shifter 132 and the ground layer 143, so the ground layer 142 of the planar antenna 1 (FIG. 1) is not necessary.

[0035] [Modification 2] 7 is a cross-sectional view showing a cross section of a part of a planar antenna according to the present disclosure. A planar antenna 1-2 according to the second modification is an example in which an upper layer structure U and a lower layer structure L are formed separately. The upper layer structure U includes a patch antenna P, a signal line L, and a S2 , signal line L S1 , and a first insulating layer 111. The lower structure L includes a ground layer 143 and a TFT substrate 120 having a phase shifter layer 130-1 formed on its upper surface. A dielectric layer (not shown) is disposed between the upper structure U and the lower structure L.

[0036] The phase shifter layer 130-1 is formed with a phase shifter 132 and a TFT wiring 135. The phase shifter 132 extends to a region below the patch antenna P. The ground layer 141 is provided with two types of slots S for the phase shifter. t (Phase shifter slot S t1 , phase shifter slot S t2 ) is formed. Phase shifter slot S t1 is a signal line L S1 The phase shifter slot S is formed between the first end and the second end of the phase shifter. t2 is a part of the upper surface of the phase shifter 132 and the signal line L S2 is formed between the first end of the

[0037] In the planar antenna 1-2, the phase shifter slot S t1 Through the signal line L S1 and the phase shifter 132 are connected by electromagnetic coupling EC. In addition, in the planar antenna 1-1, the phase shifter slot S t2 Through the signal line L S2 and the phase shifter 132 are connected by electromagnetic coupling EC. According to this modification, the TFT substrate 120 and the ground layer 143 can be integrally formed by TFT process technology. Furthermore, according to the configuration of this modification, the upper layer structure U and the lower layer structure L can be manufactured by different manufacturing methods. For example, the upper layer structure U can be manufactured by micro LED process technology, and the lower layer structure L can be manufactured by TFT process technology. Therefore, compared to modification 1, this modification has a greater degree of freedom in manufacturing.

[0038] (Comparative Example) Next, a comparative example of this embodiment will be described with reference to the drawings. The following comparative example relates to a two-dimensional phased array antenna in which a phase shifter is driven by a TFT. When a phase shifter is driven by a TFT, wiring is formed for selecting the phase shifter and writing phase shift data. In the following comparative example, a figure in which the wiring portion is emphasized is used.

[0039] Comparative Example 1 8 is a plan view of a planar antenna according to Comparative Example 1. The planar antenna 101 of this comparative example has a plurality of patch antennas P and a plurality of phase shifters 13 arranged in a lattice pattern. The planar antenna 101 also has a plurality of selection lines L PS and multiple data lines L PD Furthermore, the planar antenna 101 has a signal line L for transmitting a signal (radio wave) emitted from the patch antenna P. S has.

[0040] Multiple selection lines L PS The selection lines L extend in the row direction. PS Each of the selection lines L PS Each of the selection lines L passes under a plurality of patch antennas P arranged in the row direction. PS is used to select the phase shifter 13.

[0041] Multiple data lines L PD The data lines L extend in the column direction. PD Each of the data lines L passes through a plurality of phase shifters 13 arranged in the column direction. PD is used to write phase shift data to the phase shifter 13.

[0042] In the layout of this comparative example, the signal line L S At multiple points, the selection line L PS and data line L PD Intersects with the signal line L S In the layout of this comparative example, the selection line L PS and the patch antenna P intersect.

[0043] Comparative Example 2 9 is a plan view of a planar antenna according to Comparative Example 2. The planar antenna 102 of this comparative example has a plurality of patch antennas P and a plurality of phase shifters 13 arranged in a lattice pattern. The planar antenna 102 also has a plurality of selection lines L PS and multiple data lines L PDFurthermore, the planar antenna 102 has a signal line L for transmitting a signal (radio wave) emitted from the patch antenna P. S has.

[0044] Multiple selection lines L PS The selection lines L extend in the row direction. PS Each of the selection lines L PS Each of the selection lines L is arranged to avoid the patch antennas P arranged in the row direction. PS is used to select the phase shifter 13.

[0045] Multiple data lines L PD The data lines L extend in the column direction. PD Each of the data lines L passes through a plurality of phase shifters 13 arranged in the column direction. PD is used to write phase shift data to the phase shifter 13.

[0046] In the layout of this comparative example, the selection line L PS There is no intersection between the selection line L and the patch antenna P. Therefore, according to this comparative example, compared to the first comparative example, PS The interference between the selection line L and the patch antenna P is reduced. However, in the layout of this comparative example, the selection line L PS and data line L PD is the signal line L S Intersects with.

[0047] 10 is a cross-sectional view of the planar antenna of this comparative example. The planar antenna 102 includes a patch antenna P, a first insulating layer 111, a second insulating layer 112, a phase shifter layer 130, a TFT substrate 120, a TFT wiring 135, a ground layer 144, a ground layer 145, and an isolation layer 170.

[0048] A plurality of patch antennas P are disposed on the upper surface of the first insulating layer 111. The plurality of patch antennas P are arranged in a two-dimensional lattice pattern. The plurality of patch antennas P arranged in a two-dimensional lattice pattern constitute a phased array antenna. A second insulating layer 112 is disposed on the lower surface of the first insulating layer 111. An opening is formed in the second insulating layer 112 in a region below the patch antennas P. The opening portion of the second insulating layer 112 forms an air gap according to the thickness of the second insulating layer 112. A ground layer 144 is disposed on the lower surface of the second insulating layer 112. In the region below the patch antennas P, the ground layer 144 has a communication slot S c is formed.

[0049] 10, a phase shifter layer 130 is formed on the upper surface of the TFT substrate 120. In addition, a signal line L S1 and signal line L S2 The phase shifter layer 130, the signal line L S1 , and signal line L S2 The signal lines L are formed in the same layer. A ground layer 145 is formed on the lower surface of the TFT substrate 120. S2 The upper communication slot S c The patch antenna P is coupled to the signal line L via an air gap G. S1 The signal supplied to the signal line L is phase-shifted by the phase shifter formed in the phase shifter layer 130. S2 Slot S for communication above c and propagates through the air gap G to the patch antenna P.

[0050] 10, an isolation layer 170 is formed. The isolation layer 170 is provided between the ground layer 144 and the signal line L. S The separation layer 170 is disposed between the TFT wiring 135 and the signal line L. S 10, the characteristic impedance varies in the vicinity of the isolation layer 170.

[0051] In this embodiment, the signal line LS A ground layer is interposed between the signal line (signal line L S1 and signal line L S2 ) and the TFT wiring, and is formed uniformly along the surface of the TFT substrate. S1 and signal line L S2 Since interference can be prevented without providing a local isolation layer at the intersection of the pixel electrode and the TFT wiring, fluctuations in characteristic impedance are reduced.

[0052] As described above, the planar antenna of this embodiment includes a plurality of patch antennas, a substrate, a signal line, and a ground layer. The plurality of patch antennas are arranged in a two-dimensional array. The plurality of patch antennas arranged in a two-dimensional array constitute an antenna array. A phase shifter layer including a phase shifter and wiring is formed on the substrate. The phase shifter is associated with each of the plurality of patch antennas. The wiring is used to control the phase shifter. The signal line is formed on the same plane as the antenna array. A signal to be communicated propagates through the signal line. The ground layer is disposed between the phase shifter layer and the signal line. A slot is formed on the ground layer at least between the signal line and the phase shifter.

[0053] In the planar antenna of this embodiment, the signal line formed on the same plane as the antenna array and the wiring of the phase shifter layer are formed on different layers. The wiring of the phase shifter layer and the signal line are separated via a ground layer. Therefore, according to this embodiment, the fluctuation of the characteristic impedance of the signal line that may occur at the intersection of the wiring of the phase shifter layer and the signal line is suppressed.

[0054] In one aspect of the present embodiment, a slot is formed in the ground layer above the phase shifter. The signal line and the phase shifter are connected by electromagnetic coupling through the slot. According to this aspect, the signal line and the phase shifter can be connected by electromagnetic coupling through the slot formed in the ground layer.

[0055] In one aspect of this embodiment, the signal line includes a first signal line and a second signal line. The first signal line is extended from the signal source to above the first end of the phase shifter. The second signal line is extended from above the second end of the phase shifter to the patch antenna. The first signal line is connected to the first end of the phase shifter by electromagnetic coupling. The second signal line is connected to the second end of the phase shifter by electromagnetic coupling. According to this aspect, a signal propagating through the first signal line can be transmitted to the phase shifter by electromagnetic coupling, and the phase of the signal can be shifted by the phase shifter.

[0056] In one aspect of the present embodiment, the second signal line is integrally formed with the patch antenna, which simplifies the structure and manufacturing of the second signal line and the patch antenna.

[0057] In one aspect of this embodiment, a slot is formed in the ground layer below the second end of the first signal line and below the first end of the second signal line. The phase shifter is extended to the area below the patch antenna. According to this aspect, by forming a slot corresponding to each of the first signal line and the second signal line, interference between the upper layer and the lower layer of the ground layer is reduced. Therefore, according to this aspect, the area of ​​the phase shifter can be extended to the area below the patch antenna.

[0058] The planar antenna according to one aspect of the present embodiment includes a first insulating layer and a second insulating layer. The first insulating layer has a signal line and a patch antenna disposed on its upper surface, and a ground layer disposed on its lower surface. The second insulating layer has a ground layer disposed on its upper surface, and its lower surface contacts the upper surface of the phase shifter layer. According to this aspect, the capacitance between the signal line and the phase shifter can be set according to the dielectric constants of the first insulating layer and the second insulating layer.

[0059] In one aspect of the present embodiment, a ground plate is disposed on the underside of the substrate. According to this aspect, by disposing the ground plate on the underside of the substrate, disturbance due to radio waves propagating from below the substrate can be prevented.

[0060] The planar antenna of this embodiment includes a first insulating layer. A signal line and a patch antenna are disposed on the upper surface of the first insulating layer. The ground layer is disposed on the upper surface of the substrate with a dielectric layer that covers the surface of the phase shifter layer sandwiched therebetween. The planar antenna of this embodiment has a structure in which an upper layer structure and a lower layer structure are laminated. The upper layer structure includes a signal line, a patch antenna, and a first insulating layer. The lower layer structure includes a ground layer, a phase shifter layer, and a substrate. According to this aspect, the upper layer structure and the lower layer structure can be manufactured by different manufacturing methods. For example, the upper layer structure U can be manufactured by a micro LED process technology, and the lower layer structure L can be manufactured by a TFT process technology.

[0061] For mobile communication of B5G (Beyond 5 Generation) following 5G (5 Generation), an antenna device compatible with electromagnetic waves in a high frequency band has been developed. In B5G, millimeter waves and terahertz waves are expected to be used to accommodate the increase in communication capacity. Compared to radio waves used before 5G, millimeter waves and terahertz waves are easily attenuated. Therefore, compared to radio waves used before 5G, millimeter waves and terahertz waves have a shorter communication distance. If the number of elements mounted on the antenna device can be multi-elemented up to a scale of 10,000, the shorter communication distance can be covered by improving the antenna gain. However, when the number of elements increases to a scale of 10,000, there is a possibility that the wiring used for selecting the phase shifter and writing data and the signal line will intersect at a portion, causing mutual interference. If the wiring used for selecting the phase shifter and writing data and the signal line interfere with each other, the characteristic impedance of the signal line may fluctuate. According to the configuration of this embodiment, a ground layer is disposed between the wiring and the signal line, so that the wiring and the signal line are less likely to interfere with each other. Therefore, according to this embodiment, fluctuations in the characteristic impedance of the signal line, which may occur at the points where the wiring of the phase shifter layer and the signal line intersect, are suppressed.

[0062] Second embodiment Next, an antenna device according to a second embodiment will be described with reference to the drawings. The antenna device according to the present disclosure includes the planar antenna according to the first embodiment. The antenna device according to the present embodiment has a configuration in which a signal source and a circuit are added to the planar antenna according to the first embodiment. The following configuration is an example and does not limit the configuration of the antenna device according to the present disclosure.

[0063] (composition) Fig. 11 is a conceptual diagram showing an example of the configuration of an antenna device in the present disclosure. Fig. 11 shows an example of the external appearance of an antenna device. The antenna device 2 includes a planar antenna 200. The planar antenna 200 includes the planar antenna of the first embodiment. Details of the planar antenna 200 will not be described. An antenna array 20 composed of a plurality of patch antennas P arranged in a two-dimensional array is disposed on the upper surface of the planar antenna 200. In the example of Fig. 11, the plurality of patch antennas P are arranged along the X direction and the Y direction. The plurality of patch antennas P are arranged in a phased array.

[0064] The antenna device 2 is mounted with a first driving circuit 271 and a second driving circuit 272. The first driving circuit 271 and the second driving circuit 272 are circuits used to specify the patch antenna P to be driven. By driving the first driving circuit 271 and the second driving circuit 272, it is possible to specify an address associated with each patch antenna P. For example, the first driving circuit 271 and the second driving circuit 272 are formed on the surface of the planar antenna 200. The first driving circuit 271 and the second driving circuit 272 may be formed inside the planar antenna 200.

[0065] 12 is a block diagram showing an example of the configuration of the antenna device 2. The antenna device 2 includes an antenna array 20, a phase shifter 21, a matrix circuit 22, a drive circuit 27, a control circuit 28, and a signal source 29.

[0066] The patch antenna P is a plate-shaped radiating element. In this embodiment, the patch antenna P is rectangular. The shape of the patch antenna P is not limited to rectangular, and may be circular or other shapes. An air gap and a slot are opened below the patch antenna P. The patch antenna P is connected to a signal line by electromagnetic coupling through the air gap and slot formed below. The patch antenna P is an open resonator. The patch antenna P resonates at a frequency that corresponds to an integer multiple of 1 / 2 the wavelength of the length of the patch antenna P. The size of the patch antenna P is set according to the wavelength of the radio waves used for communication.

[0067] The matrix circuit 22 has a configuration in which a plurality of thin film transistors (TFTs) are arranged in a two-dimensional array. The matrix circuit 22 is formed using a TFT process technology. For example, a ground layer is formed above the matrix circuit 22. The ground layer is formed to prevent electromagnetic coupling above and below the ground layer. For example, the ground layer includes a conductor. The potential of the ground layer is basically a ground potential. Therefore, a capacitance according to the dielectric constant of a dielectric layer such as an insulating layer or a TFT substrate is formed between the signal line included in the phase shifter 21 and the ground layer. Each of the plurality of TFTs included in the matrix circuit 22 is associated with one of the plurality of patch antennas P included in the antenna array 20. For example, the TFT includes a semiconductor layer such as amorphous silicon, polysilicon, or oxide semiconductor.

[0068] The phase shifter 21 is disposed for each antenna unit. The phase shifter 21 is any one of the phase shifters included in the planar antenna of the first embodiment.

[0069] The drive circuit 27 includes a first drive circuit 271 and a second drive circuit 272. The first drive circuit 271 is a circuit for performing addressing in the X direction. The second drive circuit 272 is a circuit for performing addressing in the Y direction. The drive circuit 27 drives the first drive circuit 271 and the second drive circuit 272 to specify an address associated with each patch antenna P. The drive circuit 27 drives a plurality of TFTs included in the matrix circuit 22 under the control of the control circuit 28. The drive circuit 27 individually drives a plurality of TFTs arranged in a two-dimensional array.

[0070] The control circuit 28 drives the drive circuit 27 in response to a control signal from the outside. The control circuit 28 drives the drive circuit 27 by an active matrix drive method. The control circuit 28 also outputs the control signal from the outside to the signal source 29. For example, the control circuit 28 is realized by a microcomputer (also called a microcomputer) or a microcontroller. For example, the control circuit 28 has a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, etc. The control circuit 28 executes control and processing according to a program stored in advance. The control circuit 28 executes control and processing according to a program in response to a preset schedule, timing, a control instruction from the outside, etc. For example, the control circuit 28 controls the antenna array 20 composed of a plurality of patch antennas P included in the planar antenna 200 to transmit directional radio waves from the antenna array 20. In this way, the antenna array 20 is used as a phased array antenna.

[0071] The signal source 29 is connected to the multiple switch groups SW included in the phase shifter 21. The signal source 29 is also connected to the control circuit 28. The signal source 29 obtains a control signal from the control circuit 28. The signal source 29 controls the ON / OFF of the multiple switch groups SW that constitute the switch group in response to the control signal. The signal source 29 may be configured to directly receive a control signal from the outside without passing through the control circuit 28.

[0072] A signal that reaches the signal input section of the phase shifter 21 through a signal line (not shown) connected to an ON-state TFT is phase-shifted by an amount of phase shift according to the line length set in the phase shifter 21 and the dielectric constant of dielectric materials such as an insulating layer and a TFT substrate. The phase-shifted signal propagates from the signal line to the patch antenna P by electromagnetic coupling. The signal propagated to the patch antenna P is transmitted from the patch antenna P as a radio wave to be transmitted. The radio wave transmitted from the patch antenna P is based on a signal output from a transmission circuit (not shown). There are no particular limitations on the information contained in the signal.

[0073] Moreover, the radio waves received by the patch antenna P are received according to a capacitance based on the dielectric constant of a dielectric material such as an insulating layer or a TFT substrate interposed between the patch antenna P and the signal line. The phase of the received radio waves is shifted by an amount of phase shift based on the line length set in the phase shifter 21 and the dielectric constant of a dielectric material such as an insulating layer or a TFT substrate. The phase-shifted signal is received by a receiving circuit (not shown) through the signal line. Information contained in the signal received by the receiving circuit is decoded by a decoder not shown.

[0074] As described above, the antenna device of the present embodiment includes the planar antenna, signal source, matrix circuit, drive circuit, and control circuit of the first embodiment. The signal source is connected to a signal line included in the planar antenna. The matrix circuit has a structure in which a plurality of thin film transistors connected to wiring included in the planar antenna are arranged in a two-dimensional array. The drive circuit drives the thin film transistors included in the matrix circuit. The control circuit drives the drive circuit in response to a control signal. The antenna device of this aspect includes the planar antenna of the first embodiment. Therefore, according to this aspect, it is possible to provide an antenna device in which fluctuations in characteristic impedance in the signal line included in the planar antenna are suppressed.

[0075] In one aspect of the present embodiment, the control circuit controls a plurality of patch antennas included in the planar antenna to transmit directional radio waves from an antenna array configured by the plurality of patch antennas. According to this aspect, the antenna array configured by the plurality of patch antennas can be used as a phased array antenna.

[0076] Third embodiment Next, a planar antenna according to a third embodiment will be described with reference to the drawings. The planar antenna of this embodiment has a simplified configuration of the planar antenna of the first embodiment. FIG. 13 is a conceptual diagram showing an example of the configuration of a planar antenna in this disclosure. The planar antenna 3 includes a plurality of patch antennas P, a substrate 320, a signal line L S , and a ground layer 340.

[0077] The patch antennas P are arranged in a two-dimensional array. The patch antennas P arranged in a two-dimensional array form an antenna array. A phase shifter layer 330 including phase shifters 331 and wiring 335 is formed on the substrate 320. The phase shifters 331 correspond to each of the patch antennas P. The wiring 335 is used to control the phase shifters 331. A signal line L S is formed on the same plane as the antenna array. S The ground layer 340 is connected to the phase shifter layer 330 and the signal line L S The ground layer 340 is disposed between the signal line L S A slot is formed between the phase shifter 331 and the phase shifter 331 .

[0078] In the planar antenna of this embodiment, the signal line formed on the same plane as the antenna array and the wiring of the phase shifter layer are formed on different layers. The wiring of the phase shifter layer and the signal line are separated via a ground layer. Therefore, according to this embodiment, the fluctuation of the characteristic impedance of the signal line that may occur at the intersection of the wiring of the phase shifter layer and the signal line is suppressed.

[0079] (Hardware) Next, a hardware configuration for executing the control and processing in the present disclosure will be described with reference to the drawings. Here, an information processing device 90 (computer) in Fig. 14 is given as an example of such a hardware configuration. The information processing device 90 in Fig. 14 is an example of a configuration for executing the control and processing in the present disclosure, and does not limit the scope of the present disclosure.

[0080] As shown in Fig. 14, an information processing device 90 includes a processor 91, a memory 92, an auxiliary storage device 93, an input / output interface 95, and a communication interface 96. In Fig. 14, the interface is abbreviated as I / F (Interface). The processor 91, the memory 92, the auxiliary storage device 93, the input / output interface 95, and the communication interface 96 are connected to each other via a bus 98 so as to be able to communicate data with each other. In addition, the processor 91, the memory 92, the auxiliary storage device 93, and the input / output interface 95 are connected to a network such as the Internet or an intranet via the communication interface 96.

[0081] The processor 91 loads a program (instructions) stored in an auxiliary storage device 93 or the like into the memory 92. For example, the program is a software program for executing the control and processing in the present disclosure. The processor 91 executes the program loaded into the memory 92. The processor 91 executes the program to execute the control and processing in the present disclosure.

[0082] The memory 92 is a memory having an area in which a program is loaded. A program stored in an auxiliary storage device 93 or the like is loaded into the memory 92 by the processor 91. The memory 92 is realized by a volatile memory such as a dynamic random access memory (DRAM). Alternatively, a non-volatile memory such as a magnetoresistive random access memory (MRAM) may be used as the memory 92.

[0083] The auxiliary storage device 93 stores various data such as programs. For example, the auxiliary storage device 93 is realized by a local disk such as a hard disk or a flash memory. Note that it is also possible to store various data in the memory 92 and omit the auxiliary storage device 93.

[0084] The input / output interface 95 is an interface for connecting the information processing device 90 to peripheral devices based on standards and specifications. The communication interface 96 is an interface for connecting to an external system or device through a network such as the Internet or an intranet based on standards and specifications. The input / output interface 95 and the communication interface 96 may be a common interface for connecting to an external device.

[0085] Input devices such as a keyboard, a mouse, and a touch panel may be connected to the information processing device 90 as necessary. These input devices are used to input information and settings. When a touch panel is used as the input device, a screen having the function of the touch panel becomes the interface. The processor 91 and the input devices are connected via an input / output interface 95.

[0086] The information processing device 90 may be equipped with a display device for displaying information. When the display device is equipped, the information processing device 90 is equipped with a display control device (not shown) for controlling the display of the display device. The information processing device 90 and the display device are connected via an input / output interface 95.

[0087] The information processing device 90 may be provided with a drive device. The drive device mediates between the processor 91 and a recording medium (program recording medium) in reading data and programs stored in the recording medium and writing the processing results of the information processing device 90 to the recording medium. The information processing device 90 and the drive device are connected via an input / output interface 95.

[0088] The above is an example of a hardware configuration for enabling the control and processing in the present disclosure. The hardware configuration in FIG. 14 is an example of a hardware configuration for executing the control and processing in the present disclosure, and does not limit the scope of the present disclosure. A program for causing a computer to execute the control and processing in the present disclosure is also included in the scope of the present disclosure.

[0089] A program recording medium on which a program for executing the processing in this embodiment is recorded is also included in the scope of the present invention. For example, the program recording medium is a computer-readable non-transient recording medium. The recording medium can be realized by an optical recording medium such as a CD (Compact Disc) or a DVD (Digital Versatile Disc). The recording medium may be realized by a semiconductor recording medium such as a USB (Universal Serial Bus) memory or an SD (Secure Digital) card. The recording medium may also be realized by a magnetic recording medium such as a flexible disk or other recording medium.

[0090] The components in the present disclosure may be combined in any manner. The components in the present disclosure may be realized by software. The components in the present disclosure may be realized by a circuit.

[0091] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-mentioned embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be appropriately combined with other embodiments.

[0092] Some or all of the above embodiments may be described as, but are not limited to, the following supplementary notes. In the supplementary notes, the dependent claims of each category may also be dependent on other categories. The descriptions in the supplementary notes have the meaning as a basis for amendment. (Appendix 1) an antenna array in which a plurality of patch antennas are arranged in a two-dimensional array; a substrate on which a phase shifter layer is formed, the phase shifter layer including phase shifters corresponding to each of the plurality of patch antennas and wiring used to control the phase shifters; a signal line formed on the same plane as the antenna array and through which a signal to be communicated propagates; a ground layer disposed between the phase shifter layer and the signal line, the ground layer having a slot formed at least between the signal line and the phase shifter. (Appendix 2) the slot is formed in the ground layer above the phase shifter, 2. The planar antenna according to claim 1, wherein the signal line and the phase shifter are connected by electromagnetic coupling via the slot. (Appendix 3) The signal line is a first signal line extending from a signal source to above a first end of the phase shifter; a second signal line extending from above the second end of the phase shifter to the patch antenna; The first signal line is connected to a first end of the phase shifter by electromagnetic coupling; The second signal line is 3. The planar antenna according to claim 2, connected to a second end of the phase shifter by electromagnetic coupling. (Appendix 4) 4. The planar antenna according to claim 3, wherein the second signal line is integrally formed with the patch antenna. (Appendix 5) the slots are formed in the ground layer below the second end of the first signal line and below the first end of the second signal line; The phase shifter comprises: 4. The planar antenna of claim 3, which extends to a region below the patch antenna. (Appendix 6) a first insulating layer having the signal line and the patch antenna disposed on an upper surface thereof and the ground layer disposed on a lower surface thereof; A planar antenna as described in Appendix 1, comprising: a second insulating layer having an upper surface on which the ground layer is disposed and whose lower surface is in contact with the upper surface of the phase shifter layer. (Appendix 7) 7. The planar antenna according to claim 6, wherein a ground plate is disposed on a lower surface of the substrate. (Appendix 8) a first insulating layer on which the signal line and the patch antenna are disposed; The ground layer is a dielectric layer that covers a surface of the phase shifter layer and is disposed on the upper surface of the substrate; 6. The planar antenna described in Appendix 5, having a laminated structure in which an upper layer structure including the signal line, the patch antenna, and the first insulating layer and a lower layer structure including the ground layer, the phase shifter layer, and the substrate are laminated. (Appendix 9) A planar antenna according to any one of Supplementary Notes 1 to 8; a signal source connected to the signal line included in the planar antenna; a matrix circuit in which a plurality of thin film transistors connected to wiring included in the planar antenna are arranged in a two-dimensional array; a drive circuit for driving the thin film transistors included in the matrix circuit; A control circuit that drives the drive circuit in response to a control signal. (Appendix 10) The control circuit includes: 10. The antenna device according to claim 9, wherein the patch antennas included in the planar antenna are controlled to transmit directional radio waves from the antenna array formed by the patch antennas. [Explanation of symbols]

[0093] 1, 3 Planar antenna 2 Antenna equipment 20 Antenna Array 21 Phase shifter 22 Matrix Circuit 27 Drive circuit 28 Control Circuit 29 Signal source 111 First insulating layer 112 Second insulating layer 120 TFT substrate 130 Phase shifter layer 131 Phase shifter 135 TFT wiring 141, 142, 143 Ground layer 150 Memory for phase shifter 200 Planar antenna 271 First drive circuit 272 Second drive circuit 320 Substrate 330 Phase shifter layer 331 Phase shifter 335 Wiring 340 Ground layer

Claims

1. an antenna array in which a plurality of patch antennas are arranged in a two-dimensional array; a substrate on which a phase shifter layer is formed, the phase shifter layer including phase shifters corresponding to each of the plurality of patch antennas and wiring used to control the phase shifters; a signal line formed on the same plane as the antenna array and through which a signal to be communicated propagates; a ground layer disposed between the phase shifter layer and the signal line, the ground layer having a slot formed at least between the signal line and the phase shifter.

2. the slot is formed in the ground layer above the phase shifter, The planar antenna according to claim 1 , wherein the signal line and the phase shifter are connected to each other by electromagnetic coupling through the slot.

3. The signal line is a first signal line extending from a signal source to above a first end of the phase shifter; a second signal line extending from above the second end of the phase shifter to the patch antenna; The first signal line is a first end of the phase shifter connected by electromagnetic coupling; The second signal line is 3. The planar antenna according to claim 2, wherein the planar antenna is connected to the second end of the phase shifter by electromagnetic coupling.

4. The planar antenna according to claim 3 , wherein the second signal line is formed integrally with the patch antenna.

5. the slots are formed in the ground layer below the second end of the first signal line and below the first end of the second signal line; The phase shifter comprises:

4. The planar antenna according to claim 3, which extends to a region below the patch antenna.

6. a first insulating layer having an upper surface on which the signal line and the patch antenna are disposed and a lower surface on which the ground layer is disposed; 2. The planar antenna according to claim 1, further comprising: a second insulating layer having an upper surface on which the ground layer is disposed and a lower surface of which is in contact with the upper surface of the phase shifter layer.

7. The planar antenna according to claim 6, further comprising a ground plane disposed on the underside of said substrate.

8. a first insulating layer on which the signal line and the patch antenna are disposed; The ground layer is a dielectric layer that covers a surface of the phase shifter layer and is disposed on the upper surface of the substrate; 6. The planar antenna according to claim 5, having a laminated structure in which an upper layer structure including the signal line, the patch antenna, and the first insulating layer and a lower layer structure including the ground layer, the phase shifter layer, and the substrate are laminated.

9. A planar antenna according to any one of claims 1 to 8; a signal source connected to the signal line included in the planar antenna; a matrix circuit in which a plurality of thin film transistors connected to wiring included in the planar antenna are arranged in a two-dimensional array; a drive circuit for driving the thin film transistors included in the matrix circuit; A control circuit that drives the drive circuit in response to a control signal.

10. The control circuit includes: The antenna device according to claim 9 , wherein a plurality of the patch antennas included in the planar antenna are controlled to transmit directional radio waves from the antenna array formed by the plurality of the patch antennas.

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